An input matching stable gain adjustable mixer receiver

Abstract

This invention discloses an input-matched, gain-adjustable mixer-priority receiver, belonging to the field of mixer-priority receivers. The invention cascades an impedance-matched buffer amplifier within the operational amplifier of the transimpedance amplifier (TIA), including an adjustable bias passive mixer and a gain-adjustable TIA connected in sequence, and is equipped with an eight-phase non-overlapping local oscillator signal generator. The RF input signal undergoes RF down-conversion by the eight passive mixers before being input to the baseband amplification link; the eight-phase non-overlapping local oscillator signal generator provides the eight passive mixers with a uniformly distributed phase and a 12.5% ​​duty cycle local oscillator drive signal. This structure effectively eliminates the strong coupling constraint between the gain and input impedance of traditional transimpedance amplifiers, achieving near-stable input impedance during gain adjustment without significantly degrading noise performance, and eliminating the input matching degradation problem caused by gain switching.

Description

Technical Field

[0001] This invention belongs to the field of mixer priority receivers, and specifically relates to an input-matched, gain-adjustable mixer priority receiver. Background Technology

[0002] With the rapid development of the Internet of Things, wireless sensing, and multi-band communication technologies, wireless communication terminals are placing higher demands on the frequency band adaptability and dynamic signal reception performance of receivers. Frequency-tunable narrowband receivers have become the core front-end module of various wireless communication systems. Compared with traditional receiver architectures, mixer-first receivers have become a research hotspot in RF receiving circuits due to their advantages such as flexible frequency band adaptability, simple architecture, and excellent broadband characteristics. Existing technologies have conducted extensive research and developed corresponding technical solutions around the performance optimization directions of this architecture, such as bandwidth expansion, linearity improvement, noise cancellation, and out-of-band interference suppression.

[0003] Current industry research on Mixer-First architecture optimization largely focuses on performance improvements in fixed-gain scenarios, with very little attention paid to the development and application of wide-range gain-adjustable technology. However, in real-world complex wireless communication scenarios, the power fluctuation range of the RF input signal received by the receiver is significant, making it difficult for fixed-gain receivers to adapt to complex signal input environments: under weak signal conditions, increasing gain cannot guarantee receiving sensitivity and noise performance; under strong signal conditions, reducing gain suppression circuit saturation and avoiding nonlinear distortion cannot be achieved, easily leading to signal reception failure and demodulation distortion. Therefore, a receiver front-end with wide-range gain adjustment capability is a core requirement for expanding the dynamic range of wireless reception and improving the adaptability of the terminal environment.

[0004] Input matching stability during receiver gain switching is a key technical challenge for achieving wide dynamic range and high-performance reception. In the current mainstream low-noise amplifier-first (LNA-First) receiver architecture, the overall input impedance is dominated by the front-end low-noise amplifier. The industry has maturely achieved stable input matching control under wide-range gain adjustment conditions, effectively ensuring reception performance. In contrast, the Mixer-First architecture uses a front-end passive mixer topology. Passive mixers possess transparent signal transmission characteristics, and the performance of the back-end transimpedance amplifier (TIA) is directly mapped to the RF front-end. Therefore, the overall input impedance is entirely determined by the TIA circuitry.

[0005] To meet the low-noise design specifications of receivers, the TIA circuits in traditional Mixer-First architectures generally exhibit a strong coupling between gain and input impedance, with their parameters mutually constraining each other and unable to be independently adjusted. This characteristic leads to a significant degradation in the input impedance matching characteristics of existing gain-adjustable Mixer-First receivers during wide-range gain switching, resulting in a substantial deterioration in input return loss. Consequently, they cannot maintain stable RF input matching performance across the entire gain adjustment range, making it difficult to meet the engineering application requirements of multi-scenario, wide-dynamic wireless communication. This has become the core technical bottleneck for the implementation of high-performance gain-adjustable technology in the current Mixer-First architecture. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art. Addressing the difficulty of existing mixer-priority architecture receivers in simultaneously achieving wide-range gain adjustment, stable input matching, and low noise performance, this invention provides a gain-adjustable mixer-priority receiver with stable input matching. Through innovative circuit topology design, it achieves decoupling control of TIA gain and input impedance, enabling wide-range gain adjustment while ensuring stable input impedance matching across the entire gain range, without degrading the overall noise performance of the receiver.

[0007] The specific technical solution adopted in this invention is as follows: This invention provides an input-matched, stable, gain-adjustable mixer-priority receiver, comprising an eight-phase non-overlapping local oscillator signal generator, four identical passive mixers, four identical operational amplifiers, eight identical adjustable resistors, eight identical capacitors, and six identical summing amplifiers. Each of the passive mixers has its radio frequency input terminal connected to the input signal, its two LO input terminals connected to the output terminals of the eight-phase non-overlapping local oscillator signal generator, and its two intermediate frequency output terminals connected to the two input terminals of the corresponding operational amplifier. Each operational amplifier has a corresponding adjustable resistor and a capacitor connected in parallel across its input and corresponding output terminals. The input terminals of the first summing amplifier, the second summing amplifier, and the third summing amplifier are respectively connected to the output terminals of the first operational amplifier, the second operational amplifier, and the third operational amplifier. The output terminals of the first summing amplifier, the second summing amplifier, and the third summing amplifier converge to form an I-channel differential output. The input terminals of the fourth, fifth, and sixth summing amplifiers are connected to the output terminals of the second, third, and fourth operational amplifiers, respectively. The output terminals of the fourth, fifth, and sixth summing amplifiers converge to form a Q-channel differential output.

[0008] Preferably, the passive mixer includes two identical passive mixer NMOS transistors, two identical passive mixer resistors, and two identical passive mixer capacitors. The sources of both passive mixer NMOS transistors are connected to the RF input terminal, and the substrates of both are connected to the substrate bias voltage. Each passive mixer resistor has one end connected to the bias voltage and the other end connected to the gate of the corresponding passive mixer NMOS transistor. Each passive mixer capacitor has one end connected to the gate of the corresponding passive mixer NMOS transistor and the other end connected to the positive LO input terminal and the negative LO input terminal, respectively. The drain of the passive mixer NMOS transistor corresponding to the positive LO input terminal is the positive intermediate frequency output terminal, and the drain of the passive mixer NMOS transistor corresponding to the negative LO input terminal is the negative intermediate frequency output terminal.

[0009] Preferably, the eight-phase non-overlapping local oscillator signal generator includes two identical clock drive buffers, four identical D latches, and eight AND gates. The positive and negative terminals of the differential clock signal provided externally are connected to the input terminals of the first and second clock drive buffers, respectively. The output terminals of the first and second clock drive buffers are cross-coupled to the clock control terminals of each D latch to provide complementary clock control signals. The D latches are cascaded sequentially along the signal transmission direction, and the differential output terminal of the last-stage D latch is fed back and coupled to the differential input terminal of the first-stage D latch, forming a ring shift register structure for frequency division and phase shifting of the differential clock signal, and generating multiple differential intermediate signals at the signal transmission nodes of each adjacent stage. The differential intermediate signals at each signal transmission node are processed by a clock logic processing circuit composed of eight AND gates to generate a non-overlapping 12.5% ​​duty cycle local oscillator signal, which is then sequentially connected to the two LO input terminals of each passive mixer.

[0010] Specifically, the positive and negative terminals of the differential clock signal provided externally are connected to the input terminals of the first clock drive buffer and the second clock drive buffer, respectively. The output terminal of the first clock drive buffer is connected to the positive clock input terminal of the first D latch, the negative clock input terminal of the second D latch, the positive clock input terminal of the third D latch, and the negative clock input terminal of the fourth D latch, respectively. The output terminal of the second clock drive buffer is connected to the negative clock input terminal of the first D latch, the positive clock input terminal of the second D latch, the negative clock input terminal of the third D latch, and the positive clock input terminal of the fourth D latch, respectively. The positive output of the first D latch is connected to the positive input of the second D latch via a first positive signal line. The negative output of the first D latch is connected to the negative input of the second D latch via a first negative signal line. The positive output of the second D latch is connected to the positive input of the third D latch via a second positive signal line. The negative output of the second D latch is connected to the negative input of the third D latch via a second negative signal line. The positive output of the third D latch is connected to the positive input of the fourth D latch via a third positive signal line. The negative output of the third D latch is connected to the negative input of the fourth D latch via a third negative signal line. The positive output of the fourth D latch is connected to the negative input of the first D latch via a fourth positive signal line. The negative output of the fourth D latch is connected to the positive input of the first D latch via a fourth negative signal line. The first positive signal line, the first negative signal line, the second positive signal line, the second negative signal line, the third positive signal line, the third negative signal line, the fourth positive signal line, and the fourth negative signal line are processed by a clock logic processing circuit composed of eight AND gates to generate a non-overlapping 12.5% ​​duty cycle local oscillator signal, which is then connected sequentially to the two LO input terminals of each passive mixer.

[0011] Preferably, the first negative signal line and the second positive signal line are respectively connected to the two input terminals of the first AND gate, the second negative signal line and the third positive signal line are respectively connected to the two input terminals of the second AND gate, the third negative signal line and the fourth positive signal line are respectively connected to the two input terminals of the third AND gate, the fourth negative signal line and the first negative signal line are respectively connected to the two input terminals of the fourth AND gate, the first positive signal line and the second negative signal line are respectively connected to the two input terminals of the fifth AND gate, the second positive signal line and the third negative signal line are respectively connected to the two input terminals of the sixth AND gate, the third positive signal line and the fourth negative signal line are respectively connected to the two input terminals of the seventh AND gate, and the fourth positive signal line and the first positive signal line are respectively connected to the two input terminals of the eighth AND gate. The outputs of the first and fifth AND gates are connected to the two LO inputs of the first passive mixer, respectively. The outputs of the second and sixth AND gates are connected to the two LO inputs of the second passive mixer, respectively. The outputs of the third and seventh AND gates are connected to the two LO inputs of the third passive mixer, respectively. The outputs of the fourth and eighth AND gates are connected to the two LO inputs of the fourth passive mixer, respectively.

[0012] Preferably, the clock drive buffer includes two identical clock drive buffer NMOS transistors, two identical clock drive buffer PMOS transistors, two identical clock drive buffer resistors, and two identical clock drive buffer capacitors. One end of the first clock drive buffer capacitor is connected to the differential clock signal provided externally, and the other end is connected to one end of the first clock drive buffer resistor, the gate of the first clock drive buffer NMOS transistor, and the gate of the first clock drive buffer PMOS transistor, respectively. The other end of the first clock drive buffer resistor is connected to one end of the second clock drive buffer capacitor, the drain of the first clock drive buffer NMOS transistor, and the drain of the first clock drive buffer PMOS transistor, respectively. The other end of the second clock drive buffer capacitor is connected to one end of the second clock drive buffer resistor, the gate of the second clock drive buffer NMOS transistor, and the gate of the second clock drive buffer PMOS transistor, respectively. The other end of the second clock drive buffer resistor is connected to the drain of the second clock drive buffer NMOS transistor and the drain of the second clock drive buffer PMOS transistor, respectively, and serves as the output terminal of the clock drive buffer. The sources of both the first and second clock drive buffer NMOS transistors are connected to ground, and the sources of both the first and second clock drive buffer PMOS transistors are connected to the power supply voltage.

[0013] Preferably, the D latch includes four inverters with the same structure, four NMOS transistors with the same structure, and four PMOS transistors with the same structure. The positive clock signal is connected to the gates of the first D latch NMOS transistor and the third D latch NMOS transistor respectively. The sources of the first D latch NMOS transistor and the third D latch NMOS transistor are both connected to the ground terminal. The drain of the first D latch NMOS transistor is connected to the source of the second D latch NMOS transistor, and the drain of the third D latch NMOS transistor is connected to the source of the fourth D latch NMOS transistor. The negative clock signal is connected to the gates of the second D latch PMOS transistor and the fourth D latch PMOS transistor respectively. The sources of the second D latch PMOS transistor and the fourth D latch PMOS transistor are both connected to the ground terminal. The drain of the second D latch PMOS transistor is connected to the source of the first D latch PMOS transistor, and the drain of the fourth D latch PMOS transistor is connected to the source of the third D latch PMOS transistor. The positive input signal is connected to the gates of the second D latch NMOS transistor and the first D latch PMOS transistor respectively. The drain of the second D latch NMOS transistor, the drain of the second D latch PMOS transistor, the input terminal of the first inverter, the input terminal of the second inverter, and the output terminal of the third inverter are connected. The output terminal of the first inverter is connected to the positive output terminal. The negative input signal is connected to the gates of the fourth D latch NMOS transistor and the third D latch PMOS transistor, respectively. The drain of the fourth D latch NMOS transistor, the drain of the third D latch PMOS transistor, the input of the fourth inverter, the input of the third inverter, and the output of the second inverter are connected. The output of the fourth inverter is connected to the negative output.

[0014] Preferably, the adjustable resistor includes seven NMOS transistors with identical structures and seven sub-resistors with identical structures; The input terminals of the adjustable resistors are connected to the drains of the seven adjustable NMOS transistors, respectively. One end of the first sub-resistor is connected to the source of the first adjustable resistor NMOS transistor, and the other end is connected to the source of the second adjustable resistor NMOS transistor; one end of the second sub-resistor is connected to the source of the second adjustable resistor NMOS transistor, and the other end is connected to the source of the third adjustable resistor NMOS transistor; one end of the third sub-resistor is connected to the source of the third adjustable resistor NMOS transistor, and the other end is connected to the source of the fourth adjustable resistor NMOS transistor; one end of the fourth sub-resistor is connected to the source of the fourth adjustable resistor NMOS transistor, and the other end is connected to the source of the fifth adjustable resistor NMOS transistor; one end of the fifth sub-resistor is connected to the source of the fifth adjustable resistor NMOS transistor, and the other end is connected to the source of the sixth adjustable resistor NMOS transistor; one end of the sixth sub-resistor is connected to the source of the sixth adjustable resistor NMOS transistor, and the other end is connected to the source of the seventh adjustable resistor NMOS transistor; one end of the seventh sub-resistor is connected to the source of the seventh adjustable resistor NMOS transistor, and the other end is the output terminal of the adjustable resistor. The control signals are connected to the gates of the seven adjustable resistor NMOS transistors to adjust the resistance values ​​of the adjustable resistors.

[0015] Preferably, the operational amplifier includes a low-noise operational amplifier and an impedance matching buffer amplifier; the differential input signal is connected to the differential input terminal of the low-noise operational amplifier, the differential output terminal of the low-noise operational amplifier is connected to the differential input terminal of the impedance matching buffer amplifier, and the differential output terminal of the impedance matching buffer amplifier is the differential output terminal of the entire operational amplifier.

[0016] Specifically, the operational amplifier includes six identical operational amplifier resistors, two identical operational amplifier capacitors, four identical operational amplifier NMOS transistors, five identical operational amplifier PMOS transistors, and a sub-amplifier. The low-noise operational amplifier includes a fifth operational amplifier PMOS transistor, a first operational amplifier PMOS transistor, a second operational amplifier PMOS transistor, a first operational amplifier resistor, a second operational amplifier resistor, a first operational amplifier NMOS transistor, and a second operational amplifier NMOS transistor. The impedance matching buffer amplifier includes a third operational amplifier NMOS transistor, a fourth operational amplifier NMOS transistor, a third operational amplifier resistor, a fourth operational amplifier resistor, a fifth operational amplifier resistor, a sixth operational amplifier resistor, a third operational amplifier PMOS transistor, a fourth operational amplifier PMOS transistor, and a sub-amplifier. The specific connection methods for each component are as follows: The positive input signal is connected to the gate of the first operational amplifier PMOS transistor, and the negative input signal is connected to the gate of the second operational amplifier PMOS transistor. The sources of the first and second operational amplifier PMOS transistors are connected to the drain of the fifth operational amplifier PMOS transistor. The gate of the fifth operational amplifier PMOS transistor is connected to the bias voltage, and its source is connected to the power supply voltage. The drains of the first operational amplifier PMOS transistor, the drains of the first operational amplifier NMOS transistor, one end of the first operational amplifier resistor, and one end of the second operational amplifier capacitor are connected to the gate of the fourth operational amplifier NMOS transistor. The drains of the second operational amplifier PMOS transistor, the drains of the second operational amplifier NMOS transistor, one end of the second operational amplifier resistor, and one end of the first operational amplifier capacitor are connected to the gate of the third operational amplifier NMOS transistor. The other end of the first operational amplifier resistor, the other end of the second operational amplifier resistor, and the gate of the first operational amplifier NMOS transistor are connected to the gate of the second operational amplifier NMOS transistor. All four operational amplifiers... The sources of all NMOS transistors in the operational amplifier are connected to ground. The drain of the third NMOS transistor, one end of the third operational amplifier resistor, one end of the fifth operational amplifier resistor, and the drain of the third operational amplifier PMOS transistor are connected to the negative output terminal. The other end of the first operational amplifier capacitor is connected to the other end of the third operational amplifier resistor. The drain of the fourth NMOS transistor, one end of the fourth operational amplifier resistor, one end of the sixth operational amplifier resistor, and the drain of the fourth operational amplifier PMOS transistor are connected to the positive output terminal. The other end of the second operational amplifier capacitor is connected to the other end of the fourth operational amplifier resistor. The other ends of the fifth and sixth operational amplifier resistors are connected to the positive input terminal of the sub-amplifier. The reference voltage is connected to the negative input terminal of the sub-amplifier. The gates of the third and fourth operational amplifier PMOS transistors are connected to the output terminal of the sub-amplifier. The sources of both the third and fourth operational amplifier PMOS transistors are connected to the power supply voltage.

[0017] Preferably, the summing amplifier includes two NMOS transistors with identical structures, two PMOS transistors with identical structures, and two resistors with identical structures. The positive input signal is connected to the gate of the first summing amplification NMOS transistor, and the negative input signal is connected to the gate of the second summing amplification NMOS transistor. The sources of both the first and second summing amplification NMOS transistors are connected to ground. The drains of the first summing amplification NMOS transistor, the drains of the first summing amplification PMOS transistor, and one end of the first summing amplification resistor are connected to the negative output terminal. The drains of the second summing amplification NMOS transistor, the drains of the second summing amplification PMOS transistor, and one end of the second summing amplification resistor are connected to the positive output terminal. The other end of the first summing amplification resistor, the other end of the second summing amplification resistor, and the gate of the first summing amplification PMOS transistor are connected to the gate of the second summing amplification PMOS transistor. The sources of both the first and second summing amplification PMOS transistors are connected to the power supply voltage.

[0018] Compared with the prior art, the present invention has the following advantages:

[0019] 1) Existing mixer-priority receivers lack gain adjustment functionality in their front-end modules, resulting in a narrow dynamic reception range. When faced with input signals exhibiting significant power fluctuations, they suffer from insufficient sensitivity under weak signal conditions and circuit saturation distortion under strong signal conditions. This invention enables wide-range gain adjustment in the receiver, adapting to complex and ever-changing communication scenarios and effectively expanding the overall dynamic signal reception range.

[0020] 2) In traditional circuits, TIA gain and input impedance are strongly coupled. Adjusting the gain will cause significant degradation of RF input matching, and optimizing matching performance usually sacrifices noise performance, making it difficult to achieve all three. This invention adopts a two-stage operational amplifier topology. The first stage is a low-noise operational amplifier, which is specifically optimized for noise performance. The second stage is an impedance matching buffer amplifier. With the help of a feedback resistor, the relationship between gain and input impedance is decoupled, maintaining a nearly stable input impedance across the entire gain adjustment range without degrading the overall noise performance. This breaks the performance trade-off limitation of existing technologies, adds an independent degree of control freedom to the mixer-priority receiver circuit design, and greatly improves the flexibility of circuit optimization. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the overall structure of the gain-adjustable mixer priority receiver of the present invention in a preferred embodiment; Figure 2 This is a schematic diagram of a passive mixer in a preferred configuration. Figure 3 This is a schematic diagram of an eight-phase non-overlapping local oscillator signal generator in a preferred configuration. Figure 4 This is a schematic diagram of the structure of a clock-driven buffer in a preferred configuration. Figure 5 This is a schematic diagram of the structure of a D latch in a preferred configuration. Figure 6 This is a schematic diagram of an adjustable resistor in a preferred configuration. Figure 7 This is a simplified model of the mixer-priority architecture receiver used in this invention; Figure 8 This is the LO signal required by the mixer; Figure 9 A linear time-invariant model for a noisy mixer-first architecture receiver; Figure 10 This is a schematic diagram of the operational amplifier in a TIA according to a preferred embodiment; Figure 11 Input impedance varies with R F The simulation results show the changes; Figure 12 This is a schematic diagram of a summing amplifier under a preferred configuration. Figure 13 The simulation results show the receiver gain and noise figure as a function of the control word. Figure 14 The simulation results for NF, gain, and S11 as a function of frequency are shown in the figure. Figure 15 The simulation results for IIP3 and OIP3 as a function of gain are shown in the figure. Detailed Implementation

[0022] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention can be practiced in many other ways different from those described herein, and those skilled in the art can make similar modifications without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below. Technical features in various embodiments of the present invention can be combined accordingly without mutual conflict.

[0023] This invention provides a gain-adjustable mixer-priority receiver with stable input matching, addressing the shortcomings of existing technologies: 1) Existing mixer-priority receivers are mostly fixed-gain designs, lacking gain adjustment capabilities. In actual wireless communication scenarios, the input signal power fluctuates widely, and fixed-gain receivers are prone to insufficient gain for weak signals and saturation distortion for strong signals, resulting in limited dynamic reception range and inability to adapt to complex operating conditions; 2) The back-end TIA circuit of traditional mixer-priority receivers has an inherent defect of strong coupling between gain and input impedance. When performing wide-range gain adjustment, it will cause a large shift in input impedance and deterioration of input matching performance, leading to RF front-end mismatch problems, which seriously affects the receiver's operational stability and signal transmission efficiency; 3) Traditional adjustable-gain topologies require trade-offs between gain adjustment, input matching, and noise performance. Optimizing gain adjustment and input matching performance can lead to a deterioration in the receiver's noise figure and a decrease in sensitivity, making it impossible to simultaneously achieve multiple core performance indicators. The device of this invention solves the following problems: 1) The problem of traditional mixer-priority receivers lacking gain adjustment capability, enabling the receiver front-end to have a wide range of gain control function, adapting to scenarios with high-power dynamic fluctuations in input signals, avoiding strong signal saturation distortion and insufficient reception sensitivity for weak signals, and broadening the receiver's dynamic signal reception range; 2) The technical pain point of strong coupling between gain adjustment and input impedance in traditional solutions, maintaining stable input impedance matching performance of the receiver during the full gain range adjustment process, avoiding significant degradation of input return loss indicators during gain switching, and ensuring good RF front-end matching characteristics under full gain conditions; 3) The problem of noise performance degradation when conventional adjustable gain circuits achieve stable input matching across the full gain range, eliminating the need for noise performance trade-offs, ensuring excellent low-noise reception characteristics of the entire receiver, and achieving a unity of gain adjustment, stable matching, and low noise performance.

[0024] like Figure 1 As shown, the device of the present invention includes an adjustable bias passive mixer and a gain adjustable TIA connected in sequence, and is equipped with an eight-phase non-overlapping local oscillator signal generator. The RF input signal is input to the baseband amplification link after being down-converted by the eight-channel passive mixer; the eight-phase non-overlapping local oscillator signal generator provides the eight-channel passive mixer with a local oscillator drive signal with a uniform phase distribution and a duty cycle of 12.5%.

[0025] The core improvement of this invention lies in cascading an impedance matching buffer amplifier into the operational amplifier of the TIA. This structure effectively removes the strong coupling constraint between the gain and input impedance of the traditional transimpedance amplifier, achieving near-stable input impedance during gain adjustment without significantly degrading noise performance, thus eliminating the input matching degradation problem caused by gain switching. The stable input impedance of the TIA is mapped to the RF port via a passive mixer, ensuring that the receiver maintains a stable input impedance throughout the full gain adjustment range, guaranteeing constant RF port matching characteristics. The output signals of each TIA channel are weighted and combined to output four differential quadrature baseband signals.

[0026] Furthermore, the adjustable bias passive mixer adopts an NMOS switching structure, which independently biases the gate and substrate of the switching transistor. This reduces the on-resistance of the switch, avoids the risk of device breakdown, and improves the mixing linearity and reliability.

[0027] Eight-phase non-overlapping local oscillator signal generator, such as Figure 3 As shown, it consists of a clock drive buffer, a frequency divider circuit, and an eight-phase non-overlapping clock generation circuit. The clock drive buffer employs a two-stage, two-way inverter amplification structure to generate two externally input clocks with a phase difference of 180° and a frequency of 4×f. LO The sinusoidal signal is shaped and pre-amplified into differential local oscillator drive signals LO+ and LO- with stable amplitude, 50% duty cycle, and complementary phase. The four-frequency divider circuit consists of four sets of cascaded differential D latches, which divide the input 4×f LO The local oscillator signal is down-frequencyed to the target frequency f. LO Then, an eight-phase non-overlapping clock generation circuit generates eight clocks with a duty cycle of 12.5%, an adjacent phase interval of 45°, and a frequency of f. LO The non-overlapping local oscillator signals LO1 to LO8 provide precise phase drive for the eight-channel passive mixer.

[0028] The gain-adjustable TIA employs a two-stage operational amplifier cascade structure in conjunction with, for example... Figure 6 The adjustable resistors shown enable wide-range gain adjustment. The first-stage operational amplifier primarily optimizes overall noise performance, achieving low-noise amplification; the second-stage operational amplifier is an impedance-matched buffer amplifier, decoupling the gain from the input impedance and ensuring stable input impedance across the entire gain range. A weighted summation circuit is incorporated at the output, consisting of multiple sets of common-source amplifiers with fixed current-source gain ratios, to perform weighted combining and output of multi-channel baseband signals.

[0029] In mixer-priority architectures, the receiver's RF input impedance is dominated by the input impedance of the back-end TIA (Transient Implant Array). Traditional TIAs exhibit a high dependence on feedback resistor parameters for both input impedance and gain, resulting in strong coupling between the two. In conventional designs, to reduce input equivalent noise, the input transistor employs a high transconductance design, leading to a small output equivalent resistance and a essentially fixed open-loop gain for the operational amplifier. This causes a significant synchronous shift in input impedance when the gain is changed by adjusting the feedback resistor, resulting in severe input matching degradation. This invention introduces an impedance matching buffer amplifier into the traditional amplification topology, decoupling the TIA's gain characteristics from its input impedance characteristics. This achieves adjustable gain while ensuring stable input impedance matching across the entire gain range, without sacrificing noise performance, effectively solving the performance trade-off problem of existing technologies.

[0030] In a preferred embodiment, the device of the present invention mainly includes an eight-phase non-overlapping local oscillator signal generator, four identical passive mixers (first passive mixer MX1, second passive mixer MX2, third passive mixer MX3, and fourth passive mixer MX4), four identical operational amplifiers (first operational amplifier A1, second operational amplifier A2, third operational amplifier A3, and fourth operational amplifier A4), and eight identical adjustable resistors (first adjustable resistor R...). F1 The second adjustable resistor R F2 The third adjustable resistor R F3 Fourth adjustable resistor R F4 Fifth adjustable resistor R F5 The sixth adjustable resistor R F6 The seventh adjustable resistor R F7 The eighth adjustable resistor R F8 ), eight identical capacitors (first capacitor C) F1 Second capacitor C F2 Third capacitor C F3 Fourth capacitor C F4 Fifth capacitor C F5 The sixth capacitor C F6 Seventh capacitor C F7 Eighth capacitor C F8 ) and six summing amplifiers with the same structure (first summing amplifier GM1, second summing amplifier GM2, third summing amplifier GM3, fourth summing amplifier GM4, fifth summing amplifier GM5, and sixth summing amplifier GM6).

[0031] The structure and connection methods of each component will be explained in detail below.

[0032] In the device of the present invention, such as Figure 1As shown, the RF input terminals of the first passive mixer MX1, the second passive mixer MX2, the third passive mixer MX3, and the fourth passive mixer MX4 are all connected to the input signal RF_IN. The LO input terminals of the first passive mixer MX1, the second passive mixer MX2, the third passive mixer MX3, and the fourth passive mixer MX4 are respectively connected to the output terminals of the eight-phase non-overlapping local oscillator signal generator.

[0033] In this embodiment, as Figure 1 As shown, the eight-phase non-overlapping local oscillator signal generator has two input terminals, which are external input differential signals LO+ and LO-, and eight output terminals, which are LO1, LO2, LO3, LO4, LO5, LO6, LO7, and LO8. The two LO input terminals of the first passive mixer MX1 ​​are connected to LO1 and LO5 respectively; the two LO input terminals of the second passive mixer MX2 are connected to LO2 and LO6 respectively; the two LO input terminals of the third passive mixer MX3 are connected to LO3 and LO7 respectively; and the two LO input terminals of the fourth passive mixer MX4 are connected to LO4 and LO8 respectively.

[0034] In the device of the present invention, such as Figure 1 As shown, the intermediate frequency output terminals of the first passive mixer MX1, the second passive mixer MX2, the third passive mixer MX3, and the fourth passive mixer MX4 are connected to the input terminals of the first operational amplifier A1, the second operational amplifier A2, the third operational amplifier A3, and the fourth operational amplifier A4, respectively.

[0035] Specifically, the two intermediate frequency (IF) outputs of the first passive mixer MX1 ​​are connected to the two inputs of the first operational amplifier A1, and the connections (i.e., signal lines) are named "IF_IN1+" and "IF_IN1-" respectively; the two IF outputs of the second passive mixer MX2 are connected to the two inputs of the second operational amplifier A2, and the connections are named "IF_IN2+" and "IF_IN2-" respectively; the two IF outputs of the third passive mixer MX3 are connected to the two inputs of the third operational amplifier A3, and the connections are named "IF_IN3+" and "IF_IN3-" respectively; and the two IF outputs of the fourth passive mixer MX4 are connected to the two inputs of the fourth operational amplifier A4, and the connections are named "IF_IN4+" and "IF_IN4-" respectively.

[0036] In the device of the present invention, such as Figure 1 As shown, each operational amplifier has an adjustable resistor and capacitor connected in parallel across its input and corresponding output terminals.

[0037] Specifically, the input terminal IF_IN1+ of the first operational amplifier A1 is connected to the first adjustable resistor R. F1 and the first capacitor CF1 One end is connected, and the output terminal IF_OUT1- is connected to the first adjustable resistor R. F1 and the first capacitor C F1 The other end is connected, and the input terminal IF_IN1- is connected to the second adjustable resistor R. F2 Second capacitor C F2 One end is connected, and the output terminal IF_OUT1+ is connected to the second adjustable resistor R. F2 Second capacitor C F2 The other end is connected; the input terminal IF_IN2+ of the second operational amplifier A2 is connected to the third adjustable resistor R. F3 and the third capacitor C F3 One end is connected, and the output terminal IF_OUT2- is connected to the third adjustable resistor R. F3 and the third capacitor C F3 The other end is connected, and the input terminal IF_IN2- is connected to the fourth adjustable resistor R. F4 and the fourth capacitor C F4 One end is connected, and the output terminal IF_OUT2+ is connected to the fourth adjustable resistor R. F4 and the fourth capacitor C F4 The other end is connected; the input terminal IF_IN3+ of the third operational amplifier A3 is connected to the fifth adjustable resistor R. F5 and the fifth capacitor C F5 One end is connected, and the output terminal IF_OUT3- is connected to the fifth adjustable resistor R. F5 and the fifth capacitor C F5 The other end is connected, and the input terminal IF_IN3- is connected to the sixth adjustable resistor R. F6 and the sixth capacitor C F6 One end is connected, and the output terminal IF_OUT3+ is connected to the sixth adjustable resistor R. F6 and the sixth capacitor C F6 The other end is connected; the input terminal IF_IN4+ of the fourth operational amplifier A4 is connected to the seventh adjustable resistor R. F7 and the seventh capacitor C F7 One end is connected, and the output terminal IF_OUT4- is connected to the seventh adjustable resistor R. F7 and the seventh capacitor C F7 The other end is connected; the input terminal IF_IN4- is connected to the eighth adjustable resistor R. F8 and the eighth capacitor C F8 One end is connected, and the output terminal IF_OUT4+ is connected to the eighth adjustable resistor R. F8 and the eighth capacitor C F8 The other end is connected.

[0038] In the device of the present invention, such as Figure 1As shown, the input terminals of the first, second, and third summing amplifiers are connected to the output terminals of the first, second, and third operational amplifiers, respectively, and the output terminals of the first, second, and third summing amplifiers converge to form an I-channel differential output; the input terminals of the fourth, fifth, and sixth summing amplifiers are connected to the output terminals of the second, third, and fourth operational amplifiers, respectively, and the output terminals of the fourth, fifth, and sixth summing amplifiers converge to form a Q-channel differential output.

[0039] Specifically, the two inputs of the first summing amplifier GM1 are connected to the two outputs IF_OUT1- and IF_OUT1+ of the first operational amplifier A1, respectively; the two inputs of the second summing amplifier GM2 are connected to the two outputs IF_OUT2- and IF_OUT2+ of the second operational amplifier A2, respectively; the two inputs of the third summing amplifier GM3 are connected to the two outputs IF_OUT3- and IF_OUT3+ of the third operational amplifier A3, respectively; the two inputs of the fourth summing amplifier GM4 are connected to the two outputs IF_OUT2- and IF_OUT2+ of the second operational amplifier A2, respectively; the two inputs of the fifth summing amplifier GM5 are connected to the two outputs IF_OUT3- and IF_OUT3+ of the third operational amplifier A3, respectively; and the two inputs of the sixth summing amplifier GM6 are connected to the two outputs of the fourth operational amplifier A2, respectively. The two output terminals IF_OUT4- and IF_OUT4+ of amplifier A4 are connected together; the three output terminals of the first summing amplifier GM1, the second summing amplifier GM2, and the third summing amplifier GM3, which are in phase with the input signal, are connected together and named "V_OUTI+"; the three output terminals of the first summing amplifier GM1, the second summing amplifier GM2, and the third summing amplifier GM3, which are in opposite phase with the input signal, are connected together and named "V_OUTI-"; the three output terminals of the fourth summing amplifier GM4, the fifth summing amplifier GM5, and the sixth summing amplifier GM6, which are in phase with the input signal, are connected together and named "V_OUTQ+"; the three output terminals of the fourth summing amplifier GM4, the fifth summing amplifier GM5, and the sixth summing amplifier GM6, which are in opposite phase with the input signal, are connected together and named "V_OUTQ-".

[0040] In this embodiment, as Figure 2 As shown, the passive mixer mainly includes two identical passive mixer NMOS transistors (first passive mixer NMOS transistor M1 and second passive mixer NMOS transistor M2) and two identical passive mixer resistors (first passive mixer resistor R). BIAS1 The second passive mixer resistor R BIAS2) and two identical passive mixer capacitors (the first passive mixer capacitor C) BIAS1 Second passive mixer capacitor C BIAS2 The connection methods for each component are as follows: The RF_IN terminal of the differential passive mixer is connected to the source of the first passive mixer NMOS transistor M1 and the source of the second passive mixer NMOS transistor M2; the resistor R of the first passive mixer... BIAS1 One end is connected to the bias voltage VBIAS, and the other end is connected to the gate of the first passive mixer NMOS transistor M1; the second passive mixer resistor R BIAS2 One end is connected to the bias voltage VBIAS, and the other end is connected to the gate of the second passive mixer NMOS transistor M2; the first passive mixer capacitor C BIAS1 One end is connected to the positive LO input terminal LO+, and the other end is connected to the gate of the first passive mixer NMOS transistor M1; the second passive mixer capacitor C BIAS2 One end is connected to the negative LO input terminal LO-, and the other end is connected to the gate of the second passive mixer NMOS transistor M2; the substrate of the first passive mixer NMOS transistor M1 and the substrate of the second passive mixer NMOS transistor M2 are connected to the substrate bias voltage SUB_BIAS; the drain of the first passive mixer NMOS transistor M1 is the positive intermediate frequency output terminal IF_IN+, and the drain of the second passive mixer NMOS transistor M2 is the negative intermediate frequency output terminal IF_IN-.

[0041] In this embodiment, as Figure 3 As shown, the eight-phase non-overlapping local oscillator signal generator mainly includes two identical clock drive buffers (first clock drive buffer BUF1 and second clock drive buffer BUF2), four identical D latches, and eight AND gates. The specific connection methods of each component are as follows: The positive terminal LO+ and the negative terminal LO- of the differential clock signal provided externally are connected to the input terminals of the first clock drive buffer BUF1 and the second clock drive buffer BUF2, respectively. The output terminal of the first clock drive buffer BUF1 is connected to the positive clock input terminal of the first D latch, the negative clock input terminal of the second D latch, the positive clock input terminal of the third D latch, and the negative clock input terminal of the fourth D latch, respectively. The output terminal of the second clock drive buffer BUF2 is connected to the negative clock input terminal of the first D latch, the positive clock input terminal of the second D latch, the negative clock input terminal of the third D latch, and the positive clock input terminal of the fourth D latch, respectively.

[0042] The positive output of the first D latch is connected to the positive input of the second D latch via a first positive signal line Q0. The negative output of the first D latch is connected to the negative input of the second D latch via a first negative signal line QN0. The positive output of the second D latch is connected to the positive input of the third D latch via a second positive signal line Q1. The negative output of the second D latch is connected to the negative input of the third D latch via a second negative signal line QN1. The positive output of the third D latch is connected to the positive input of the fourth D latch via a third positive signal line Q2. The negative output of the third D latch is connected to the negative input of the fourth D latch via a third negative signal line QN2. The positive output of the fourth D latch is connected to the negative input of the first D latch via a fourth positive signal line Q3. The negative output of the fourth D latch is connected to the positive input of the first D latch via a fourth negative signal line QN3.

[0043] The first positive signal line Q0, the first negative signal line QN0, the second positive signal line Q1, the second negative signal line QN1, the third positive signal line Q2, the third negative signal line QN2, the fourth positive signal line Q3, and the fourth negative signal line QN3 are clock signals with a duty cycle of 50% after being divided by four. They are processed by a clock logic processing circuit composed of eight AND gates to generate a non-overlapping 12.5% ​​duty cycle local oscillator signal, which is then connected to the two LO input terminals of each passive mixer in sequence.

[0044] Specifically, such as Figure 3 As shown, the first negative signal line QN0 and the second positive signal line Q1 are respectively connected to the two inputs of the first AND gate, outputting LO1; the second negative signal line QN1 and the third positive signal line Q2 are respectively connected to the two inputs of the second AND gate, outputting LO2; the third negative signal line QN2 and the fourth positive signal line Q3 are respectively connected to the two inputs of the third AND gate, outputting LO3; the fourth negative signal line QN3 and the first negative signal line QN0 are respectively connected to the two inputs of the fourth AND gate, outputting LO4; the first positive signal line Q0 and the second negative signal line QN1 are respectively connected to the two inputs of the fifth AND gate, outputting LO5; the second positive signal line Q1 and the third negative signal line QN2 are respectively connected to the two inputs of the sixth AND gate, outputting LO6; the third positive signal line Q2 and the fourth negative signal line QN3 are respectively connected to the two inputs of the seventh AND gate, outputting LO7; the fourth positive signal line Q3 and the first positive signal line Q0 are respectively connected to the two inputs of the eighth AND gate, outputting LO8. Through the above method, eight-phase local oscillator signals LO1, LO2, LO3, LO4, LO5, LO6, LO7 and LO8 are finally generated to control the duty cycle of the eight-channel passive mixer at 12.5%.

[0045] Specifically, such as Figure 4As shown, the clock drive buffer mainly consists of two identical clock drive buffer NMOS transistors (the first clock drive buffer NMOS transistor M...). N1 The second clock drive buffer NMOS transistor M N2 Two identical clock drive buffer PMOS transistors (the first clock drive buffer PMOS transistor M) P1 Second clock drive buffer PMOS transistor M P2 The system includes two identical clock drive buffer resistors (R1 and R2) and two identical clock drive buffer capacitors (C1 and C2). The specific connection methods for each component are as follows: The differential clock signal provided externally is input from the LO_IN port. One end of the first clock drive buffer capacitor C1 is connected to the LO_IN port, and the other end is connected to one end of the first clock drive buffer resistor R1 and the first clock drive buffer NMOS transistor M. N1 The gate of the first clock drive buffer PMOS transistor M P1 The gate of the first clock drive buffer is connected; the other end of the resistor R1 of the first clock drive buffer is connected to one end of the capacitor C2 of the second clock drive buffer and the NMOS transistor M of the first clock drive buffer. N1 The drain of the first clock drive buffer PMOS transistor M P1 The drain of the second clock drive buffer is connected; the other end of the capacitor C2 of the second clock drive buffer is connected to one end of the resistor R2 of the second clock drive buffer and the NMOS transistor M of the second clock drive buffer. N2 The gate, the second clock drive buffer PMOS transistor M P2 The gate of the second clock drive buffer is connected; the other end of the resistor R2 of the second clock drive buffer is connected to the gate of the second clock drive buffer NMOS transistor M. N2 The drain of the second clock drive buffer PMOS transistor M P2 The drain of the first clock drive buffer is connected to the output terminal LO_OUT of the clock drive buffer; the first clock drive buffer NMOS transistor M N1 The source and second clock drive buffer NMOS transistor M N2 The sources of all transistors are connected to ground (GND), and the first clock drive buffer PMOS transistor M... P1 The source and second clock drive buffer PMOS transistor M P2 The sources of all are connected to the power supply voltage V. DD .

[0046] Specifically, such as Figure 5As shown, the D latch includes four inverters with identical structures (first inverter INV1, second inverter INV2, third inverter INV3, and fourth inverter INV4) and four NMOS transistors with identical structures (first D latch NMOS transistor M). N11 The second D latch NMOS transistor M N21 The third D latch NMOS transistor M N31 The fourth D latch NMOS transistor M N41 Four identical D-latch PMOS transistors (the first D-latch PMOS transistor M) P11 The second D latch PMOS transistor M P21 The third D latch PMOS transistor M P31 The fourth D latch PMOS transistor M P41 The connection methods for each component are as follows: The positive clock signal CLKP is respectively connected to the first D latch NMOS transistor M N11 The gate and the third D latch NMOS transistor M N31 The gates of the first D latch NMOS transistor M are connected. N11 The source and the third D latch NMOS transistor M N31 The sources of all are connected to ground GND, and the first D latch NMOS transistor M N11 The drain of the second D latch NMOS transistor M N21 The source is connected to the third D latch NMOS transistor M. N31 The drain of the fourth D latch NMOS transistor M N41 The source is connected; the negative clock signal CLKN is connected to the PMOS transistor M of the second D latch. P21 The gate and the fourth D latch PMOS transistor M P41 The gate of the second D latch PMOS transistor M is connected. P21 The source and the fourth D latch PMOS transistor M P41 The sources are all connected to the ground terminal V. DD The second D latch PMOS transistor M P21 The drain of the first D latch PMOS transistor M P11 The source is connected to the fourth D latch PMOS transistor M. P41 The drain and the third D latch PMOS transistor M P31 The source is connected; the positive input signal DP is connected to the second D latch NMOS transistor M. N21 The gate and the first D latch PMOS transistor M P11 The gate of the second D latch is connected to the NMOS transistor M. N21 The drain of the second D latch PMOS transistor M P11The drain of the first inverter, the input of the first inverter INV1, the input of the second inverter INV2, and the output of the third inverter INV3 are connected. The output of the first inverter INV1 is connected to the positive output QP. The negative input signal DN is connected to the fourth D latch NMOS transistor M. N41 The gate and third D latch PMOS transistor M P31 The gates are connected, and the fourth D latch NMOS transistor M N41 The drain of the third D latch PMOS transistor M P31 The drain of the first inverter, the input of the fourth inverter INV4, the input of the third inverter INV3, and the output of the second inverter INV2 are connected. The output of the fourth inverter INV4 is connected to the negative output QN.

[0047] In this embodiment, as Figure 6 As shown, the adjustable resistor mainly consists of seven structurally identical adjustable NMOS transistors (the first adjustable NMOS transistor M...). 11 The second adjustable resistor NMOS transistor M 21 The third adjustable resistor NMOS transistor M 31 The fourth adjustable resistor NMOS transistor M 41 The fifth adjustable resistor NMOS transistor M 51 The sixth adjustable resistor NMOS transistor M 61 The seventh adjustable resistor NMOS transistor M 71 ), seven identical sub-resistors (the first sub-resistor R) 11 Second sub-resistor R 21 Third sub-resistor R 31 Fourth sub-resistor R 41 Fifth sub-resistor R 51 The sixth sub-resistor R 61 Seventh sub-resistor R 71 The connection methods for each component are as follows: The input terminal TIA_IN of the adjustable resistor is connected to the first adjustable resistor NMOS transistor M. 11 The drain of the NMOS transistor M, the second adjustable resistor 21 The drain of the NMOS transistor M, the third adjustable resistor 31 The drain of the NMOS transistor M, the fourth adjustable resistor 41 The drain of the NMOS transistor M, the fifth adjustable resistor 51 The drain of the NMOS transistor M, the sixth adjustable resistor 61 The drain and the seventh adjustable resistor of the NMOS transistor M 71 The drains are connected; the first sub-resistor R 11 One end is connected to the first adjustable resistor NMOS transistor M 11 The source of the transistor is connected to the source of the second adjustable resistor, and the other end is connected to the second adjustable resistor of the NMOS transistor M.21 The source is connected; the second sub-resistor R 21 One end is connected to the second adjustable resistor NMOS transistor M 21 The source of the transistor is connected to the source of the transistor, and the other end is connected to the third adjustable resistor, NMOS transistor M. 31 The source is connected; the third sub-resistor R 31 One end is connected to the third adjustable resistor NMOS transistor M 31 The source of one is connected to the other end, and the fourth adjustable resistor is connected to the NMOS transistor M. 41 The source is connected; the fourth sub-resistor R 41 One end is connected to the fourth adjustable resistor NMOS transistor M 41 The source of one is connected to the other end, and the other end is connected to the fifth adjustable resistor NMOS transistor M. 51 The source is connected; the fifth sub-resistor R 51 One end is connected to the fifth adjustable resistor NMOS transistor M 51 The source of the transistor is connected to the source of the transistor, and the other end is connected to the sixth adjustable resistor, NMOS transistor M. 61 The source is connected; the sixth sub-resistor R 61 One end is connected to the sixth adjustable resistor NMOS transistor M 61 The source of one is connected to the other end, and the other end is connected to the seventh adjustable resistor NMOS transistor M. 71 The source terminals are connected; the seventh sub-resistor R 71 One end is connected to the seventh adjustable resistor NMOS transistor M 71 The source of one transistor is connected to the other end, which is the output terminal TIA_OUT of an adjustable resistor; the first control signal CT1 is connected to the first adjustable resistor NMOS transistor M. 11 The gate of the NMOS transistor is connected, and the second control signal CT2 is connected to the second adjustable resistor M. 21 The gate of the NMOS transistor is connected, and the third control signal CT3 is connected to the third adjustable resistor M. 31 The gate of the NMOS transistor is connected, and the fourth control signal CT4 is connected to the fourth adjustable resistor M. 41 The gate of the NMOS transistor is connected, and the fifth control signal CT5 is connected to the fifth adjustable resistor M. 51 The gate of the NMOS transistor is connected, and the sixth control signal CT6 is connected to the sixth adjustable resistor M. 61 The gate of the NMOS transistor is connected, and the seventh control signal CT7 is connected to the seventh adjustable resistor M. 71 The gates are connected. Control signals CT1, CT2, CT3, CT4, CT5, CT6, and CT7 are used to adjust the resistance value of the adjustable resistor.

[0048] In this embodiment, as Figure 8 As shown, the operational amplifier mainly includes six identical operational amplifier resistors (the first operational amplifier resistor R...). 12 The second operational amplifier resistor R 22 The third operational amplifier resistor R32 Fourth operational amplifier resistor R 42 Fifth operational amplifier resistor R 52 6th operational amplifier resistor R 62 Two operational amplifier capacitors with identical structures (first operational amplifier capacitor C) 11 Second operational amplifier capacitor C 21 Four identical operational amplifier NMOS transistors (the first operational amplifier NMOS transistor M) N12 The second operational amplifier NMOS transistor M N22 The third operational amplifier NMOS transistor M N32 Fourth operational amplifier NMOS transistor M N42 Five identical operational amplifier PMOS transistors (the fifth operational amplifier PMOS transistor M) PB The first operational amplifier PMOS transistor M P12 The second operational amplifier PMOS transistor M P22 The third operational amplifier PMOS transistor M P32 The fourth operational amplifier PMOS transistor M P42 ), sub-amplifier (amplifier A). The specific connection methods for each component are as follows: The positive input signal IN+ and the first operational amplifier PMOS transistor M P12 The gate of the second operational amplifier PMOS transistor is connected, and the negative input signal IN- is connected to the gate of the second operational amplifier PMOS transistor M. P22 The gate of the first operational amplifier PMOS transistor M is connected to the gate of the first operational amplifier. P12 The source of the second operational amplifier PMOS transistor M P22 The source of the fifth operational amplifier PMOS transistor M PB The drains are connected; the fifth operational amplifier PMOS transistor M PB Gate and bias voltage V B,P Connected, source connected to power supply voltage V DD The first operational amplifier PMOS transistor M P12 The drain of the first operational amplifier NMOS transistor M N12 The drain of the first operational amplifier, resistor R 12 One end, the second operational amplifier capacitor C 21 One end is connected to the fourth operational amplifier NMOS transistor M N42 The gate of the second operational amplifier PMOS transistor is connected to the gate of the second operational amplifier. P22 The drain of the second operational amplifier NMOS transistor M N22 The drain of the second operational amplifier, resistor R 22 One end, the first operational amplifier capacitor C 11 One end is connected to the third operational amplifier NMOS transistor M N32The gate is connected, and the first operational amplifier resistor R 12 At the other end, the second operational amplifier resistor R 22 At the other end, the first operational amplifier NMOS transistor M N12 The gate of the second operational amplifier NMOS transistor M N22 The gates of the first operational amplifier NMOS transistor M are connected. N12 The source of the second operational amplifier NMOS transistor M N22 The source of the third operational amplifier NMOS transistor M N32 The source of the fourth operational amplifier NMOS transistor M N42 The sources of all three operational amplifier transistors are connected to ground (GND); the third operational amplifier NMOS transistor M... N32 The drain of the third operational amplifier, resistor R 32 One end, resistor R of the fifth operational amplifier 52 One end, the third operational amplifier PMOS transistor M P32 The drain of the first operational amplifier is connected to the negative output terminal OUT-, and the capacitor C of the first operational amplifier is connected to the negative output terminal OUT-. 11 The other end is connected to the third operational amplifier resistor R. 32 The other end is connected to the fourth operational amplifier NMOS transistor M. N42 The drain of the fourth operational amplifier, resistor R 42 One end, the sixth operational amplifier resistor R 62 One end, the fourth operational amplifier PMOS transistor M P42 The drain of the second operational amplifier is connected to the positive output terminal OUT+, and the capacitor C of the second operational amplifier is connected to the positive output terminal OUT+. 21 The other end is connected to the fourth operational amplifier resistor R. 42 The other end is connected to the resistor R of the fifth operational amplifier. 52 At the other end, the sixth operational amplifier resistor R 62 The other end is connected to the positive input terminal of the sub-amplifier (amplifier A), with a reference voltage V. REF The third operational amplifier PMOS transistor M is connected to the negative input terminal of the sub-amplifier (amplifier A). P32 The gate of the fourth operational amplifier PMOS transistor M P42 The gate of the third operational amplifier is connected to the output of the sub-amplifier (amplifier A), and the PMOS transistor M is connected to the output of the sub-amplifier. P32 The source of the fourth operational amplifier PMOS transistor M P42 The sources of all are connected to the power supply voltage V. DD .

[0049] In this embodiment, as Figure 10 As shown, the summing amplifier mainly consists of two NMOS transistors with identical structures (the first NMOS transistor M). N13The second summation amplifier NMOS transistor M N23 Two identical summing amplification PMOS transistors (the first summing amplification PMOS transistor M) P13 The second summation amplifier PMOS transistor M P23 Two identical summing amplification resistors (the first summing amplification resistor R) 13 The second summation amplification resistor R 23 ).

[0050] The positive input signal IN+ and the first summing amplifier NMOS transistor M N13 The gate of the transistor is connected, and the negative input signal IN- is connected to the gate of the second summing amplifier NMOS transistor M. N23 The gates are connected, and the first summing amplifier NMOS transistor M... N13 The source and the second summation amplifier NMOS transistor M N23 The sources of all transistors are connected to ground (GND). The first summing amplifier NMOS transistor M... N13 The drain of the first summation amplifier PMOS transistor M P13 The drain, the first summing amplification resistor R 13 One end is connected to the negative output terminal OUT-, and the second summing amplifier NMOS transistor M N23 The drain of the second summing amplifier PMOS transistor M P23 The drain, the second summing amplification resistor R 23 One end is connected to the positive output terminal OUT+, and the first summing amplification resistor R 13 The other end, the second summing amplification resistor R 23 At the other end, the first summing amplification PMOS transistor M P13 The gate of the second summing amplifier PMOS transistor M P23 The gates are connected, and the first summing amplifier PMOS transistor M... P13 The source and the second summation amplifier PMOS transistor M P23 The sources of all are connected to the power supply voltage V. DD .

[0051] This invention proposes a mixer-priority architecture receiver with wide-range gain adjustability, adaptable to complex communication scenarios with large fluctuations in input signal power, and achieving a large dynamic range of reception. The mixer-priority architecture receiver proposed in this invention can maintain near-stable RF input matching across the entire gain adjustment range, solving the problem of the inability to simultaneously achieve gain adjustment and input matching in traditional mixer-priority receivers, without degrading the overall noise performance, thus adding an independent degree of freedom for receiver design. This invention adds an impedance matching buffer inside the gain-adjustable transimpedance amplifier, decoupling gain and input impedance between the operational amplifier and the feedback resistor. It employs a two-stage operational amplifier split-function TIA topology: the first stage operational amplifier optimizes noise performance, while the second stage is an impedance matching buffer amplifier used to stabilize the input impedance. Combined with a series of switched resistors, it achieves wide-range gain control, eliminating the need for performance trade-offs among low noise, gain adjustability, and stable matching.

[0052] The device and performance effects of the present invention will be specifically described below through examples.

[0053] Example

[0054] This embodiment provides a gain-adjustable mixer-priority receiver with stable input matching. Its basic working principle is as follows: Figure 1 As shown. This embodiment of the variable gain mixer-priority RF receiver comprises an adjustable bias 8-path passive mixer, an adjustable gain baseband TIA with common-mode negative feedback, a clock drive buffer, and an eight-phase non-overlapping clock generator. RF_IN is the RF input signal, and its modulation signal center frequency is f. LO +f BB (f) BB <Baseband bandwidth); After the RF_IN radio frequency input signal enters, it first passes through an 8-path adjustable bias passive mixer. MX1, MX2, MX3, and MX4 are four differential mixers that convert the frequency f to f. LO +f BB The radio frequency signal is down-converted to frequency f BB Low-frequency or baseband signals, combined with bias resistor R BIAS With bias capacitor C BIAS The mixer is biased; after downconversion, the RF signal is converted into a baseband signal, and the weak baseband signal is amplified by TIA; finally, the eight baseband signals are summed by a weighted summation circuit according to a certain ratio, and four differential quadrature baseband signals I+, I-, Q+, and Q- are output.

[0055] Among them, mixers such as Figure 2As shown, its RF input signal RF_IN is a single-ended signal, the local oscillator input signals LO+ and LO- are differential input signals, and the down-conversion output signals IF_IN+ and IF_IN- are differential output signals. The gate bias voltage and substrate bias voltage of the first passive mixer NMOS transistor M1 and the second passive mixer NMOS transistor M2 are provided separately to avoid breakdown.

[0056] Among them, the eight-phase non-overlapping local oscillator signal generator is as follows: Figure 3 As shown, it is implemented using a clock-driven buffer, four D latches connected end-to-end, and eight AND gates. It connects LO+ and LO-, two latches with a 50% duty cycle, a 180° phase difference, and a frequency of f. LO The square wave signal output has a duty cycle of 12.5%, a phase difference of 45°, and a frequency of 4×f. LO The input local oscillator signal is used; the clock drive buffer employs a two-stage inverter structure for step-by-step driving, providing high-drive local oscillator signals LO1, LO2, LO3, LO4, LO5, LO6, LO7, and LO8 for the adjustable bias passive mixer. The clock drive buffer is as follows... Figure 4 As shown, the D latch is as follows Figure 5 As shown.

[0057] The gain of TIA is adjusted as follows: Figure 6 The adjustable resistor shown is implemented by an adjustable resistor NMOS transistor M. 11 M 21 M 31 M 41 M 51 M 61 M 71 And sub-resistance R 11 R 21 R 31 R 41 R 51 R 61 R 71 Composition. The adjustable resistor NMOS transistor is controlled by control signals CT1, CT2, CT3, CT4, CT5, CT6, and CT7. When the control signal is 0 V, the adjustable resistor NMOS transistor is off; when the control signal is 1.2 V, the adjustable resistor NMOS transistor is on. M 11 M 21 M 31 M 41 M 51 M 61 M 71 When fully conducting, the adjustable resistor has its minimum resistance, R. 71 Disconnect M sequentially 71 M 61 M 51 M41 M 31 M 21 M 11 The adjustable resistance value gradually increases, when M 71 M 61 M 51 M 41 M 31 M 21 M 11 When all switches are disconnected, the adjustable resistor value reaches its maximum value R. 71 + R 61 + R 51 + R 41 + R 31 + R 21 + R 11 .

[0058] The above modules work together to form a complete mixer-priority receiver system, which can perform down-conversion and amplification of the effective RF input signal, and achieve wide-range adjustable gain. It maintains stable input impedance matching characteristics throughout the gain adjustment process, and the overall noise performance of the unit will not deteriorate.

[0059] Figure 7 This is a simplified model of the mixer-first architecture receiver used in this embodiment, where R s R is the source impedance. sw C is the on-resistance of the switching mixer. L R is the load capacitance. B Given the input impedance of TIA, LON is an equivalent ideal switch, and its corresponding eight-phase non-overlapping LO signals LO1, LO2, LO3, LO4, LO5, LO6, LO7, and LO8 with a duty cycle of 12.5% ​​and a phase difference of 45° are as follows: Figure 8 As shown. Figure 9 It is a linear time-invariant model of a noisy mixer-first architecture receiver, where, This is the thermal noise voltage source corresponding to the source impedance. R is the thermal noise voltage source corresponding to the on-resistance of the switching mixer. sh For parallel equivalent harmonic loss resistors, For its corresponding thermal noise voltage source, kR B The impedance is the baseband impedance mapped to the RF input port, and k is the scaling factor. This corresponds to its thermal noise voltage source. Reaching C L The signal at that point is the down-converted signal with a frequency of ω. IF =ω RF - ω LO , where ω RF ω is the frequency of the radio frequency input signal. LOThis is the LO frequency. For in-band signals, the load capacitance C... L The capacitive reactance is approximately infinite, and R B The impedance value of parallel circuits is still approximately R. B At this time, the receiver's input impedance R in The expression for R is shown in formula (1), and the expression for the noise figure F is shown in formula (2). When the mixer path is four-way, R sh The value is 150 Ω. When the mixer has eight paths, R sh The value of Ω is 450 Ω, at which point the receiver has a lower noise figure. To achieve better noise performance, R... sw The value of R is usually small, generally around 10 Ω, at which point R sh ||kR BB A 40 Ω input impedance is required, and R sh >>40 Ω, therefore kR is required BB Approximately 40 Ω is needed to achieve a 50 Ω input impedance. At this point, R... in By kR BB leading.

[0060] ;

[0061] ;

[0062] Under the constraint of a low supply voltage of 1.2 V in advanced CMOS processes, the output voltage swing of op-amps in TIAs is significantly limited. To obtain a sufficient voltage swing under low supply conditions, a five-transistor OTA structure or an inverter structure is typically selected. The voltage gain of this type of op-amp can be expressed as G. m,eq ·r o,eq G m,eq For equivalent transconductance, r o,eq = r o,N ||r o,P This represents the equivalent output impedance of the operational amplifier. In a typical TIA structure, A... v =G m,eq ·r o,eq ||R F >>1 represents the open-loop gain of the op-amp, R F For feedback resistors. The gain A of a traditional TIA. TIA,conv and input impedance R B,conv The expressions are shown in formulas (3) and (4).

[0063] ;

[0064] ;

[0065] In the formula, Gm1 It is the equivalent transconductance of the operational amplifier, r o1,eq It is the equivalent output impedance of the op-amp.

[0066] Figure 9 The noise model shown only considers the thermal noise contribution of the passive resistor. In fact, the channel thermal noise of the TIA input amplifier transistor referred to the gate also contributes to the receiver's noise figure. The transistor channel thermal noise current spectral density is γ4kTg. m The equivalent noise voltage referred to the input terminal can be expressed as γ4kT / g m To achieve low noise performance, a larger g is required. m Therefore, in Mixer-First receiver architectures, the TIA typically requires tens of milliamps of current. This is due to the intrinsic gain g of the MOSFET. m r o The equivalent output resistance is approximately constant under high operating current and satisfies r. o,eq < <R F At this point, formula (4) can be approximated as R F / G m1 ·r o1,eq At this point, if the gain R of TIA is adjusted... F The input impedance will also change proportionally.

[0067] The operational amplifier in the TIA used in this embodiment is as follows: Figure 10 As shown, compared to the traditional structure, the output stage adds an impedance matching buffer amplifier, which allows the TIA to achieve a gain R... F While offering a wide adjustable range, the input impedance remains approximately constant. This impedance-matched buffer amplifier employs a small DC bias current design, and its equivalent transconductance G... m2 The effective output resistance (r) is relatively small. Thanks to the near-constant intrinsic gain of the MOSFET, the impedance-matched buffer amplifier can achieve a larger effective output resistance (r). o,eq2 Satisfying r o,eq2 >>R F At this point, the open-loop gain of the op-amp becomes G. m1 ·r o1,eq ·G m2 ·(r o2,eq ||R F )>>1. Under this architecture, the gain A of the TIA proposed in this embodiment TIA,prop and impedance R B,prop The expressions are shown in formulas (5) and (6).

[0068] ;

[0069] ;

[0070] In the formula, Gm2 It is the equivalent transconductance of the impedance-matched buffer amplifier, r o2,eq It is the equivalent output impedance of the impedance-matched buffer amplifier.

[0071] Equations (5) and (6) show that the gain of TIA in the structure proposed in this embodiment is still R. F However, the input impedance expression no longer includes R. F This achieves decoupling of gain and input impedance, which can be achieved by adjusting R. F Flexible TIA gain configuration while maintaining stable input impedance. Although the noise referred to the input of the impedance-matched buffer amplifier under a small bias current design is relatively large, this noise source is suppressed by the gain of the preamplifier. At the same time, its noise component is not directly mapped to the RF input, so its contribution to the overall system noise is limited and will not significantly worsen the receiver's noise figure.

[0072] Before and after adding the impedance matching buffer amplifier, the impedance kR mapped from the TIA to the RF input port B With R F The simulation comparison results of the changes are as follows Figure 11 As shown in the simulation curves, without the introduction of an impedance matching buffer amplifier, kR B With R F The decrease is approximately proportional to the reduction. After introducing an impedance-matched buffer amplifier, even if R is adjusted... F Change the TIA gain, kR B It can still remain basically stable.

[0073] The outputs of the four TIA channels are summed using a summing amplifier, resulting in four differential quadrature baseband signals: I+, I-, Q+, and Q-. The summing amplifier is as follows: Figure 12 As shown.

[0074] The proposed TIA has a gain adjustment step of approximately 6 dB. The first-stage amplifier in the TIA uses an OTA structure, while the second stage is a common-source amplifier with a current mirror load. The first stage employs a high-current bias to obtain a high equivalent transconductance G. m1 This optimizes the receiver's noise performance; the second stage uses a small current bias to reduce r o,eq2 >>R F This achieves stable input impedance across the entire gain range. Furthermore, an RC negative feedback structure is introduced into the impedance matching buffer amplifier to further enhance the closed-loop stability of the circuit.

[0075] Figure 13The figure shows the simulation results of receiver gain and noise figure as a function of control word when the LO frequency is 433MHz. When the control word is adjusted from 6 to 0, the gain decreases from 43dB to 8dB, while the noise factor (NF) increases from 4.2dB to 25.1dB. The gain decreases by 35dB and the NF increases by 20.9dB. Figure 14 The simulation results of NF, gain, and S11 as a function of LO frequency are shown in the maximum gain mode. The gain is 42.5~43dB, the minimum NF is 4dB, and S11 is always less than -20dB. Figure 15 The simulation results of IIP3 and OIP3 with gain at an LO frequency of 433MHz are shown. As the gain decreases from 43dB to 8dB, IIP3 increases from -26dBm to 12.4dBm, while OIP3 ranges from 17.2 to 19.6dB. When the gain decreases by 35dB, IIP3 increases by 38.4dBm, while OIP3 remains basically unchanged.

[0076] This invention achieves adjustable gain while maintaining the receiver's original low noise and high linearity performance. Furthermore, the input matching characteristics remain stable across the entire gain adjustment range, effectively solving the technical challenge of balancing gain adjustment and input matching performance in traditional architectures. This significantly improves the dynamic reception range and scene adaptability of the Mixer-First receiver.

[0077] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, all technical solutions obtained through equivalent substitution or transformation fall within the protection scope of the present invention.

Claims

1. A gain-adjustable mixer-priority receiver with stable input matching, characterized in that, It includes an eight-phase non-overlapping local oscillator signal generator, four passive mixers with the same structure, four operational amplifiers with the same structure, eight adjustable resistors with the same structure, eight capacitors with the same structure, and six summing amplifiers with the same structure. Each of the passive mixers has its radio frequency input terminal connected to the input signal, its two LO input terminals connected to the output terminals of the eight-phase non-overlapping local oscillator signal generator, and its two intermediate frequency output terminals connected to the two input terminals of the corresponding operational amplifier. Each operational amplifier has a corresponding adjustable resistor and a capacitor connected in parallel across its input and corresponding output terminals. The input terminals of the first summing amplifier, the second summing amplifier, and the third summing amplifier are respectively connected to the output terminals of the first operational amplifier, the second operational amplifier, and the third operational amplifier. The output terminals of the first summing amplifier, the second summing amplifier, and the third summing amplifier converge to form an I-channel differential output. The input terminals of the fourth, fifth, and sixth summation amplifiers are connected to the output terminals of the second, third, and fourth operational amplifiers, respectively. The output terminals of the fourth, fifth, and sixth summation amplifiers converge to form a Q-channel differential output. The operational amplifier includes a low-noise operational amplifier and an impedance matching buffer amplifier; the differential input signal is connected to the differential input terminal of the low-noise operational amplifier, the differential output terminal of the low-noise operational amplifier is connected to the differential input terminal of the impedance matching buffer amplifier, and the differential output terminal of the impedance matching buffer amplifier is the differential output terminal of the entire operational amplifier.

2. The input-matched, gain-adjustable mixer priority receiver according to claim 1, characterized in that, The passive mixer includes two identical passive mixer NMOS transistors, two identical passive mixer resistors, and two identical passive mixer capacitors. The sources of both passive mixer NMOS transistors are connected to the RF input terminal, and the substrates of both are connected to the substrate bias voltage. Each passive mixer resistor has one end connected to the bias voltage and the other end connected to the gate of the corresponding passive mixer NMOS transistor. Each passive mixer capacitor has one end connected to the gate of the corresponding passive mixer NMOS transistor and the other end connected to the positive LO input terminal and the negative LO input terminal, respectively. The drain of the passive mixer NMOS transistor corresponding to the positive LO input terminal is the positive intermediate frequency output terminal, and the drain of the passive mixer NMOS transistor corresponding to the negative LO input terminal is the negative intermediate frequency output terminal.

3. The input-matched, gain-adjustable mixer priority receiver according to claim 1, characterized in that, The eight-phase non-overlapping local oscillator signal generator includes two identical clock drive buffers, four identical D latches, and eight AND gates. The positive and negative terminals of the differential clock signal provided from outside the chip are connected to the input terminals of the first clock drive buffer and the second clock drive buffer, respectively. The output terminals of the first clock drive buffer and the second clock drive buffer are cross-coupled to the clock control terminals of each D latch to provide complementary clock control signals. Each D latch is cascaded sequentially along the signal transmission direction, and the differential output of the last D latch is fed back and coupled to the differential input of the first D latch, forming a ring shift register structure, which is used to perform frequency division and phase shifting processing on the differential clock signal, and generate multiple differential intermediate signals at the signal transmission nodes of each adjacent stage. The differential intermediate signals at each signal transmission node are processed by a clock logic circuit composed of eight AND gates to generate a non-overlapping 12.5% ​​duty cycle local oscillator signal, which is then connected sequentially to the two LO input terminals of each passive mixer.

4. The input-matched, gain-adjustable mixer priority receiver according to claim 3, characterized in that, The two inputs of the first AND gate are connected to the first negative signal line and the second positive signal line, respectively. The two inputs of the second AND gate are connected to the second negative signal line and the third positive signal line, respectively. The two inputs of the third AND gate are connected to the third negative signal line and the fourth positive signal line, respectively. The two inputs of the fourth AND gate are connected to the fourth negative signal line and the first negative signal line, respectively. The two inputs of the fifth AND gate are connected to the first positive signal line and the second negative signal line, respectively. The two inputs of the sixth AND gate are connected to the second positive signal line and the third negative signal line, respectively. The two inputs of the seventh AND gate are connected to the third positive signal line and the fourth negative signal line, respectively. The two inputs of the eighth AND gate are connected to the fourth positive signal line and the first positive signal line, respectively. The outputs of the first and fifth AND gates are connected to the two LO inputs of the first passive mixer, respectively. The outputs of the second and sixth AND gates are connected to the two LO inputs of the second passive mixer, respectively. The outputs of the third and seventh AND gates are connected to the two LO inputs of the third passive mixer, respectively. The outputs of the fourth and eighth AND gates are connected to the two LO inputs of the fourth passive mixer, respectively.

5. A gain-adjustable mixer priority receiver with stable input matching according to claim 3, characterized in that, The clock drive buffer includes two identical clock drive buffer NMOS transistors, two identical clock drive buffer PMOS transistors, two identical clock drive buffer resistors, and two identical clock drive buffer capacitors. One end of the first clock drive buffer capacitor is connected to the differential clock signal provided externally, and the other end is connected to one end of the first clock drive buffer resistor, the gate of the first clock drive buffer NMOS transistor, and the gate of the first clock drive buffer PMOS transistor, respectively. The other end of the first clock drive buffer resistor is connected to one end of the second clock drive buffer capacitor, the drain of the first clock drive buffer NMOS transistor, and the drain of the first clock drive buffer PMOS transistor, respectively. The other end of the second clock drive buffer capacitor is connected to one end of the second clock drive buffer resistor, the gate of the second clock drive buffer NMOS transistor, and the gate of the second clock drive buffer PMOS transistor, respectively. The other end of the second clock drive buffer resistor is connected to the drain of the second clock drive buffer NMOS transistor and the drain of the second clock drive buffer PMOS transistor, respectively, and serves as the output terminal of the clock drive buffer. The sources of both the first clock drive buffer NMOS transistor and the second clock drive buffer NMOS transistor are connected to the ground terminal, and the sources of both the first clock drive buffer PMOS transistor and the second clock drive buffer PMOS transistor are connected to the power supply voltage.

6. The input-matched, gain-adjustable mixer priority receiver according to claim 3, characterized in that, The D latch includes four inverters with the same structure, four NMOS transistors with the same structure, and four PMOS transistors with the same structure. The positive clock signal is connected to the gates of the first D latch NMOS transistor and the third D latch NMOS transistor respectively. The sources of the first D latch NMOS transistor and the third D latch NMOS transistor are both connected to the ground terminal. The drain of the first D latch NMOS transistor is connected to the source of the second D latch NMOS transistor, and the drain of the third D latch NMOS transistor is connected to the source of the fourth D latch NMOS transistor. The negative clock signal is connected to the gates of the second D latch PMOS transistor and the fourth D latch PMOS transistor respectively. The sources of the second D latch PMOS transistor and the fourth D latch PMOS transistor are both connected to the ground terminal. The drain of the second D latch PMOS transistor is connected to the source of the first D latch PMOS transistor, and the drain of the fourth D latch PMOS transistor is connected to the source of the third D latch PMOS transistor. The positive input signal is connected to the gates of the second D latch NMOS transistor and the first D latch PMOS transistor respectively. The drain of the second D latch NMOS transistor, the drain of the second D latch PMOS transistor, the input terminal of the first inverter, the input terminal of the second inverter, and the output terminal of the third inverter are connected. The output terminal of the first inverter is connected to the positive output terminal. The negative input signal is connected to the gates of the fourth D latch NMOS transistor and the third D latch PMOS transistor, respectively. The drain of the fourth D latch NMOS transistor, the drain of the third D latch PMOS transistor, the input of the fourth inverter, the input of the third inverter, and the output of the second inverter are connected. The output of the fourth inverter is connected to the negative output.

7. A gain-adjustable mixer priority receiver with stable input matching according to claim 1, characterized in that, The adjustable resistor includes seven NMOS transistors with identical structures and seven sub-resistors with identical structures; The input terminals of the adjustable resistors are connected to the drains of the seven adjustable NMOS transistors, respectively. One end of the first sub-resistor is connected to the source of the first adjustable resistor NMOS transistor, and the other end is connected to the source of the second adjustable resistor NMOS transistor; one end of the second sub-resistor is connected to the source of the second adjustable resistor NMOS transistor, and the other end is connected to the source of the third adjustable resistor NMOS transistor; one end of the third sub-resistor is connected to the source of the third adjustable resistor NMOS transistor, and the other end is connected to the source of the fourth adjustable resistor NMOS transistor; one end of the fourth sub-resistor is connected to the source of the fourth adjustable resistor NMOS transistor, and the other end is connected to the source of the fifth adjustable resistor NMOS transistor; one end of the fifth sub-resistor is connected to the source of the fifth adjustable resistor NMOS transistor, and the other end is connected to the source of the sixth adjustable resistor NMOS transistor; one end of the sixth sub-resistor is connected to the source of the sixth adjustable resistor NMOS transistor, and the other end is connected to the source of the seventh adjustable resistor NMOS transistor; one end of the seventh sub-resistor is connected to the source of the seventh adjustable resistor NMOS transistor, and the other end is the output terminal of the adjustable resistor. The control signals are connected to the gates of the seven adjustable resistor NMOS transistors to adjust the resistance values ​​of the adjustable resistors.

8. A gain-adjustable mixer priority receiver with stable input matching according to claim 1, characterized in that, The summing amplifier includes two NMOS transistors with identical structures, two PMOS transistors with identical structures, and two resistors with identical structures. The positive input signal is connected to the gate of the first summing amplification NMOS transistor, and the negative input signal is connected to the gate of the second summing amplification NMOS transistor. The sources of both the first and second summing amplification NMOS transistors are connected to ground. The drains of the first summing amplification NMOS transistor, the drains of the first summing amplification PMOS transistor, and one end of the first summing amplification resistor are connected to the negative output terminal. The drains of the second summing amplification NMOS transistor, the drains of the second summing amplification PMOS transistor, and one end of the second summing amplification resistor are connected to the positive output terminal. The other end of the first summing amplification resistor, the other end of the second summing amplification resistor, and the gate of the first summing amplification PMOS transistor are connected to the gate of the second summing amplification PMOS transistor. The sources of both the first and second summing amplification PMOS transistors are connected to the power supply voltage.

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