Wireless memory interface array, transmit circuit, receive circuit for 3D stacked memory chips

Abstract

The application provides a wireless memory interface array, a transmitting circuit and a receiving circuit for a 3D stacked memory chip, the wireless memory interface array comprising a first memory chip and a second memory chip, the first memory chip being integrated with a transmitting circuit and a transmitting coil, and the second memory chip being integrated with a receiving circuit and a receiving coil; the transmitting circuit being connected with the transmitting coil; the transmitting coil being magnetically coupled with the receiving coil; the receiving circuit being connected with the receiving coil, demodulating a modulated signal, recovering baseband data and transmitting the baseband data to the second memory chip; wherein the transmitting circuit generates a carrier wave in a millimeter wave frequency band by using an LC oscillator and modulates the baseband data, realizes wireless transmission through magnetic coupling and improves chip area utilization efficiency; meanwhile, the baseband signal is modulated onto a high-frequency carrier wave, the anti-interference ability to power noise is enhanced, and high-density and high-speed wireless interconnection between 3D stacked chips is realized.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and in particular to a wireless memory interface array, transmitting circuit, and receiving circuit for 3D stacked memory chips. Background Technology

[0002] AI training, inference chips, GPUs, and high-performance CPUs all require large-capacity, high-bandwidth memory to process large amounts of data. However, due to area limitations, a single memory chip often cannot meet the demand. Therefore, some solutions use 3D stacking technology to vertically interconnect multiple memory chips. This architecture requires high-density, high-speed inter-chip interface technology.

[0003] For chip-to-chip interface technology, one approach is to achieve vertical interconnection between chips based on through-silicon vias (TSVs), which requires fabricating metal vias that penetrate the substrate on the chip; another approach is to use baseband pulse through-chip interfaces, which utilize coil coupling to transmit narrow pulse baseband signals.

[0004] However, the aforementioned through-silicon via (TSV) technology requires additional process steps, the via layout encroaches on chip area leading to increased manufacturing costs, and the baseband pulse transmission is sensitive to power supply noise, which can easily cause data errors. None of these technologies can achieve high-density, high-speed wireless interconnection between 3D stacked chips. Summary of the Invention

[0005] This application provides a wireless memory interface array, transmitting circuit, and receiving circuit for 3D stacked memory chips to solve the problem of not being able to achieve high-density, high-speed wireless interconnection between 3D stacked chips.

[0006] In a first aspect, this application provides a wireless memory interface array for a 3D stacked memory chip, comprising: At least one first memory chip integrates a transmitting circuit and a transmitting coil; At least one second memory chip, which integrates a receiving circuit and a receiving coil; The transmitting circuit is connected to the transmitting coil and is configured to: generate a millimeter-wave frequency carrier using an LC oscillator, and modulate the carrier in response to baseband data to generate a modulated signal; The transmitting coil is magnetically coupled to the receiving coil, and is used to transmit the modulated signal to the receiving coil; The receiving circuit is connected to the receiving coil and is configured to demodulate the modulated signal to recover the baseband data and transmit it to the second memory chip.

[0007] In some feasible embodiments, the transmitting circuit further includes a carrier generation circuit, which, together with the transmitting coil, constitutes an LC oscillator; The carrier generation circuit includes a cross-coupled pair of transistors connected to the transmitting coil and configured to control the oscillation state of the LC oscillator to a target oscillation state.

[0008] In some feasible embodiments, the transmitting circuit further includes a modulation circuit connected to the carrier generation circuit; The modulation circuit is configured to: control the operating state of the carrier generation circuit in response to the baseband data, and modulate the baseband data onto the carrier.

[0009] In some feasible embodiments, the modulation circuit includes a first tail current source and a second tail current source connected in parallel; The first tail current source is controlled by a bias voltage and is configured to provide a current to the carrier generation circuit to sustain oscillation. The second tail current source is controlled by the baseband data and is configured to: turn on when the baseband data is signal 1, controlling the LC oscillator to be in a first swing state; and turn off when the baseband data is signal 0, controlling the LC oscillator to be in a second swing state, so as to modulate the baseband data onto the carrier.

[0010] In some feasible embodiments, the receiving circuit includes a self-mixing circuit connected to the receiving coil and configured to mix the modulation signal with itself to extract the baseband envelope and recover the baseband data.

[0011] In some feasible embodiments, the receiving circuit further includes a sampling circuit and an output driving circuit; The sampling circuit is connected to the self-mixing circuit, the output driving circuit is connected to the sampling circuit, and the sampling circuit is configured to sample the demodulated signal. The output drive circuit is configured to: shape and amplify the sampled signal to output baseband data in digital form.

[0012] In some feasible embodiments, the transmitting coil and the receiving coil are arranged vertically; The number of transmitting coils and receiving coils is multiple, and the multiple transmitting coils and multiple receiving coils constitute a channel array.

[0013] In some feasible embodiments, the transmitting circuit further includes an input driving circuit; The driving circuit is connected to the second tail current source of the LC oscillator and is configured to amplify or shape the baseband data to drive the second tail current source of the LC oscillator.

[0014] Secondly, this application provides a transmitting circuit for a 3D stacked memory chip, integrated on a first memory chip. The first memory chip integrates a transmitting circuit and a transmitting coil. The transmitting circuit includes: An LC oscillator, connected to the transmitting coil, is used to generate a carrier wave in the millimeter-wave band. The transmitting circuit is configured to: generate a millimeter-wave frequency carrier using an LC oscillator, and modulate the carrier in response to baseband data to generate a modulated signal; The transmitting coil is magnetically coupled to the receiving coil of the second memory chip, and is used to transmit the modulated signal to the receiving coil; wherein, the second memory chip integrates a receiving circuit and a receiving coil; The receiving circuit is connected to the receiving coil and is configured to demodulate the modulated signal to recover the baseband data and transmit it to the second memory chip.

[0015] Thirdly, this application provides a receiving circuit for a 3D stacked memory chip, integrated on a second memory chip, wherein the second memory chip integrates a receiving circuit and a receiving coil, the receiving circuit comprising: The receiving circuit is configured to: receive a modulated signal from the transmitting coil of the first memory chip via the receiving coil, demodulate the modulated signal to recover the baseband data, and transmit it to the second memory chip; The receiving coil is magnetically coupled to the transmitting coil of the first memory chip for receiving the modulated signal; wherein, the first memory chip integrates a transmitting circuit and a transmitting coil; The transmitting circuit is connected to the transmitting coil and is configured to: generate a carrier wave in the millimeter-wave band using an LC oscillator, and modulate the carrier wave in response to baseband data to generate the modulated signal.

[0016] As can be seen from the above technical solutions, this application provides a wireless memory interface array, a transmitting circuit, and a receiving circuit for 3D stacked memory chips. The wireless memory interface array includes a first memory chip and a second memory chip. The first memory chip integrates a transmitting circuit and a transmitting coil, and the second memory chip integrates a receiving circuit and a receiving coil. The transmitting circuit is connected to the transmitting coil, uses an LC oscillator to generate a millimeter-wave frequency carrier, and modulates the carrier in response to baseband data to generate a modulated signal. The transmitting coil is magnetically coupled to the receiving coil to transmit the modulated signal to the receiving coil. The receiving circuit is connected to the receiving coil, demodulates the modulated signal, recovers the baseband data, and transmits it to the second memory chip. The transmitting circuit uses an LC oscillator to generate a millimeter-wave frequency carrier and modulates the baseband data, achieving wireless transmission through magnetic coupling, thus improving chip area utilization efficiency. Simultaneously, modulating the baseband signal onto a high-frequency carrier enhances the anti-interference capability against power supply noise, enabling high-density, high-speed wireless interconnection between 3D stacked chips. Attached Figure Description

[0017] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the circuit structure of a traditional millimeter-wave wireless transceiver. Figure 2 This is a schematic diagram of the baseband transmission scheme circuit and waveforms; Figure 3 This is a schematic diagram of a memory interface array provided in an embodiment of this application; Figure 4 This is a schematic diagram of a memory interface array circuit provided in an embodiment of this application; Figure 5 A schematic diagram of simulation results provided for an embodiment of this application. Detailed Implementation

[0019] The embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following examples do not represent all embodiments consistent with this application.

[0020] 3D stacked memory chips are integrated circuit structures that assemble multiple memory chips by stacking them vertically. 3D stacking technology allows for the integration of more memory cells within a limited chip area, significantly increasing memory density and bandwidth. However, high-density interconnects are needed between stacked chips to facilitate data exchange. Traditional through-silicon via (TSV) technology requires fabricating metal vias that penetrate the substrate on the chip. These vias encroach on chip area and require additional processing steps.

[0021] One wireless interconnection solution between chips is based on millimeter-wave transmission, such as... Figure 1 As shown, TX is the transmitting circuit and RX is the receiving circuit. This scheme transmits the baseband signal by modulating it onto the carrier wave in the millimeter-wave band. Therefore, it usually requires a large number of inductors, consuming a large chip area. In addition, RF modules such as VCO, PA, and LNA usually cause a large power consumption.

[0022] Another interconnection solution between memory chips is based on baseband transmission TCI (Thru-Chip Interface) technology, such as... Figure 2 As shown, TX and RX are the transmitter and receiver, respectively, responsible for interconnecting the memory chips. TX and RX transmit data through magnetic coupling between coils. In the figure, TxData is the waveform input to the transmitter TX, VRP is the waveform received by the receiver RX, and RxData is the waveform recovered by the receiver. It can be seen that VRP is a pulse signal with a very short duration, which is easily affected by power supply voltage jitter, resulting in data recovery errors and poor anti-interference capability.

[0023] To address the aforementioned issues, the wireless memory interface array proposed in this embodiment can solve the inter-chip interconnection problem in 3D stacking scenarios. For example, in a stacked structure of high-bandwidth memory or processor and cache, multiple first memory chips and multiple second memory chips are vertically stacked, with each chip integrating a wireless interface circuit, and wireless data transmission between stacked chips is achieved through magnetic coupling.

[0024] This application can be applied to various 3D stacked storage scenarios. For example, in artificial intelligence training chips, a large amount of high-bandwidth on-chip storage is required. Multiple SRAM chips can be stacked together via a wireless memory interface to provide large-capacity, high-bandwidth storage resources. Another example is in high-performance CPUs, where L3 cache chips can be stacked on top of the CPU core, enabling high-speed data exchange via a wireless interface and reducing memory access latency. Yet another example is in graphics processing units (GPUs), where DRAM chips can be stacked near the GPU core, providing high-bandwidth video memory access via a high-density wireless interface.

[0025] like Figure 3 , Figure 4As shown, the wireless memory interface array includes at least one first memory chip (chip1) and at least one second memory chip (chip2). The first memory chip integrates a transmitting circuit and a transmitting coil, and the second memory chip integrates a receiving circuit and a receiving coil.

[0026] In some embodiments, the transmitting and receiving circuits can be integrated onto the corresponding memory chip using CMOS technology. CMOS technology has the advantages of low cost, high integration, and low power consumption. By using standard CMOS technology, the wireless memory interface can be directly integrated onto the same chip as other logic circuits of the memory chip without the need for additional special processes, thus reducing manufacturing costs.

[0027] The transmitting circuit is connected to the transmitting coil and is configured to: generate a millimeter-wave frequency carrier using an LC oscillator, and modulate the carrier in response to baseband data to generate a modulated signal.

[0028] An LC oscillator is an oscillation circuit composed of an inductor L and a capacitor C, used to generate a high-frequency carrier signal. In some embodiments, the transmitting circuit further includes a carrier generation circuit, which, together with the transmitting coil, constitutes an LC oscillator. The carrier generation circuit includes cross-coupled transistor pairs, eliminating the need for a separate inductor and saving chip area.

[0029] The cross-coupled transistor pair is connected to the transmitting coil and is configured to control the oscillation state of the LC oscillator to the target oscillation state.

[0030] In this embodiment, the target oscillation state is a stable oscillation state to ensure the generation of a stable millimeter-wave carrier. The cross-coupled transistor pair provides negative resistance to compensate for the energy loss of the LC oscillator and maintain the oscillation. The size of the transistor pair is optimized according to the operating frequency and power consumption requirements to ensure that the oscillator can reliably start oscillating in the millimeter-wave band.

[0031] The millimeter wave band has a frequency range of 30GHz-300GHz. The carriers in this band have the characteristics of short wavelength and small antenna size, making them suitable for chip-level integration. By using the high-frequency carriers in the millimeter wave band, the baseband signal can be shifted to a higher frequency for transmission, thereby obtaining a wider signal bandwidth and supporting higher data rates. At the same time, the high-frequency carriers are not sensitive to low-frequency power supply noise, which can enhance the anti-interference capability of signal transmission.

[0032] By adjusting the coil size and transistor dimensions, the oscillation frequency can be set in the millimeter-wave band, such as 70 GHz or higher. In the 28nm CMOS process, the transistor cutoff frequency is high enough to support circuit designs in the millimeter-wave band.

[0033] In memory chips, baseband data comes from binary information stored in memory cells. These raw signals have low frequencies and are not suitable for direct transmission in wireless channels. Baseband data is easily affected by low-frequency noise such as power supply voltage fluctuations and crosstalk, and direct transmission will lead to data errors.

[0034] In this embodiment, baseband data is loaded onto a millimeter-wave carrier wave through a modulation circuit to form a modulated signal. The frequency of the modulated signal is much higher than the noise frequency, and low-frequency noise can be effectively suppressed by filtering and other methods. The receiving end extracts the baseband envelope from the modulated signal through a demodulation circuit to recover the original data. This modulation and demodulation method moves the baseband signal from the low-frequency noise sensitive area to the high-frequency anti-interference area, which can solve the problem of baseband pulse transmission being sensitive to power supply noise.

[0035] Specifically, the transmitting circuit generates a high-frequency carrier wave in the millimeter-wave band using an LC oscillator. Baseband data (Tx Data) is input to the modulation circuit. The modulation circuit controls the first swing state of the LC oscillator based on the level of the baseband data. When the baseband data is high (signal 1), the modulation circuit causes the LC oscillator to output a larger amplitude high-frequency carrier wave (first swing state). When the baseband data is low (signal 0), the modulation circuit causes the LC oscillator to reduce its output amplitude (second swing state). In this way, the baseband data is directly modulated onto the high-frequency carrier wave, forming an OOK modulated signal. This modulated signal is then transmitted to the receiving coil via magnetic coupling through the transmitting coil.

[0036] The transmitting coil and the receiving coil are magnetically coupled. Magnetic coupling is a near-field wireless transmission method. When the two coils are aligned in the vertical direction, the signal is transmitted through the change of the magnetic field. The transmission distance is in the micrometer to millimeter range, which is suitable for inter-layer communication of 3D stacked chips. After receiving the modulated signal, the receiving coil transmits it to the receiving circuit.

[0037] The receiving circuit is connected to the receiving coil and is configured to demodulate the modulated signal to recover the baseband data and transmit it to the second memory chip.

[0038] The receiving circuit mixes the modulated signal with itself and extracts the envelope waveform of the signal. This envelope waveform is the reproduction of the original baseband data, which is then used by the second memory chip to achieve high-speed wireless data transmission from the first memory chip to the second memory chip. This eliminates the need for physical connections such as through-silicon vias (TSVs) and avoids the complex steps and area occupation of the TSV process.

[0039] Tx Data is the input starting point of the communication link (the original data to be sent), and Rx Data is the recovered data. This embodiment can ensure that in high-speed, high-density interconnection, Rx Data can reproduce the information carried by Tx Data with high fidelity and low bit error rate.

[0040] In some embodiments, the transmitting circuit further includes a modulation circuit connected to the carrier generating circuit; the modulation circuit is configured to: in response to the baseband data, control the operating state of the carrier generating circuit and modulate the baseband data onto the carrier.

[0041] The modulation circuit receives baseband data from external input and controls the tail current of the carrier generation circuit according to the high or low level of the baseband data, thereby controlling the carrier output state. This modulation method is direct and efficient, avoids complex baseband signal processing circuits, and reduces power consumption and delay.

[0042] The modulation circuit includes a first tail current source and a second tail current source connected in parallel. The first tail current source, controlled by a bias voltage, is configured to provide a current to the carrier generation circuit to sustain oscillation. This current ensures that the LC oscillator can start oscillating under any circumstances and maintain basic oscillation. The bias voltage Vbias is provided by an on-chip or off-chip reference voltage source, exhibiting good temperature stability and process robustness. The current value of the first tail current source can be set according to the oscillator's start-up conditions and power consumption requirements, ensuring that the LC oscillator can reliably start oscillating under various process angles and temperature conditions.

[0043] The second tail current source is controlled by the baseband data and is configured to: turn on when the baseband data is signal 1 (high level) to control the LC oscillator to be in a first swing state; turn off when the baseband data is signal 0 (low level) to control the second swing state of the LC oscillator and modulate the baseband data onto the carrier.

[0044] In some embodiments, both the transmitting and receiving circuits employ a low-voltage design, with operating voltages as low as below 1V. The bias voltage of the first tail current source is provided by a bandgap reference source, exhibiting good temperature stability. The second tail current source is directly driven by baseband data, eliminating the need for level conversion circuitry and reducing power consumption and latency. When there is no data transmission, the power supply to some circuits can be turned off, entering a sleep mode to further reduce standby power consumption.

[0045] Specifically, when the baseband data is high, the second tail current source is turned on, providing additional current to the LC oscillator, enabling the oscillator to output a high-frequency carrier with a larger amplitude. When the baseband data is low, the second tail current source is turned off, and the LC oscillator is powered only by the first tail current source. At this time, the oscillator oscillation amplitude is extremely small. In this way, the baseband data is directly modulated onto the high-frequency carrier to form a modulated signal. This OOK modulation method has a simple circuit structure, low power consumption, and due to the high carrier frequency and wide signal bandwidth, it can support single-channel data rates of up to 20Gb / s or more. The parallel structure of the two tail current sources separates the modulation process from the oscillator bias, and the modulation depth can be adjusted independently, improving design flexibility.

[0046] In some embodiments, the baseband signal to be modulated is amplified by an input driver circuit to ensure that it can drive the second tail current source.

[0047] In some embodiments, the receiving circuit includes a self-mixer connected to the receiving coil and configured to mix the modulated signal with itself to extract the baseband envelope and recover the baseband data.

[0048] The self-mixing circuit adopts a differential structure, including two input terminals, V+ and V-. It multiplies the received differential modulation signal to directly demodulate the envelope of the baseband signal. By using envelope detection, it overcomes the problem of baseband pulse transmission being sensitive to power supply noise and enhances anti-interference capability.

[0049] In some embodiments, the receiving circuit further includes an output driving circuit (CML) and a sampling circuit (Sample); the sampling circuit is connected to the self-mixing circuit, the output driving circuit is connected to the sampling circuit, and the sampling circuit is configured to sample the demodulated signal; the output driving circuit is configured to shape and amplify the sampled signal to output baseband data in digital form.

[0050] Specifically, the output drive circuit can be a CML driver. The analog baseband signal output from the self-mixing circuit is sampled by the sampling circuit, then shaped and amplified by the CML driver, and finally output as a standard digital baseband signal for use by the internal circuit of the second memory chip.

[0051] The sampling circuit can use a D flip-flop or latch structure to sample data at the recovered clock edge. The CML driver has the characteristics of high speed and low swing, making it suitable for driving long-distance on-chip wiring.

[0052] In this embodiment, the diameters of the transmitting coil and the receiving coil are designed to be the same to achieve efficient magnetic coupling signal transmission in the vertical direction. Furthermore, there can be multiple transmitting coils and multiple receiving coils, which together form a channel array to achieve multi-channel parallel data transmission. The center distance between adjacent channels is less than or equal to 1.2 times the coil diameter.

[0053] In some embodiments, the transmitting and receiving coils are arranged symmetrically to ensure coil overlap when the upper and lower chips are aligned. The coils employ a circular or octagonal helical structure to reduce eddy current losses. Isolation structures, such as grounding rings, are provided between coils of adjacent channels to suppress inter-channel crosstalk. Other parts of the transmitting and receiving circuits are arranged around the coils, minimizing connection lengths and reducing the impact of parasitic parameters.

[0054] like Figure 3 As shown, the coil diameter is 100μm, i.e., D1-D2, and the center distance between coils of adjacent channels is set to 120μm, for example, AB, AC. This can effectively suppress signal crosstalk between channels while ensuring high integration density. The optimized design of coil size and spacing allows more channels to be arranged in a unit area, improving I / O density. The number of channels can be expanded according to bandwidth requirements, for example, a few channels, or even hundreds of channels.

[0055] The coil can be wound with a top layer of metal, resulting in a high quality factor. The coil shape can be circular, octagonal, or square helical to reduce eddy current losses. Isolation structures, such as grounding rings, can be installed between coils in adjacent channels to further suppress crosstalk between channels.

[0056] In some embodiments, the transmitting circuit further includes a driving circuit connected between the input port and the second tail current source of the LC oscillator. The driving circuit is configured to amplify the power of the modulated signal or shape the waveform to enhance the signal driving capability and ensure the reliability of magnetic coupling transmission. The driving circuit can adopt an inverter chain structure and be designed according to the output power requirements. In cases where the distance between the input port and the transmitting circuit is far, the driving circuit can effectively compensate for signal attenuation and ensure the quality of the baseband signal.

[0057] In this embodiment, the single-channel data rate of the wireless memory interface array can reach over 20Gb / s. This high-speed data transmission capability benefits from the high carrier frequency of the millimeter-wave band and the simplicity and efficiency of OOK modulation. Due to the high carrier frequency and wide bandwidth, it can support extremely high symbol rates. At the same time, the OOK modulation method allows the transmitter to directly control the oscillator start and stop with baseband data, avoiding complex modulation circuits and digital signal processing, thereby reducing circuit delay and increasing data rate.

[0058] Furthermore, the compact circuit design and optimized coil layout enable the wireless memory interface array to achieve an I / O area efficiency of 1388 Gb / s / mm². 2 The transmitting circuit uses only one coil to simultaneously generate and modulate the carrier wave, saving additional inductor area compared to traditional solutions. The receiving circuit employs a self-mixing structure, eliminating the need for a local oscillator and complex clock recovery circuits, further reducing the area required. Optimized coil size and spacing allow for more channels to be arranged within a unit area, increasing I / O density.

[0059] In this embodiment, the anti-interference capability of millimeter-wave transmission and the envelope detection method of the receiving circuit enable the bit error rate of the wireless memory interface array to be less than 10. -15The high-frequency carrier is not sensitive to low-frequency noise, and the magnetic coupling transmission method has good anti-crosstalk capability. The self-mixing receiving circuit extracts the signal envelope, avoiding the accumulation of bit errors in clock recovery and data decision.

[0060] The simulation results of this embodiment at a data rate of 20Gb / s are as follows: Figure 5 As shown, (a) is the transmitter input data waveform; (b) is the transmitter output waveform; (c) is the receiver input waveform; (d) is the receiver output waveform; (e) is the transmitter input data eye diagram; and (f) is the receiver output data eye diagram.

[0061] The table below compares the performance of the present invention with that of existing circuit structures.

[0062]

[0063] The formula for calculating I / O area efficiency is as follows: ; In summary, this embodiment significantly improves both data rate and I / O area utilization efficiency compared to existing structures.

[0064] Based on the aforementioned wireless memory interface array, some embodiments of this application also provide a transmitting circuit for a 3D stacked memory chip, integrated on a first memory chip. The first memory chip integrates a transmitting circuit and a transmitting coil. The transmitting circuit includes: An LC oscillator, connected to the transmitting coil, is used to generate a carrier wave in the millimeter-wave band. The transmitting circuit is configured to: generate a millimeter-wave frequency carrier using an LC oscillator, and modulate the carrier in response to baseband data to generate a modulated signal; The transmitting coil is magnetically coupled to the receiving coil of the second memory chip, and is used to transmit the modulated signal to the receiving coil; wherein, the second memory chip integrates a receiving circuit and a receiving coil; The receiving circuit is connected to the receiving coil and is configured to demodulate the modulated signal to recover the baseband data and transmit it to the second memory chip.

[0065] Based on the aforementioned wireless memory interface array, some embodiments of this application also provide a receiving circuit for a 3D stacked memory chip, integrated on a second memory chip. The second memory chip integrates a receiving circuit and a receiving coil. The receiving circuit includes: The receiving circuit is configured to: receive a modulated signal from the transmitting coil of the first memory chip via the receiving coil, demodulate the modulated signal to recover the baseband data, and transmit it to the second memory chip; The receiving coil is magnetically coupled to the transmitting coil of the first memory chip for receiving the modulated signal; wherein, the first memory chip integrates a transmitting circuit and a transmitting coil; The transmitting circuit is connected to the transmitting coil and is configured to: generate a carrier wave in the millimeter-wave band using an LC oscillator, and modulate the carrier wave in response to baseband data to generate the modulated signal.

[0066] Similar parts between the embodiments provided in this application can be referred to mutually. The specific implementation methods provided above are only a few examples under the overall concept of this application and do not constitute a limitation on the scope of protection of this application. For those skilled in the art, any other implementation methods extended from the solution of this application without creative effort shall fall within the scope of protection of this application.

Claims

1. A wireless memory interface array for 3D stacked memory chips, characterized in that, include: At least one first memory chip integrates a transmitting circuit and a transmitting coil; At least one second memory chip, which integrates a receiving circuit and a receiving coil; The transmitting circuit is connected to the transmitting coil and is configured to: generate a millimeter-wave frequency carrier using an LC oscillator, and modulate the carrier in response to baseband data to generate a modulated signal; The transmitting coil is magnetically coupled to the receiving coil, and is used to transmit the modulated signal to the receiving coil; The receiving circuit is connected to the receiving coil and is configured to demodulate the modulated signal to recover the baseband data and transmit it to the second memory chip.

2. The wireless memory interface array for 3D stacked memory chips according to claim 1, characterized in that, The transmitting circuit also includes a carrier generation circuit, which together with the transmitting coil forms an LC oscillator. The carrier generation circuit includes a cross-coupled pair of transistors connected to the transmitting coil and configured to control the oscillation state of the LC oscillator to a target oscillation state.

3. The wireless memory interface array for 3D stacked memory chips according to claim 2, characterized in that, The transmitting circuit further includes a modulation circuit, which is connected to the carrier generation circuit. The modulation circuit is configured to: control the operating state of the carrier generation circuit in response to the baseband data, and modulate the baseband data onto the carrier.

4. The wireless memory interface array for 3D stacked memory chips according to claim 3, characterized in that, The modulation circuit includes a first tail current source and a second tail current source connected in parallel. The first tail current source is controlled by a bias voltage and is configured to provide a current to the carrier generation circuit to sustain oscillation. The second tail current source is controlled by the baseband data and is configured to: turn on when the baseband data is signal 1, controlling the LC oscillator to be in a first swing state; and turn off when the baseband data is signal 0, controlling the LC oscillator to be in a second swing state, so as to modulate the baseband data onto the carrier.

5. The wireless memory interface array for 3D stacked memory chips according to claim 1, characterized in that, The receiving circuit includes a self-mixing circuit connected to the receiving coil and configured to mix the modulation signal with itself to extract the baseband envelope and recover the baseband data.

6. The wireless memory interface array for 3D stacked memory chips according to claim 5, characterized in that, The receiving circuit also includes a sampling circuit and an output driving circuit; The sampling circuit is connected to the self-mixing circuit, the output driving circuit is connected to the sampling circuit, and the sampling circuit is configured to sample the demodulated signal. The output drive circuit is configured to: shape and amplify the sampled signal to output baseband data in digital form.

7. The wireless memory interface array for 3D stacked memory chips according to claim 1, characterized in that, The transmitting coil and the receiving coil are arranged vertically; The number of transmitting coils and receiving coils is multiple, and the multiple transmitting coils and multiple receiving coils constitute a channel array.

8. The wireless memory interface array for 3D stacked memory chips according to claim 1, characterized in that, The transmitting circuit also includes an input driving circuit; The driving circuit is connected to the second tail current source of the LC oscillator and is configured to amplify or shape the baseband data to drive the second tail current source of the LC oscillator.

9. A transmitting circuit for a 3D stacked memory chip, characterized in that, Integrated on a first memory chip, the first memory chip integrates a transmitting circuit and a transmitting coil, the transmitting circuit comprising: An LC oscillator, connected to the transmitting coil, is used to generate a carrier wave in the millimeter-wave band. The transmitting circuit is configured to: generate a millimeter-wave frequency carrier using an LC oscillator, and modulate the carrier in response to baseband data to generate a modulated signal; The transmitting coil is magnetically coupled to the receiving coil of the second memory chip, and is used to transmit the modulated signal to the receiving coil; wherein, the second memory chip integrates a receiving circuit and a receiving coil; The receiving circuit is connected to the receiving coil and is configured to demodulate the modulated signal to recover the baseband data and transmit it to the second memory chip.

10. A receiving circuit for a 3D stacked memory chip, characterized in that, Integrated on a second memory chip, the second memory chip integrates a receiving circuit and a receiving coil, the receiving circuit including: The receiving circuit is configured to: receive a modulated signal from the transmitting coil of the first memory chip via the receiving coil, demodulate the modulated signal to recover the baseband data, and transmit it to the second memory chip; The receiving coil is magnetically coupled to the transmitting coil of the first memory chip for receiving the modulated signal; wherein, the first memory chip integrates a transmitting circuit and a transmitting coil; The transmitting circuit is connected to the transmitting coil and is configured to: generate a carrier wave in the millimeter-wave band using an LC oscillator, and modulate the carrier wave in response to baseband data to generate the modulated signal.

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