Method for acquisition of burst spread spectrum system at low signal-to-noise ratio

Abstract

The application discloses a burst spread spectrum system acquisition implementation method under low signal-to-noise ratio, and relates to the technical field of spread spectrum communication. The method comprises the following steps: storing a pre-processed receiving signal into a block random memory; segmenting a local PN code and performing a sliding correlation operation with the buffered data; performing two-stage parallel accumulation on the segmented correlation results; performing a differential operation on adjacent data after accumulation to eliminate phase errors caused by frequency offset, and calculating power accumulation to find extreme values; comparing the extreme values with a threshold value, extracting a sequence corresponding to an extreme value exceeding the threshold value to obtain a frequency offset through fast Fourier transform; and finally performing frequency offset compensation and outputting acquisition information. The application replaces a shift register with a block random memory, combines a segmented differential operation with a post-fast Fourier transform mechanism, greatly reduces hardware resource consumption, and realizes fast and stable acquisition of a short frame burst signal under the conditions of extremely low signal-to-noise ratio and large frequency offset.

Description

Technical Field

[0001] This invention belongs to the field of spread spectrum communication and signal processing technology, and in particular relates to a method for capturing burst spread spectrum systems under low signal-to-noise ratio conditions. Background Technology

[0002] Spread spectrum communication is widely used in military and civilian communications fields due to its strong anti-interference and anti-interception capabilities, as well as its ability to achieve reliable communication at low signal-to-noise ratios. Especially in high-speed mobile scenarios such as missile-borne platforms, communication systems typically employ burst spread spectrum communication modes to meet the requirements of short frames, intermittent transmission, and high real-time performance.

[0003] In traditional burst spread spectrum signal acquisition systems, the receiver typically uses a serial shift register for sliding correlation operations, combined with a parallel slotted architecture of frequency sweeping and Fast Fourier Transform (FFT) to complete code phase search and frequency offset estimation. However, with the increasing demands of modern communication systems for symbol rate, spreading factor, and Doppler immunity, traditional acquisition schemes have gradually revealed the following technical shortcomings in practical applications: First, low signal-to-noise ratio (SNR) acquisition is difficult. Conventional serial shift correlation methods rely on long-term energy accumulation to improve the SNR, but in bursty communication scenarios, signal frame lengths are extremely short, and the accumulation time is strictly limited. In extreme environments with SNRs as low as -20dB, traditional methods cannot achieve effective acquisition due to insufficient accumulation gain.

[0004] Secondly, it has poor adaptability to large frequency offsets. Traditional solutions typically use frequency sweeping combined with FFT parallel slotting to resist Doppler frequency offset. When the frequency offset reaches the 10kHz level, in order to cover the frequency offset range, a large number of parallel processing channels need to be opened, resulting in an exponential increase in the number of parallel channels, which can easily exhaust the registers and logic resources of the field-programmable gate array (FPGA).

[0005] Secondly, high symbol rates incur enormous hardware resource overhead. At symbol rates of 4 Msps and spread factors of 1000 to 2000 times, traditional shift register-based sliding correlation architectures require tens of thousands of register resources. This not only severely overloads FPGA resources but also causes serious timing closure problems, making the system unstable.

[0006] Finally, burst adaptability is weak. Traditional acquisition mechanisms typically employ long accumulation times and slow frequency sweeping strategies, which are severely mismatched with the characteristics of burst communication—short frames, rapid changes, and one-time transmissions—making it easy for the receiver to miss the brief acquisition window, thereby reducing the acquisition success rate.

[0007] In summary, existing technologies struggle to simultaneously meet the four stringent conditions of low signal-to-noise ratio, large frequency offset, high symbol rate, and bursty short frames. Therefore, there is an urgent need in this field for a signal acquisition method that is low in resource consumption, fast in acquisition speed, highly resistant to frequency offset, and highly adaptable to bursty communication scenarios. Summary of the Invention

[0008] In view of this, the present invention aims to propose a method for capturing burst spread spectrum systems under low signal-to-noise ratio conditions, in order to solve the technical problems of existing burst spread spectrum signal acquisition technology in low signal-to-noise ratio, large frequency offset, high symbol rate and short frame burst scenarios, such as insufficient cumulative gain, huge hardware resource overhead, poor frequency offset adaptability and low acquisition window matching degree.

[0009] To achieve the above objectives, the technical solution of the present invention is implemented as follows: This invention provides a method for acquiring burst spread spectrum systems at low signal-to-noise ratios, comprising the following steps: Step 1, Signal preprocessing and buffering: The received burst spread spectrum signal is sampled, filtered and down-converted to obtain the baseband signal, and the baseband signal and local PN code are stored in the memory; Step 2, PN segment correlation operation: Divide the local PN code evenly into multiple sub-code segments, perform sliding correlation operation between each local PN code segment and the baseband data cached in the memory, and output the multi-channel segment correlation results; Step 3, Multi-level parallel accumulation: Perform two-level parallel accumulation on the multi-path segmentation correlation results to obtain the cumulative gain; Step 4, Differential and Power Accumulation: Perform differential operation on the data corresponding to adjacent sub-code segments after accumulation to eliminate the phase error introduced by frequency offset, calculate the sum of the squares of the I-path component and the squares of the Q-path component of the differential result, and accumulate the power values ​​of all channels to find the extreme value of the sequence. Step 5, Peak detection and frequency offset estimation: Compare the found extreme value with a preset threshold. If it exceeds the threshold, extract the accumulated data sequence corresponding to the extreme value and perform a fast Fourier transform operation on the sequence to obtain the frequency offset. Step 6, Frequency Offset Compensation and Output: Based on the solution results of the Fast Fourier Transform, complete the link frequency offset compensation and output the code phase and frequency offset information.

[0010] Furthermore, in step 2, the local PN code is divided into 64 sub-code segments; in step 3, the two-level parallel accumulation is as follows: the 64 segmented correlation results are first accumulated in two parallel channels, and then accumulated in two secondary channels. The single-channel accumulation gain reaches 4 times, the total number of data points participating in the accumulation reaches 256, and the corresponding total accumulation gain reaches 256 times.

[0011] Furthermore, in step 4, the formula for the difference operation is: ,in and The results are the correlation between two adjacent segments; after differential operation, the first-order linear phase component caused by frequency offset is canceled out, and only the effective signal information related to the code phase delay is retained.

[0012] Furthermore, in step 5, the preset threshold is determined using a formula. ,in, The total number of data samples used in the judgment. Indicates the first The power value of each data sample after differential operation is the sum of the squares of the I-path component and the Q-path component; the numerator represents the energy after coherent accumulation of the power values, and the denominator represents the energy after incoherent accumulation of the squares of the power values; when A value between 8 and 10 indicates a successful capture.

[0013] Furthermore, in step 5, the number of points in the Fast Fourier Transform operation is the same as the number of sub-code segments; the Fast Fourier Transform operation is only performed after the accumulated data sequence is extracted.

[0014] Furthermore, in step 1, the memory is a block random access memory on a field-programmable gate array (FPGA); the block random access memory is configured in a dual-port mode and a circular buffer, with one port used to write sampled data and the other port used to read data at the system processing clock for related operations.

[0015] Furthermore, the target symbol rate is 4 Msps, the single symbol duration is 250 ns, the system processing clock frequency is 300 MHz, the total number of system clocks contained in a single symbol period is approximately 75, and the number of sub-code segments is 64, which meets the segmentation processing requirement of no less than 64 clock cycles.

[0016] Furthermore, when the burst spread spectrum signal is QPSK modulated, in step 1, orthogonal downconversion is required to separate the I-channel and Q-channel data; in step 2, the local PN code is correlated with the I-channel and Q-channel data respectively; in step 4, the squares of the I-channel component difference and the squares of the Q-channel component difference are calculated and then added together.

[0017] Furthermore, the number of sub-code segments in step 2 is adjusted according to the system processing clock frequency; when the system processing clock frequency is increased, the number of sub-code segments is increased to improve the anti-frequency deviation capability.

[0018] Furthermore, in step 5, when the frequency offset range exceeds the preset value, zero-padding is performed on the accumulated data sequence to increase the number of points in the fast Fourier transform operation and improve the frequency offset estimation resolution.

[0019] Compared with the prior art, the burst spread spectrum system of the present invention has the following advantages in acquisition implementation method under low signal-to-noise ratio: 1. Significantly reduces hardware resource overhead, overcoming resource bottlenecks at high symbol rates. This invention abandons the traditional serial shift register architecture and employs on-chip block random access memory (BRAM) on a field-programmable gate array (FPGA) to buffer received data and local pseudo-random codes. Through a dual-port circular buffer and a high-speed clock polling read mechanism, high-speed serial data is converted into parallel or low-speed serial data streams for processing. Compared to traditional solutions, this architecture reduces FPGA register resource overhead by more than 90%, effectively solving the technical bottleneck of hardware resource constraints under high spread factor and high symbol rate conditions.

[0020] 2. It possesses excellent resistance to large frequency offsets, balancing frequency offset robustness with resource controllability. This invention employs a mechanism combining PN code segmented correlation with adjacent segmented differential operations. Short-sequence segmented integration reduces the attenuation of single-segment correlation peaks due to frequency offset, and differential operations fundamentally offset the first-order linear phase rotation error caused by Doppler frequency offset. Simultaneously, the Fast Fourier Transform (FFT) frequency offset estimation is deferred to the peak selection stage, performing a single FFT operation only on valid peak data. This avoids the problem of a surge in parallel paths in traditional frequency-sweeping parallel slotting architectures when dealing with large frequency offsets of 10kHz, significantly reducing logic and storage resource consumption while ensuring strong resistance to frequency offsets.

[0021] 3. Achieve stable acquisition under extremely low signal-to-noise ratio (SNR) conditions, significantly improving weak signal detection capabilities. Addressing the challenge of short bursts of frames not accumulating over extended periods, this invention employs a 64-segment segmentation and two-stage parallel accumulation architecture. This mechanism achieves a 256-fold accumulation gain of approximately 24dB within a single symbol period. Combined with a 1000-2000-fold spread spectrum processing gain, it effectively raises the original -20dB extremely low SNR signal above the acquisition decision threshold, meeting the reliable acquisition requirements under harsh weak signal environments.

[0022] 4. Excellent adaptation to the characteristics of bursty short frames, enabling rapid acquisition within an extremely short window. This invention employs a segmented parallel processing architecture, eliminating the need for long-term serial energy accumulation. The entire acquisition process (including code phase search and joint frequency offset estimation) can be completed within an extremely short window of no more than one symbol period (250ns). This short accumulation time mechanism is highly compatible with the characteristics of burst communication—short frames, rapid changes, and one-time transmission—effectively preventing the receiver from missing the acquisition opportunity and significantly improving the success rate of burst signal acquisition and the system's real-time response capability. Attached Figure Description

[0023] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1This is a schematic diagram of the receiver acquisition block diagram of the acquisition implementation method of the burst spread spectrum system under low signal-to-noise ratio provided in the embodiment of the present invention; Figure 2 This is a schematic diagram of the relationship between the amplitude of the correlation peak and the frequency offset under different cumulative sequence lengths provided in the embodiments of the present invention. Detailed Implementation

[0024] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0025] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0026] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0027] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0028] like Figures 1 to 2 As shown, the method for acquiring a burst spread spectrum system under low signal-to-noise ratio includes the following steps: Step 1, Signal preprocessing and buffering: The received burst spread spectrum signal is sampled, filtered and down-converted to obtain the baseband signal, and the baseband signal and local PN code are stored in the memory; Step 2, PN segment correlation operation: Divide the local PN code evenly into multiple sub-code segments, perform sliding correlation operation between each local PN code segment and the baseband data cached in the memory, and output the multi-channel segment correlation results; Step 3, Multi-level parallel accumulation: Perform two-level parallel accumulation on the multi-path segmentation correlation results to obtain the cumulative gain; Step 4, Differential and Power Accumulation: Perform differential operation on the data corresponding to adjacent sub-code segments after accumulation to eliminate the phase error introduced by frequency offset, calculate the sum of the squares of the I-path component and the squares of the Q-path component of the differential result, and accumulate the power values ​​of all channels to find the extreme value of the sequence. Step 5, Peak detection and frequency offset estimation: Compare the found extreme value with a preset threshold. If it exceeds the threshold, extract the accumulated data sequence corresponding to the extreme value and perform a fast Fourier transform operation on the sequence to obtain the frequency offset. Step 6, Frequency Offset Compensation and Output: Based on the solution results of the Fast Fourier Transform, complete the link frequency offset compensation and output the code phase and frequency offset information.

[0029] The specific embodiments of the present invention are as follows: This invention provides a method for acquiring burst spread spectrum systems under low signal-to-noise ratio (SNR) conditions, primarily applicable to missile-borne network communication, burst spread spectrum signal acquisition, low SNR signal processing, and large frequency offset Doppler suppression technologies. This embodiment is particularly suitable for rapid acquisition in BPSK or QPSK modulation, high symbol rate, large frequency offset, low SNR, and short-frame burst scenarios.

[0030] In a preferred embodiment of the present invention, the system hardware platform is implemented based on a Field-Programmable Gate Array (FPGA) architecture, specifically a Xilinx Zynq-7045. The system processing clock frequency is configured as follows: The system is equipped with no fewer than 20 blocks of Block Random Access Memory (BRAM) resources to replace the traditional shift register architecture. The system supports BPSK and QPSK modulation and demodulation.

[0031] The technical solution of the present invention will be described in detail below, combining theoretical derivation of the formula with specific implementation steps.

[0032] I. Matching Analysis of Symbol Rate and FPGA Processing Clock Timing This invention provides timing optimizations for high symbol rate scenarios. The target symbol rate is set to... .

[0033] Single symbol duration The calculation is as follows: ; The FPGA system processing clock frequency is set to .

[0034] Single clock cycle duration The calculation is as follows: ; Total number of system clocks contained in a single symbol period The calculation is as follows: ; In terms of timing constraints, the minimum number of clock cycles required for segmented parallel processing is 64. Because... The timing margin is ample. This means that within a single 250ns symbol period, the system has a sufficient time window to complete 64 parallel segmented related operations without any timing establishment or maintenance violations, and can stably support a high symbol rate of 4Msps.

[0035] For high spread ratios of 1000 to 2000 times, traditional shift register schemes require extremely long register chains, leading to resource exhaustion. This invention addresses this issue by using BRAM to cache data and polling the data every 75 cycles with a 300MHz clock, cleverly converting high-speed serial data into a parallel or low-speed serial data stream that can be processed by the FPGA. Specifically, the BRAM is configured in a dual-port mode: port A is used for high-speed writing of analog-to-digital converter (ADC) sampling data, and port B is used for reading data at a 300MHz clock for related operations. This architecture reduces resource overhead by more than 90% compared to traditional solutions, effectively solving the bottleneck of FPGA register resources being insufficient under high spread ratio conditions.

[0036] II. Modeling of Baseband Received Signals Containing Frequency Offset Noise In high-speed missile-borne scenarios, the receiver signal is affected by Doppler frequency shift and Gaussian white noise. The mathematical model for the baseband received signal of the BPSK modulated signal is as follows.

[0037] Received baseband signal expression Defined as: ; In the formula, The amplitude of the received signal; It is a local PN pseudo-random spreading code; This refers to the code phase delay; The center frequency of the carrier. This is due to Doppler frequency shift; The initial carrier phase; It is additive white Gaussian noise.

[0038] Subject to Doppler frequency deviation Due to the influence of the channel, the signal phase rotates linearly over time. Directly performing traditional correlation calculations would result in correlation peak dispersion and significant amplitude attenuation. Therefore, this invention introduces a differential processing mechanism to eliminate linear phase interference terms introduced by the channel.

[0039] III. PN code segmentation correlation operation and differential frequency offset resistance mechanism In order to complete the acquisition and resist frequency offset within a limited time window, the embodiments of the present invention adopt a strategy of combining PN code segmentation correlation with differential calculation.

[0040] 1. PN code segmentation related operations The entire PN code is evenly divided into 64 sub-code segments, with a single segment length of 1. . No. Discrete correlation output results of each sub-code segment The calculation formula is as follows: ; In the formula, It is a local PN code conjugate sequence. This is the k-th sampling time. Single-shot piecewise correlation results. It also includes effective code phase information, as well as linear phase interference terms introduced by Doppler frequency offset. By segmenting, we decompose the correlation operation of the long sequence into multiple short sequence operations. The integration time of each short sequence is short, thereby reducing the attenuation effect of frequency offset on the correlation peak of a single segment.

[0041] 2. Derivation of the theory of adjacent piecewise differential frequency offset resistance To eliminate the phase rotation caused by frequency offset, a difference operation is performed on the correlation results of adjacent segments. The formula for the difference operation of adjacent segments is as follows: The definition is as follows: ; After the above difference operation, the first-order linear phase component caused by the Doppler frequency offset is completely canceled out. Difference sequence Only the code phase delay was retained. The relevant effective signal information is obtained, thereby eliminating the suppression effect of frequency offset on the relevant peak value from the root. This mechanism is the key to the stable acquisition under large frequency offset conditions in the embodiments of the present invention, avoiding the problem of the exponential increase in the number of parallel paths when the frequency offset is 10kHz in the traditional frequency sweep plus FFT parallel slotting architecture.

[0042] IV. Derivation of Multi-stage Parallel Cumulative Gain Quantization For low signal-to-noise ratio environments, this invention employs a multi-stage parallel accumulation architecture to enhance signal energy. This invention utilizes a 64-channel segmented input combined with a two-stage parallel accumulation architecture.

[0043] Total signal spatial accumulation gain The calculation is as follows: ; Log-cumulative gain conversion as follows: ; Considering that differential operations will introduce a performance loss of approximately 3dB.

[0044] The inherent processing gain of superimposed spread spectrum: if the spread factor is 1000 times, the gain is 30dB; if it is 2000 times, the gain is 33dB.

[0045] The total system gain is approximately 30dB to 33dB.

[0046] Based on comprehensive calculations, the original extremely low signal-to-noise ratio (SNR) signal of -20dB can be boosted to 10dB to 13dB. After subtracting the differential loss of 3dB, the overall signal-to-noise ratio is approximately 7dB to 10dB. This value is higher than the signal acquisition decision threshold, meeting the requirements for weak signal acquisition.

[0047] It should be noted that this design employs a strategy of partial accumulation, but not full accumulation. If full accumulation were used, the frequency offset resistance would be severely compromised. This embodiment uses... That is, 256 data segments are accumulated to form 64 data sets. Differentiation is performed on these 64 data sets to remove the frequency offset within 10kHz in the IQ data. On this basis, the sum of the squares of the I-path components and the squares of the Q-path components is calculated to find the extreme value.

[0048] V. Detailed Explanation of Implementation Steps and System Flow Combination Figure 1 The receiver acquisition block diagram and the specific implementation process of this embodiment are as follows. Figure 1 The complete data flow from signal reception to final frequency offset compensation is shown, which includes a signal reception preprocessing module, a BRAM storage N-block module, a data sequential reading module, a segmented parallel correlation operation module, an adjacent segment data accumulation module, an adjacent data difference module, a module for calculating the sum of the squares of the I-channel component and the squares of the Q-channel component, a peak acquisition module, a module for performing FFT operation on the peak corresponding sequence, and a frequency offset compensation output signal-to-noise ratio and timing module.

[0049] Step 1: Signal preprocessing and BRAM buffering The ADC samples BPSK or QPSK signals at a rate of 4Msps, and then filters and down-converts them into baseband signals.

[0050] Baseband data and the local PN code are stored in the FPGA's on-chip BRAM. This step utilizes BRAM instead of a traditional shift register. Specifically, the BRAM is configured as a circular buffer with a depth set to accommodate at least one symbol cycle of data. The data write pointer increments with the ADC sampling clock, while the read pointer is controlled by relevant operational logic. This architecture significantly reduces FPGA resource overhead under high spread spectrum conditions.

[0051] Step 2: PN segmentation related calculations The local PN code is divided into 64 segments. Each PN code segment is subjected to sliding correlation operation with the received data buffered in the BRAM.

[0052] The system is equipped with a 300MHz high-speed processing clock, with approximately 75 clock cycles within a single 250ns symbol period, meeting the requirement of segmented processing of no less than 64 clock cycles.

[0053] This step outputs 64 segmented results. This process corresponds to... Figure 1 The segmented parallel correlation operation module is implemented in the FPGA. In terms of hardware implementation, 64 parallel multiplication and accumulation units are used. Each unit is responsible for the correlation operation between a PN code and the corresponding data segment. The sliding correlation operation and parallel accumulation operation are implemented by calling the digital signal processing (DSP) slice resources inside the FPGA. The read address of the BRAM is controlled by the counter logic to realize the movement of the sliding window.

[0054] Step 3: Two-stage parallel accumulation The 64-way results output from step 2 are accumulated in two stages in parallel. Specifically, the 64-way results are first accumulated in parallel in two stages, and then accumulated in two stages in a second stage.

[0055] The total cumulative gain reached 256 times. This step corresponds to... Figure 1 The adjacent segment data accumulation module in the middle. Through this tree-structured accumulation, the signal energy under low signal-to-noise ratio is effectively improved. The first-stage accumulation combines 64 data channels in pairs to form 32 data channels; the second-stage accumulation combines the 32 data channels in pairs again to finally form a high-gain accumulation result.

[0056] Step 4: Differential and Power Accumulation Perform differential operations on the 64 channels of IQ adjacent data accumulated above. This step corresponds to... Figure 1 The adjacent data difference module in the middle.

[0057] Differential operations can effectively compensate for the phase error introduced by the 10kHz Doppler frequency offset.

[0058] Subsequently, the sum of the squares of the I-path components and the squares of the Q-path components of the difference result is calculated, and the power values ​​of all channels are accumulated to find the maximum extremum in the sequence. This step corresponds to... Figure 1 The module for calculating the sum of the squares of the I-path components and the squares of the Q-path components.

[0059] Step 5: Peak Detection and FFT Frequency Offset Estimation The extreme values ​​obtained in step 4 are compared with the preset threshold.

[0060] If the threshold is exceeded, the accumulated IQ data sequence corresponding to that extreme value is extracted. (This corresponds to...) Figure 1The data stream originates from the adjacent segment data accumulation module and points to the FFT operation module corresponding to the peak value sequence.

[0061] The frequency offset is obtained by performing a Fast Fourier Transform (FFT) on the sequence. Here, the number of points in the FFT operation matches the number of segments, and a 64-point FFT operation is used.

[0062] The Doppler frequency offset of the current communication sequence is accurately calculated using FFT. This step corresponds to... Figure 1 The FFT operation module is used to perform FFT operations on the peak corresponding sequence. It is worth noting that the FFT is only performed after peak selection, rather than in parallel slotting throughout the entire process. Traditional solutions may require dozens of parallel FFT channels to perform a full-coverage search for a 10kHz frequency offset, while this embodiment of the invention only performs a single FFT operation on the selected valid peak data, significantly reducing the FPGA logic and storage resource usage.

[0063] Step 6: Frequency Offset Compensation and Capture Output Link frequency offset compensation is performed based on the FFT calculation results.

[0064] Output code phase and frequency offset information to complete burst signal acquisition. This step corresponds to... Figure 1 The frequency offset compensation output signal-to-noise ratio and timing module are included. The entire acquisition process is completed within a time of no more than 250ns, adapting to the fast acquisition requirements of short frame burst communication.

[0065] VI. Peak Detection Threshold Determination Formula In step 5, the method for determining the peak value preset uses the following formula: ; In the formula, The total number of data samples used in the judgment. Indicates the first The power value of each data sample after differential operation, that is, the sum of the squares of the I-path component and the squares of the Q-path component; numerator The denominator represents the energy obtained after coherently summing the power values; This indicates that the square of the power value is incoherently accumulated.

[0066] Based on actual testing experience, this threshold A value between 8 and 10 is sufficient to meet the decision requirements. This formula is essentially a normalized detection statistic that adapts to changes in noise power. When a signal is present, the numerator (coherent cumulative energy) grows faster than the denominator (incoherent power sum), resulting in... The value increases significantly; when there is only noise, The value remained at a low level.

[0067] VII. Analysis and Parameter Configuration Explanation Based on Attached Figures about Figure 2 A detailed explanation of the relationship between the cumulative sequence length and frequency offset. Figure 2 The correlation peak amplitude and frequency offset are shown for different sequence lengths. The relationship curve has a symbol rate of 4.00 Msps.

[0068] The horizontal axis in the figure represents frequency offset. The units are in kHz; the vertical axis represents the normalized correlation peak amplitude. The dashed line indicates the 3dB threshold, i.e., the position where the amplitude is 0.707.

[0069] The curves correspond to The blue curve The red curve The yellow curve The purple curve and The green curve.

[0070] observe Figure 2 It can be seen that as the sequence length increases... As the value increases, the width of the main lobe of the curve narrows, which is consistent with the characteristics of the Sinc function.

[0071] when When the curve is extremely narrow, the frequency offset is only a few kHz, and the amplitude drops to below 0.7, indicating that the direct accumulation of long sequences is extremely sensitive to frequency offset.

[0072] when When the frequency offset reaches about 30kHz, the curve is the widest, and the amplitude only drops to 0.7, indicating the strongest resistance to frequency offset.

[0073] The yellow dots in the picture are marked The intersection of the curve with the 3dB threshold shows that at a frequency offset of about 8 to 10kHz, the amplitude of the traditional 256-point accumulation scheme has been attenuated to below 0.7, resulting in a significant frequency offset loss.

[0074] Although the total cumulative gain in the embodiments of the present invention reaches 256 times, corresponding to Energy accumulation, but through 64 segmentation, using similar methods The wideband characteristics of the blue curve and the differential mechanism effectively overcome the limitations of... Figure 2 The frequency offset limitation shown by the yellow curve in the middle achieves excellent performance with a frequency offset loss of less than 3dB at a frequency offset of 10kHz.

[0075] Summary of parameter configuration and explanation of higher-level implementation Symbol rate: 4 Msps.

[0076] Spread spectrum ratio: 1000 times, or 2000 times.

[0077] Frequency offset range: 10kHz.

[0078] Signal-to-noise ratio: -20dB.

[0079] Number of segments: 64.

[0080] Parallel accumulation series: two levels, i.e. structure.

[0081] It should be noted that the number of segments (64), accumulation multiplier (256), and clock frequency (300MHz) in the above embodiments are merely preferred parameters. In other embodiments of the present invention, the number of segments... The timing margin can be selected between 16 and 128, and the number of accumulation stages can be adjusted according to the signal-to-noise ratio requirements. As long as the segmented correlation and accumulation operations are completed within a single symbol period, they all fall within the protection scope of this invention.

[0082] VIII. Extended Implementation Examples To further illustrate the versatility of the embodiments of the present invention, several extended embodiments are provided below.

[0083] Example 2: Processing differences under QPSK modulation When the system uses QPSK modulation, the baseband signal contains two components: I-channel and Q-channel. In step 1, after ADC sampling, quadrature down-conversion is required to separate the I-channel and Q-channel data. In the segmented correlation operation in step 2, the local PN code needs to be correlated with both the I-channel and Q-channel data separately. In the calculation in step 4, the squares of the I-channel difference and the Q-channel difference need to be calculated separately and then added together. The remaining process is the same as BPSK modulation.

[0084] Example 3: Selection of Different Numbers of Segments While this embodiment preferably uses 64 segments, in other application scenarios, the number of segments may vary. It can be adjusted according to timing margin. If the system clock... Increasing to 600MHz, the number of clock cycles per symbol period... Increase to 150, at which point you can choose Segmentation. The more segments, the stronger the frequency offset resistance. (Reference) Figure 2 middle The curve is more demanding, but requires higher hardware parallelism. This invention utilizes a BRAM caching mechanism, allowing adjustments to the number of segments to be made only by modifying the read logic, without altering the core architecture.

[0085] Example 4: Adaptive FFT Point Count In step 5, the number of FFT points is usually the same as the number of segments, i.e., 64 points. However, in scenarios with a very large frequency offset, such as exceeding 20kHz, zero-padding can be performed on the peak-corresponding sequence to perform a 128-point or 256-point FFT, thereby improving the resolution of the frequency offset estimation. Zero-padding does not increase the signal energy, but it refines the spectrum, making the frequency offset compensation more accurate.

[0086] Compared with existing technologies, this invention provides a method for acquiring burst spread spectrum systems under low signal-to-noise ratio conditions. Through the synergistic innovation of multiple core technologies, it achieves significant progress and excellent engineering practical effects. Specifically, this invention has the following beneficial effects: First, this invention significantly reduces hardware resource overhead, successfully overcoming the resource bottleneck at high symbol rates. Addressing the problem of register resource explosion caused by traditional shift register architectures at high symbol rates of 4Msps and spread factor of 1000 to 2000 times, this invention innovatively replaces traditional shift registers with on-chip block random access memory (BRAM) within a field-programmable gate array (FPGA). By configuring the BRAM in a dual-port mode and a circular buffer, and utilizing a high-speed processing clock to poll and read data within a limited timing margin, the high-speed serial data stream is cleverly converted into a parallel data stream that can be efficiently processed by the hardware. This architecture design not only effectively meets the timing requirements of 64 parallel segmented correlation operations within a single symbol cycle, but also significantly reduces FPGA register resource overhead by more than 90% compared to traditional solutions, completely solving the technical bottleneck of hardware resource constraints under high spread factor conditions and providing a solid foundation for low-cost FPGA implementation.

[0087] Secondly, this invention possesses excellent resistance to large frequency offsets, achieving high resource control while ensuring robustness against frequency offsets. Addressing the pain points of continuous signal phase rotation and severe attenuation of correlation peaks caused by large frequency offsets on the order of 10kHz, this invention employs a mechanism combining PN code segmented correlation with differential operations on adjacent segments. Through short-sequence segmented integration, the attenuation impact of frequency offset on individual segmented correlation peaks is effectively reduced; simultaneously, differential operations completely cancel the first-order linear phase rotation error caused by Doppler frequency offset at its source, retaining only the effective signal information related to code phase delay. More importantly, this invention postpones the Fast Fourier Transform (FFT) frequency offset estimation to the peak selection stage, performing a single 64-point FFT operation only on the selected effective peak data sequence. This design completely eliminates the redundancy of traditional frequency sweeping combined with parallel slotting architectures that require dozens of parallel channels to handle large frequency offsets, achieving excellent performance with a frequency offset loss of less than 3dB at 10kHz while significantly reducing the FPGA logic and storage resource requirements.

[0088] Furthermore, this invention achieves stable acquisition in extremely low signal-to-noise ratio (SNR) environments, significantly improving weak signal detection and accumulation capabilities. Addressing the challenge of prolonged energy accumulation for bursty short frames, this invention designs a high-gain accumulation architecture with 64 segmented inputs and two-stage parallel accumulation. Through a tree structure where the 64 results are first accumulated in two parallel stages and then in two secondary stages, a spatial accumulation gain of approximately 24dB (256 times) is achieved within a single symbol period. This gain, combined with the inherent processing gain of 30dB to 33dB from 1000 to 2000 times spread spectrum, and after deducting the approximately 3dB performance loss introduced by differential operations, results in a comprehensive SNR improvement of 7dB to 10dB. This quantization gain successfully raises the original -20dB extremely low SNR signal above the acquisition decision threshold, meeting the high-probability acquisition requirements in harsh weak signal environments and ensuring the reliability of the communication link.

[0089] Finally, this invention is well adapted to the characteristics of bursty short frames, achieving extremely rapid acquisition within an extremely short window. The segmented parallel processing architecture adopted in this invention does not rely on long-term serial energy accumulation. The entire acquisition process, including code phase search, differential frequency offset resistance, power accumulation, and joint frequency offset estimation, can be completed within an extremely short window of no more than one symbol period, or 250ns. This short accumulation time mechanism is highly compatible with the physical characteristics of bursty communication—short frames, rapid changes, and one-time transmission—in high-speed maneuvering scenarios such as missile platforms. It effectively avoids the receiver missing fleeting acquisition opportunities due to processing delays, significantly improving the success rate of burst signal acquisition and the real-time response capability of the system.

[0090] In summary, this invention, through the synergistic application of four core technologies—BRAM low-resource architecture, two-level parallel accumulation, differential frequency offset resistance, and short window burst adaptation—simultaneously and perfectly satisfies the four stringent conditions of low signal-to-noise ratio, large frequency offset, high symbol rate, and burst, and has extremely high engineering practical value and broad prospects for promotion and application.

[0091] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for acquiring a burst spread spectrum system under low signal-to-noise ratio, characterized in that, Includes the following steps: Step 1, Signal preprocessing and buffering: The received burst spread spectrum signal is sampled, filtered and down-converted to obtain the baseband signal, and the baseband signal and local PN code are stored in the memory; Step 2, PN segment correlation operation: Divide the local PN code evenly into multiple sub-code segments, perform sliding correlation operation between each local PN code segment and the baseband data cached in the memory, and output the multi-channel segment correlation results; Step 3, Multi-level parallel accumulation: Perform two-level parallel accumulation on the multi-path segmentation correlation results to obtain the cumulative gain; Step 4, Differential and Power Accumulation: Perform differential operation on the data corresponding to adjacent sub-code segments after accumulation to eliminate the phase error introduced by frequency offset, calculate the sum of the squares of the I-path component and the squares of the Q-path component of the differential result, and accumulate the power values ​​of all channels to find the extreme value of the sequence. Step 5, Peak detection and frequency offset estimation: Compare the found extreme value with a preset threshold. If it exceeds the threshold, extract the accumulated data sequence corresponding to the extreme value and perform a fast Fourier transform operation on the sequence to obtain the frequency offset. Step 6, Frequency Offset Compensation and Output: Based on the solution results of the Fast Fourier Transform, complete the link frequency offset compensation and output the code phase and frequency offset information.

2. The method for acquiring a burst spread spectrum system at low signal-to-noise ratio according to claim 1, characterized in that, In step 2, the local PN code is divided into 64 sub-code segments; in step 3, the two-level parallel accumulation is as follows: the 64 segmented correlation results are first accumulated in two parallel channels, and then accumulated in two secondary channels. The single-channel accumulation gain reaches 4 times, the total number of data points participating in the accumulation reaches 256, and the corresponding total accumulation gain reaches 256 times.

3. The method for acquiring a burst spread spectrum system at low signal-to-noise ratio according to claim 1, characterized in that, In step 4, the formula for the difference operation is: ,in and The results are related to two adjacent segments; After differential operation, the first-order linear phase component caused by frequency offset is canceled out, and only the effective signal information related to code phase delay is retained.

4. The method for acquiring a burst spread spectrum system at low signal-to-noise ratio according to claim 1, characterized in that, In step 5, the preset threshold is determined using a formula. ,in The total number of data samples used in the judgment. Indicates the first The power value of each data sample point after differential operation is the sum of the squares of the I-path component and the Q-path component; the numerator represents the energy after coherent accumulation of the power values, and the denominator represents the energy after incoherent accumulation of the squares of the power values; when A value between 8 and 10 indicates a successful capture.

5. The method for acquiring a burst spread spectrum system at low signal-to-noise ratio according to claim 1, characterized in that, In step 5, the number of points in the Fast Fourier Transform operation is the same as the number of sub-code segments; the Fast Fourier Transform operation is only performed after the accumulated data sequence is extracted.

6. The method for acquiring a burst spread spectrum system at low signal-to-noise ratio according to claim 1, characterized in that, In step 1, the memory is a block random access memory on a field-programmable gate array (FPGA). The block random access memory is configured as a dual-port mode and a circular buffer, with one port used to write sampled data and the other port used to read data and perform related operations at the system processing clock.

7. The method for acquiring a burst spread spectrum system at low signal-to-noise ratio according to claim 6, characterized in that, The target symbol rate is 4 Msps, and the duration of a single symbol is 250 ns; the system processing clock frequency is 300 MHz, and the total number of system clocks contained in a single symbol period is 75; the number of sub-code segments is 64, which meets the segmentation processing requirement of no less than 64 clock cycles.

8. The method for acquiring a burst spread spectrum system at low signal-to-noise ratio according to claim 1, characterized in that, When the burst spread spectrum signal is QPSK modulated, in step 1, orthogonal downconversion is required to separate the I-channel and Q-channel data; in step 2, the local PN code is correlated with the I-channel and Q-channel data respectively; in step 4, the squares of the I-channel component difference and the squares of the Q-channel component difference are calculated and then added together.

9. The method for acquiring a burst spread spectrum system at low signal-to-noise ratio according to claim 1, characterized in that, The number of sub-code segments in step 2 is adjusted according to the system processing clock frequency; when the system processing clock frequency is increased, the number of sub-code segments is increased to improve the anti-frequency deviation capability.

10. The method for acquiring a burst spread spectrum system at low signal-to-noise ratio according to claim 1, characterized in that, In step 5, when the frequency offset range exceeds the preset value, zero-padding is performed on the accumulated data sequence to increase the number of points in the fast Fourier transform operation and improve the frequency offset estimation resolution.

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