Time synchronization method, device, system, apparatus and medium for distributed simulation

Abstract

The embodiment of the application discloses a kind of distributed simulation time synchronization method, device, system, equipment and medium, it is related to simulation technical field, the method comprises: first signal is sent to each slave node, the first signal includes first timestamp;Each sent first response is received, the first response is generated by each slave node in response to the first signal, and the first response includes second timestamp;Based on the first timestamp and the second timestamp, the one-way delay between the master node and each slave node is determined;Based on the one-way delay, the delay compensation parameter corresponding to each slave node is generated, and the corresponding delay compensation parameter is sent to each slave node, and the delay compensation parameter is used to calibrate the clock of the slave node.The embodiment of the application ensures the time consistency of virtual-real combined simulation data, and provides accurate time basis for fault detection and diagnosis.

Description

Technical Field

[0001] This application relates to the field of simulation technology, and more specifically, to a time synchronization method, apparatus, system, device, and medium for distributed simulation. Background Technology

[0002] Launch vehicles are expensive, and flight safety is crucial to their success. For spacecraft, especially reusable rockets, fault diagnosis using digital twin technology can accurately identify potential risks before flight, effectively preventing flight test failures. Currently, the mainstream method for assessing launch vehicle flight safety is to conduct hardware-in-the-loop (HIL) simulation tests involving some onboard components.

[0003] However, hardware-in-the-loop (HIL) simulation equipment and virtual simulation systems are often located in different regions, and the time asynchrony caused by geographically dispersed deployment becomes a bottleneck restricting the real-time performance of experiments. Data transmission latency will cause inaccurate or misaligned timestamps of each simulation node, significantly reducing the reliability of fault detection and diagnosis results and making it difficult to support efficient, long-distance collaborative joint experiments. Summary of the Invention

[0004] This application provides a time synchronization method, apparatus, system, device, and medium for distributed simulation to solve the time synchronization problem between remote systems in hardware-in-the-loop simulation experiments in the prior art.

[0005] According to a first aspect of the embodiments of this application, a time synchronization method for distributed simulation is provided. The method is applied to a distributed simulation system for an aircraft, the distributed simulation system including a master node and at least one slave node. The method is executed by the master node, and the method includes: Send a first signal to each slave node, the first signal including a first timestamp; Receive each transmitted first response, the first response being generated by each slave node in response to the first signal, the first response including a second timestamp; Based on the first timestamp and the second timestamp, the one-way delay between the master node and each slave node is determined; Based on the unidirectional delay, a delay compensation parameter is generated for each slave node, and the corresponding delay compensation parameter is sent to each slave node. The delay compensation parameter is used to calibrate the clock of the slave node.

[0006] As an optional implementation, sending a first signal to each slave node, the first signal including a first timestamp includes: The timing module obtains clock information sent by an external clock source and synchronizes the local clock source based on the clock information. Based on the synchronized local clock source, a first signal is generated and sent to the slave node. The first signal includes a first timestamp.

[0007] As an optional implementation, after generating the delay compensation parameters based on the unidirectional delay, the method further includes: Send at least one test data packet to each slave node, each data packet including a third timestamp, and each data packet having a different length; Receive response data packets sent by each slave node, each response data packet corresponding to a test data packet, and each response data packet including a fourth timestamp; Based on the third timestamp and the fourth timestamp, the transmission delay corresponding to data packets of different lengths is determined; The length of the data packets transmitted between the master node and the slave node is determined based on the transmission delay corresponding to data packets of different lengths.

[0008] As an optional implementation, determining the length of the data packets transmitted between the master node and the slave node based on the transmission delay corresponding to data packets of different lengths includes: A mapping table is constructed based on the identifier of each slave node, the length of the test data packet sent by the master node to the slave node, and the transmission delay corresponding to the test data packet of the corresponding length; Based on the mapping table, the length of the data packets transmitted between the master node and the slave node is determined.

[0009] As an optional implementation, determining the length of the data packets transmitted between the master node and the slave node based on the mapping table includes: Obtain the instruction cycle between the master node and the slave node; If the transmission delay corresponding to at least one data packet in the mapping table is less than the instruction period, the length of the data packet transmitted between the master node and the slave node is determined based on the length of the at least one data packet. If the transmission delay corresponding to all data packets in the mapping table is greater than or equal to the instruction period, the length of the data packets transmitted between the master node and the slave node is determined by a preset method.

[0010] As an optional implementation, the preset method includes at least one of the following: Reduce the length of data packets transmitted between the master node and the slave node; Increase the duration of the instruction cycle; Shorten the transmission distance between the master node and the slave node.

[0011] According to a second aspect of the embodiments of this application, a time synchronization method for distributed simulation is provided. The method is applied to a distributed simulation system for an aircraft, the distributed simulation system including a master node and at least one slave node. The method is executed by the slave node, and the method includes: Receive a first signal sent by the master node, the first signal including a first timestamp; In response to the first signal, a first response is generated, the first response including a second timestamp; The system receives delay compensation parameters sent by the master node and calibrates the local clock based on the delay compensation parameters; wherein the delay compensation parameters are generated based on the one-way delay between the master node and the slave node, and the one-way delay is determined based on the first timestamp and the second timestamp.

[0012] As an optional implementation, after calibrating the local clock based on the delay compensation parameters, the method further includes: Receive at least one test data packet sent by the master node, and each test data packet includes a third timestamp; In response to the at least one test data packet, at least one response data packet is sent to the master node, each response data packet corresponding to a test data packet, and each response data packet including a fourth timestamp.

[0013] According to a third aspect of the embodiments of this application, a time synchronization device for distributed simulation is provided, the device being applied to the master node of a distributed simulation system, the device comprising: The first transceiver module is used to send a first signal to each slave node, the first signal including a first timestamp; The second transceiver module is used to receive each transmitted first response, the first response being generated by each slave node in response to the first signal, and the first response including a second timestamp; The first processing module is used to determine the one-way delay between the master node and each slave node based on the first timestamp and the second timestamp; The second processing module is used to generate a delay compensation parameter for each slave node based on the one-way delay, and send the corresponding delay compensation parameter to each slave node. The delay compensation parameter is used to calibrate the clock of the slave node.

[0014] According to a fourth aspect of the embodiments of this application, a time synchronization device for distributed simulation is provided, the device being applied to a slave node of a distributed simulation system, the device comprising: The third transceiver module is used to receive a first signal sent by the master node, the first signal including a first timestamp; The third processing module is used to generate a first response in response to the first signal, wherein the first response includes a second timestamp; The fourth transceiver module is used to receive the delay compensation parameters sent by the master node and calibrate the local clock based on the delay compensation parameters; wherein the delay compensation parameters are generated based on the one-way delay between the master node and the slave node, and the one-way delay is determined based on the first timestamp and the second timestamp.

[0015] According to a fifth aspect of the embodiments of this application, a time synchronization system for distributed simulation is provided, the system comprising a master node and at least one slave node; The master node sends a first signal to each slave node and receives a first response from each slave node in response to the first signal. The first signal includes a first timestamp, and the first response includes a second timestamp. Based on the first timestamp and the second timestamp, the master node determines the one-way delay between itself and each slave node, generates a delay compensation parameter for each slave node based on the one-way delay, and sends the corresponding delay compensation parameter to each slave node. Each slave node receives a first signal sent by the master node and generates a first response in response to the first signal, the first signal including a first timestamp and the first response including a second timestamp; and receives a delay compensation parameter sent by the master node and calibrates its local clock based on the delay compensation parameter.

[0016] According to a sixth aspect of the embodiments of this application, an electronic device is provided, including: a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the method of any one of the first and second aspects.

[0017] According to a seventh aspect of the present application, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the method as described in any one of the first and second aspects.

[0018] The beneficial effects of the technical solutions provided in this application are: This application provides a time synchronization method, apparatus, system, device, and medium for distributed simulation. In this embodiment, the master node determines the one-way delay between the master node and each slave node by sending a first signal with a first timestamp to each slave node and receiving a first response with a second timestamp from each slave node. Based on this one-way delay, a delay compensation parameter is generated and sent to each slave node, thereby achieving time synchronization of all nodes and providing a precise time basis for fault detection and diagnosis. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below.

[0020] Figure 1 This application provides a schematic diagram of the architecture of a distributed simulation system. Figure 2 A flowchart illustrating a time synchronization method for distributed simulation provided in this application embodiment; Figure 3 A flowchart illustrating another time synchronization method for distributed simulation provided in this application embodiment; Figure 4 A schematic diagram of a time synchronization device for distributed simulation provided in this application embodiment; Figure 5 A schematic diagram of another distributed simulation time synchronization device provided in this application embodiment; Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0021] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0022] Those skilled in the art will understand that, unless otherwise stated, the singular forms “a,” “an,” and “the” used herein may also include the plural forms. It should be further understood that the terms “comprising” and “including” as used in embodiments of this application mean that the corresponding feature can be implemented as the presented feature, information, data, step, operation, element, and / or component, but do not exclude implementation as other features, information, data, step, operation, element, component, and / or combinations thereof supported by the art. It should be understood that when we say that an element is “connected” or “coupled” to another element, the one element can be directly connected or coupled to the other element, or it can mean that the one element and the other element establish a connection relationship through an intermediate element. Furthermore, “connected” or “coupled” as used herein can include wireless connection or wireless coupling. The term “and / or” as used herein indicates at least one of the items defined by the term; for example, “A and / or B” can be implemented as “A,” or as “B,” or as “A and B.”

[0023] In the embodiments of this application, the terms "module" or "unit" refer to a computer program or part of a computer program that has a predetermined function and works with other related parts to achieve a predetermined goal, and can be implemented wholly or partially using software, hardware (such as processing circuitry or memory), or a combination thereof. Similarly, a processor (or multiple processors or memory) can be used to implement one or more modules or units. Furthermore, each module or unit can be part of an overall module or unit that includes the functionality of that module or unit.

[0024] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0025] Launch vehicles are expensive, and flight safety is crucial to their success. For spacecraft, especially reusable rockets, fault diagnosis using digital twin technology can accurately identify potential risks before flight, effectively preventing flight test failures. Currently, the mainstream method for assessing launch vehicle flight safety is to conduct hardware-in-the-loop (HIL) simulation tests involving some onboard components.

[0026] However, hardware-in-the-loop (HIL) simulation equipment and virtual simulation systems are often located in different regions, and the time asynchrony caused by geographically dispersed deployment becomes a bottleneck restricting the real-time performance of experiments. Data transmission latency will cause inaccurate or misaligned timestamps of each simulation node, significantly reducing the reliability of fault detection and diagnosis results and making it difficult to support efficient, long-distance collaborative joint experiments.

[0027] The time synchronization method, apparatus, electronic device, and computer-readable storage medium for distributed simulation provided in this application aim to solve the above-mentioned technical problems of the prior art.

[0028] The technical solutions of this application and their effects are described below through several exemplary embodiments. It should be noted that the following embodiments can be referenced, borrowed from, or combined with each other. Identical terms, similar features, and similar implementation steps in different embodiments will not be repeated.

[0029] Figure 1 This is a schematic diagram of the architecture of a distributed simulation system provided in an embodiment of this application; as shown in the figure, the distributed simulation system includes a master node 1, slave node 1, slave node 2 and slave node 3; wherein, the master node can be a physical real-time simulation system 1, slave node 1 can be a physical real-time simulation system 2, slave node 2 can be a physical real-time simulation system 3, and slave node 3 can be a virtual real-time simulation system 1. In some embodiments, the physical real-time simulation system 2 is configured with a three-axis turntable, which is used to simulate the attitude angles sensed and output by the inertial measurement unit in real time.

[0030] In some embodiments, the physical real-time simulation system 2 deploys a three-axis turntable to simulate the real-time attitude angles of the inertial navigation system.

[0031] In some embodiments, the physical real-time simulation system 3 is set on the test stand. The system collects the real-time sway angle generated by the actual engine test on the test stand, or the real-time sway angle generated by the engine load simulator simulating the load characteristics of the nozzle flight test conditions.

[0032] In some embodiments, the virtual real-time simulation system 1 serves as a digital twin platform, in which all models related to rocket launch are built, such as the Earth environment model, launch site model, measurement and control model, and rocket body model. Each model includes, but is not limited to, mathematical models, 3D physical models, etc.

[0033] In some embodiments, to obtain accurate timestamps, a time synchronization module is installed in the simulation computer of the physical real-time simulation system 1, through which accurate UTC timestamps can be obtained. Simultaneously, the master node and slave nodes are connected to a switch via optical fiber, and the switch transmits the UTC time to each slave node.

[0034] It should be noted that, in the embodiments of this application, the number and type of slave nodes can be adjusted according to the needs of the simulation experiment, and are not limited to the situations listed in the specification or figures of this application.

[0035] Figure 2 This application provides a flowchart illustrating a time synchronization method for distributed simulation. The method is applied to a distributed simulation system for an aircraft, which includes a master node and at least one slave node. The method is executed by the master node and includes: S201. Send a first signal to each slave node, the first signal including a first timestamp.

[0036] Specifically, in this embodiment of the application, the distributed simulation system is built on a unified local area network. To ensure the uniformity of time synchronization, the distributed simulation system includes a single master node, which provides a globally unified absolute timestamp reference; the remaining nodes act as slave nodes, and complete their own clock calibration based on the master node's time reference.

[0037] Specifically, in this embodiment of the application, the master node calibrates its local clock using a GPS or BeiDou timing module and sends a first signal to each slave node. The first signal encapsulates a first timestamp, which is the local time when the master node sends the first signal.

[0038] In some embodiments, the first signal is a clock frequency standard signal, which is output by the master node and distributed to each slave node via a switch.

[0039] S202, Receive each transmitted first response, the first response being generated by each slave node in response to the first signal, the first response including a second timestamp.

[0040] Specifically, in this embodiment, the system clock of each slave node is set to an external frequency standard, waiting for the master node's frequency standard to arrive. According to the relevant clock synchronization protocol, each slave node immediately sends a first response to the master node upon receiving the clock frequency standard signal for the first time. The first response includes a second timestamp, which is the local time when the slave node receives the first signal.

[0041] S203. Based on the first timestamp and the second timestamp, determine the one-way delay between the master node and each slave node.

[0042] Specifically, in this embodiment of the application, the master node subtracts the first timestamp carried by the first signal from the second timestamp carried by the first response to obtain the one-way delay between the master node and the slave node.

[0043] S204. Based on the unidirectional delay, generate a delay compensation parameter corresponding to each slave node, and send the corresponding delay compensation parameter to each slave node. The delay compensation parameter is used to calibrate the clock of the slave node.

[0044] Specifically, in this embodiment, the master node generates a delay compensation parameter based on the one-way delay with each slave node, and feeds the delay compensation parameter back to the corresponding slave node; the slave node adjusts its own clock according to the delay compensation parameter, and finally achieves time synchronization of all nodes.

[0045] In this embodiment, the master node determines the one-way delay between the master node and each slave node by sending a first signal with a first timestamp to each slave node and receiving a first response with a second timestamp from each slave node. Based on this one-way delay, a delay compensation parameter is generated and sent to each slave node, thereby synchronizing the local clock of each slave node with the time of the master node and providing an accurate time basis for fault detection and diagnosis.

[0046] Based on the above embodiments, as an optional embodiment, sending a first signal to each slave node, wherein the first signal includes a first timestamp, includes: The timing module obtains clock information sent by an external clock source and synchronizes the local clock source based on the clock information. Based on the synchronized local clock source, a first signal is generated and sent to the slave node. The first signal includes a first timestamp.

[0047] Specifically, in this embodiment of the application, the simulation computer of the master node is equipped with a time synchronization module. Through this time synchronization module, clock information sent by an external clock source can be received. The clock information includes high-precision UTC time, which enables high-precision synchronization between the master node's local clock and the external clock source.

[0048] Specifically, in this embodiment of the application, after completing the local clock source synchronization calibration, the master node generates a first signal carrying a first timestamp based on the local clock, and then sends the first signal to each slave node.

[0049] This application embodiment completes local clock calibration through a timing module, avoiding timing errors caused by the master node's own clock drift, and providing a reliable time origin for timing synchronization of all nodes in the network.

[0050] Based on the above embodiments, as an optional embodiment, after generating the delay compensation parameters based on the unidirectional delay, the method further includes: Send at least one test data packet to each slave node, each data packet including a third timestamp, and each data packet having a different length; Receive response data packets sent by each slave node, each response data packet corresponds to a test data packet, and each response data packet includes a fourth timestamp; Based on the third timestamp and the fourth timestamp, the transmission delay corresponding to data packets of different lengths is determined; The length of the data packets transmitted between the master node and the slave node is determined based on the transmission delay corresponding to data packets of different lengths.

[0051] Specifically, in this embodiment of the application, after the master node and slave nodes complete time synchronization, it is necessary to determine the throughput of data interaction between the master node and each slave node, so as to ensure that the operation does not time out within a single simulation cycle.

[0052] In some embodiments, the data transmission delay between the master node and the slave node must not exceed the iteration cycle of the rocket body or flight control system; otherwise, the simulation system will experience distortion of simulation results due to the transmission delay.

[0053] In some embodiments, the master node sends test data packets of different bytes to each slave node. Each test data packet includes a third timestamp, which is the local time when the master node sent the test data packet. After receiving the test data packet sent by the master node, the slave node generates a response data packet, which includes a fourth timestamp, which is the local time when the slave node received the test data packet.

[0054] In some embodiments, the master node determines the transmission delay corresponding to data packets of different lengths based on the third and fourth timestamps, and determines the length of the data packets transmitted between the master node and the slave node based on the transmission delay.

[0055] In some embodiments, the length of the data packets transmitted between the master node and the slave node can be selected according to the actual time consumption of different systems. If the transmission delay is less than the rocket body or flight control cycle, it means that the construction of the remote real-time simulation system can be completed. Conversely, if the transmission delay is greater than or equal to the rocket body or flight control cycle, it is theoretically impossible to complete the construction of the remote real-time simulation system. It is necessary to reduce the number of bytes transmitted per packet or shorten the distance between the two nodes in the optical fiber network.

[0056] This application uses multi-length test data packets to conduct link delay tests, eliminating the computation timeout problem caused by excessively long transmission time of large data packets at the message transmission level, and effectively improving the real-time performance and accuracy of hardware-in-the-loop simulation.

[0057] Based on the above embodiments, as an optional embodiment, determining the length of the data packets transmitted between the master node and the slave node based on the transmission delay corresponding to data packets of different lengths includes: A mapping table is constructed based on the identifier of each slave node, the length of the test data packet sent by the master node to the slave node, and the transmission delay corresponding to the test data packet of the corresponding length; Based on the mapping table, the length of the data packets transmitted between the master node and the slave node is determined.

[0058] Specifically, in this embodiment of the application, the mapping table consists of a three-dimensional array. The first dimension array is the slave node identifier, which is used to record the slave node to which the data belongs. The second dimension array is the length of the data packet sent from the master node to the slave node (usually the number of bytes in the data packet). The third dimension array is the transmission delay from the master node to the slave node (i.e., the one-way time consumption corresponding to the length of the data packet).

[0059] This can be understood as follows: the mapping table fully records the transmission delay of the master node and slave node in the semi-physical simulation system under different message payloads. Combined with constraints such as the flight control iteration cycle and the duration of a single simulation cycle, the maximum length of the transmission delay that meets the requirements is selected from the mapping table, thereby determining the length of the data packets used in the data interaction process between the master node and slave node.

[0060] This application embodiment quickly filters out data packet lengths that meet real-time requirements by constructing a mapping table, avoiding problems such as simulation calculation anomalies and simulation result distortion caused by excessively large data packets and transmission timeouts, thus ensuring the real-time performance of the simulation system.

[0061] Based on the above embodiments, as an optional embodiment, determining the length of the data packet transmitted between the master node and the slave node based on the mapping table includes: Obtain the instruction cycle between the master node and the slave node; If the transmission delay corresponding to at least one data packet in the mapping table is less than the instruction period, the length of the data packet transmitted between the master node and the slave node is determined based on the length of the at least one data packet. If the transmission delay corresponding to all data packets in the mapping table is greater than or equal to the instruction period, the length of the data packets transmitted between the master node and the slave node is determined by a preset method.

[0062] Specifically, in this embodiment, the flight control command cycle corresponding to the interaction between the master node and the slave node under the current simulation condition is read. This command cycle is a real-time constraint threshold pre-configured by the system. Then, the pre-built mapping table is retrieved to obtain the length of all data packets associated with the slave node identifier and the corresponding transmission delay. If the transmission delay corresponding to any data packet length in the mapping table is less than the duration of the flight control command cycle, then the length of the data packet is determined to be the length of the data packet transmitted between the master node and the slave node.

[0063] In some embodiments, when multiple data packet lengths in the mapping table correspond to transmission delays less than the duration of a flight control command cycle, the maximum value among these data packet lengths is determined as the length of the data packet transmitted between the master node and the slave node. For example, if the data packet length is 16 bytes, and the transmission delays corresponding to 32 bytes and 64 bytes are both less than the duration of a flight control command cycle, then 64 bytes is chosen as the length of the data packet transmitted between the master node and the slave node.

[0064] In some embodiments, if after traversal it is found that the transmission delay corresponding to the length of all data packets recorded in the mapping table is greater than or equal to the flight control command cycle, it indicates that the length of the existing test messages cannot meet the requirements of real-time interaction. At this time, the system will use a preset method to determine the length of the data packets transmitted between the master node and the slave node.

[0065] In some embodiments, the business control logic and closed-loop iteration rate of different types of slave nodes differ significantly. Therefore, the instruction cycle between the master node and different types of slave nodes can be set to be the same, or it can be configured to be different according to the simulation requirements. When the instruction cycle differs, the maximum allowable transmission latency of the slave nodes also differs, that is, the length of the data packets transmitted between the master node and different slave nodes can be different. For slave nodes with shorter instruction cycles and higher real-time requirements, the system will select smaller data packets with lower transmission time to ensure that the network transmission latency does not exceed the strict cycle constraints; for slave nodes with longer instruction cycles and sufficient latency margin, larger data packets can be selected to reduce the frequency of message transmission and reception, improve the overall data transmission efficiency, and realize differentiated and refined network transmission management for various simulation devices.

[0066] The following will illustrate this with specific examples.

[0067] Example 1: The slave node is a physical real-time simulation system. The three-axis turntable receives rotation commands from the simulator, and the attitude measurement data output by the inertial navigation system is transmitted back to the master node. The turntable command cycle is 1ms, the inertial navigation system acquisition cycle is 10ms, and 3 double-precision floating-point numbers are transmitted unidirectionally in each minimum cycle, with a total data volume of 24 bytes. The unidirectional delay of the 24-byte data transmission between the master node and the physical real-time simulation system is 1.83ms, which does not meet the closed-loop requirement of a 1ms turntable command cycle.

[0068] Example 2: The slave node is a physical real-time simulation system. The flight control computer sends servo actuator swing angle commands to the engine test stand and load simulator. The engine test stand and load simulator then transmit the measured swing angle data back to the flight control computer. The servo command cycle is 10ms, the servo feedback reception cycle is 1ms, and two double-precision floating-point numbers are transmitted unidirectionally in each minimum cycle, with a total data volume of 16 bytes. The unidirectional delay of the 16-byte data transmission between the master node and the physical real-time simulation system is 1.22ms, which does not meet the closed-loop requirement of a 1ms turntable command cycle.

[0069] This application embodiment iterates through the transmission delay corresponding to each message length in the mapping table and compares it with the flight control command cycle to ensure that the transmission time of a single message is less than the system's real-time limit. This avoids problems such as simulation operation interruption, output data corruption, and simulation result distortion caused by the network transmission time exceeding the iteration cycle, effectively ensuring the operational stability of the hardware-in-the-loop simulation system.

[0070] Based on the above embodiments, as an optional embodiment, the preset method includes at least one of the following: Reduce the length of data packets transmitted between the master node and the slave node; Increase the duration of the instruction cycle; Shorten the transmission distance between the master node and the slave node.

[0071] In some embodiments, when the transmission delay corresponding to all data packets of all lengths in the mapping table is greater than the duration of the instruction cycle, the length of the data packets transmitted between the master node and the slave node can be reduced, that is: by reducing the length of the data packets transmitted between the master node and the slave node, the transmission delay is made less than the duration of the instruction cycle.

[0072] It's important to note that there's a lower limit to the length of data packets transmitted between the master and slave nodes. This lower limit is determined by fixed overhead bytes in the Ethernet underlying communication protocol frame header, checksum field, and synchronization flag. In other words, the length of data packets transmitted between the master and slave nodes cannot be less than this lower limit. Therefore, when reducing the length of data packets transmitted between the master and slave nodes, it's necessary to verify that this length is greater than or equal to the minimum data packet length, i.e., the lower limit of the data packet length.

[0073] In some embodiments, when the transmission delay corresponding to all data packets of all lengths in the mapping table is greater than the duration of the instruction cycle, the duration of the instruction cycle can be increased to make the transmission delay less than the duration of the instruction cycle.

[0074] In some embodiments, when the transmission delay corresponding to all data packets of all lengths in the mapping table is greater than the duration of the instruction cycle, the transmission distance between the master node and the slave node can be shortened, and the transmission delay between the master node and the slave node can be reduced, thereby making the transmission delay less than the duration of the instruction cycle.

[0075] This application embodiment ensures that the data transmission delay is less than the iteration cycle of the rocket body or flight control system by reducing the length of the transmitted data packets, increasing the duration of the command cycle, and shortening the transmission distance between the master node and the slave node. This avoids the distortion of simulation results caused by data delay, ensures the real-time response performance of the virtual-real combined simulation test, and improves the reliability and credibility of the test results.

[0076] Figure 3 A flowchart illustrating another time synchronization method for distributed simulation provided in this application embodiment; the method is applied to a distributed simulation system for an aircraft, the distributed simulation system including a master node and at least one slave node; the method is executed by the slave node, and the method includes: S301. Receive a first signal sent by the master node, wherein the first signal includes a first timestamp.

[0077] Specifically, in this embodiment of the application, the first signal is a clock frequency standard signal, which is output by the master node and distributed to each slave node via a switch.

[0078] S302. In response to the first signal, generate a first response, the first response including a second timestamp.

[0079] Specifically, in this embodiment of the application, after receiving the first signal, the slave node immediately responds to the first signal and generates a first response. The first response includes a second timestamp, which is the local time when the slave node receives the first signal.

[0080] S303. Receive the delay compensation parameters sent by the master node, and calibrate the local clock based on the delay compensation parameters; wherein, the delay compensation parameters are generated based on the one-way delay between the master node and the slave node, and the one-way delay is determined based on the first timestamp and the second timestamp.

[0081] Specifically, in this embodiment, the slave node receives the delay compensation parameters sent by the master node, and performs overall offset compensation on the local clock reference according to the one-way delay deviation of the link corresponding to the delay compensation parameters. This corrects the inherent time difference caused by fiber optic transmission and switch forwarding, gradually smooths out the timing gap between its own timing and the master node's standard clock, and completes the time synchronization between the local clock and the master node's reference clock.

[0082] In some embodiments, the delay compensation parameters sent from the master node to each slave node are not fixed and uniform values, but are calculated and generated independently for each slave node. The generation is based on the measured one-way delay between the master node and the corresponding slave node; wherein, the one-way delay is calculated based on a first timestamp and a second timestamp. Specifically, the master node extracts the time information corresponding to the two sets of timestamps, calculates the one-way link delay caused by the master node transmitting a message to the slave node through difference calculation, and then combines it with the system clock compensation algorithm to obtain the exclusive delay compensation parameters adapted to the link and sends them to the corresponding slave node.

[0083] In this embodiment, the master node uses the absolute timestamp of the first response generated by each slave node to accurately calculate the one-way time delay between each slave node and the master node, and feeds back the delay compensation parameter to the corresponding slave node; the slave node adjusts its own clock according to the delay compensation parameter, and finally realizes the time synchronization of all nodes, providing an accurate time basis for fault detection and diagnosis.

[0084] Based on the above embodiments, as an optional embodiment, after calibrating the local clock based on the delay compensation parameters, the following is further included: Receive at least one test data packet sent by the master node, and each test data packet includes a third timestamp; In response to the at least one test data packet, at least one response data packet is sent to the master node, each response data packet corresponding to a test data packet, and each response data packet including a fourth timestamp.

[0085] Specifically, in this embodiment, the slave node receives at least one test data packet sent by the master node. In other words, the master node generates multiple test data packets of different lengths according to the business data interaction scenario of the simulation system, and each test data packet is encapsulated with a unique corresponding third timestamp. The third timestamp is generated based on the standard clock calibrated by the master node, accurately recording the time when the master node generates the test data packet, and providing an accurate transmission timing reference for subsequent latency calculation.

[0086] Specifically, in this embodiment, after receiving any test data packet, the slave node triggers an acknowledgment mechanism to generate a unique acknowledgment data packet for each received test data packet. Simultaneously, based on its synchronized local clock, the slave node writes a corresponding fourth timestamp into each acknowledgment data packet. This fourth timestamp represents the moment the slave node received the corresponding test data packet. The slave node promptly sends the acknowledgment data packet containing the fourth timestamp back to the master node, providing comprehensive and accurate measured timing data support for the master node's subsequent calculation of the transmission delay of different data packets and the construction of delay mapping relationships.

[0087] In this embodiment, the third and fourth timestamps are both timestamps generated after time synchronization. There is no timing difference caused by the clock drift of the master and slave nodes themselves. The calculated transmission delay simply reflects the actual time consumption generated by the network link, switch forwarding, and packet payload, which greatly improves the accuracy of the delay calculation results.

[0088] Figure 4 This application provides a schematic diagram of the structure of a time synchronization device for distributed simulation. The device is applied to the master node of a distributed simulation system and includes: a first transceiver module 4001, a second transceiver module 4002, a first processing module 4003, and a second processing module 4004; wherein: The first transceiver module 4001 is used to send a first signal to each slave node, the first signal including a first timestamp; The second transceiver module 4002 is used to receive each transmitted first response, the first response being generated by each slave node in response to the first signal, and the first response including a second timestamp; The first processing module 4003 is used to determine the one-way delay between the master node and each slave node based on the first timestamp and the second timestamp; The second processing module 4004 is used to generate a delay compensation parameter for each slave node based on the one-way delay, and send the corresponding delay compensation parameter to each slave node. The delay compensation parameter is used to calibrate the clock of the slave node.

[0089] The time synchronization device for distributed simulation applied to the master node provided in this application embodiment can execute the time synchronization method for distributed simulation applied to the master node provided in this application embodiment. The implementation principle is similar. The actions performed by each module in the time synchronization device for distributed simulation applied to the master node provided in each embodiment of this application correspond to the steps in the time synchronization method for distributed simulation applied to the master node provided in each embodiment of this application. For detailed functional descriptions of each module of the time synchronization device for distributed simulation applied to the master node, please refer to the descriptions in the corresponding methods shown above, which will not be repeated here.

[0090] Figure 5 This application provides a schematic diagram of another distributed simulation time synchronization device according to an embodiment of the present application; the device is applied to a slave node of a distributed simulation system, and the device includes: a third transceiver module 5001, a third processing module 5002, and a fourth transceiver module 5003; wherein: The third transceiver module 5001 is used to receive a first signal sent by the master node, the first signal including a first timestamp; The third processing module 5002 is used to generate a first response in response to the first signal, wherein the first response includes a second timestamp; The fourth transceiver module 5003 is used to receive the delay compensation parameters sent by the master node and calibrate the local clock based on the delay compensation parameters; wherein the delay compensation parameters are generated based on the one-way delay between the master node and the slave node, and the one-way delay is determined based on the first timestamp and the second timestamp.

[0091] The time synchronization device for distributed simulation of slave nodes provided in this application can execute the time synchronization method for distributed simulation of slave nodes provided in this application. The implementation principles are similar. The actions performed by each module in the time synchronization device for distributed simulation of slave nodes provided in each embodiment of this application correspond to the steps in the time synchronization method for distributed simulation of slave nodes provided in each embodiment of this application. For detailed functional descriptions of each module in the time synchronization device for distributed simulation of slave nodes, please refer to the descriptions in the corresponding methods shown above, which will not be repeated here.

[0092] In this embodiment, the master node determines the one-way delay between the master node and each slave node by sending a first signal with a first timestamp to each slave node and receiving a first response with a second timestamp from each slave node. Based on this one-way delay, a delay compensation parameter is generated and sent to each slave node, thereby achieving time synchronization of all nodes and providing an accurate time basis for fault detection and diagnosis.

[0093] Furthermore, this application embodiment ensures that the data transmission delay is less than the iteration cycle of the rocket body or flight control system by reducing the length of the transmitted data packets, increasing the duration of the instruction cycle, and shortening the transmission distance between the master node and the slave node. This avoids the distortion of simulation results caused by data delay, ensures the real-time response performance of the virtual-real combined simulation test, and improves the reliability and credibility of the test results.

[0094] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, such as... Figure 6 As shown, the electronic device 6000 includes a processor 6001 and a memory 6003. The processor 6001 and the memory 6003 are connected, for example, via a bus 6002. Optionally, the electronic device 6000 may further include a transceiver 6004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 6004 is not limited to one type, and the structure of the electronic device 6000 does not constitute a limitation on the embodiments of this application.

[0095] Processor 6001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), a FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 6001 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0096] Bus 6002 may include a pathway for transmitting information between the aforementioned components. Bus 6002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. Bus 6002 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 6 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0097] The memory 6003 may be ROM (Read-Only Memory) or other types of static storage devices capable of storing static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices capable of storing information and instructions, or EEPROM (Electrically Erasable Programmable Read-Only Memory), CD-ROM (Compact Disc Read-Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media, other magnetic storage devices, or any other medium capable of carrying or storing computer programs and capable of being read by a computer, without limitation herein.

[0098] The memory 6003 stores computer programs that execute embodiments of this application, and its execution is controlled by the processor 6001. The processor 6001 executes the computer programs stored in the memory 6003 to implement the steps shown in the foregoing method embodiments.

[0099] The electronic device package may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital radio receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), and in-vehicle terminals (such as in-vehicle navigation terminals), as well as fixed terminals such as digital TVs and desktop computers. Figure 6 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of use of the embodiments disclosed herein.

[0100] This application provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement the steps and corresponding content of the aforementioned method embodiments.

[0101] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium, a computer-readable medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0102] This application also provides a computer program product, including a computer program that, when executed by a processor, can implement the steps and corresponding content of the aforementioned method embodiments.

[0103] The terms "first," "second," "third," "fourth," "1," "2," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown in the illustrations or text descriptions.

[0104] It should be understood that although arrows indicate various operation steps in the flowcharts of this application's embodiments, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of this application's embodiments, the implementation steps in each flowchart can be executed in other orders as required. Furthermore, some or all steps in each flowchart, based on the actual implementation scenario, may include multiple sub-steps or multiple stages. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage can also be executed at different times. In scenarios where execution times differ, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and this application's embodiments do not limit this.

[0105] The above are only optional implementation methods for some implementation scenarios of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application, without departing from the technical concept of this application, also fall within the protection scope of the embodiments of this application.

Claims

1. A time synchronization method for distributed simulation, characterized in that, The method is applied to a distributed simulation system for an aircraft, the distributed simulation system including a master node and at least one slave node; The method is executed by the master node, and the method includes: Send a first signal to each slave node, the first signal including a first timestamp; Receive each transmitted first response, the first response being generated by each slave node in response to the first signal, the first response including a second timestamp; Based on the first timestamp and the second timestamp, the one-way delay between the master node and each slave node is determined; Based on the unidirectional delay, a delay compensation parameter is generated for each slave node, and the corresponding delay compensation parameter is sent to each slave node. The delay compensation parameter is used to calibrate the clock of the slave node.

2. The time synchronization method for distributed simulation according to claim 1, characterized in that, Sending a first signal to each slave node, the first signal including a first timestamp includes: The timing module obtains clock information sent by an external clock source and synchronizes the local clock source based on the clock information. Based on the synchronized local clock source, a first signal is generated and sent to the slave node. The first signal includes a first timestamp.

3. The time synchronization method for distributed simulation according to claim 1 or 2, characterized in that, After generating the delay compensation parameters based on the unidirectional delay, the process further includes: Send at least one test data packet to each slave node, each data packet including a third timestamp, and each data packet having a different length; Receive response data packets sent by each slave node. Each response data packet corresponds to a test data packet, and each response data packet includes a fourth timestamp. Based on the third timestamp and the fourth timestamp, the transmission delay corresponding to data packets of different lengths is determined; The length of the data packets transmitted between the master node and the slave node is determined based on the transmission delay corresponding to data packets of different lengths.

4. The time synchronization method for distributed simulation according to claim 3, characterized in that, Determining the length of data packets transmitted between the master node and the slave node based on the transmission delay corresponding to data packets of different lengths includes: A mapping table is constructed based on the identifier of each slave node, the length of the test data packet sent by the master node to the slave node, and the transmission delay corresponding to the test data packet of the corresponding length; Based on the mapping table, the length of the data packets transmitted between the master node and the slave node is determined.

5. The time synchronization method for distributed simulation according to claim 4, characterized in that, Determining the length of the data packets transmitted between the master node and the slave node based on the mapping table includes: Obtain the instruction cycle between the master node and the slave node; If the transmission delay corresponding to at least one data packet in the mapping table is less than the instruction period, the length of the data packet transmitted between the master node and the slave node is determined based on the length of the at least one data packet. If the transmission delay corresponding to all data packets in the mapping table is greater than or equal to the instruction period, the length of the data packets transmitted between the master node and the slave node is determined by a preset method.

6. The time synchronization method for distributed simulation according to claim 5, characterized in that, The preset method includes at least one of the following: Reduce the length of data packets transmitted between the master node and the slave node; Increase the duration of the instruction cycle; Shorten the transmission distance between the master node and the slave node.

7. A time synchronization method for distributed simulation, characterized in that, The method is applied to a distributed simulation system for an aircraft, the distributed simulation system including a master node and at least one slave node; The method is executed by the slave node, and the method includes: Receive a first signal sent by the master node, the first signal including a first timestamp; In response to the first signal, a first response is generated, the first response including a second timestamp; The system receives delay compensation parameters sent by the master node and calibrates the local clock based on the delay compensation parameters; wherein the delay compensation parameters are generated based on the one-way delay between the master node and the slave node, and the one-way delay is determined based on the first timestamp and the second timestamp.

8. The time synchronization method for distributed simulation according to claim 7, characterized in that, After calibrating the local clock based on the delay compensation parameters, the process also includes: Receive at least one test data packet sent by the master node, and each test data packet includes a third timestamp; In response to the at least one test data packet, at least one response data packet is sent to the master node, each response data packet corresponding to a test data packet, and each response data packet including a fourth timestamp.

9. A time synchronization device for distributed simulation, characterized in that, The device is applied to the master node of a distributed simulation system, and the device includes: The first transceiver module is used to send a first signal to each slave node, the first signal including a first timestamp; The second transceiver module is used to receive each transmitted first response, the first response being generated by each slave node in response to the first signal, and the first response including a second timestamp; The first processing module is used to determine the one-way delay between the master node and each slave node based on the first timestamp and the second timestamp; The second processing module is used to generate a delay compensation parameter for each slave node based on the one-way delay, and send the corresponding delay compensation parameter to each slave node. The delay compensation parameter is used to calibrate the clock of the slave node.

10. A time synchronization device for distributed simulation, characterized in that, The device is applied to a slave node of a distributed simulation system, and the device includes: The third transceiver module is used to receive a first signal sent by the master node, the first signal including a first timestamp; The third processing module is used to generate a first response in response to the first signal, wherein the first response includes a second timestamp; The fourth transceiver module is used to receive the delay compensation parameters sent by the master node and calibrate the local clock based on the delay compensation parameters; wherein the delay compensation parameters are generated based on the one-way delay between the master node and the slave node, and the one-way delay is determined based on the first timestamp and the second timestamp.

11. A time synchronization system for distributed simulation, characterized in that, The system includes a master node and at least one slave node; The master node sends a first signal to each slave node and receives a first response from each slave node in response to the first signal. The first signal includes a first timestamp, and the first response includes a second timestamp. Based on the first timestamp and the second timestamp, the master node determines the one-way delay between itself and each slave node, generates a delay compensation parameter for each slave node based on the one-way delay, and sends the corresponding delay compensation parameter to each slave node. Each slave node receives a first signal sent by the master node and generates a first response in response to the first signal, the first signal including a first timestamp and the first response including a second timestamp; and receives a delay compensation parameter sent by the master node and calibrates its local clock based on the delay compensation parameter.

12. An electronic device comprising a memory, a processor, and a computer program stored in the memory, characterized in that, The processor executes the computer program to implement the method of any one of claims 1 to 8.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 8.

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