Bus system, bus control method based on bus system, and electronic device
Patent Information
- Application Number
- CN202510323096.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-18
- Publication Date
- 2026-09-25
AI Technical Summary
但这种方法会大量占用主控MCU(微控制单元，Microcontroller Unit)的UART(Universal Asynchronous Receiver/Transmitter，通用异步收发器)资源，而UART资源数量极为有限，过度占用不利于MCU的成本控制，也增加了电路的复杂性
[0047]在实施本申请提供的总线系统技术方案中，本申请的总线系统包括主控模块、第一功能模块和第二功能模块；主控模块包括控制器和总线切换单元；总线切换单元的第一端与控制器的通信接口连接；总线切换单元的第二端通过第一总线与第一功能模块连接；总线切换单元的第三端通过第二总线与第二功能模块连接；总线切换单元的第四端与控制器的控制信号接口连接；总线切换单元根据控制信号输出接口输出的控制信号，实现控制通信接口与第一功能模块或第二功能模块之间的建立连接。通过上述配置方式，本申请能够实现通过总线切换单元实现第一功能模块与控制器的通信接口连接，或者第二功能模块与控制器的通信接口连接。能够实现基于一个通信接口的分时复用，从而实现对控制器资源的高效利用。同时由于总线切换单元能够实现第一功能模块和第二功能模块其中之一与控制器的通信接口连接，也能够避免第一功能模块和第二功能模块存在地址冲突的问题。本申请的总线系统，能够在不增加控制器的通信接口资源消耗的前提下，实现总线系统的通信过程优化，有效避免地址冲突问题，从而有效提升总线系统的稳定性和成本效益。
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Figure CN122824535A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of bus communication technology, specifically to a bus system, a bus control method based on the bus system, and an electronic device. Background Technology
[0002] In a modularly designed bus system, each module is assigned an independent address to ensure accurate and orderly communication. However, when two modules with the same address are connected to the same bus system, address conflicts occur, which seriously affect the normal operation of the system.
[0003] To address the aforementioned issues, the traditional solution is to deploy multiple buses to ensure that module addresses within each bus are not duplicated. However, this method consumes a significant amount of UART (Universal Asynchronous Receiver / Transmitter) resources on the main control MCU (Microcontroller Unit). Since the number of UART resources is extremely limited, excessive consumption is detrimental to MCU cost control and also increases circuit complexity.
[0004] Accordingly, there is a need in the field for a new bus system solution to address the above problems. Summary of the Invention
[0005] In order to overcome the above-mentioned deficiencies, this application is made to solve, or at least partially solve, the technical problem of how to resolve address conflicts of a single communication interface in a bus system.
[0006] In a first aspect, a bus system is provided, the system comprising a main control module, a first functional module, and a second functional module;
[0007] The main control module includes a controller and a bus switching unit;
[0008] The first end of the bus switching unit is connected to the communication interface of the controller;
[0009] The second end of the bus switching unit is connected to the first functional module via the first bus;
[0010] The third end of the bus switching unit is connected to the second functional module via a second bus;
[0011] The fourth terminal of the bus switching unit is connected to the control signal interface of the controller;
[0012] The bus switching unit controls the establishment of a connection between the communication interface and the first functional module or the second functional module based on the control signal output by the control signal output interface.
[0013] In one technical solution of the above bus system, the communication interface includes a transmitting communication interface; the first end of the bus switching unit includes a transmitting sub-port; the bus switching unit includes a diode, a first transistor, a second transistor, and a third transistor;
[0014] The transmitting communication interface is connected to the transmitting sub-port;
[0015] The first end of the diode is connected to the transmitting sub-port; the second end of the diode is connected to the control signal output interface.
[0016] The first terminal of the first transistor is connected to the control signal output interface; the second terminal of the first transistor is connected to the transmitting sub-port; and the third terminal of the first transistor is grounded.
[0017] The first terminal of the second transistor is connected to the transmitting sub-port, the second terminal of the second transistor is connected to the second bus, and the third terminal of the second transistor is grounded.
[0018] The first end of the third transistor is connected to the transmitting sub-port, the second end of the third transistor is connected to the first bus, and the third end of the third transistor is grounded.
[0019] In one technical solution of the above-mentioned bus system, the bus switching unit further includes a first resistor;
[0020] The diode is connected to the transmitting sub-port via the first resistor;
[0021] The second transistor is connected to the transmitting sub-port through the first resistor.
[0022] In one technical solution of the above-mentioned bus system, the bus switching unit further includes a second resistor;
[0023] The first terminal of the second transistor is connected to the second terminal of the second resistor; the first terminal of the second resistor is connected to the second terminal of the first resistor; and the first terminal of the first resistor is connected to the transmitting sub-port.
[0024] In one technical solution of the above-mentioned bus system, the bus switching unit further includes a third resistor;
[0025] The first terminal of the first transistor is connected to the control signal output interface through the third resistor.
[0026] In one technical solution of the above-mentioned bus system, the bus switching unit further includes a fourth resistor;
[0027] The first terminal of the fourth resistor is connected to the transmitting sub-port; the second terminal of the fourth resistor is connected to the second terminal of the first transistor; the second terminal of the fourth resistor is also connected to the first terminal of the third transistor; and / or,
[0028] The bus switching unit also includes a first transistor damping resistor, a second transistor damping resistor, and a third transistor damping resistor;
[0029] The first terminal of the first transistor is connected to the third terminal of the first transistor through the first transistor damping resistor;
[0030] The first terminal of the second transistor is connected to the third terminal of the second transistor through the second transistor damping resistor;
[0031] The first terminal of the third transistor is connected to the third terminal of the third transistor through the third transistor damping resistor; and / or,
[0032] The communication interface further includes a receiving communication interface; the first end of the bus switching unit includes a receiving sub-port; the bus switching unit further includes a fourth transistor, a fifth transistor, and a sixth transistor;
[0033] The receiving communication interface is connected to the receiving sub-port;
[0034] The first terminal of the fourth transistor is connected to the receiving sub-port; the second terminal of the fourth transistor is grounded; the third terminal of the fourth transistor is connected to the second terminal of the fifth transistor and the second terminal of the sixth transistor, respectively.
[0035] The first terminal of the fifth transistor is connected to the power supply; the third terminal of the fifth transistor is connected to the second bus.
[0036] The first terminal of the sixth transistor is connected to the power supply; the third terminal of the sixth transistor is connected to the first bus; and / or,
[0037] The bus switching unit also includes a seventh transistor;
[0038] The first end of the seventh transistor is connected to the transmitting sub-port; the second end of the seventh transistor is connected to the power supply; and the third end of the seventh transistor is connected to the first end of the second transistor.
[0039] In one technical solution of the above bus system, the communication interface is a universal asynchronous transceiver interface.
[0040] In a second aspect, a bus control method based on a bus system is provided, characterized in that the bus system is any one of the bus system technical solutions described above; the method includes:
[0041] Based on the preset bus control requirements, the control signal output through the controller's control signal output interface is used to establish a connection between the communication interface and the first functional module or the second functional module.
[0042] In one technical solution of the above-mentioned bus control method, the control signal output through the control signal output interface of the controller based on the preset bus control requirements includes:
[0043] When the bus control requirement is to establish a connection with the first functional module, the control signal output interface is controlled to output a low-level signal.
[0044] When the bus control requirement is to establish a connection with the second functional module, the control signal output interface is controlled to output a high-level signal.
[0045] In a third aspect, an electronic device is provided, the electronic device comprising any one of the bus system technical solutions described above.
[0046] The above-described technical solutions of this application have at least one or more of the following beneficial effects:
[0047] In implementing the bus system technical solution provided in this application, the bus system includes a main control module, a first functional module, and a second functional module. The main control module includes a controller and a bus switching unit. The first end of the bus switching unit is connected to the communication interface of the controller. The second end of the bus switching unit is connected to the first functional module via a first bus. The third end of the bus switching unit is connected to the second functional module via a second bus. The fourth end of the bus switching unit is connected to the control signal interface of the controller. The bus switching unit establishes a connection between the control communication interface and the first or second functional module based on the control signal output by the control signal output interface. Through the above configuration, this application can realize the connection between the first functional module and the controller's communication interface, or the connection between the second functional module and the controller's communication interface, through the bus switching unit. It can achieve time-division multiplexing based on a single communication interface, thereby achieving efficient utilization of controller resources. Furthermore, since the bus switching unit can connect one of the first or second functional modules to the controller's communication interface, it can also avoid address conflicts between the first and second functional modules. The bus system of this application can optimize the communication process of the bus system without increasing the communication interface resource consumption of the controller, effectively avoid address conflict problems, and thus effectively improve the stability and cost-effectiveness of the bus system. Attached Figure Description
[0048] The disclosure of this application will become more readily understood with reference to the accompanying drawings. It will be readily understood by those skilled in the art that these drawings are for illustrative purposes only and are not intended to limit the scope of protection of this application. Wherein:
[0049] Figure 1 This is a schematic diagram of the main components of a bus system according to an embodiment of this application;
[0050] Figure 2 A schematic diagram of the main components of a bus system according to an embodiment of this application;
[0051] Figure 3 This is a schematic diagram of the main components of a bus system in the prior art;
[0052] Figure 4 This is a schematic diagram of the main components of a bus switching module according to one embodiment of the present application.
[0053] Figure 5 This is a schematic diagram of the main components of a bus switching module according to another embodiment of the present application.
[0054] Figure 6 This is a schematic flowchart of the main steps of a bus control method based on a bus system according to an embodiment of this application.
[0055] Figure label:
[0056] Main control module: 1; Controller: 11; Communication interface: 111; Control signal output interface: 112; Bus switching unit: 12; First functional module: 2; Second functional module: 3. Detailed Implementation
[0057] Some embodiments of this application are described below with reference to the accompanying drawings. Those skilled in the art should understand that these embodiments are merely illustrative of the technical principles of this application and are not intended to limit the scope of protection of this application.
[0058] In the description of this application, "module" and "processor" can include hardware, software, or a combination of both. A module can include hardware circuitry, various suitable sensors, communication ports, and memory, and may also include software components, such as program code, or a combination of software and hardware. The term "A and / or B" means all possible combinations of A and B, such as only A, only B, or A and B. The terms "at least one A or B" or "at least one of A and B" have a similar meaning to "A and / or B" and can include only A, only B, or A and B. The singular forms of the terms "a" and "this" can also include plural forms.
[0059] In the existing technology, please refer to the appendix. Figure 3 , Figure 3 This is a schematic diagram of the main structural components of a bus system in existing technology. For example... Figure 3 As shown, functional module D exists in both the first functional module 2 and the second functional module 3. In this case, since the two functional modules share the same address, the main control module 1 needs to construct different buses (BUS1, BUS2) connected to different communication interfaces 111 (UART1, UART2), distributing modules with the same address across different buses to avoid address conflicts. This would require two UART interfaces, wasting the interface resources of the controller 11 (MCU).
[0060] See appendix Figure 1 , Figure 1 This is a schematic diagram of the main structural components of a bus system according to an embodiment of this application. Figure 1 As shown, the bus system in this embodiment mainly includes a main control module 1, a first functional module 2, and a second functional module 3.
[0061] In this embodiment, the main control module 1 may include a controller 11 and a bus switching unit 12; the first end of the bus switching unit 12 may be connected to the communication interface 111 of the controller 11; the second end of the bus switching unit 12 may be connected to the first functional module 2 through a first bus; the third end of the bus switching unit 12 may be connected to the second functional module 3 through a second bus; the fourth end of the bus switching unit 12 may be connected to the control signal interface of the controller 11; the bus switching unit 12 realizes the establishment of a connection between the control communication interface 111 and the first functional module 2 or the second functional module 3 according to the control signal output by the control signal output interface 112.
[0062] In this system, the first functional module 2 and the second functional module 3 can be expansion modules in the bus system. The first functional module 2 can be one expansion module or multiple expansion modules with different addresses. The second functional module 3 can be one expansion module or multiple expansion modules with different addresses. The addresses of the expansion modules in the first functional module 2 and the second functional module 3 can be the same or different.
[0063] In one embodiment, the bus switching module can be a state converter based on control signals, which can control the communication interface 111 to connect with the first functional module 2 or the communication interface 111 to connect with the second functional module 3 based on different control signals.
[0064] In one implementation, the communication interface 111 can be a universal asynchronous transceiver interface, i.e., a UART (Universal Asynchronous Receiver / Transmitter) interface. The UART interface is a communication protocol and hardware interface used for asynchronous data transmission between a computer system and external devices. In the controller 11 (MCU, Microcontroller Unit), the number of UART interface resources is often very limited. By implementing time-division multiplexing of the first functional module 2 and the second functional module 3 through a single UART interface using the bus switching unit 12, the resources of the controller 11 can be effectively saved, improving efficiency.
[0065] Based on the above configuration, the bus system of this embodiment includes a main control module 1, a first functional module 2, and a second functional module 3. The main control module 1 includes a controller 11 and a bus switching unit 12. The first end of the bus switching unit 12 is connected to the communication interface 111 of the controller 11. The second end of the bus switching unit 12 is connected to the first functional module 2 via a first bus. The third end of the bus switching unit 12 is connected to the second functional module 3 via a second bus. The fourth end of the bus switching unit 12 is connected to the control signal interface of the controller 11. The bus switching unit 12 establishes a connection between the control communication interface 111 and the first functional module 2 or the second functional module 3 according to the control signal output by the control signal output interface 112. This embodiment enables the connection between the first functional module 2 and the communication interface 111 of the controller 11, or the connection between the second functional module 3 and the communication interface 111 of the controller 11, through the bus switching unit 12. Time-division multiplexing based on a single communication interface 111 is achieved, thereby enabling efficient utilization of the controller 11 resources. Meanwhile, since the bus switching unit 12 can connect one of the first functional module 2 and the second functional module 3 to the communication interface 111 of the controller 11, it can also avoid the problem of address conflict between the first functional module 2 and the second functional module 3. The bus system of this embodiment can optimize the communication process of the bus system without increasing the resource consumption of the communication interface 111 of the controller 11, effectively avoid the address conflict problem, and thus effectively improve the stability and cost-effectiveness of the bus system.
[0066] The following is combined Figure 2 and Figure 4 The present application will describe a bus system according to one embodiment of the present application. Figure 2 A schematic diagram of the main components of a bus system according to an embodiment of this application; Figure 4 This is a schematic diagram of the main components of a bus switching module according to one embodiment of the present application.
[0067] like Figure 2 As shown, the MCU of the main control module 1 is the controller 11. The communication interface 111 of the controller 11 is UART1, and the bus switching unit 12 is a BUS circuit. UART1 is connected to the BUS circuit. The BUS circuit is connected to the first functional module 2 through BUS1 (i.e., the first bus). The first functional module 2 includes functional modules A, B, C, and D. The BUS circuit is connected to the second functional module 3 through BUS2 (i.e., the second bus). The second functional module 3 includes functional module D. The GPIO of the MCU is the control signal output interface 112, which is connected to the fourth terminal of the bus switching unit 12. It is used to output control signals to establish a connection between the communication interface 111 and the first functional module 2, or between the communication interface 111 and the second functional module 3.
[0068] In one embodiment, the communication interface 111 may include a transmitting communication interface; the first end of the bus switching unit 12 may include a transmitting sub-port; the bus switching unit 12 may include a diode, a first transistor, a second transistor, and a third transistor; the transmitting communication interface may be connected to the transmitting sub-port; the first end of the diode may be connected to the transmitting sub-port; the second end of the diode may be connected to the control signal output interface 112; the first end of the first transistor may be connected to the control signal output interface 112; the second end of the first transistor may be connected to the transmitting sub-port; the third end of the first transistor is grounded; the first end of the second transistor may be connected to the transmitting sub-port, the second end of the second transistor may be connected to the second bus, and the third end of the second transistor is grounded; the first end of the third transistor may be connected to the transmitting sub-port, the second end of the third transistor may be connected to the first bus, and the third end of the third transistor is grounded.
[0069] In this embodiment, such as Figure 4 As shown, the transmitting sub-port of the bus switching unit 12 is... Figure 4 TXD in Figure 4 In this circuit, D2 is a diode, Q6 is the first transistor, Q3 is the second transistor, and Q5 is the third transistor. CTL_Channel is the fourth terminal of the bus switching unit 12, used to receive control signals output from the control signal output interface 112 of the controller 11. The second terminal of Q3 is connected to the second bus (BUS2); the second terminal of Q5 is connected to the first bus (BUS1). The third terminals of Q6, Q3, and Q5 are all grounded (GND).
[0070] In one embodiment, the bus switching unit 12 may further include a first resistor; a diode may be connected to the transmitting sub-port via the first resistor; and a second transistor may be connected to the transmitting sub-port via the first resistor.
[0071] In this embodiment, such as Figure 4As shown, Figure 4 R6 in the diagram is the first resistor.
[0072] In one embodiment, the bus switching unit 12 may further include a second resistor and a third resistor; the first terminal of the second transistor is connected through the second terminal of the second resistor; the first terminal of the second resistor is connected to the second terminal of the first resistor; the first terminal of the first resistor is connected to the transmitting sub-port; and the first terminal of the first transistor is connected to the control signal output interface 112 through the third resistor.
[0073] In this embodiment, such as Figure 4 As shown, Figure 4 R7 in the diagram is the second resistor, and the resistor in Q6 that is connected to CTL_Channel is the third resistor.
[0074] In one embodiment, the bus switching unit 12 may further include a fourth resistor; a first end of the fourth resistor is connected to the transmitting sub-port; a second end of the fourth resistor is connected to the second end of the first transistor; and the second end of the fourth resistor is also connected to the first end of the third transistor.
[0075] In this embodiment, such as Figure 4 As shown, Figure 4 R13 in the diagram is the fourth resistor.
[0076] In one embodiment, the bus switching unit 12 further includes a first transistor damping resistor, a second transistor damping resistor, and a third transistor damping resistor; the first terminal of the first transistor is connected to the third terminal of the first transistor through the first transistor damping resistor; the first terminal of the second transistor is connected to the third terminal of the second transistor through the second transistor damping resistor; and the first terminal of the third transistor is connected to the third terminal of the third transistor through the third transistor damping resistor.
[0077] In this embodiment, such as Figure 4 As shown, Figure 4 The resistor below Q6 is the damping resistor for the first transistor; R8 is the damping resistor for the second transistor; and R14 is the damping resistor for the third transistor. R8 and R14 act as pull-down resistors for the base of the transistors, ensuring a stable cutoff state when the controller is reset. Simultaneously, when CTL_Channel is low, the positive terminal of D2 is clamped to a low level. However, due to the diode's forward voltage drop and the controller pin's output voltage capability (i.e., when the controller pin's sink current is large, the pin voltage may rise to some extent due to its internal impedance), a certain voltage will still exist. The voltage divider circuit formed by R7 and R8 prevents this voltage from turning on Q3.
[0078] In one embodiment, the communication interface 111 further includes a receiving communication interface; the first end of the bus switching unit 12 includes a receiving sub-port; the bus switching unit 12 further includes a fourth transistor, a fifth transistor, and a sixth transistor; the receiving communication interface is connected to the receiving sub-port; the first end of the fourth transistor is connected to the receiving sub-port; the second end of the fourth transistor is grounded; the third end of the fourth transistor is connected to the second end of the fifth transistor and the second end of the sixth transistor, respectively; the first end of the fifth transistor is connected to a power supply; the third end of the fifth transistor is connected to a second bus; the first end of the sixth transistor is connected to a power supply; and the third end of the sixth transistor is connected to a first bus.
[0079] In this embodiment, such as Figure 4 As shown, Figure 4 In the diagram, Q1 is the fourth transistor, Q2 is the fifth transistor, Q4 is the sixth transistor, and RXD is the receiver sub-port.
[0080] like Figure 4 As shown, through Figure 4 The bus switching unit 12 enables TXD to achieve inversion (i.e., TXD is low when idle). When CTL_Channel is low, D2 turns on when TXD sends a high-level signal, clamping the base voltage of Q3 below the on-junction voltage, thus preventing the high level of TXD from being transmitted to BUS2 through Q3; correspondingly, Q6 is off at this time, and the high level sent by TXD can be transmitted to the base of Q5 through R13, making Q5 turn on, so that the low level can be transmitted to BUS1. At this time, the communication interface 111 of the controller 11 establishes a communication connection with the first functional module 2 through the first bus. When CTL_Channel is high, D2 is off. The high level emitted by TXD can be transmitted to the base of Q3 through R6 and R7, making Q3 conduct and thus transmitting the level to BUS2. Correspondingly, Q6 is on at this time, making the base voltage of Q5 locked at 0V, thus preventing the high level of TXD from transmitting a low level to BUS1 through Q5. At this time, the communication interface 111 of the controller 11 establishes a communication connection with the second functional module 3 through the second bus.
[0081] In one implementation, see Appendix Figure 5 , Figure 5 This is a schematic diagram of the main structural components of a bus switching module according to another embodiment of this application. Figure 5 As shown, for controller 11 that does not have TXD output inversion function, bus switching unit 12 can be equipped with a seventh transistor. Figure 5Q10 in the diagram is the seventh transistor. The first terminal of the seventh transistor is connected to the transmitting sub-port; the second terminal is connected to the power supply; and the third terminal is connected to the first terminal of the second transistor. The seventh transistor enables level inversion: a high level becomes a low level after passing through Q10, and vice versa. Figure 5 D3 is a diode; Q11 is the first transistor, Q9 is the second transistor, and Q13 and Q14 together form the third transistor. BUS1 is the first bus, and BUS2 is the second bus. Q7 is the fourth transistor, Q8 is the fifth transistor, and Q12 is the sixth transistor.
[0082] In one implementation, Figure 4 and Figure 5 The transistor in the transistor can be a transistor with an internal resistor or a transistor with an external resistor.
[0083] Furthermore, this application also provides a bus control method for a bus system.
[0084] See appendix Figure 6 , Figure 6 This is a schematic flowchart illustrating the main steps of a bus control method based on a bus system according to an embodiment of this application. Figure 6 As shown, the bus system in this application embodiment is the bus system described in the above-mentioned bus system embodiments. The bus control method based on the bus system in this application embodiment mainly includes the following steps S101:
[0085] Step S101: Based on the preset bus control requirements, the control signal output through the control signal output interface 112 of the controller 11 is used to establish a connection between the communication interface 111 and the first functional module 2 or the second functional module 3 according to the control signal.
[0086] In this embodiment, step S101 may further include steps S1011 and S1012:
[0087] Step S1011: When the bus control requirement is to establish a connection with the first functional module 2, the control signal output interface 112 outputs a low-level signal.
[0088] Step S1012: When the bus control requirement is to establish a connection with the second functional module 3, the control signal output interface 112 outputs a high-level signal.
[0089] It should be noted that although the steps in the above embodiments are described in a specific order, those skilled in the art will understand that in order to achieve the effect of this application, different steps do not necessarily have to be executed in such an order. They can be executed simultaneously (in parallel) or in other orders. These adjusted solutions are equivalent to the technical solutions described in this application and therefore will also fall within the protection scope of this application.
[0090] Those skilled in the art will understand that all or part of the processes in the method of the above-described embodiment can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable file, or some intermediate form. The computer-readable storage medium can include any entity or device capable of carrying the computer program code, a medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, a read-only memory, a random access memory, an electrical carrier signal, a telecommunication signal, and a software distribution medium, etc.
[0091] Another aspect of this application provides an electronic device.
[0092] In one embodiment of an electronic device according to this application, the electronic device may include the bus system described in the above bus system embodiments.
[0093] In one implementation, the electronic device can be a washing and care device.
[0094] The technical solution of this application has been described above with reference to one embodiment shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of this application.
Claims
1. A bus system, characterized in that, The system includes a main control module, a first functional module, and a second functional module; The main control module includes a controller and a bus switching unit; The first end of the bus switching unit is connected to the communication interface of the controller; The second end of the bus switching unit is connected to the first functional module via the first bus; The third end of the bus switching unit is connected to the second functional module via a second bus; The fourth terminal of the bus switching unit is connected to the control signal interface of the controller; The bus switching unit controls the establishment of a connection between the communication interface and the first functional module or the second functional module based on the control signal output by the control signal output interface.
2. The bus system according to claim 1, characterized in that, The communication interface includes a transmitting communication interface; the first end of the bus switching unit includes a transmitting sub-port; the bus switching unit includes a diode, a first transistor, a second transistor, and a third transistor; The transmitting communication interface is connected to the transmitting sub-port; The first end of the diode is connected to the transmitting sub-port; the second end of the diode is connected to the control signal output interface. The first terminal of the first transistor is connected to the control signal output interface; the second terminal of the first transistor is connected to the transmitting sub-port; and the third terminal of the first transistor is grounded. The first terminal of the second transistor is connected to the transmitting sub-port, the second terminal of the second transistor is connected to the second bus, and the third terminal of the second transistor is grounded. The first end of the third transistor is connected to the transmitting sub-port, the second end of the third transistor is connected to the first bus, and the third end of the third transistor is grounded.
3. The bus system according to claim 2, characterized in that, The bus switching unit also includes a first resistor; The diode is connected to the transmitting sub-port via the first resistor; The second transistor is connected to the transmitting sub-port through the first resistor.
4. The bus system according to claim 3, characterized in that, The bus switching unit also includes a second resistor; The first terminal of the second transistor is connected to the second terminal of the second resistor; the first terminal of the second resistor is connected to the second terminal of the first resistor; and the first terminal of the first resistor is connected to the transmitting sub-port.
5. The bus system according to claim 4, characterized in that, The bus switching unit also includes a third resistor; The first terminal of the first transistor is connected to the control signal output interface through the third resistor.
6. The bus system according to claim 2, characterized in that, The bus switching unit also includes a fourth resistor; The first terminal of the fourth resistor is connected to the transmitting sub-port; the second terminal of the fourth resistor is connected to the second terminal of the first transistor; the second terminal of the fourth resistor is also connected to the first terminal of the third transistor; and / or, The bus switching unit also includes a first transistor damping resistor, a second transistor damping resistor, and a third transistor damping resistor; The first terminal of the first transistor is connected to the third terminal of the first transistor through the first transistor damping resistor; The first terminal of the second transistor is connected to the third terminal of the second transistor through the second transistor damping resistor; The first terminal of the third transistor is connected to the third terminal of the third transistor through the third transistor damping resistor; and / or, The communication interface further includes a receiving communication interface; the first end of the bus switching unit includes a receiving sub-port; the bus switching unit further includes a fourth transistor, a fifth transistor, and a sixth transistor; The receiving communication interface is connected to the receiving sub-port; The first terminal of the fourth transistor is connected to the receiving sub-port; the second terminal of the fourth transistor is grounded; the third terminal of the fourth transistor is connected to the second terminal of the fifth transistor and the second terminal of the sixth transistor, respectively. The first terminal of the fifth transistor is connected to the power supply; the third terminal of the fifth transistor is connected to the second bus. The first terminal of the sixth transistor is connected to the power supply; the third terminal of the sixth transistor is connected to the first bus; and / or, The bus switching unit also includes a seventh transistor; The first end of the seventh transistor is connected to the transmitting sub-port; the second end of the seventh transistor is connected to the power supply; and the third end of the seventh transistor is connected to the first end of the second transistor.
7. The bus system according to any one of claims 1 to 6, characterized in that, The communication interface is a general asynchronous transceiver interface.
8. A bus control method based on a bus system, characterized in that, The bus system is the bus system according to any one of claims 1 to 7; the method includes: Based on the preset bus control requirements, the control signal output through the controller's control signal output interface is used to establish a connection between the communication interface and the first functional module or the second functional module.
9. The bus control method according to claim 8, characterized in that, The control signals output through the controller's control signal output interface, based on preset bus control requirements, include: When the bus control requirement is to establish a connection with the first functional module, the control signal output interface is controlled to output a low-level signal. When the bus control requirement is to establish a connection with the second functional module, the control signal output interface is controlled to output a high-level signal.
10. An electronic device, characterized in that, The electronic device includes the bus system described in any one of claims 1 to 7.