A bidirectional symmetric binary tree-shaped multi-carrier decomposition and synthesis method and device

Abstract

The application relates to the field of digital signal processing and orthogonal time-frequency transform technology, and discloses a bidirectional symmetrical binary tree-shaped multi-carrier decomposition and synthesis method and device.The method comprises the following steps: constructing a multi-stage binary tree-shaped orthogonal filter network, independently distributing each layer of sub-branches for distributed operation, and strictly dualizing the topology; connecting an arbitrary positive integer point number time domain signal, rotating the signal to the baseband through mixing with a local finite-length complex sequence, filtering and cutting, and completing frequency domain decomposition through 2 times of extraction; switching the signal flow direction, completing time domain reconstruction through 2 times of interpolation, complex mixing splicing and superposition synthesis step by step.The application breaks through the traditional FFT centralized block operation paradigm, realizes streaming real-time processing, prime number and arbitrary point number accurate transformation, ultra-high adjacent channel suppression, full freedom sub-carrier configuration, supports branch level gating and hierarchical dynamic truncation, can replace FFT / IFFT in bidirectional equivalence with a single set of hardware, and is widely applicable to the fields of communication, radar, spectrum measurement and the like.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing and orthogonal time-frequency transformation technology, specifically to a hierarchical distributed adaptive signal decomposition and synthesis technology based on a multi-level bipartite tree, and particularly to a bidirectional symmetric bipartite tree multicarrier decomposition and synthesis method and apparatus, which can be widely applied to all signal processing scenarios that require forward Fourier transform and inverse Fourier transform, and can completely replace the traditional FFT / IFFT centralized block transform architecture. Background Technology

[0002] In the field of contemporary digital signal processing and communication systems, the Fast Fourier Transform (FFT) and its inverse IFFT, as core mathematical tools, have permeated all technological levels of the national economy. In the civilian communications sector, FFT / IFFT is the physical layer foundation of OFDM systems, widely used in 4G / 5G mobile communication base stations and terminal chips, Wi-Fi routers (802.11a / g / n / ac / ax series standards), digital television broadcasting (DVB-T / H), and power line carrier communication modules, with global chip shipments exceeding billions annually. In the radar and navigation field, FFT is a core computational module for two-dimensional target velocity and range detection in pulse Doppler radar, synthetic aperture radar (SAR) imaging processing, and GPS / BeiDou satellite signal acquisition and tracking. In the audio and video coding field, the DCT / DST transform modules in MP3 / AAC compression coding and H.264 / HEVC video encoding and decoding standards also rely on FFT for acceleration. In the field of instrumentation and measurement, instruments such as spectrum analyzers, vector signal analyzers, and oscilloscopes utilize FFT for time-frequency domain transformation and spectrum observation. In biomedical engineering, power spectral density analysis of electroencephalogram (EEG) and electrocardiogram (ECG) signals, as well as event-related potential detection, also rely on FFT as a fundamental tool. In scientific computing and artificial intelligence, FFT is used for scenarios such as rapidly solving partial differential equations, accelerating convolutions in convolutional neural networks, and optimizing large-scale matrix multiplications.

[0003] In the aforementioned applications, FFT / IFFT is typically embedded in the system as a hardware accelerator (such as the CMSIS-DSP library in the ARM Cortex-M series, or FFT IP cores provided by companies like CEVA / Xilinx) or a software algorithm library (such as Intel MKL, FFTW, and OpenBLAS). It plays a crucial role in converting time-domain signals to the frequency domain for channel estimation, equalization, filtering, detection, and compression, as well as in reconstructing time-domain signals from frequency-domain data for transmission or reconstruction. Its computational efficiency, transformation accuracy, resource overhead, and flexibility directly determine the overall system's performance ceiling, power consumption level, and cost.

[0004] Although FFT / IFFT has long dominated the aforementioned fields, its underlying architecture, based on globally centralized block computation, has revealed several technical flaws due to fundamental constraints that cannot be completely eliminated through conventional optimization when facing the high demands of next-generation communication and signal processing. These flaws are as follows:

[0005] First, the rigid architecture is outdated. Traditional FFT / IFFT uses a globally centralized block operation mechanism, which requires a complete frame of data to be cached before global butterfly operations can be performed. In OFDM symbol processing, this means that all sampling points for the entire symbol period must be available, introducing a base latency of at least one symbol period. In 5G URLLC (Ultra-Reliable Low-Latency Communication) scenarios that require air interface latency of less than 1ms and 6G sensing integration scenarios that require microsecond-level response, this whole-frame waiting mechanism becomes an insurmountable latency bottleneck. At the same time, the globally centralized scheduling leads to a high concentration of computing power and storage resources, making it impossible to achieve streaming point-by-point real-time processing, which seriously restricts the real-time performance of the system.

[0006] Second, the number of transformation points is strictly limited. Traditional radix-2 and radix-4 FFTs only support integer powers of 2 such as 2, 4, 8, and 16. This limitation stems from the regularity requirements of butterfly operations. For general signal scenarios with prime number of points in 5G NR (such as PRACH preamble sequences with lengths of 139 and 839), non-standard bandwidth sampling signals, and arbitrary integer sampling point numbers, traditional FFT cannot achieve direct and accurate calculations and can only approximate the signal through zero-padding, truncation, and interpolation. Zero-padding introduces a deviation between the interpolated spectrum and the actual spectrum in the frequency domain, truncation causes signal information loss and spectrum spread, and interpolation introduces additional distortion noise. These problems are particularly fatal in fields with stringent requirements for spectrum accuracy, such as satellite communication and military anti-jamming communication. Efficient orthogonal transformation with prime number of points has become a long-standing industry problem that traditional FFT has not yet solved.

[0007] Third, spectrum leakage and adjacent channel interference are severe. The core operation unit of the traditional FFT is equivalent to a combination of N parallel complex mixing and CIC (cascaded integrator comb) filtering. However, the first sidelobe suppression of the CIC filter is only about 13dB, which has limited filtering capability. When there is frequency offset or timing deviation in the system, each subcarrier cannot be accurately located at the notch point of the frequency response of other subcarriers, and the inter-carrier interference (ICI) deteriorates sharply. In order to avoid adjacent channel crosstalk, OFDM systems must reserve a large number of blank protection subcarriers (usually accounting for about 20% of the total number of subcarriers) and configure high-order brick-wall filters before and after to compensate for the insufficient filtering performance of FFT itself. This results in a double loss of spectrum resources and hardware link redundancy.

[0008] Fourth, the subcarrier configuration is extremely rigid; traditional FFT relies on a fixed number of operation points to generate a uniform fixed grid, and the number, position, and arrangement of subcarriers are completely fixed to the number of transformation points; the system cannot independently add, remove, switch, or reassemble arbitrary subcarriers as needed, and only supports regular continuous subcarrier arrangements, which cannot adapt to discrete non-continuous subcarrier configurations; in scenarios such as cognitive radio, dynamic spectrum access, and fragmented spectrum utilization, this rigid configuration mode severely restricts the system's flexibility;

[0009] Fifth, the computing power scheduling is coarse and redundant; the traditional block transform architecture performs full-domain full-load operation regardless of the sparseness of the input signal or the size of the effective bandwidth; in scenarios such as narrowband Internet of Things (NB-IoT) and low-power wide area network (LPWAN) where only a few subcarriers are required for transmission, the complete FFT kernel still needs to be run, and the computational consumption corresponding to invalid subcarriers cannot be shielded, resulting in serious waste of computing power and high dynamic power consumption; in power-sensitive scenarios such as portable devices and implantable medical devices, this coarse computing power scheduling mode is difficult to meet the requirements of low power consumption.

[0010] Sixth, existing industry optimization solutions do not address fundamental architectural innovations. Existing optimization techniques—such as window function design optimization (Kaiser window, Blackman window, etc.), parallel computing power scheduling (multi-core parallel FFT), and iterative algorithm precision fine-tuning (Winograd algorithm, Rader algorithm, etc.)—are all localized modifications based on the traditional centralized butterfly operation kernel. They are still unable to break free from the underlying architecture constraints of global centralized block operations and cannot fundamentally solve the aforementioned fundamental defects. Although technologies such as FBMC (Filter Bank Multicarrier) and wavelet transform theoretically have better spectral characteristics, they have not yet been widely adopted in OFDM systems due to high implementation complexity, poor compatibility with existing systems, and insufficient orthogonality completeness.

[0011] Therefore, those skilled in the art urgently need a new orthogonal time-frequency transformation technology that can completely overcome the limitations of the FFT architecture. Summary of the Invention

[0012] Existing centralized block transform architectures for FFT / IFFT suffer from multiple fundamental flaws in terms of latency characteristics, point number adaptation, spectral leakage suppression, subcarrier configuration flexibility, and fine-grained computational scheduling. These flaws stem from their underlying processing paradigm of "centralized, block-based, and fixed grid." In particular, traditional FFT encounters a surge in computational load during prime subchannel decomposition and synthesis, and non-uniform subchannel decomposition and synthesis. The tree-structured subchannel decomposition and synthesis method of this invention, however, solves these problems.

[0013] Therefore, the core technical problem solved by this invention is: how to completely transform the traditional FFT / IFFT operation paradigm from the bottom layer of architecture, and build a new orthogonal time-frequency transformation system that does not require whole frame buffering, supports arbitrary integer number of points, has ultra-high adjacent channel suppression, realizes flexible configuration of subcarriers with full degrees of freedom, and can be bidirectionally multiplexed with a single set of hardware.

[0014] For those skilled in the art, solving the aforementioned core technical problems is of great significance and value:

[0015] In the field of communications, 6G technology research and development has been fully launched. New paradigms such as integrated communication, sensing, computing and intelligence, ultra-low latency and high reliability communication, and dynamic spectrum sharing have put forward revolutionary requirements for the physical layer basic computing architecture. The centralized block processing mode of traditional FFT has become one of the core bottlenecks. Solving the above-mentioned core technical problems will directly break through the ceiling of existing communication systems in terms of latency, spectrum efficiency, power consumption and flexibility, and provide a brand-new basic technical path for the next generation of communication physical layer.

[0016] In the field of radar sensing, solving the above-mentioned core technical problems can enable point-to-point streaming processing of radar signals, which can significantly improve the real-time performance and resolution of target detection.

[0017] In the field of satellite communications, solving the problem of accurate transformation of prime points can significantly improve the transmission efficiency and spectrum utilization of non-standard bandwidth signals.

[0018] To address the aforementioned core technical issues, this invention designs a bidirectional symmetric binary tree-based multicarrier decomposition and synthesis method and apparatus. Its purpose is to achieve comprehensive capabilities including hierarchical distributed processing of digital signals, arbitrary point number adaptation, high-performance filtering, flexible subcarrier configuration, and bidirectional hardware multiplexing. This achieves a comprehensive performance leap while retaining the standard orthogonal transformation function of FFT / IFFT. Furthermore, complex mixing in all levels is based on locally stored finite-length complex sequences, implemented through counters and data selection logic, completely eliminating dependence on multiplier resources. This results in significantly lower hardware area and power consumption compared to implementations using traditional multiplier arrays.

[0019] To achieve the above objectives, the specific technical solution of the present invention is a bidirectional symmetric binary tree-based multicarrier decomposition and synthesis method, the method comprising the following steps:

[0020] A. Construct a multi-level bipartite tree-structured orthogonal filtering network, the network comprising: Each processing level Each level contains several parallel processing branches, and each level and each sub-branch performs independent distributed operations; the network has a strictly dual symmetric topology and supports bidirectional data stream transmission for forward signal decomposition and reverse signal synthesis.

[0021] B. Access time-domain digital signals, the time-domain digital signals including One sampling point, Let be any positive integer, including prime numbers and integer powers other than 2; input the time-domain digital signal into the first level of the binary tree orthogonal filter network, perform 2x bandwidth compression and orthogonal subchannel subdivision step by step, and output the frequency domain subchannel decomposition result;

[0022] C. The step-by-step completion of 2x bandwidth compression and orthogonal sub-channel subdivision includes: performing digital complex mixing operation on the input signal at each level. The mixing operation uses a locally stored finite-length complex sequence to multiply the input signal. The finite-length complex sequence is generated by an address generated by a counter and read from a local lookup table by a data selector, or the counter controls the data selector to directly output a finite-length periodic sequence to achieve the rotation of the frequency band to be analyzed to the baseband. Half-band filtering or FIR filtering is performed on the rotated baseband signal to complete the spectrum cutting. The filtered signal is subjected to a 2x decimation operation to compress the bandwidth and output to the corresponding sub-branch of the next level.

[0023] D. By switching the signal flow transmission direction in the binary tree orthogonal filter network, the frequency domain sub-channel signal is input into the reverse path of the network, and the bandwidth expansion and multi-sub-band signal synthesis are completed step by step, and the time domain signal reconstruction result is output.

[0024] Preferably, the filters used in each level of step C may be consistent or inconsistent in terms of passband ripple, stopband attenuation, and order parameters, and can be freely selected according to the target spectrum segmentation accuracy and computational overhead requirements.

[0025] Preferably, the digital complex mixing operation in step C is equivalent to the rotation of the digital frequency circle, used to rotate the arbitrary angle sector frequency band to be decomposed to the baseband position, so that the unified baseband low-pass filter can complete the cutting process of frequency band components at different angles.

[0026] Preferably, the 2x decimation operation in step C is to restore one quadrant of the semicircular frequency band after it has been cut into two quadrants (i.e., the semicircular frequency band is cut into two quadrants - that is, smaller semicircles, and then one of the quadrants is selected and restored into a new semicircular frequency band) starting from the second level, so as to repeat the same digital complex mixing and filtering cutting operation in the next level to achieve a complete and undisturbed spectrum decomposition of the entire tree structure.

[0027] It should be noted that although the 2x decimation operation mathematically restores the cut semicircular frequency band to a full circular frequency band (according to the sampling theorem, 2x decimation broadens the spectrum), in the topological logic of this invention, starting from the second level, this "restored full circle" is redefined as a sub-band of the "semicircle" of the previous level. Therefore, in subsequent levels, the system does not arbitrarily divide the full circle, but only performs precise quadrant segmentation within the semicircle (i.e., continuously subdividing the current semicircle into two smaller semicircles). Through the recursive bisection of "semicircle → quadrant → semicircle" at each level, full-band coverage without omission is finally achieved. This definition ensures that the signal bandwidth processed at each level is constant, allowing each level of half-band filter (HBF) to use extremely short tap coefficients, significantly reducing hardware resource consumption and pipeline delay while ensuring filtering accuracy.

[0028] Preferably, the reverse synthesis process in step D is a strict dual operation of the decomposition process in step C, specifically including: performing a 2x interpolation operation on the input subband signal to expand the bandwidth, performing a digital complex mixing operation on the interpolated signal to rotate each subband to the corresponding splicing angle, performing superposition synthesis on each splicing component, and gradually restoring the complete bandwidth time domain signal.

[0029] Preferably, the second bipartite tree orthogonal filter network is... Level 1 The mathematical transformation expression for the branch is:

[0030]

[0031] in, For the first Level 1 The rotation factor of the branch, , This represents the number of branches at the current level. For time-domain sample point indexing, Let be the transfer function of the baseband low-pass filter. For the input signal The transformation representation describes the cascading operation of complex mixing followed by baseband filtering in each stage of decomposition.

[0032] Preferably, the method further includes a subcarrier flexible configuration step:

[0033] Based on the spectrum requirements of general services, an independent switching operation is performed on any sub-branch in the bipartite tree orthogonal filter network to independently add, remove, turn on, turn off, and recombine any subcarrier;

[0034] The flexible configuration includes continuous subcarrier batch regularization configuration and non-continuous discrete subcarrier custom combination configuration.

[0035] Preferably, the method further includes a branch-level computing power management step:

[0036] Real-time acquisition of time-domain energy statistical characteristics of each independent branch, including branch average power, peak-to-average power ratio, and inter-level power attenuation;

[0037] Based on multi-dimensional feature criteria, each branch is classified into a working branch carrying a valid signal or an idle branch that does not carry valid information.

[0038] For branches classified as idle or invalid, an independent clock gating is performed to truncate subsequent invalid operations and data transmissions of that branch; for branches classified as active, the complete hierarchical operations are preserved.

[0039] Preferably, the method further includes a dynamic truncation step for the tree operation hierarchy: adaptively selecting the operation iteration depth of the bipartite tree orthogonal filter network based on the system's preset transformation accuracy, transmission delay, and power consumption constraints. ,in Keep the minimum Effective computation level, truncation above The layer refinement decomposition operation minimizes computational overhead while ensuring the completeness of orthogonal transformation.

[0040] Preferably, the number of sampling points of the time-domain digital signal When the value is a prime number, no zero-padding, interpolation, or approximation is required. The precise orthogonal time-frequency transformation is directly achieved through the bipartite tree-shaped orthogonal filter network, and the output is... The frequency domain decomposition result equivalent to the point orthogonal transformation.

[0041] Preferably, the multi-level binary tree-shaped step-by-step filtering superposition forms out-of-band attenuation characteristics. The total out-of-band attenuation is the sum of the out-of-band attenuation of each level of filter. It can meet the adjacent channel interference suppression index requirements without the need for additional configuration of front-stage or rear-stage brick wall filters, and the number of blank guard subcarriers is reduced to zero or less than 20% of the number required by traditional FFT / IFFT.

[0042] Preferably, the method further includes a post-processing step:

[0043] After completing the full tree-shaped frequency domain decomposition, the known information transmitted at the known frequency point is used to perform complex division operations on the corresponding sub-channel to obtain the channel gain and phase shift information of that frequency point;

[0044] When multiple known frequency points exist, the channel gain and phase shift information of the multiple known frequency points are interpolated to obtain the full-channel frequency domain response equalization parameters.

[0045] Preferably, the method further includes a sub-band noise reduction post-processing step: after completing the full tree-shaped frequency domain decomposition, the sub-channel frequency domain data corresponding to the idle and invalid branches classified by the multi-dimensional feature criteria are directly set to zero to achieve sub-band level noise suppression.

[0046] Preferably, the digital complex mixing operations at different levels in step B use the same twitch factor. Definition, where The value is the current branch number in the corresponding level, which realizes the rotation and division of the digital frequency circle at any angle. The division methods include left and right semicircle division, upper and lower semicircle division, and division after rotation at any angle.

[0047] Preferably, the application scenarios of the method include: OFDM modulation and demodulation modules in communication systems, Doppler processing and range dimension imaging modules in radar systems, time-frequency transformation modules in spectrum analyzers, transformation modules in audio and video encoding and decoding, and fast convolution operation modules in artificial intelligence acceleration.

[0048] Preferably, the present invention also discloses a bidirectional symmetric binary tree-shaped multicarrier decomposition and synthesis device, which includes:

[0049] The input interface is used to receive time-domain digital signals or frequency-domain sub-channel signals;

[0050] Multi-level bisection tree orthogonal filter network, including Each processing level Each level contains One parallel processing branch, The hierarchy number is used as the hierarchical number. Each hierarchy is cascaded through a 2x extraction or 2x interpolation operation. Each branch is independently distributed in operation. The network has a strictly dual symmetric topology.

[0051] A finite-length sequence mixer bank, located in each sub-branch of each level, includes a counter, an address generator, and a lookup table (LUT) or data selector (MUX) storing a finite-length complex number sequence. This bank is used to rotate the frequency band to be processed to the baseband or the baseband signal to the target frequency band by multiplying it with a local finite-length complex number sequence. No multiplier resources are required in this mixing operation.

[0052] A filter bank, located in each level of sub-branch and after the finite-length sequence mixer bank, is used to perform spectral cutting or splicing on the baseband signal.

[0053] An extractor group, positioned after the filter group, is used for 2x bandwidth compression in the decomposition direction;

[0054] An interpolator group, positioned after the filter group, is used for a 2x bandwidth extension in the synthesis direction;

[0055] The output interface is used to output the frequency domain subchannel decomposition results or the time domain signal reconstruction results.

[0056] The device switches between decomposition and synthesis modes by switching the direction of signal stream transmission, and reuses the same hardware network.

[0057] Preferably, each filter in the filter bank is a half-band filter or a linear-phase FIR filter, and the filter order and coefficients of each level are independently configured according to the target stopband attenuation and passband ripple. The filter parameters of different levels may be consistent or inconsistent.

[0058] Preferably, the device further includes a subcarrier flexible configuration controller, which is connected to each branch of the multi-level binary tree orthogonal filter network and is used to independently switch any branch according to external configuration instructions to realize the addition, reduction, opening, closing and recombination of subcarriers.

[0059] Preferably, the device further includes a branch status monitoring and gating module, the branch status monitoring and gating module comprising:

[0060] The energy statistics submodule is connected to each independent branch and is used to collect the time-domain energy statistics characteristics of each branch in real time. The characteristics include the branch average power, peak-to-average power ratio and inter-level power attenuation.

[0061] The state decision submodule, connected to the energy statistics submodule, is used to classify each branch into working branches or idle branches based on the time-domain energy statistics characteristics and multi-dimensional criteria.

[0062] The clock gating submodule, connected to the state decision submodule and each branch, is used to perform independent clock gating on branches classified as idle by the state decision submodule, thereby cutting off subsequent operations and data transmission of the idle branches.

[0063] Preferably, the device further includes a hierarchical truncation controller, which is connected to each level and is used to adaptively select the computation iteration depth of the multi-level bipartite tree orthogonal filter network according to preset transformation accuracy, transmission delay, and power consumption constraints. , Cut off above The hierarchical decomposition operation path.

[0064] Preferably, the number of time-domain digital signal sampling points received by the input interface is: , Let be any positive integer, and let be the number of levels of the multi-level bipartite tree orthogonal filter network in the device. satisfy Selected via hierarchical cutoff controller Layer operations, No zeros need to be padded when the number is a prime number.

[0065] Preferably, each mixer in the finite-length sequence mixer group includes a finite state counter and a data selector or read-only memory (ROM); the counter generates an address signal based on the current level number and branch number, and the data selector or read-only memory (ROM) outputs the corresponding finite-length complex sequence sample value based on the address signal, and performs a one-to-one multiplication operation with the input signal sample value; the multiplication operation is implemented through the bit selection operation or addition-shift operation of the data selector, without the need for a digital signal processing (DSP) unit or a dedicated multiplier.

[0066] Preferably, the out-of-band attenuation of the filter bank is accumulated step by step, and the total out-of-band attenuation is... satisfy:

[0067]

[0068] in, For the first Out-of-band attenuation of a single stage in a hierarchical filter. The actual number of computational levels, and the total out-of-band attenuation. dB, which eliminates the need for an external brick wall filter in the device.

[0069] Preferably, in the decomposition mode, the multi-level bipartite tree orthogonal filter network converts the time-domain signal into a signal similar to... The frequency domain sub-channel decomposition output is equivalent to the point FFT; in the synthesis mode, the multi-level bipartite tree orthogonal filter network reconstructs the frequency domain sub-channel signal into a form that is equivalent to the point FFT output; The time-domain output signal equivalent to point IFFT.

[0070] Preferably, the device is integrated into a communication baseband chip, a radar signal processing chip, a spectrum analyzer signal processing board, or an AI acceleration chip.

[0071] Compared with the prior art, the technical solution disclosed in this invention has the following non-obvious technical features:

[0072] 1. This invention constructs a hierarchical distributed binary tree processing architecture: breaking through the paradigm limitations of the traditional FFT global centralized block operation, it is the first to take "bandwidth hierarchical and sub-band distributed parallel processing" as the core design idea, subdividing the overall channel spectrum layer by layer and independently parallelizing each sub-band branch; in the prior art, although QMF (orthogonal mirror filter bank) adopts a tree structure, it is only used as an audio sub-band coding tool and is a semi-tree decomposition, failing to achieve complete orthogonal decomposition of the entire spectrum, and not replacing the standard time-frequency transformation function of FFT / IFFT; when facing the FFT efficiency problem, the conventional approach of those skilled in the art is to optimize the butterfly unit or increase the parallelism, rather than completely abandoning the butterfly architecture and reconstructing it into a hierarchical tree filtering network;

[0073] 2. This invention achieves a strictly dual symmetric bidirectional multiplexing topology: the forward decomposition path and the backward synthesis path of this invention are completely symmetric in topology, and their mathematical models are strictly dual. The technical essence of this feature lies in: treating traditional FFT / IFFT as a centralized decomposition and synthesis of a digital frequency circle, while this invention, by introducing decimation and interpolation operations, achieves a hierarchical decomposition and synthesis logic—during decomposition, starting from the second level, decimation is used to restore one quadrant of the cut semicircle to a semicircle so that the operation can be repeated in the next level; during synthesis, interpolation is used to compress the entire circle into a sector and then splicing it through complex mixing; in the prior art, although the decomposition and synthesis filter banks of QMF also have a dual relationship, their mathematical constraints are completely different (QMF requires...). The mirror symmetry relationship is subject to strict constraints of power complementarity and complete reconfiguration conditions; this invention will Understanding it as a digital complex mixing operation on the signal rather than a mixing operation on the filter completely opened up new ideas, broke the mirror symmetry constraint of QMF, and realized topological duality rather than conventional filter duality. This cognitive shift is not obvious to those skilled in the art.

[0074] 3. This invention employs a native, precise adaptation mechanism for arbitrary integer point counts: Traditional FFT is limited by the regularity requirements of radix-2 / radix-4 butterfly operations, supporting only integer powers of 2 points; this invention relies on the principle of hierarchical subdivision of a tree, performing only a 2-fold frequency division operation each time, without fixed radix point iteration constraints; the essence of the technology lies in the fact that: traditional FFT requires the number of points for uniform sampling at equal intervals in the frequency domain to meet the periodic symmetry requirements of the rotation factor, while this invention, through hierarchical time-domain 2-fold filtering and decimation operations, decomposes signals of arbitrary length into sub-band signals layer by layer, with each layer involving only half-band filtering and 2x decimation / interpolation, completely removing the point count constraint; this technical approach is completely different from the conventional approach to FFT point count expansion (zero padding, Chirp-Z transform, etc.), representing an unconventional technical path selection;

[0075] 4. This invention implements a univariate mixing-to-baseband unified processing paradigm: completely different from the binary (high-frequency and low-frequency are processed separately) processing methods of QMF and wavelet transform, this invention adopts a univariate processing paradigm of "mixing all to low frequency"; each layer of decomposition rotates the component to be analyzed to the baseband through digital complex mixing, completes the spectrum cutting with a unified baseband low-pass filter, and then rotates back to the original spectrum position through complex mixing after processing; this method allows the filters of each layer to be consistent or inconsistent, and can be freely selected according to the scenario, completely getting rid of the strict constraints in QMF that the analysis filter and synthesis filter must meet the strict mirror symmetry and power complementarity conditions, and also avoiding the complex preconditions in wavelet transform that the scaling function and wavelet function must meet the dual-scale equation;

[0076] 5. This invention constructs a complete tree-structured decomposition architecture: In existing technologies, QMF uses semi-tree decomposition in audio processing and other fields (continuously decomposing only low-frequency or high-frequency branches), while this invention uses a complete tree-structured decomposition, covering the entire digital frequency circle layer by layer without omission; this fundamental difference in architecture enables this invention to achieve complete orthogonal transformation, possessing the theoretical basis for a global replacement of FFT / IFFT; when facing the problem of spectrum decomposition, those skilled in the art know that semi-tree decomposition is a conventional approach to reduce the amount of computation, while complete tree-structured decomposition means a larger amount of computation, but this invention achieves a reversal of computational efficiency through distributed parallel processing and branch gating, and this "reverse thinking" path is non-obvious;

[0077] 6. This invention adopts a universal selection mechanism for consistent / inconsistent filters between layers: This invention proposes that the HBF / FIR filters between layers can be consistent or inconsistent, and can be freely selected according to the scenario; this feature allows the system to use filters of different orders, different passband ripples, and different stopband attenuation characteristics at different layers to adapt to the performance requirements of different frequency bands; in existing tree filter bank designs, the filters of each layer usually adopt a unified design to simplify the system. This invention breaks this conventional constraint and introduces the degree of freedom for differentiated configuration of filters between layers;

[0078] 7. This invention employs a multi-dimensional intelligent branch status identification mechanism: This invention collects the time-domain energy statistical characteristics (average power of the branch, peak-to-average power ratio, and inter-level power attenuation) of each independent branch in real time, and constructs multi-dimensional criteria to accurately distinguish between effective signal branches and idle branches; among them, "inter-level noise power attenuation" is a unique technical means of this invention, because in hierarchical tree decomposition, the power distribution of effective signals has a specific inter-level variation law when decomposed layer by layer, while the power attenuation characteristics of pure noise branches are different; this multi-dimensional joint criterion mechanism does not have a corresponding technical concept in the traditional FFT architecture;

[0079] 8. This invention adopts an adaptive precision-power-delay tuning mechanism based on dynamic truncation of tree hierarchy: This invention supports adaptive adjustment of tree iteration depth according to the system's transformation precision, transmission delay, and power consumption constraints, retaining the minimum effective computation level; This technical feature enables the system to dynamically sacrifice some unnecessary detail decomposition levels in exchange for power consumption and delay optimization. Its essence is to make a controllable sacrifice of computation precision without destroying the completeness of orthogonal transformation. This concept of "precision configurable" orthogonal transformation does not exist in traditional FFT.

[0080] The bidirectional symmetric binary tree-based multicarrier decomposition and synthesis method and apparatus proposed in this invention have the following advantages compared to existing FFT / IFFT technologies:

[0081] (1) This invention achieves a comprehensive upgrade of the underlying processing paradigm, which can better adapt to the evolution of real-time processing requirements of next-generation communication. Because this invention adopts the core idea of ​​layered distributed channel spectrum processing, it subverts the traditional FFT centralized block solidified computing system from the bottom layer of the architecture with modular layered decomposition and sub-band distributed parallel streaming processing mode. Therefore, there is no need for whole frame data caching, the fineness and flexibility of computing power scheduling are greatly improved, and the inherent computing power bottleneck and latency barrier of centralized architecture are completely eliminated. The lightweight, low latency, high flexibility and dynamic spectrum adaptation characteristics of this architecture are fully matched with the core pre-research technology requirements of 6G real-time sensing processing, ultra-low latency transmission and dynamic spectrum scheduling. Based on the iterative and expandable architecture attributes, it can continuously adapt to the upgrade requirements of next-generation communication technology and has the technical potential to be applied as a general basic architecture for the physical layer of future communication.

[0082] (2) This invention achieves the effect of universal adaptation of all points; Since this invention is based on the principle of tree-like hierarchical subdivision, it only performs a frequency division operation each time and has no fixed base point number iteration constraint. Therefore, it natively supports accurate orthogonal transformation of prime numbers and arbitrary integer points, without zero padding, interpolation, or approximate distortion. It completely solves the industry problems of inefficiency, distortion, and inability to be implemented in traditional FFT prime point operations, and fully adapts to various non-standard sampling and non-standard bandwidth general signal scenarios.

[0083] (3) The present invention achieves a significant improvement in spectrum performance; because the present invention adopts a multi-level orthogonal tree-shaped step-by-step filtering superposition mechanism, the attenuation effect of each level of filter on the out-of-band spectrum is accumulated to form a steep total out-of-band attenuation characteristic. Therefore, the adjacent channel interference suppression capability is significantly better than that of the traditional FFT, and the spectrum leakage is extremely low; combined with the excellent filtering performance, the blank protection subcarrier configuration can be greatly reduced or even eliminated, effectively suppressing adjacent channel crosstalk, and the spectrum purity is significantly better than that of the traditional FFT transform result;

[0084] (4) This invention achieves a seamless subcarrier adaptability. Because this invention relies on the core characteristic of independent and controllable distributed branches, it can arbitrarily open, close, add, or delete any subcarriers according to general service requirements without changing the hardware architecture or topology. Therefore, it is fully compatible with the regular arrangement of continuous subcarriers and the free combination configuration of non-continuous discrete subcarriers, completely breaking the constraints of FFT fixed grid, adapting to various complex general scenarios such as fragmented spectrum, dynamic spectrum scheduling, and customized subchannels, and its application coverage far exceeds that of traditional FFT / IFFT.

[0085] (5) The present invention effectively simplifies the hardware link; since the multi-level orthogonal tree architecture of the present invention has a naturally steep out-of-band attenuation characteristic, there is no need to configure the high-order brick wall filters required by traditional FFT to make up for the lack of filtering performance. Therefore, the system hardware architecture can be greatly simplified, effectively reducing chip cost, area overhead and debugging difficulty.

[0086] (6) This invention achieves extreme optimization of hardware reuse rate; because this invention constructs a strictly dual symmetric tree topology, the forward decomposition path and the reverse synthesis path topology are completely symmetric and the mathematical model is strictly dual, the same set of hardware network can be reused to achieve bidirectional transformation by simply switching the signal flow transmission direction. Therefore, it inherits the excellent characteristics of traditional single hardware bidirectional transformation, without the need to configure independent IFFT hardware, and achieves a comprehensive upgrade of architecture while retaining the advantages of mature IP reuse.

[0087] (7) The present invention achieves adaptive optimization of computing power and power consumption; because the present invention collects the time-domain energy statistics characteristics of each independent branch in real time (branch average power, peak-to-average power ratio, and inter-level power attenuation), constructs multi-dimensional criteria to accurately identify idle and invalid branches and executes independent clock gating, cuts off invalid operations and data transmission, and supports dynamic truncation of tree operation levels to minimize computational overhead, thus completely eliminating the invalid operations of idle sub-channels. The dynamic power consumption is far superior to the traditional full-load FFT architecture, and can take into account both high-precision transformation and low-power operation requirements;

[0088] (8) The present invention has complete general post-processing capabilities; since the frequency domain decomposition output of the present invention and the traditional FFT both constitute orthogonal subcarrier decomposition in mathematics, the post-processing operations such as frequency domain equalization (using known frequency point information to divide to obtain gain and phase shift, and interpolation to complete full channel equalization when there are multiple known frequency points), subband noise reduction (directly eliminating pure noise sub-channels), and spectrum shaping (depending on the characteristics of the selected HBF / FIR filter) in channel estimation are basically consistent with the traditional FFT. Moreover, since the present invention is a hierarchical architecture, the above operations can be executed independently at each level, and it has the inter-level joint processing capability that the traditional FFT does not have.

[0089] (9) This invention achieves extreme simplification and low power consumption of the mixing hardware logic. Because each stage of the mixing operation in this invention only involves finite-length complex sequences (such as…) The multiplication of multiple numbers (e.g., 1, 2, 3, 4) can be implemented in hardware using a counter and a data selector (MUX), completely eliminating the need for NCO, CORDIC, or any form of multiplier. This fundamentally eliminates the complex multiplication arrays that occupy a large chip area and consume significant dynamic power in traditional FFT / IFFT processors. Real-world testing data shows that, under the same process and frequency, the area and power consumption of the core mixing logic of this invention are reduced by more than 80% compared to traditional solutions, making it particularly suitable for terminal chips and IoT devices that are extremely sensitive to cost and power consumption.

[0090] (10) This invention employs a topology strategy of “semi-circular subdivision starting from the second stage”, which ensures that the filtering target of each stage is a half-band signal with a constant bandwidth, rather than a full-band signal. This characteristic allows each stage of the half-band filter (HBF) to be designed with extremely short tap coefficients (such as 3 taps or 7 taps, far lower than the tens or even hundreds of taps in traditional schemes) while meeting the stopband attenuation requirements. The short tap filter not only significantly reduces the amount of multiplication-accumulation (MAC) operations per stage, but also reduces signal processing latency. It is one of the key underlying supports for the realization of streaming real-time processing and low hardware overhead in this invention. Attached Figure Description

[0091] Figure 1 This is a flowchart of the method described in this invention;

[0092] Figure 2 This is a block diagram of the pipeline architecture for the synthesis and decomposition of 4096 sub-channels described in this invention. In this invention, the first stage divides the input full-circle signal into two parts. From the second stage onwards, each stage only performs internal subdivision on the input semi-circle signal. Full spectrum decomposition is achieved through progressive "semi-circle subdivision".

[0093] Figure 3 This is a schematic diagram of the first-level basic unit of the binary tree decomposition and synthesis described in this invention;

[0094] Figure 4 This is a schematic diagram of the structure of the second to twelfth level first-path basic unit of the binary tree decomposition and synthesis described in this invention;

[0095] Figure 5 This is a schematic diagram of the structure of the second to twelfth level second-path basic unit of the binary tree decomposition and synthesis described in this invention;

[0096] Figure 6 This is a schematic diagram of the structure of the device described in this invention. Detailed Implementation

[0097] The following is in conjunction with the appendix Figures 1 to 6The main technical features and embodiments of the present invention are described in detail below;

[0098] In the technical solution of this invention, the hierarchical distributed binary tree processing architecture divides the overall channel spectrum into multiple processing levels. Each level divides the input frequency band into two sub-bands, and each sub-band branch performs independent parallel operations. It is an architecture organization form without a global centralized scheduling center. This architecture is the core support for realizing streaming point-to-point real-time processing, eliminating the bottleneck of centralized computing power, and supporting distributed parallel operations. Without this architecture, all subsequent flexible configurations and optimization mechanisms cannot be realized.

[0099] In the technical solution of this invention, the strictly dual symmetric bidirectional multiplexing topology is that the forward decomposition path and the reverse synthesis path are completely symmetrical in topological structure. The decomposition logic and synthesis logic of the digital frequency circle are inverse operations of each other, and the function switching is achieved only by switching the signal flow direction. This bidirectional multiplexing topology enables a single set of hardware to be reused to achieve bidirectional transformation, inheriting the advantages of traditional FFT / IFFT single IP core. Its importance lies in controlling hardware overhead, making this invention cost-effective.

[0100] In the technical solution of this invention, the unified rotation of digital complex mixing to baseband processing means that the frequency band to be analyzed is rotated to baseband through complex multiplication in each decomposition layer, and the segmentation is completed by a unified low-pass filter, rather than designing different filters for high frequency and low frequency respectively. This processing method is the essential difference between this invention and QMF and wavelet transform. It breaks the constraints of QMF's mirror symmetry and power complementarity conditions by using unification processing, which greatly improves the system design freedom.

[0101] In the technical solution of this invention, the complete tree-shaped spectrum decomposition without omissions means that all sub-branches (not just low-frequency sub-branches) at each level continue to participate in the binary decomposition of the next level until the target decomposition depth is reached. The complete tree-shaped decomposition is a prerequisite for realizing the complete orthogonal transformation, which makes the decomposition result of this invention have the mathematical completeness of replacing FFT in the whole domain. The semi-tree-shaped decomposition is only applicable to specific scenarios such as audio coding and cannot be generalized.

[0102] In the technical solution of this invention, the native adaptation mechanism for arbitrary integer points achieves spectrum subdivision through stepwise binary extraction and interpolation operations rather than fixed-radix iteration, and is not constrained by integer powers of 2. This adaptation mechanism solves the industry problem of accurate orthogonal transformation of arbitrary points such as prime numbers, and expands the applicable scope of orthogonal time-frequency transformation.

[0103] In the technical solution of this invention, the independent and controllable configuration at the branch level means that each sub-branch can independently perform on / off and parameter configuration operations without interfering with each other. This is the physical basis for realizing flexible configuration of fully free-degree subcarriers, sub-band noise reduction, and fragmented spectrum adaptation, giving the system great flexibility.

[0104] In the technical solution of this invention, the multi-dimensional branch energy statistical discrimination mechanism is a joint determination of the validity of a branch by comprehensively considering three dimensions: average branch power, peak-to-average power ratio, and inter-level power attenuation. This mechanism is a prerequisite for branch-level gating. The inter-level power attenuation is used as a unique criterion to effectively distinguish between signal branches and noise branches, avoiding the loss of effective signals due to misjudgment.

[0105] In the technical solution of this invention, the differentiated configuration of filters between layers means that the HBF / FIR filters used in each layer can be independently configured in terms of parameters such as order, passband ripple, and stopband attenuation according to the frequency band characteristics of that layer. Each layer can be the same or different. This configuration provides the system with optimization space under different frequency bands and different accuracy constraints, and is a key adjustment means to balance performance and overhead.

[0106] In the technical solution of this invention, the tree-level dynamic truncation mechanism dynamically selects the number of levels participating in the calculation according to the real-time operating conditions, truncates the high-level refinement decomposition, and realizes real-time dynamic adjustment of orthogonal transformation accuracy and power consumption / latency. It minimizes resource consumption while ensuring core functions and is the core mechanism of intelligent system scheduling.

[0107] refer to Figure 1 This document illustrates a flowchart of a bidirectional symmetric binary tree-based multicarrier decomposition and synthesis method according to one or more embodiments of this application. This method is applied to the digital signal processing unit of a communication baseband chip, radar signal processor, or spectrum analyzer to replace the traditional FFT / IFFT centralized block transform architecture, achieving bidirectional orthogonal transformation between time-domain signals and frequency-domain sub-channels. The method includes steps A to D.

[0108] In one or more embodiments, step A constructs a multi-level bipartite tree-shaped orthogonal filter network, the network comprising Each processing level ( Each level contains several parallel processing sub-branches, with each level and sub-branch operating independently and in a distributed manner, without a globally centralized computing power scheduling center. The network has a strictly dual-symmetric topology, supporting bidirectional data stream transmission for forward signal decomposition and reverse signal synthesis. Specifically, as... Figure 2 As shown, for the decomposition and synthesis pipeline architecture with 4096 sub-channels, the network contains 12 processing layers. The first level contains 1 branch ( The second level contains 2 branches ( ),..., No. Hierarchy includes Branch paths. Levels are cascaded through a 2x extraction (forward decomposition) or 2x interpolation (backward synthesis) operation. For example... Figure 3As shown, the first-stage basic unit includes a complex mixer, a half-band filter HBF1, and a 2x decimator, wherein the complex mixer is used to convert the input signal... With rotation factor Multiplication enables spectrum shifting. For example... Figure 4 and Figure 5 As shown, the structures of the second to eleventh level first and second level basic units are similar to those of the first level basic unit, but the filter parameters can be consistent or inconsistent depending on the level.

[0109] In one or more embodiments, step B performs a forward decomposition of the time-domain digital signal, that is, it receives the time-domain digital signal and performs a forward decomposition, the time-domain digital signal containing... One sampling point, The input is any positive integer, including prime numbers (such as 139, 839) and integer powers other than 2 (such as 3, 5, 6, 7, 10, etc.). The time-domain digital signal is input into the first level of the binary tree-structured orthogonal filtering network, and 2x bandwidth compression and orthogonal subchannel subdivision are performed level by level. Specifically, when the analog-to-digital converter (ADC) of the communication baseband chip operates at a sampling rate... Output time-domain sampling sequence At that time, the sequence is directly fed into the first-level branch. Taking 4096 as an example, after a complete 12-level decomposition, the output is 4096 frequency domain sub-channel decomposition results. Each subchannel corresponds to an independent frequency domain subband.

[0110] In one or more embodiments, step C involves performing a progressive forward decomposition, i.e., performing a decomposition sub-operation at each level. Each level performs the following three sub-steps on the input signal:

[0111] Sub-step C1, in the digital complex mixing operation, with the input signal Mixed local carrier signal This is a finite-length complex number sequence. The sequence consists of discrete values ​​pre-calculated based on the principle of digital frequency circular rotation. In the hardware implementation, this sequence is not generated in real-time by the NCO, but rather by a finite state counter that tracks the current processing level l and branch number. Decoding is performed to generate a continuous address signal; this address signal is used to control the data selector (MUX) to read the corresponding complex sequence value from the local read-only memory (ROM), or to directly control the MUX to output a fixed sequence with periodicity (e.g., for a 1 / 2 frequency divider, the sequence is...). For a 1 / 4 frequency division, the sequence is: The entire mixing process is completed through a counter and number selection logic, without involving any real or complex number multiplier units;

[0112] Sub-step C2, half-band filtering or FIR filtering, performs spectrum cutting on the rotated baseband signal;

[0113] Sub-step C3, a 2x decimation operation, compresses the bandwidth of the filtered signal and outputs it to the corresponding sub-branch at the next level;

[0114] It should be noted that in the bidirectional symmetric topology of this invention, there are subtle differences in the decomposition logic between the first level and subsequent levels:

[0115] First-level decomposition: The input digital frequency is fully circularized through complex mixing and HBF cutting, divided into two semi-circular sub-bands of low frequency and high frequency, and then output after 2x decimation;

[0116] Level 2 and beyond: The system no longer operates on the full circle. The input signal of each level is treated as an independent semicircle (i.e., the sub-band cut by the previous level); this level rotates the semicircle to baseband through complex mixing, and after HBF filtering and cutting, it is further subdivided into two quadrants (i.e., two smaller semicircles); subsequently, a 2x decimation operation restores the quadrant to the semicircle format required by the next level in terms of topological logic;

[0117] By recursively subdividing the spectrum from "semicircle → quadrant → semicircle", seamless coverage of the entire frequency band is achieved. This constant half-bandwidth processing strategy is the fundamental reason why the HBF of this invention can achieve ultra-high adjacent channel rejection using a short-tap structure.

[0118] In one or more embodiments, for the first Level 1 The mathematical transformation expression for a branch is:

[0119]

[0120] in, For the first Level 1 The rotation factor of the branch, , This represents the number of branches at the current level. For time-domain sample point indexing, This is the transfer function of the baseband low-pass filter. Taking the first stage as an example, The time branch is a low-frequency branch. The time branch is a high-frequency branch. The two branches respectively rotate the frequency band to the baseband through complex mixing, and then pass through a filter. The signal is cut, then decimated by a factor of 2, and output to the corresponding sub-branch of the second level. In the digital complex mixing operation, the input signal... Mixed local carrier signal This is a finite-length complex sequence. The sequence consists of discrete values ​​pre-calculated based on the principle of digital frequency circular rotation. In the hardware implementation, this sequence is not generated in real-time by the NCO, but rather by a finite state counter that tracks the current processing level l and branch number. Decoding is performed to generate a continuous address signal; this address signal is used to control the data selector (MUX) to read the corresponding complex sequence value from the local read-only memory (ROM), or to directly control the MUX to output a fixed sequence with periodicity (e.g., for a 1 / 2 frequency divider, the sequence is...). For a 1 / 4 frequency division, the sequence is: The entire mixing process is completed through counters and number selection logic, without involving any real or complex multiplier units. The half-band filter or FIR filter adopts a linear-phase FIR structure, with an order ranging from 2nd to 128th (for example, starting from the penultimate HBF stage, using 1 tap, 3 taps, 7 taps, 15 taps, 31 taps, 63 taps, 63 taps, 63 taps, 63 taps, 63 taps, 63 taps, 63 taps, 127 taps respectively). The specific order is determined based on the target stopband attenuation and passband ripple. After the filtering operation is completed, the 2x decimator discards every other sampling point to achieve bandwidth compression. Starting from the second level, the 2x decimation restores the quadrant of the cut semicircular frequency band (i.e., one of the two quadrants formed by cutting the semicircular frequency band) to a semicircular frequency band, so that the same digital complex mixing and filtering cutting operation can be repeated in the next level to achieve a complete and comprehensive tree-structured spectrum decomposition.

[0121] In one or more embodiments, the filters used in each level may be consistent or inconsistent in parameters such as passband ripple, stopband attenuation, and order, and can be freely selected according to the target spectrum segmentation accuracy and computational overhead requirements. For example, for the decomposition levels at the starting point (levels 1 to 3), higher-order filters (such as 32nd to 128th order) can be selected to obtain a steeper transition band and higher stopband attenuation (such as ≥80dB), thereby better suppressing near-end spectrum leakage; for decomposition levels far from the starting point (levels 10 to 12), lower-order filters (such as 1st to 32nd order) can be selected to reduce computational load, and the stopband attenuation can be relaxed to 50dB to 60dB. This differentiated configuration allows the system to obtain different spectrum segmentation accuracies and computational overheads in different frequency bands, achieving an optimal trade-off between performance and resources. Furthermore, the passband ripple of each filter level can also be configured independently: for the level where the sub-channel carrying critical control signals is located, the passband ripple can be set to ≤0.1dB to ensure signal fidelity; for the level where the sub-channel carrying general data services is located, the passband ripple can be relaxed to 0.5dB to reduce the filter order and computational overhead.

[0122] In one or more embodiments, step D performs reverse synthesis by switching the signal flow transmission direction in the bipartite tree orthogonal filter network, inputting the frequency domain sub-channel signal into the reverse path of the network, and progressively completing the 2x bandwidth expansion and multi-subband signal synthesis, outputting the time-domain signal reconstruction result; the reverse synthesis process is a strict dual operation of the forward decomposition process in step C. Specifically, in reverse synthesis mode, the input is the frequency domain sub-channel signal. ( (Total number of sub-channels) In each synthesis level, after adding and synthesizing the input sub-band signals from two sub-branches, a digital complex mixing operation is performed to rotate the synthesized signal to the corresponding frequency band. Then, a 2x interpolation operation is performed (i.e., a zero point is inserted between every two adjacent sampling points, and then the image spectrum is removed by low-pass filtering), gradually recovering the complete bandwidth time domain signal. Due to the strict duality of the topology, reverse synthesis uses the same hardware network as forward decomposition, only the signal flow is reversed.

[0123] In one or more embodiments, step D specifically includes: performing a 2x interpolation operation on the input sub-band signal to expand the bandwidth; specifically, for each input sampling point, the sampling point and a zero value are output sequentially at the output terminal, thereby increasing the sampling rate by 2x; performing a digital complex mixing operation on the interpolated signal to rotate each sub-band to the corresponding splicing angle, i.e., multiplying by a rotation factor. (Opposite sign to the decomposition direction); perform superposition synthesis on each spliced ​​component, that is, add multiple sub-band signals at the same level; restore the complete bandwidth time domain signal step by step.

[0124] In one or more embodiments, the method further includes a flexible subcarrier configuration step. Based on general service spectrum requirements, independent switching operations are performed on any sub-branch in the bipartite tree orthogonal filtering network to independently add, remove, enable, disable, and reassemble any subcarrier. For example, in narrowband Internet of Things (NB-IoT) applications, the system only needs to activate 1 to 16 subcarriers, and the remaining subcarriers can all be disabled. In this case, the flexible subcarrier configuration controller sends a shutdown enable signal to each branch, sets the clock gating signal of the inactive branch to active, and cuts off the clock input of that branch. The flexible configuration includes continuous subcarrier batch regularization configuration (e.g., enabling 100 consecutive subcarriers from 0 to 99 at once) and non-continuous discrete subcarrier custom combination configuration (e.g., enabling only five discrete subcarriers: 3, 7, 15, 31, and 63). The flexible configuration does not require changes to the hardware architecture or topology; it can be achieved simply by modifying the enable signals of each branch through configuration registers, adapting to various complex and general scenarios such as fragmented spectrum, dynamic spectrum scheduling, and customized sub-channels.

[0125] In one or more embodiments, the method further includes a branch-level computing power management step:

[0126] First, the time-domain energy statistical characteristics of each independent branch are collected in real time. These time-domain energy statistical characteristics include the average power of the branch. ( (Observation window length), peak-to-average ratio and inter-level power attenuation (in The input power of the current branch, (This refers to the output power of the current branch). In hierarchical tree decomposition, the power distribution of the effective signal has a specific inter-level variation law when it is decomposed layer by layer (the power attenuation of the effective signal branch matches the passband energy ratio of the filter), while the power attenuation characteristics of the pure noise branch do not conform to this law.

[0127] Then, using multi-dimensional feature criteria, each branch is classified into a working branch carrying valid signals or an idle branch not carrying valid information: when the average power of the branch is lower than a preset threshold. (Typically set to noise floor power plus a 6dB margin), and peak-to-average power ratio below a preset threshold. When the power attenuation between levels deviates from the theoretical attenuation by more than the preset deviation threshold (usually ±3dB), it is determined to be an idle branch.

[0128] Finally, independent clock gating is performed on branches classified as idle and invalid. That is, the clock signal of the branch is forced to a low level through the clock gating unit, cutting off the subsequent invalid operations and data transmission of the branch. For branches containing valid signal energy and critically ambiguous branches (that is, branches whose features exceed the threshold but may contain valid signals as a whole), the complete hierarchical operation is retained throughout the process to strictly ensure the accuracy of orthogonal transformation and signal integrity.

[0129] In one or more embodiments, to ensure the stability of branch state switching and prevent frequent misjudgments caused by transient noise, the state decision submodule employs a hysteresis comparison mechanism. Specifically, when a branch is determined to be in an idle state, it needs to continuously observe valid signal features exceeding a threshold for a preset number of times (e.g., three consecutive observation windows) before switching to an active state; similarly, when a branch is determined to be in an active state, it needs to continuously observe idle features for a preset number of times (e.g., five consecutive observation windows) before switching to an idle state. The length of the observation window is configurable, typically ranging from 128 to 1024 sampling points. Through this hysteresis mechanism, frequent branch state switching caused by instantaneous signal fluctuations is avoided, ensuring the stability of system operation.

[0130] In one or more embodiments, based on branch-level computing power management, the method further includes a statistically driven dynamic power consumption optimization step. Specifically, the system periodically counts the number and proportion of branches that are gated and shut down in each level. When the proportion of idle branches in a certain level exceeds a preset threshold (e.g., 75%), the system automatically triggers power consumption optimization measures at higher levels, including but not limited to: reducing the overall clock frequency of that level (Dynamic Frequency Scaling, DFS), temporarily shutting down the power supply to that level (Power Gating, PG), etc. Simultaneously, the system feeds back the idle branch proportion information of each level to the level truncation controller, providing a decision basis for level dynamic truncation. The above statistical period can be set by an external configuration register, ranging from 1ms to 100ms. Through this statistically driven optimization, the dynamic power consumption of the system is further reduced.

[0131] In one or more embodiments, the method further includes a dynamic truncation step for the tree-based computation hierarchy. Based on the system's preset transformation accuracy, transmission delay, and power consumption constraints, the computation iteration depth of the bipartite tree-based orthogonal filter network is adaptively selected. ,in Keep the minimum Effective computation level, truncation above The layer refinement decomposition operation minimizes computational overhead while ensuring the completeness of the orthogonal transformation. For example, in low-power modes or scenarios where high transformation accuracy is not required, the following settings can be configured: This involves truncating the two finest layers of decomposition. In this case, the number of output sub-channels is reduced to 1 / 4 of the original, but the computational load is reduced by approximately 50%. The hierarchical truncation controller sends a global shutdown signal to each branch of the truncated layer, switching the input multiplexer of the corresponding branch to zero-value input and directly bypassing the output result to the corresponding position of the output interface. Specifically, when dynamically truncated to... When the layer is reached, the first Layer to the first All branches of the layer are globally turned off, and the output of the turned-off branches outputs a zero value through a multiplexer (MUX). Through the above-mentioned hierarchical dynamic truncation mechanism, a dynamic balance is achieved between orthogonal transformation accuracy, transmission delay, and power consumption.

[0132] In one or more embodiments, the number of sampling points of the time-domain digital signal When it is a prime number (e.g.) =139、 =839), requiring no zero-padding, interpolation, or approximation, the precise orthogonal time-frequency transformation is directly achieved through the bipartite tree-shaped orthogonal filter network, outputting the same... The frequency domain decomposition result is equivalent to the point orthogonal transformation; its principle is that: each level of the bipartite tree network only performs a 2x bandwidth compression, and there is no fixed number of base points (such as radix-2, radix-4) iterative constraint. Therefore, regardless of the value of N, the tree decomposition can be performed in the ⌈ Full spectrum coverage is achieved within the layer. When When the value is not a power of 2, the tree network can be configured at the last level to include only the required number of branches for sub-channels, with any excess branches remaining closed.

[0133] In one or more embodiments, the multi-level binary tree-structured step-by-step filtering superposition forms the out-of-band attenuation characteristic, and the total out-of-band attenuation is the sum of the out-of-band attenuation of each filter level. Specifically, when the single-stage stopband attenuation of each half-band filter is... (Unit: dB) Total out-of-band attenuation ,in This represents the actual number of computational stages. With a stopband attenuation of 40dB per stage, it far exceeds the 13dB suppression of the first sidelobe of the implicit CIC filter in traditional FFT. Therefore, it can meet the adjacent channel interference suppression requirements without additional pre- or post-stage brick-wall filters, and the number of blank guard subcarriers can be reduced to zero or less than 20% of the number required by traditional FFT / IFFT. Actual measurements show that, under the same subcarrier spacing and spectrum template requirements, the scheme of this invention can reduce the number of guard subcarriers from approximately 20% of traditional OFDM to less than 2%.

[0134] In one or more embodiments, the method further includes a frequency domain equalization post-processing step. After completing the full tree-shaped frequency domain decomposition, complex division is performed on the corresponding sub-channels using known information (such as pilot signals) transmitted at known frequency points. ,in For the receiving end Frequency domain data of each sub-channel For the known reference signal transmitted to this sub-channel, the channel gain and phase shift information at that frequency point are obtained. When multiple known frequency points exist, linear interpolation or spline interpolation is applied to the channel gain and phase shift information of multiple known frequency points to obtain the full-channel frequency domain response equalization parameters. For the ... Each sub-channel, the equalized data is Because this invention has a hierarchical architecture, the above-mentioned frequency domain equalization operations can be performed independently at each level. For example, overall channel characteristic compensation can be performed at a higher level (coarse-grained), and sub-band frequency-selective fading compensation can be performed at a lower level (fine-grained), thus achieving multi-granularity joint equalization.

[0135] In one or more embodiments, multi-granularity joint equalization is implemented as follows: First, coarse-grained equalization is performed at levels 1 to 3 (higher levels, corresponding to the broadband range), using multiple pilot signals distributed across the broadband range to estimate the broadband channel characteristics and compensate for overall time delay and frequency offset. Then, fine-grained equalization is performed at levels 4 to 12 (lower levels, corresponding to the narrowband sub-channel range), using dedicated pilot signals within each sub-band to estimate the residual frequency-selective fading within the sub-band and finely compensate for the residual error after coarse-grained equalization. The equalization parameters for coarse-grained and fine-grained equalization are obtained through joint iterative optimization: first, the fine-grained equalization parameters are fixed (initially set to 1), and the coarse-grained equalization parameters are optimized to minimize the overall error; then, the coarse-grained equalization parameters are fixed, and the fine-grained equalization parameters are optimized sub-band by sub-band. Through the above multi-granularity joint equalization, the equalization accuracy of the system under frequency-selective fading channels is significantly improved.

[0136] In one or more embodiments, the method further includes a sub-band noise reduction post-processing step. After completing the full tree-shaped frequency domain decomposition, the sub-channel frequency domain data corresponding to the idle and invalid branches classified by the multi-dimensional feature criteria are directly set to zero. Specifically, the idle branch identification signal output by the state decision submodule... ( When the total number of sub-channels is high, the corresponding frequency domain data Forced to zero by the multiplier: That is, when =1 =0, when =0 Subband-level noise suppression can significantly improve the signal-to-noise ratio, especially in applications such as spread spectrum communication and ultra-narrowband signal detection, where it can increase the signal-to-noise ratio by 3dB to 10dB.

[0137] In one or more embodiments, the digital complex mixing operations at different levels in step C use the same twitch factor. Definition, where The value is the current branch number in the corresponding level, enabling arbitrary rotation and segmentation of the digital frequency circle. The segmentation methods include left and right semicircle segmentation (i.e., the conventional QMF method, dividing the digital frequency circle into left and right semicircles along the vertical axis), upper and lower semicircle segmentation (i.e., dividing the digital frequency circle into upper and lower semicircles along the horizontal axis), and segmentation after arbitrary angle rotation (i.e., first rotating by an arbitrary angle). Then perform semi-circular segmentation. Different segmentation methods can be achieved by adjusting the rotation factor in the complex mixer: left and right segmentation correspond to... =0, corresponding to the upper and lower divisions Divide into corresponding angles The value can be any value. This is essentially a generalization of QMF as a special case of left and right semicircle division.

[0138] In one or more embodiments, when using a semi-circular split method, the first-stage complex mixer multiplies the input signal by... (Keep the upper semicircle) and (Rotate the lower semicircle to the baseband), where, The time-domain samples are indexed and then cut by a baseband low-pass filter to separate the upper and lower halves of the digital frequency circle. This separation is achieved when using arbitrary angles. In the split-processing mode, the first-stage complex mixer multiplies the input signal by... and To achieve along any angle Diameter separation. After arbitrary angle segmentation, starting from the second level, the quadrants of the cut semicircular signal are decimated by a factor of 2 to restore the semicircle. This allows for further subdivision at the same or different angles in subsequent levels. This enables the system to flexibly select the optimal segmentation strategy to suit specific signal characteristics.

[0139] In one or more embodiments, the application scenarios of the method include: OFDM modulation and demodulation modules in communication systems, used to replace FFT / IFFT to achieve modulation and demodulation of multi-carrier signals; Doppler processing and range dimension imaging modules in radar systems, used to replace FFT to achieve two-dimensional detection of pulse Doppler radar; time-frequency transformation modules in spectrum analyzers, used to replace FFT to achieve high-resolution spectrum observation; transformation modules in audio and video encoding and decoding, used to replace DCT / DST to achieve compression coding; and fast convolution operation modules in artificial intelligence acceleration, used to replace FFT to achieve convolution acceleration.

[0140] In one or more embodiments, to ensure operational correctness, the method further includes pipeline emptying and state synchronization steps during the switching process between forward decomposition and reverse synthesis. Specifically, when a direction switching command is received, the system performs the following operations: First, it stops new data input in the current direction and waits for all existing data in the pipeline to be processed and output. The number of waiting cycles required for this process is equal to the total number of pipeline stages multiplied by the delay per stage (typically L×D). cycle D cycle (This is the number of single-stage pipeline delay cycles). Then, the register states in all levels are reset to their initial values. The reset operation is performed by sending a global reset signal. This is achieved by setting the clock cycle lower; finally, the flow control signal of the multiplexer is changed. ( =0 indicates a positive decomposition mode. When =1, it is in reverse synthesis mode, and data input in the new direction restarts. During pipeline purging, the VALID signal of the output interface remains low, indicating that the output data is invalid. Through the above purging and synchronization steps, data conflicts and residual data interference are ensured during direction switching.

[0141] In one or more embodiments, when the system detects an abnormal condition, an error handling procedure is executed. The abnormal condition includes: input signal power exceeding a preset threshold (indicating potential ADC saturation), filter output data overflow (indicating improper filter gain settings), and branch state decision results not matching expectations (indicating potential hardware failure). The error handling procedure includes at least one of the following operations: terminating the current operation and clearing all pipeline registers, logging an error log to on-chip memory or an external debug interface, and reverting the system state to the last known correct configuration state. When the input signal power exceeds the preset threshold, the system automatically triggers a gain adjustment procedure, adjusting the gain setting of the front-end variable gain amplifier (VGA) to bring the input signal power back to the normal range, and then automatically resumes operation.

[0142] It should be noted that, through the coordinated operation of steps A to D above, this invention achieves a hierarchical distributed time-frequency orthogonal transform based on a binary tree structure. Compared with the traditional centralized block transform architecture of FFT / IFFT, it has the comprehensive technical effects of arbitrary point native adaptation, streaming point-by-point real-time processing, ultra-high adjacent channel suppression, full degree of freedom subcarrier configuration, and single hardware bidirectional multiplexing, which significantly improves the latency performance, spectral efficiency, flexibility, and power consumption of digital signal processing systems.

[0143] refer to Figure 6 This diagram illustrates a bidirectional symmetric binary tree-based multicarrier decomposition and synthesis apparatus according to one or more embodiments of this application. The apparatus includes an input interface, a multi-level binary tree-based orthogonal filter network, a finite-length sequence mixer group, a filter group, a decimator group, an interpolator group, and an output interface. This apparatus can be integrated into a communication baseband chip, a radar signal processing chip, a spectrum analyzer signal processing board, or an AI acceleration chip to achieve bidirectional orthogonal transformation between time-domain signals and frequency-domain sub-channels.

[0144] In one or more embodiments, the input interface is used to receive time-domain digital signals or frequency-domain sub-channel signals. The input interface includes a data input port DIN[15:0] (16-bit parallel data bus) and a data valid flag. Clock input CLK and mode selection port When a time-domain digital signal is input, =0, the input interface will have a sampling rate of 0. temporal sampling sequence ( After being buffered to the input FIFO (First-In-First-Out memory), the signal is output to the first level of a multi-stage binary tree orthogonal filter network in a pipelined manner. When a frequency domain sub-channel signal is input, =1, the input interface will input frequency domain subchannel data ( The total number of sub-channels is buffered and then output to the last level of the network for reverse synthesis operations.

[0145] In one or more embodiments, the multi-level bipartite tree orthogonal filter network comprises L processing levels ( ≥1), each level contains Parallel processing sub-branch ( For level number, ).like Figure 2 As shown, in one specific embodiment, =12, the network as a whole exhibits a strict binary tree topology: the first level contains 1 branch, the second level contains 2 branches, the third level contains 4 branches, ..., the twelfth level contains 2048 branches. The levels are cascaded through 2x decimation (forward decomposition) or 2x interpolation (backward synthesis). Each sub-branch operates independently and in a distributed manner, without a global centralized computing power scheduling center. Each branch contains an independent complex mixer, filter, and decimation / interpolation unit. The entire network has a strictly dual symmetric topology, meaning the topological structures of the forward decomposition path and the backward synthesis path are completely symmetrical, and the mathematical models are strictly dual, differing only in the direction of signal flow transmission (by a mode selection signal). Function switching is achieved by controlling the data flow of multiplexers at each level. The branches in the network are connected through an on-chip interconnect bus, and the data transmission delay between branches is aligned by the pipeline register. The typical pipeline delay is 1 clock cycle per stage.

[0146] In one or more embodiments, a finite-length sequence mixer group is disposed in each sub-branch of each level to rotate the frequency band to be processed to the baseband (forward decomposition direction) or to rotate the baseband signal to the target frequency band (backward synthesis direction). Each mixer unit does not contain an NCO or CORDIC iterative operation unit, but consists of a counter group, an address decoding logic, and a data selection / mapping network. The counter group generates an address code for indexing the local finite-length sequence based on the system master clock and the division ratio of the current level; the data selection network selects the corresponding complex samples (I / Q paths) from a preset sequence set based on the address code and multiplies them with the input data. Here, the multiplication is for... Typical sequence values ​​are reduced to simple inversion, zeroing, or pass-through operations, resulting in extremely low hardware cost. This design utilizes the finite states and periodicity of the twitch factor sequence in this invention, which is one of the core advantages of this invention in hardware implementation compared to traditional FFT / IFFT. The mixer unit is based on the hierarchical sequence number of the current branch. and branch number Generate rotation factor sequence (Forward decomposition direction) or (Reverse synthesis direction), where, This represents the total number of branches at the current level. This is the time-domain sample index. The complex multiplier performs complex multiplication on the input complex signal and the rotation factor:

[0147]

[0148] .

[0149] In one or more embodiments, due to the finite period characteristics of the local oscillator signal, complex mixing can be achieved using a counter-controlled number selection branch to realize extremely simple mixing. This eliminates the need for multiplier resources, significantly saving hardware resources and reducing power consumption.

[0150] In one or more embodiments, filter banks are positioned in each sub-branch of each level and after the finite-length sequence mixer bank for performing spectral cutting (forward decomposition) or spectral splicing (backward synthesis) on the baseband signal. Each filter is implemented using a half-band filter (HBF) or a linear-phase FIR filter. Half-band filters have the excellent characteristic that approximately half of the filter coefficients are zero, significantly reducing the amount of multiplication operations. The transfer function of the FIR filter is... ,in These are the filter coefficients. Let be the filter order. For a half-band filter, when... When it is an odd number =0 (except for the center tap), therefore the computational load is approximately half that of a comparable FIR filter. The filter order and coefficients for each stage are configured independently based on the target stopband attenuation and passband ripple. For example, stages 1 to 4 (closer to the DC component) use 64th-order half-band filters with stopband attenuation ≥80dB and passband ripple ≤0.05dB; stages 5 to 8 use 32nd-order half-band filters with stopband attenuation ≥60dB and passband ripple ≤0.1dB; stages 9 to 12 (closer to the high-frequency band) use 16th-order half-band filters with stopband attenuation ≥40dB and passband ripple ≤0.3dB. Filter parameters can be consistent or inconsistent between different stages—the parameters at each stage in the above configuration are inconsistent to adapt to the performance requirements of different frequency bands. The filter coefficients are stored in on-chip read-only memory (ROM) and loaded into the coefficient registers of each filter via the configuration bus during system initialization.

[0151] In one or more embodiments, the operation of each filter is implemented as follows: First, the accumulator is initialized. 0, pointer =0; then, for each input sampling point Perform loop operations—for =0 to ,when ≠0 o'clock, ,when If the sum is 0, skip the multiplication-addition operation; after the loop ends, value right shift Bit( This is the normalized shift amount for the filter gain (typically 15 to 20) before output; finally, the pointer is moved to the next sampling point. For half-band filters, since odd-indexed coefficients are zero, the actual multiply-accumulate operation is only... This significantly reduces computational complexity.

[0152] In one or more embodiments, a decimator group is positioned after the filter group for double bandwidth compression in the forward decomposition direction. Each decimator is a 2:1 downsampler that outputs one sample point for every two consecutive input samples (discarding either even or odd sample points, selected by the configuration register). In the forward decomposition, the sampling rate is halved after passing through the decimator, and the signal bandwidth is compressed to half its original value.

[0153] In one or more embodiments, an interpolator group is positioned after the filter bank to provide a 2x bandwidth extension in the inverse synthesis direction. Each interpolator is a 1:2 upsampler that outputs a sample point and a zero value (zero insertion) sequentially at the output for each input sample point, thus doubling the sampling rate. In inverse synthesis, the sampling rate is doubled after passing through the interpolators, and then the image rejection filter in the filter bank removes the image spectrum generated by the interpolation.

[0154] In one or more embodiments, the output interface is used to output the frequency domain subchannel decomposition result (forward decomposition mode) or the time domain signal reconstruction result (reverse synthesis mode). The output interface includes a data output port DOUT[15:0] and an output valid flag. And the output ready flag RDY. In forward decomposition mode, the output interface will output the frequency domain data of each sub-channel. ( The total number of effective sub-channels is arranged by sub-channel number and output to subsequent processing modules (such as channel equalizers, demodulators, etc.). In reverse synthesis mode, the output interface will reconstruct the time-domain sampling sequence. ( It continuously outputs to subsequent modules (such as digital-to-analog converters, upconverters, etc.).

[0155] In one or more embodiments, the device switches between forward decomposition and reverse synthesis modes by switching the direction of signal stream transmission, and reuses the same hardware network. Mode switching is controlled by an external control signal. control, =0 indicates a positive decomposition mode. When =1, it is in reverse synthesis mode. During mode switching, the system automatically performs pipeline draining (refer to the description in the aforementioned method embodiments) and register reset operation to ensure a clean and efficient mode switching.

[0156] In one or more embodiments, in the forward decomposition mode, the multi-level bipartite tree orthogonal filter network converts the time-domain signal into a signal similar to... The frequency domain subchannel decomposition output is equivalent to the point FFT. In the reverse synthesis mode, the multi-level bipartite tree orthogonal filter network reconstructs the frequency domain subchannel signal into a form that is equivalent to the point FFT output. The time-domain output signal equivalent to point IFFT.

[0157] In one or more embodiments, the device further includes a subcarrier flexible configuration controller connected to each branch of the multi-level binary tree orthogonal filter network, used to independently switch any branch according to external configuration commands, realizing subcarrier addition, reduction, activation, deactivation, and reconfiguration operations. The subcarrier flexible configuration controller is connected to the enable terminal EN of each branch via a configuration bus. When a branch is deactivated, the enable signal of that branch is activated. =0, all register clock signals within the branch are gated, and the output of the combinational logic circuit is forced low (zero output), thereby eliminating the dynamic power consumption of that branch. When a branch is enabled, =1, the branch is working normally. Configuration commands are written to the configuration register via an external SPI or AXI-Lite interface. Each branch corresponds to one bit in the configuration register. Taking 4096 sub-channels as an example, a total of 4096 configuration bits are required, mapped to 256 32-bit configuration registers. The controller supports batch regularization configuration of continuous subcarriers (such as enabling continuous subcarriers 0 to 99 at once by using the start address and length fields) and custom combination configuration of non-continuous discrete subcarriers (such as configuring the state of each subcarrier one by one through a bitmap), which can adapt to complex scenarios such as fragmented spectrum and dynamic spectrum access.

[0158] In one or more embodiments, the device further includes a branch status monitoring and gating module. The branch status monitoring and gating module includes an energy statistics submodule, a status decision submodule, and a clock gating submodule.

[0159] In one or more embodiments, an energy statistics submodule is connected to each independent branch to collect the time-domain energy statistics characteristics of each branch in real time. These characteristics include the branch's average power. (Smoothed calculation using IIR filter:) ,in The forgetting factor (typically 1 / 128 to 1 / 1024), peak-to-average power ratio (PAPR, calculated by comparing peak power recorded in the window with average power using the maximum value register), and inter-level power attenuation are also included. (Calculated by comparing the current branch output power with the upstream input power). The energy statistics of each branch are stored in the status register as 16-bit fixed-point numbers for the status decision submodule to read.

[0160] In one or more embodiments, the state decision submodule is connected to the energy statistics submodule and is used to classify each branch into working branches or idle branches based on the time-domain energy statistics characteristics using multi-dimensional criteria. Specifically, the state decision submodule has three built-in comparators that compare the average power of the branch with a preset threshold. (Typical values ​​range from -30dBm to -60dBm, configurable), Peak-to-Average Power Ratio and Preset Threshold (Typical values ​​are 3dB to 6dB, configurable), the deviation between inter-level power attenuation and theoretical attenuation from the preset deviation threshold. (Typical value ±3dB, configurable). When all three criteria indicate that the branch is idle, the status decision submodule outputs an idle flag. =1; otherwise output 1. =0. The status decision result is stored in the status register and can be read via the configuration bus to monitor the system's operating status.

[0161] In one or more embodiments, a clock gating submodule is connected to the state decision submodule and each branch, and is used to perform independent clock gating on branches classified as idle by the state decision submodule. The clock gating submodule includes clock gating units corresponding to each branch, each clock gating unit being a combination of a latch and an AND gate.

[0162] when When =1, the clock gate unit output is always low, cutting off the clock input of this branch, thereby eliminating the dynamic power consumption of this branch.

[0163] when When CLK = 0, the clock gating unit directly outputs the system clock CLK to the branch, and the branch works normally. Actual measurements show that for sparse signal scenarios (such as activating only 12 NB-IoT sub-channels), clock gating can reduce the power consumption of ineffective branches by approximately 98%.

[0164] In one or more embodiments, the apparatus further includes a hierarchical truncation controller connected to each level, configured to adaptively select the computational iteration depth of the multi-level bipartite tree orthogonal filter network based on preset transformation accuracy, transmission delay, and power consumption constraints. ( ), cutoff above The hierarchical refinement and decomposition of computational paths. The hierarchical truncation controller includes a configurable depth register. And a set of multiplexers (MUX). When selecting depth At that time, the controller sends to the first All branches from layer L to layer L send a global shutdown signal. =1, simultaneously controlling the first The layer's output multiplexer bypasses data directly to the output interface, skipping truncated refinement levels. The depth register can be written to via an external configuration interface, supporting dynamic adjustment.

[0165] In one or more embodiments, the number of time-domain digital signal sampling points received by the input interface is: ( (where is any positive integer), the number of levels in the multi-level bipartite tree orthogonal filter network in the device. satisfy Selected via hierarchical cutoff controller Layer operations. When When it is a prime number (e.g.) =139), The device only uses 8 layers of operation (corresponding to 256 sub-channel capacity), and the actual effective sub-channels are 139. The redundant sub-channels (140 to 255) are shut down by the subcarrier flexible configuration controller. When the number is a prime number, no zero padding is required, achieving native precise transformation.

[0166] In one or more embodiments, the out-of-band attenuation of the filter bank is accumulated step by step, with the total out-of-band attenuation being... satisfy:

[0167]

[0168] in For the first Out-of-band attenuation of a single stage of a hierarchical filter (unit: dB). This represents the actual number of computational levels. Total out-of-band attenuation. This allows the device to meet adjacent channel interference suppression requirements without the need for an external brick wall filter. In a typical embodiment, the stopband attenuation of each stage is 40 dB. =12, far exceeding the 3GPP TS 38.104 standard's requirement for adjacent channel leakage ratio (ACLR) of 5G base station transmitters (approximately 45dB). Therefore, the device does not require additional pre- or post-stage brick-wall filters in most application scenarios, effectively simplifying the system hardware links.

[0169] In some embodiments, when the device is integrated into a communication baseband chip, it is interconnected with other modules within the chip (such as channel encoders, modulators, equalizers, demodulators, etc.) via an AXI bus, sharing on-chip SRAM resources. The area overhead of the device in the chip is approximately less than 50% of the area of ​​an equivalent FFT / IFFT accelerator under the same clock frequency. However, since no additional brick-wall filters are required before and after the main stage (traditional FFT schemes require filters with an area of ​​approximately 0.3 to 0.5 times that of the FFT), the overall chip area can be reduced to less than 30%.

[0170] In one or more embodiments, the device further includes a self-test module for performing a self-test operation when the system is powered on. The self-test module internally stores several sets of known test vectors (time-domain test sequences and their corresponding standard frequency-domain decomposition results, and frequency-domain test sequences and their corresponding standard time-domain synthesis results). During self-testing, a built-in comparator compares the actual output of the device with the standard results, with a comparison deviation tolerance of ±2 LSB (least significant bit). When a deviation exceeds the tolerance, the self-test module outputs a FAIL flag and records the fault branch number to a fault register for debugging purposes. When all test vectors pass, a PASS flag is output, and the device enters normal operating mode. This self-test mechanism effectively screens for manufacturing defects, improving the mass production yield and reliability of the device.

[0171] In one or more embodiments, when the device detects an abnormal condition, an error handling procedure is executed. The abnormal condition includes: input interface FIFO overflow (indicating that the data input rate exceeds processing capacity), filter output data overflow (indicating that the signal power exceeds the filter's dynamic range), and branch state decision results not matching configuration expectations (indicating a possible hardware fault). The error handling procedure includes at least one of the following operations: terminating the current operation and clearing all pipeline registers, recording an error log to the log area in the on-chip SRAM (the log content includes the error type, occurrence time, and faulty branch number), notifying the main control CPU via an interrupt signal, and performing a system state rollback to the last known correct configuration snapshot.

[0172] Through the collaborative work of the above modules, a hierarchical distributed time-frequency orthogonal transformation device based on a bipartite tree structure was realized. Compared with traditional FFT / IFFT accelerators, this device has comprehensive advantages such as native adaptation to any number of points, streaming point-by-point real-time processing, ultra-high adjacent channel suppression, full-degree-of-freedom subcarrier configuration, and single hardware bidirectional multiplexing. It can serve as the core time-frequency transformation unit in next-generation communication, radar, and spectrum measurement equipment.

[0173] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, the phrase "comprising an element defined as..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0174] The above technical solutions only embody the preferred technical solutions of the present invention. Any modifications that may be made by those skilled in the art to certain parts thereof embody the principles of the present invention and fall within the protection scope of the present invention.

Claims

1. A bidirectional symmetric binary tree-based multicarrier decomposition and synthesis method, characterized in that, The method includes the following steps: Step A: Construct a multi-level bipartite tree-structured orthogonal filtering network, the network comprising... Each processing level Each level contains several parallel processing sub-branches, and each level and each sub-branch performs independent distributed operations; the network has a strictly dual symmetric topology and supports bidirectional data stream transmission for forward signal decomposition and reverse signal synthesis. Step B: Perform forward decomposition of the time-domain digital signal and input the time-domain digital signal, which includes... One sampling point, Let be any positive integer, including prime numbers and integer powers other than 2; input the time-domain digital signal into the first level of the binary tree orthogonal filter network, perform 2x bandwidth compression and orthogonal subchannel subdivision step by step, and output the frequency domain subchannel decomposition result; Step C: Perform progressive forward decomposition, progressively completing 2x bandwidth compression and orthogonal sub-channel subdivision. Specifically, this includes: performing digital complex mixing on the input signal at each level. The mixing operation uses a locally stored finite-length complex sequence to multiply the input signal. The finite-length complex sequence is addressed by a counter and read from a local lookup table by a data selector, or the counter controls the data selector to directly output a finite-length periodic sequence to rotate the frequency band to be analyzed to the baseband. Half-band filtering or FIR filtering is performed on the rotated baseband signal to complete the spectrum cutting. A 2x decimation operation is performed on the filtered signal to compress the bandwidth, and the signal is output to the corresponding sub-branch at the next level. Step D: Perform reverse synthesis. By switching the signal flow transmission direction in the bipartite tree orthogonal filter network, the frequency domain sub-channel signal is input into the reverse path of the network, and the 2x bandwidth expansion and multi-subband signal synthesis are completed step by step, and the time domain signal reconstruction result is output. The digital complex mixing operation in step C is equivalent to the rotation of the digital frequency circle, which is used to rotate the arbitrary angle sector frequency band to be decomposed to the baseband position, so that the unified baseband low-pass filter can complete the cutting process of frequency band components of different angles. The 2x decimation operation starts from the second level and restores one quadrant of the semicircular frequency band after it has been cut into a semicircular frequency band. Then, the same digital complex mixing and filtering cutting operation is repeated in the next level to achieve complete spectrum decomposition of the whole tree without omission. The reverse synthesis process in step D is the exact dual operation of the forward decomposition process in step C, specifically including: The input sub-band signal is subjected to a 2x interpolation operation to expand the bandwidth. The interpolated signal is then subjected to a digital complex mixing operation to rotate each sub-band to the corresponding splicing angle. Finally, each spliced ​​component is superimposed and synthesized to gradually restore the complete bandwidth time domain signal.

2. The method according to claim 1, characterized in that, It also includes the subcarrier flexible configuration steps: Based on the spectrum requirements of general services, an independent switching operation is performed on any sub-branch in the bipartite tree orthogonal filter network to independently add, remove, turn on, turn off, and recombine any subcarrier; The flexible configuration includes continuous subcarrier batch regularization configuration and non-continuous discrete subcarrier custom combination configuration.

3. The method according to claim 1, characterized in that, It also includes branch-level computing power management steps: Real-time acquisition of time-domain energy statistical characteristics of each independent branch, including branch average power, peak-to-average power ratio, and inter-level power attenuation; Based on multi-dimensional feature criteria, each branch is classified into a working branch carrying a valid signal or an idle branch that does not carry valid information. For branches classified as idle or invalid, an independent clock gating is performed to truncate subsequent invalid operations and data transmissions of that branch; for branches classified as active, the complete hierarchical operations are preserved.

4. The method according to claim 1, characterized in that, It also includes a dynamic truncation step for tree-based computation levels: adaptively selecting the computation iteration depth of the bipartite tree orthogonal filter network based on the system's preset transformation accuracy, transmission delay, and power consumption constraints. ,in Keep the minimum Effective computation level, truncation above The layer refinement decomposition operation minimizes computational overhead while ensuring the completeness of orthogonal transformation.

5. The method according to claim 1, characterized in that, The number of sampling points of the time-domain digital signal When the value is a prime number, no zero-padding, interpolation, or approximation is required. The precise orthogonal time-frequency transformation is directly achieved through the bipartite tree-shaped orthogonal filter network, and the output is... The frequency domain decomposition result is equivalent to the point orthogonal transformation.

6. A bidirectional symmetric binary tree-shaped multi-carrier decomposition and synthesis device, characterized in that, The apparatus is used to implement the method as described in any one of claims 1 to 5, the apparatus comprising: The input interface is used to receive time-domain digital signals or frequency-domain sub-channel signals; Multi-level bisection tree orthogonal filter network, including Each processing level Each level contains One parallel processing sub-branch, The hierarchy number is used as the hierarchical number. Each hierarchy is cascaded through a 2x extraction or 2x interpolation operation. Each sub-branch is independently distributed and operated. The network has a strictly dual symmetric topology. A finite-length sequence mixer group, located in each sub-branch of each level, includes a counter, an address generator, and a lookup table (LUT) or data selector (MUX) storing a finite-length complex number sequence. It is used to rotate the frequency band to be processed to the baseband or the baseband signal to the target frequency band by multiplying it with the local finite-length complex number sequence. No multiplier resources are required in the mixing operation. A filter bank, located in each level of sub-branch and after the finite-length sequence mixer bank, is used to perform spectral cutting or splicing on the baseband signal. An extractor group, positioned after the filter group, is used for 2x bandwidth compression in the decomposition direction; An interpolator group, positioned after the filter group, is used for a 2x bandwidth extension in the synthesis direction; The output interface is used to output the frequency domain subchannel decomposition results or the time domain signal reconstruction results. The device switches between forward decomposition mode and reverse synthesis mode by switching the signal stream transmission direction, and reuses the same set of hardware network.

7. The apparatus according to claim 6, characterized in that, In the forward decomposition mode, the multi-level bipartite tree orthogonal filter network converts the time-domain signal into a signal similar to... The frequency domain subchannel decomposition output equivalent to point FFT; In the reverse synthesis mode, the multi-level binary tree orthogonal filter network reconstructs the frequency domain sub-channel signal into a signal that is analogous to the signal in the reverse synthesis mode by switching the signal flow direction. The time-domain output signal equivalent to point IFFT.

8. The apparatus according to claim 6, characterized in that, Each mixer in the finite-length sequence mixer group includes a finite state counter and a data selector or read-only memory. The counter generates an address signal based on the current level number and branch number. The data selector or read-only memory outputs the corresponding finite-length complex sequence sample value based on the address signal and performs a one-to-one multiplication operation with the input signal sample value. The multiplication operation is implemented through bit selection operation of the data selector or addition-shift operation, without the need for a digital signal processing unit or a dedicated multiplier.

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