A gigabit ethernet media access controller oriented to MCU chip integration

Abstract

The application discloses a kind of gigabit ethernet media access controllers for MCU chip integration, including encapsulation in one's body configuration interface unit, system data bus unit, DMA controller unit, MAC transport layer unit, MAC core layer unit, clock reset unit, PHY interface and management unit.The application is through the overall design of bus separation, DMA-MTL cooperation, multi-domain clock reset, interface self-adaptation and hardware function unloading, forms the realization scheme of directly reusable, high-stability, low-power ethernet controller, meets the demand of new generation embedded system to high-performance, high-reliability, low-cost gigabit ethernet communication.

Description

Technical Field

[0001] This invention relates to Ethernet controllers, specifically a gigabit Ethernet media access controller for MCU chip integration. Background Technology

[0002] With the rapid popularization of embedded and edge computing applications such as IoT terminals, industrial control, vehicle networks, and high-definition audio and video transmission, terminal devices are placing increasingly higher demands on high-speed, stable, and low-latency Ethernet communication capabilities. The Ethernet media access controllers integrated into traditional microcontrollers are struggling to meet the increasingly complex system requirements in terms of speed, functionality, real-time performance, and integration, becoming a key bottleneck restricting device performance improvement.

[0003] Existing Ethernet controllers generally suffer from low speed support and limited interface compatibility. Most solutions only support low-speed transmission of 10 / 100Mbps and lack support for gigabit GMII interfaces, failing to meet the high-bandwidth service requirements of high-definition video, big data interaction, and other applications, thus exhibiting significant shortcomings in high-speed communication scenarios.

[0004] Meanwhile, traditional Ethernet MAC functionality lacks integration and typically does not support enhanced features such as VLANs, Layer 3 / 4 packet filtering, and real-time Ethernet audio and video transmission. In scenarios with stringent requirements for latency, jitter, and reliability, such as automotive and industrial audio / video applications, its adaptability is poor and its scalability is limited, making it difficult to meet the communication quality requirements of professional scenarios.

[0005] In terms of data processing mechanisms, traditional solutions heavily rely on software to process messages. Operations such as checksum calculation, flow control, and message filtering all consume significant processor resources, leading to a decrease in overall system throughput and a deterioration in real-time performance, making it impossible to meet the demands of high-concurrency, low-latency communication.

[0006] Existing technologies also have significant shortcomings in bus architecture, clock reset, and data cache design. Issues such as the lack of proper separation between configuration and data transmission interfaces, inadequate cross-clock domain processing, a single DMA descriptor management mode, and inflexible FIFO cache specifications not only reduce system stability but also lead to higher power consumption and area overhead, making it difficult to match the design goals of highly integrated, low-power MCU chips.

[0007] To effectively overcome the aforementioned technical deficiencies and meet the demands of next-generation embedded systems for high-performance, high-reliability, and low-cost gigabit Ethernet communication, it is urgent to design a gigabit Ethernet MAC IP core with higher integration, more complete functions, and lower resource consumption to support the integration and application of MCU chips for complex scenarios. Summary of the Invention

[0008] To address the shortcomings of the existing technologies, this invention provides a gigabit Ethernet media access controller for MCU chip integration. Through an overall design that incorporates bus separation, DMA-MTL collaboration, multi-domain clock reset, interface adaptation, and hardware function offloading, this invention forms a directly reusable, highly stable, and low-power Ethernet controller implementation.

[0009] To achieve the above technical objectives, the present invention adopts the following technical solution: a gigabit Ethernet media access controller for MCU chip integration, comprising a configuration interface unit, a system data bus unit, a DMA controller unit, a MAC transport layer unit, a MAC core layer unit, a clock reset unit, and a PHY interface and management unit all packaged together. The configuration interface unit is connected to the processor via the APB bus, and the system data bus unit is connected to the memory and the DMA controller unit via the AHB bus, thus completely physically separating the APB configuration interface and the AHB data interface to achieve isolation between the control path and the data path. The configuration interface unit is also connected to the clock reset unit, the DMA controller unit, and the MAC core layer unit respectively, to realize register configuration, working mode setting, status monitoring and reset control; The DMA controller unit is connected to the MAC transport layer unit to realize data transfer between the memory and the MAC transport layer unit; The MAC transport layer unit is connected to the MAC core layer unit to realize cross-clock domain data forwarding and cache scheduling; The MAC core layer unit is connected to the management unit via the MII / GMII interface and the PHY interface to realize the transmission and reception of Ethernet frames and link interaction; The clock reset unit is connected to the configuration interface unit, the system data bus unit, the MAC core layer unit, and the PHY interface and management unit to provide clock signals and reset signals; the clock reset unit is also connected to the DMA controller unit and the MAC transport layer unit to provide reset signals. The PHY interface and management unit are connected to the configuration interface unit through the MDIO management interface, realizing seamless connection between the MAC core layer unit and the external physical layer.

[0010] The DMA controller unit is configured such that: the control status register of the DMA controller unit configures the starting address of the descriptor, wherein the descriptor is pre-arranged in memory, and the hardware of the DMA controller unit automatically loads the descriptor from memory; The DMA controller unit is further configured to: during transmission, after the DMA controller unit parses the descriptor to obtain the buffer address, automatically read the data to be transmitted from the memory through the AHB bus and continuously write it into the transmit FIFO of the MAC transport layer unit until the entire frame of data has been transferred. The DMA controller unit is further configured to: upon receiving data, after detecting that there is valid data in the receive FIFO of the MAC transport layer unit, automatically initiate a write operation to the AHB bus to move the data to the memory buffer specified by the receive descriptor. The DMA controller unit is further configured to automatically write back the transmission status to the corresponding descriptor control status word after each frame of data has been moved.

[0011] The DMA controller unit is configured to support both ring mode and linked list mode. In ring mode, the DMA controller unit is configured to perform data transmission based on a descriptor ring connected end to end; In linked list mode, the DMA controller unit is configured to perform data transfer based on a linked list of descriptors for discrete storage; Each descriptor is configured to support double buffering mode, wherein each descriptor includes a first buffer pointer and a second buffer pointer, such that each descriptor can point to up to two data buffers.

[0012] On the transmission path, the MAC transport layer unit is configured to operate in threshold forwarding mode or first store-and-forward mode; wherein, in the threshold forwarding mode, when the valid data in the transmission FIFO reaches the threshold, the MAC transport layer unit outputs a transmission enable signal to the MAC core layer unit; in the first store-and-forward mode, after the entire frame of data is written into the transmission FIFO, the MAC transport layer unit outputs a transmission enable signal to the MAC core layer unit. On the receiving path, the MAC transport layer unit is configured to operate in either a pass-through mode or a second store-and-forward mode. In the pass-through mode, when the valid data in the receive FIFO reaches a threshold, the MAC transport layer unit outputs a send enable signal to the MAC core layer unit, and the MAC core layer unit continues to receive subsequent data and write it into the receive FIFO. In the second store-and-forward mode, after the entire frame of data has been written into the receive FIFO, the MAC transport layer unit outputs a send enable signal to the MAC core layer unit. The transmit enable signal is used to trigger the MAC core layer unit to send the entire frame of data to the physical layer.

[0013] The DMA controller unit is connected to the MAC transport layer unit via a first interface, and the MAC transport layer unit is connected to the MAC core layer unit via a second interface.

[0014] On the transmission path, the MAC core layer unit is configured to automatically insert a preamble, frame delimiter, and cyclic redundancy check. On the receiving path, the MAC core layer unit is configured to perform frame synchronization, error detection, address filtering, and flow control frame processing.

[0015] The clock reset unit integrates clock frequency division logic, including a time synchronization clock and a transmit clock. The time synchronization clock is configured to be generated by frequency division of the APB bus clock. The transmit clock is the clock required by the PHY interface and management unit. In GMII mode, the transmit clock is configured to be generated by an external 125 MHz crystal oscillator via a clock generation module. In MII mode, the transmit clock is configured to be provided by the PHY interface and management unit as the transmit clock input, and then the clock source selection and distribution are automatically completed according to the interface type and rate. The clock reset unit also integrates reset synchronization logic: both the AHB reset signal and the APB reset signal are provided by the system on chip. All functional reset signals are derived from the AHB reset signal and are synchronized to the corresponding clock domain by the internal reset synchronization logic before being released, so as to ensure the reset reliability of cross-clock domain circuits. The clock reset unit also integrates a two-level reset control logic: after the on-chip system bus reset signal arrives and the clock frequency stabilizes, a two-level reset is initiated on the Ethernet core through the kernel reset signal, and the kernel reset signal is revoked after the reset is completed.

[0016] All hardware acceleration functions of the media access controller are integrated into the transmit and receive data path of the MAC core layer unit. When a network packet passes through the hardware processing pipeline once, it can sequentially complete checksum calculation and verification, multi-layer filtering condition matching, audio and video AV timestamp marking and queue scheduling without having to move data between multiple independent modules. All hardware acceleration functions share the same APB register for access, and share the same set of DMA descriptor status words and interrupt lines to report to the processor.

[0017] It also includes a top-level APB extension register; the top-level APB extension register includes: The PTP timestamp high and low 32-bit read-only registers are used to store the 64-bit timestamp value generated by the PTP hardware unit inside the media access controller. Current DMA Channel ID Register: Indicates the DMA channel number currently occupying the MDIO bus for PHY register access; PTP Second Pulse Status Register: Used to capture the status of the output PTP second pulse signal; MAC Rate Indicator Register: Used to output the actual operating rate of the current MAC core layer unit.

[0018] The logic synthesis area of ​​the media access controller is less than 400 kilogates and the power consumption is less than 4 milliwatts.

[0019] In summary, the present invention has achieved the following technical effects: This invention is based on Synopsys DesignWare Ethernet QoS 5.20a IP, featuring architecture optimization and module customization, and is compatible with the IEEE 802.3 Ethernet standard and real-time audio / video transmission standards such as 802.1-AS / QAV. The system supports three adaptive speeds of 10 / 100 / 1000Mbps, is compatible with both MII and GMII PHY interfaces, supports full-duplex / half-duplex modes, and can handle standard 1.5KB Ethernet frames and up to 16KB jumbo frames. It also includes built-in hardware CRC checksum, flow control, VLAN processing, and multi-layer packet filtering capabilities. This invention adopts a layered architecture of "configuration interface—data interface—DMA controller—MTL transport layer—MAC core layer". High-speed data transfer is achieved via the AHB bus, register configuration is implemented via the APB bus, and a dual-port SRAM is used to construct transmit and receive FIFOs (2KB each) to achieve cross-clock domain data buffering and rate matching. The system supports a hardware checksum offload engine (COE), which can perform checksum calculation and insertion of IP headers and complete TCP / UDP frames in the transmit and receive paths, significantly reducing CPU load. It also supports multi-dimensional frame filtering based on source / destination addresses, L3 network addresses, L4 transport ports, and VLANs to accurately filter target packets. To meet the real-time service requirements of audio and video, this invention supports Ethernet audio and video transmission characteristics and complies with 802.1AS time synchronization and 802.1Qav queue scheduling specifications. The system features a complete clock reset architecture, with AHB and APB clock resets provided uniformly by the SOC. Internally, it implements multi-clock domain synchronization and soft reset management, and completes PHY chip status management and register access through the MDIO interface. The overall IP area is less than 400K gates and power consumption is less than 4mW, allowing for stable integration into MCU systems. This invention adopts an architecture with completely separated AHB data path and APB configuration path. The 32-bit AHB is responsible for high-speed data transfer, and the 32-bit APB is responsible for register control and status acquisition. This ensures that the control flow and data flow do not interfere with each other, improves system throughput and stability, and realizes an integrated architecture with dual-bus isolation. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of this application. Detailed Implementation

[0021] The present invention will be further described in detail below with reference to the accompanying drawings.

[0022] This specific embodiment is merely an explanation of the present invention and is not intended to limit the invention. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of the claims of the present invention.

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the device proposed by this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, only for the purpose of conveniently and clearly illustrating the embodiments of this invention. Please refer to the accompanying drawings to make the objectives, features, and advantages of this invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed in the specification, and are not intended to limit the implementation conditions of this invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives achieved by this invention, should still fall within the scope of the technical content disclosed in this invention.

[0024] Example: like Figure 1 As shown, a Gigabit Ethernet Media Access Controller (GMAC) subsystem for MCU chip integration includes a configuration interface unit, a system data bus unit, a DMA controller unit, a MAC transport layer unit, a MAC core layer unit, a clock reset unit, and a PHY interface and management unit, all packaged together. These seven modules enable stable transmission and reception, hardware offloading, real-time transmission, and reliable control of Gigabit Ethernet.

[0025] This application adopts an integrated architecture with layered decoupling, modular collaboration, and clock domain isolation. It unifies and coordinates functions such as configuration control, data transfer, cache scheduling, MAC protocol processing, PHY interface interaction, and clock reset management, realizing full-link connectivity from the system bus to the physical layer interface. Through the docking, unified management and control, and protocol adaptation of the bus interface, DMA controller, MAC transport layer, MAC core layer, clock reset, and PHY interface, it achieves the design of an integrated high-performance Ethernet communication subsystem.

[0026] The specific integration design is as follows: The configuration interface unit is connected to the processor (CPU) via the APB bus, and the system data bus unit is connected to the memory (main memory) and the DMA controller unit via the AHB bus. The APB configuration interface and the AHB data interface are completely physically separated, realizing the isolation between the control path and the data path.

[0027] The configuration interface unit is also connected to the clock reset unit, DMA controller unit, and MAC core layer unit to realize register configuration, working mode setting, status monitoring and reset control.

[0028] In this application, the configuration interface unit serves as the system control hub, employing the APB 3.0 slave interface with a 32-bit data width, a 14-bit address width, and a 16KB address space. It is used for register configuration, status reading, and clock division control. The top-level APB interface provides key registers such as core reset, PTP timestamp, DMA channel ID, and MAC rate monitoring, supporting flexible software control of the GMAC subsystem's operating mode and status monitoring, ensuring simple and efficient configuration operations.

[0029] The system data bus unit serves as the data interaction hub. The system data transmission of the system data bus unit adopts the AHB 3.0 host interface, with a data bit width and address bit width of 32 bits, which is dedicated to high-speed data interaction between DMA and system main memory.

[0030] The AHB data transmission interface and APB configuration interface of the system data bus unit are completely separated, enabling the "control path" and "data path" to work independently, avoiding bus contention, improving data throughput efficiency, and meeting the gigabit Ethernet bandwidth requirements.

[0031] The DMA controller unit is connected to the MAC transport layer unit to realize data transfer between the memory and the MAC transport layer unit; The DMA controller unit is configured as follows: (1) The starting address of the configuration descriptor in the control status register of the DMA controller unit, wherein the descriptor is pre-arranged in the main memory and the hardware of the DMA controller unit automatically loads the descriptor from the main memory. (2) When sending, after the DMA controller unit parses the descriptor and obtains the buffer address, it automatically reads the data to be sent from the main memory through the AHB bus and continuously writes it into the transmit FIFO of the MAC transport layer unit until the entire frame of data has been transferred. (3) When receiving, after the DMA controller unit detects that there is valid data in the receive FIFO of the MAC transport layer unit, it automatically initiates a write operation to the AHB bus to move the data to the main memory buffer specified by the receive descriptor. (4) After each frame of data is moved, the hardware of the DMA controller unit automatically writes the transmission status back to the corresponding descriptor control status word.

[0032] (5) The DMA controller unit is configured to support both ring mode and linked list mode; In ring mode, the DMA controller unit is configured to perform data transfer based on a descriptor ring connected end to end; In linked list mode, the DMA controller unit is configured to perform data transfer based on a linked list of descriptors for discrete storage; Each descriptor is configured to support double buffering mode, wherein each descriptor includes a first buffer pointer and a second buffer pointer, so that each descriptor can point to a maximum of two data buffers. This achieves: (1) Support for large data packet fragmentation: For giant frames that exceed the size of a single buffer, their data can be distributed to two buffers with non-contiguous physical addresses, and linked by descriptors into a complete frame for transmission, avoiding large memory copying. (2) Implementation of "ping-pong" operation: When the DMA controller unit processes one buffer, the CPU can prepare another one at the same time, realizing pipelined processing and improving throughput efficiency.

[0033] Specifically, the DMA controller unit operates based on a descriptor mechanism, supporting both linked list and circular descriptor structures. The linked list structure refers to descriptors linked together in a singly linked list via pointer fields. Descriptors can be stored non-contiguously in main memory, and traversal is achieved through pointers to the next descriptor. This structure is flexible, supports non-contiguous memory distribution, and is suitable for variable-length message scenarios. The circular structure refers to descriptors occupying contiguous address space in main memory, forming a circular buffer. The DMA controller unit uses these descriptors sequentially and cyclically. The DMA controller unit works in concert through a base address register (starting address) and a tail pointer register (address of the latest processable descriptor). The tail pointer is updated by software; once the hardware reaches this address, it enters a suspended state, waiting for a new descriptor.

[0034] The DMA controller unit uses independent descriptor chains for both transmission and reception. The transmission descriptor chain and the reception descriptor chain each support two structures: linked list and circular descriptor. The transmission and reception directions can be selected independently, for example, transmission can use a circular descriptor and reception can use a linked list, or they can be configured to have the same structure.

[0035] Each descriptor can point to up to two data buffers, supporting full frame or fragmented transmission, and adapting to standard frame and 16KB jumbo frame scenarios.

[0036] The DMA controller unit utilizes descriptor preloading and chained scheduling. Specifically, descriptors are pre-positioned in main memory, and their starting addresses are configured by the DMA controller unit's CSR (Control Status Register). The DMA controller unit hardware automatically loads the descriptors from main memory, parses the control information within them, and the entire instruction fetching process is automatically completed by the DMA controller unit's state machine. The CPU only needs to configure the starting address of the descriptor chain once during initialization. During transmission, after the DMA controller unit parses the descriptor and obtains the buffer address, it automatically reads the data to be transmitted from main memory via the AHB bus and continuously writes it to the MAC transport layer unit's transmit FIFO until the entire frame of data has been transferred. During reception, after the DMA controller unit detects valid data in the receive FIFO, it automatically initiates a write operation to the AHB bus, transferring the data to the main memory buffer specified by the receive descriptor. The entire data transfer process is independently completed by the DMA controller unit hardware. The AHB bus operation is automatically initiated and terminated by the DMA controller unit, and the CPU does not need to execute instructions during data transfer. After each frame of data transfer is completed, the DMA controller unit hardware automatically writes the transmission status back to the corresponding descriptor control status word, and the entire write-back process is automatically executed by the hardware state machine. The CPU only needs to read the status field of the corresponding descriptor in main memory after receiving the completion interrupt to know the transmission result. There is no need to perform any additional register operations to query or confirm the status. Therefore, it can realize automatic sending and receiving without CPU intervention, which greatly improves the system's concurrent processing capability.

[0037] The descriptor-based DMA and MTL collaborative scheduling mechanism provided in this application essentially involves software submitting tasks by configuring descriptors and tail pointers, while hardware automatically completes the pipelined closed loop of data transfer and status write-back. The software pre-creates descriptors (including buffer addresses and control information) in memory and starts and updates the task queue by configuring the base address and tail pointer register of the DMA controller unit. The DMA controller unit hardware automatically acquires descriptors one by one and transfers data to the FIFO of the MAC transport layer unit (or reverses the transfer). After processing each descriptor, it writes back the status and clears ownership (OWN bit) before returning it to the software. Simultaneously, the MAC transport layer unit intelligently triggers the next level of forwarding based on the FIFO pipeline status. After the MAC core layer unit completes frame processing, it sends back the status word, which is then handed over to the DMA controller unit to write back the descriptor. The DMA controller unit also supports OSF mode, which allows it to pre-process the next frame descriptor while waiting for the current frame's transmission status, thus achieving pipelined operation. This mechanism allows the hardware to operate autonomously, with the software only needing to update the tail pointer and reclaim descriptors. The CPU hardly participates in byte-by-byte movement, thus achieving high-throughput, low-overhead gigabit Ethernet communication.

[0038] The MAC transport layer unit is connected to the MAC core layer unit to realize cross-clock domain data forwarding and buffer scheduling; The MAC transport layer unit is configured as follows: (1) On the transmission path, the MAC transmission layer unit is configured to work in threshold forwarding mode or first store-and-forward mode; wherein, in threshold forwarding mode, when the valid data in the transmission FIFO reaches the threshold, the MAC transmission layer unit outputs a transmission enable signal to the MAC core layer unit; in the first store-and-forward mode, when the entire frame of data is written into the transmission FIFO, the MAC transmission layer unit outputs a transmission enable signal to the MAC core layer unit. (2) On the receiving path, the MAC transport layer unit is configured to work in either pass-through mode or second store-and-forward mode. In pass-through mode, when the valid data in the receiving FIFO reaches the threshold, the MAC transport layer unit outputs a send enable signal to the MAC core layer unit, and the MAC core layer unit continues to receive subsequent data and write it into the receiving FIFO. In the second store-and-forward mode, after the entire frame of data is written into the receiving FIFO, the MAC transport layer unit outputs a send enable signal to the MAC core layer unit. The send enable signal is used to trigger the MAC core layer unit to send the entire frame of data to the physical layer.

[0039] In this application, the MAC Transport Layer Unit (MTL) serves as a buffer and adaptation layer between the DMA controller unit and the MAC core layer unit. Specifically, the FIFO acts as a temporary data storage to address rate matching and short-term burst issues in the upstream and downstream data paths. For example, the write rate of the DMA controller unit may be higher or lower than the send rate of the MAC core layer unit; the FIFO provides elastic buffering to prevent the data from being fully written and read empty. When the DMA controller unit is busy with other tasks or the AHB bus is busy, the FIFO can buffer data that cannot be moved temporarily, preventing frame loss. When multiple frames suddenly flood the network, the FIFO provides buffer space to prevent the MAC core layer unit from dropping packets due to insufficient processing time. Simultaneously, the MAC Transport Layer Unit performs adaptation between the DMA / AHB clock domain and the MAC / PHY clock domain, including not only rate matching but also data format conversion, transmission mode adaptation, and interface protocol adaptation. For example, the DMA controller unit and the MAC core layer unit operate at different clock frequencies. Dual-port SRAM enables secure data transfer across clock domains, avoiding metastability issues. The data path widths within the DMA controller unit and the MAC core layer unit may differ. The FIFO serves as a width conversion boundary, unifying the data to a 64-bit format before converting it to both ends. When the DMA controller unit is unable to move data in time, causing the receive FIFO to approach full, the MAC transmission layer unit actively notifies the MAC core layer unit to pause transmission, preventing FIFO overflow and frame loss, and achieving rate adaptive closed-loop control.

[0040] In addition, the MAC transport layer unit uses dual-port SRAM to implement transmit and receive FIFOs. Both the transmit and receive FIFOs have a capacity of 2048 bytes and a data width of 64 bits, supporting cross-clock domain data synchronization.

[0041] The MAC transport layer unit of this application supports two modes for its transmission path: threshold forwarding and first store-and-forward. The reception path supports two modes: pass-through and second store-and-forward. When the FIFO data volume is greater than or equal to a preset threshold, it switches to threshold forwarding mode. When the entire frame is written to the FIFO, it switches to first store-and-forward mode. When the FIFO data volume is greater than or equal to 64 bytes or the frame ends, it switches to pass-through mode. When the entire frame is written to the FIFO, it switches to second store-and-forward mode. Therefore, this application can flexibly switch modes according to the business scenario.

[0042] This application provides multiple optional forwarding modes through the MAC transport layer unit, enabling the system to flexibly choose between low latency and high reliability based on business scenarios. At the hardware level, this application possesses both the hardware foundations required for low latency and the hardware foundations required for high reliability, with both mechanisms coexisting fully within the same IP address. At the configuration level, the transmitting and receiving paths of this application independently select forwarding modes, and the two directions can be configured with different modes, simultaneously achieving either "high reliability for transmission and low latency for reception" or a combination of "low latency for transmission and high reliability for reception" within the same system. Therefore, this application balances low latency and high reliability.

[0043] The MAC transport layer unit simultaneously performs key processes such as flow control, FIFO clearing, and clock domain isolation.

[0044] The MAC core layer unit connects to the management unit through the MII / GMII interface and the PHY interface to realize the transmission and reception of Ethernet frames and link interaction; The MAC core layer unit is configured as follows: (1) On the transmission path, the MAC core layer unit is configured to automatically insert a preamble, frame delimiter, and cyclic redundancy check (CRC). Specifically, the MAC core layer unit reads the data frame to be transmitted from the transmit FIFO of the MAC transport layer unit. The transmission engine automatically inserts a 7-byte preamble (0x55) and a 1-byte frame delimiter (SFD) (0xD5) into the frame header. At the same time, the hardware CRC engine calculates the 32-bit CRC checksum of the frame data in real time and automatically appends a 4-byte CRC field to the end of the frame. Then, it is sent to the PHY chip through the GMII / MII interface.

[0045] (2) On the receiving path, the MAC core layer unit is configured to perform frame synchronization, error detection, address filtering, and flow control frame processing. Specifically, the MAC core layer unit receives the PHY data stream from the GMII / MII interface. The receiving engine first detects the preamble (0x55) to complete bit synchronization, and locks the frame start boundary after detecting SFD (0xD5). During frame reception, the hardware CRC engine calculates and verifies the CRC integrity in real time, and checks whether the frame length is within the valid range. Abnormal frames are directly marked and discarded. Valid frames that pass the CRC check enter the address filtering module, and sequentially perform destination address filtering, source address filtering, VLAN ID filtering, and L3 / L4 filtering. Frames that fail at any stage are automatically discarded by the hardware and are not written to the receive FIFO. If a pause frame is detected, the MAC core layer unit automatically parses the pause time and pauses transmission. The pause frame itself is not written to the FIFO. Valid frames that pass all filtering are written to the receive FIFO, triggering the DMA controller unit to move them to main memory.

[0046] The MAC core layer unit is compatible with both MII and GMII interfaces, supports speeds of 10 / 100 / 1000Mbps and full / half-duplex modes, and follows the IEEE 802.3 protocol to complete frame encapsulation, parsing, CRC check, and collision handling. The MAC core layer unit also has a built-in hardware CRC engine, supporting message integrity verification during transmission and reception. In half-duplex mode, it can automatically handle collisions and retransmissions to ensure link stability. Specifically, the MAC core layer unit follows the IEEE 802.3 standard CRC-32 algorithm. During transmission, the MAC core layer unit calculates the CRC checksum in real time during frame data output and automatically appends a 4-byte CRC field to the end of the frame before sending it to the PHY. During reception, the MAC core layer unit recalculates the CRC of the received frame data and compares it with the CRC field carried at the end of the frame. Frames with inconsistent CRC checks are marked as erroneous and discarded in subsequent processing, ensuring message integrity verification during transmission and reception. In half-duplex mode, the MAC core layer unit's transmission engine continuously monitors the col_i collision detection signal of the PHY interface. Once a collision is detected, the hardware automatically stops the transmission of the current frame and executes the truncated binary exponential backoff algorithm defined by the IEEE 802.3 standard. After a random backoff time, the frame is automatically retransmitted. If the retransmission attempt reaches the upper limit and still fails, the retransmission is stopped and the transmission failure status is fed back through the descriptor status word, and the interrupt notifies the CPU to handle it.

[0047] Furthermore, the DMA controller unit is connected to the MAC transport layer unit via a first interface, and the MAC transport layer unit is connected to the MAC core layer unit via a second interface. The data and control interaction methods between the DMA controller unit and the MAC transport layer unit, and between the MAC transport layer unit and the MAC core layer unit, are as follows: (1) First Interface: After the DMA controller unit obtains data from main memory via the AHB bus, it pushes the data to the transmit FIFO of the MAC transport layer unit via the first interface. Simultaneously, the DMA controller unit uses sideband signals to indicate key information along the path. In the receiving direction, when the data in the FIFO of the MAC transport layer unit reaches a preset condition, the MAC transport layer unit sends a request to the DMA controller unit via the first interface. The DMA controller unit then pops the data and moves it to main memory via the AHB bus. The MAC transport layer unit also sends the transmit status returned by the MAC core layer unit back to the DMA controller unit via the first interface. The DMA controller unit then writes it into the descriptor in main memory for software querying.

[0048] (2) Second interface: The MAC transport layer unit forwards the data sent from the DMA controller unit to the MAC core layer unit through the second interface or stores the data received by the MAC core layer unit into the receive FIFO. After completing the transmission and reception of a frame, the MAC core layer unit will return a status word to the MAC transport layer unit through the second interface, which contains the specific result of this transmission.

[0049] Therefore, the DMA controller unit connects to the MAC transport layer unit through the first interface to write main memory data into the transmit FIFO or move the receive FIFO data back to main memory; the MAC transport layer unit then connects to the MAC core layer unit through the second interface to complete cross-clock domain data forwarding and cache scheduling, forming a complete data link from main memory to DMA to MTL to MAC core to PHY.

[0050] The clock reset unit provides timing support for all core units. It is connected to the configuration interface unit, system data bus unit, MAC core layer unit, PHY interface, and management unit to provide clock and reset signals. Furthermore, the clock reset unit provides APB / AHB clocks for the configuration interface unit and system data bus unit, and transmit / receive clocks that match the rate / interface mode for the MAC core layer unit, PHY interface, and management unit. The clock reset unit is also connected to the DMA controller unit and MAC transmission layer unit to provide reset signals. The clock reset unit provides synchronous reset signals for each module to achieve stable power-on and operation under multiple clock domains.

[0051] Specifically, the clock reset unit integrates clock division logic and reset synchronization logic, enabling the clock reset unit to support multi-clock domain synchronization and global reset management.

[0052] (1) Clock division logic: including time synchronization clock and transmit clock clk_tx_o; The time synchronization clock is configured to be generated by dividing the APB bus clock to support the high-precision timing requirements of AV services. Furthermore, register address 0x00 supports four division coefficients: 00 for pclk pass-through (division by 1), 01 for division by 2, 10 for division by 4, and 11 for division by 8. This allows the software to flexibly configure the PTP timestamp accuracy requirements during initialization without the need for an additional clock source, thus reducing system integration complexity. The transmit clock clk_tx_o is the clock required by the PHY interface and the management unit. In GMII 1000M mode, the transmit clock is configured to be generated by an external 125 MHz crystal oscillator via the clock generation module. In MII mode, the transmit clock is configured to be provided by the PHY interface and the management unit with transmit clock input clk_tx_i, and then the clock generation module automatically completes the selection and distribution of the clock source according to the interface type and rate. (2) Reset synchronization logic: Both the AHB reset signal and the APB reset signal are provided by the on-chip system; The APB reset signal is configured to asynchronously reset only the top-level register module and the clock generation module. The top-level register module is a set of registers located at the top level of the subsystem, including control registers and status registers. The control registers are configured by software to configure clock division and trigger core reset by writing to them. The status registers are configured to synchronize critical signals within the IP to the APB clock domain for software reading. The top-level register module operates in the APB clock domain, which is different from the internal logic of the IP. Therefore, the APB reset signal only clears the top-level registers to restore their default state and does not affect the internal logic of the IP. The clock generation module is responsible for automatically selecting a clock source and distributing it to each module based on the PHY interface type and operating speed. It also divides the APB bus clock through the top-level registers to generate the reference clock required by the PTP timestamp module. The APB reset only affects the registers controlling the division coefficients within this module and does not affect the physical generation of the clock.

[0053] All functional reset signals are derived from the AHB reset signal and are synchronized to their respective clock domains by internal reset synchronization logic before being released, ensuring the reset reliability of cross-clock domain circuits. All functional reset signals refer to the reset signals of the internal functional logic of the GMAC IP (DMA controller, MTL transmit / receive FIFO, MAC transmit / receive engine, address filtering, CRC check, COE check and offload, etc.), not all reset signals of the entire subsystem.

[0054] In addition, the clock reset unit integrates a two-level reset control logic: after the on-chip system bus reset signal arrives and the clock frequency stabilizes, a two-level reset is initiated on the Ethernet core via the core reset signal, and the core reset signal is revoked after the reset is completed. Specifically, after the SOC bus reset arrives, it needs to wait for the clock frequency to stabilize before initiating a two-level reset on the Ethernet core eth_core via the Core_reset signal in the top-level register 0x24, and revoking the reset after completion, ensuring that the core logic can reliably start after the clock stabilizes. The IP internally supports a soft reset function. Writing 1 to bit 0 (SWR) of the DMA_Mode register can trigger a global reset of the DMA controller unit, MAC transport layer unit, and MAC core layer unit. After the reset is completed, the hardware automatically clears the bit. The soft reset is only considered complete after all clock domains have completed the reset, and no registers can be operated during the reset period.

[0055] Therefore, this application utilizes a two-level reset strategy to ensure system stability, ensuring that the core logic is reset and canceled only after the clock frequency is completely stable, effectively avoiding timing abnormalities caused by clock instability.

[0056] Therefore, the clock reset unit supports both hardware and software resets. Hardware reset covers the entire subsystem, ensuring all logic enters a defined initial state. Software reset is triggered by software configuration registers and is used to reinitialize internal logic without relying on external hardware signals. Software triggers a software reset by writing a 1 to bit 0 (SWR) of the DMA_Mode register. The reset scope resets the internal logic and related registers of the DMA, MTL, and MAC subsystems in the MAC core layer and DMA controller units, restoring them to their default states. The SWR bit is automatically cleared by hardware after the reset operation. Software must poll this bit until it reads back 0 to confirm reset completion. For multi-clock domain synchronization, software reset must wait for the reset operations of all active clock domains to complete before it is truly finished. Therefore, the reset completion time depends on the slowest clock domain and is uncertain. For clock dependency, all input clocks provided by the PHY must be valid for a successful software reset; a missing clock will result in reset failure. Furthermore, no write operations can be performed on any registers of the GMAC subsystem while the SWR bit is 1. After writing a 1 to SWR, the software must wait at least 4 CSR clock cycles before reading back the bit to ensure that the status has been updated and to avoid misjudgment.

[0057] The PHY interface and management unit are connected to the configuration interface unit through the MDIO management interface, enabling seamless integration between the MAC core layer unit and the external physical layer.

[0058] The PHY interface is compatible with both MII and GMII level and timing standards, providing complete signals for data transmission and reception, enable, error, clock, and collision detection. The MDIO interface enables PHY chip register read / write and status management, supporting rate negotiation, operating mode configuration, and link status monitoring. Specifically, the MDIO interface is the channel through which the MAC core layer unit manages and controls the PHY chip via the SMI bus. It uses two signal lines (clock line MDC and data line MDIO) for serial communication to read and write PHY registers. Software configures the relevant CSR registers of the MDIO interface, specifying the target PHY address and register address. The hardware automatically sends and receives MDIO frames, enabling read / write access to the PHY chip's internal registers, thereby reading link status and configuring operating parameters. The software initiates automatic negotiation of rate and duplex mode with the PHY chip via MDIO. After negotiation, the software reads the PHY status register to obtain the negotiation result (10 / 100 / 1000Mbps rate, full-duplex / half-duplex mode) and configures the MAC core layer unit rate indication signal mac_speed_o[1:0] of the GMAC subsystem accordingly, ensuring that the MAC core layer unit and the PHY operate in the same mode. The software periodically reads the PHY link status register through MDIO to obtain the current link connectivity status, enabling real-time link monitoring. The MAC core layer unit automatically outputs the mac_speed_o[1:0] rate indication signal to the PHY, cooperating with the PHY to complete rate adaptation and achieve seamless connection between the GMAC subsystem and the external PHY.

[0059] Simultaneously, the PHY interface and management unit can automatically output MAC rate indication signals, cooperating with the PHY to achieve rate adaptation and realize seamless integration between the GMAC subsystem and the external PHY. Specifically, the GMAC subsystem initiates a negotiation request: When the system starts up or the link changes, the software writes commands to the MDIO control register of the GMAC subsystem through the APB configuration interface, and initiates an automatic negotiation request to the external PHY chip via the MDIO bus. The PHY negotiates and responds: After receiving the request, the external PHY negotiates with the link peer to determine the highest operating mode supported by both parties. After the negotiation is completed, the PHY stores the result in its status register. The GMAC subsystem reads the negotiation result: The GMAC subsystem reads the PHY status register through the MDIO bus to obtain the negotiated rate and duplex mode values. The GMAC subsystem outputs a rate indication signal and adapts: The MAC core layer unit of the GMAC subsystem automatically configures its own operating parameters to match the final operating mode of the PHY based on the read negotiation result. Meanwhile, the top-level APB register 0x20 (Speed_o) outputs the corresponding speed indication value, which is used by the software for querying and by other modules in the system for linkage, realizing a complete hardware self-adaptive closed loop and ensuring seamless connection between the GMAC subsystem and the external PHY.

[0060] All hardware acceleration functions in this application are integrated into the data transmission and reception path of the MAC core layer unit. When a network packet passes through the hardware processing pipeline once, it can sequentially complete checksum calculation and verification, multi-layer filtering condition matching, audio and video AV timestamp marking and queue scheduling without having to move data between multiple independent modules. Simultaneously, all hardware acceleration functions share the same APB register for access, and share the same set of DMA descriptor status words and interrupt lines to report to the CPU. The APB register refers to the CSR control status register space built into the IP.

[0061] This application enables the integrated implementation of COE checksum offloading, L2 / L3 / L4+VLAN multi-layer filtering, AV real-time transmission, and MAC core. Within the GMAC subsystem, multiple hardware acceleration functions (COE checksum offloading, L2 / L3 / L4+VLAN multi-layer filtering, and AV real-time transmission) are deeply integrated with the core data pathways (DMA, MTL, and MAC core) to form a tightly coordinated and uniformly managed whole, rather than a stack of independent and loosely pieced-together modules.

[0062] Specifically, this is reflected in three aspects: (1) Shared data path: All acceleration functions are integrated in the data transmission and reception path of the MAC core layer unit. When a network packet passes through, the hardware will sequentially complete the checksum calculation / verification, multi-layer filtering condition matching, AV timestamp marking and queue scheduling in the pipeline, without having to repeatedly move data between multiple independent modules.

[0063] (2) Shared configuration and status interface: All function switching control and working mode configuration are accessed through the same set of APB registers; the completion status, error information, filtering results, etc. of all functions are also reported to the CPU through the same set of DMA descriptor status words and interrupt lines. The software only needs to operate a set of registers and process one interrupt source to control all functions.

[0064] (3) Shared clock reset and resource management: All functional modules share the same clock reset system (AHB / APB clock, multi-domain synchronous reset), eliminating the need to design a separate clock domain or reset logic for each function, and eliminating the need to add a dedicated channel (such as the AV function does not add an independent transmit and receive channel), effectively controlling the total area and power consumption.

[0065] In this application, all functional modules' enable switches, operating modes, filtering rule tables, and status queries are accessed through the same set of APB bus address spaces. Software drivers only need to manipulate this set of registers to configure all hardware acceleration functions. Whether a data packet is dropped due to a checksum error, rejected due to a filtering rule mismatch, or an AV queue transmission completion or time synchronization event occurs, all events requiring CPU attention are notified to the CPU through the same physical interrupt signal line (sbd_intr_o). After responding to an interrupt, the CPU can distinguish which specific function triggered the interrupt by reading the interrupt status bits in the same set of APB registers or querying the status word in the DMA descriptor, and process them sequentially according to priority. Therefore, this application shares registers and the interrupt hierarchy for all functions, significantly reducing CPU load and improving integration.

[0066] This application also includes a top-level APB extension register, specifically including: (1) PTP timestamp high and low 32-bit read-only register (0x04 / 0x08): used to store the 64-bit timestamp value generated by the PTP hardware unit inside the media access controller, for software to read to achieve high-precision clock synchronization; (2) Current DMA Channel ID Register (0x10): Used to indicate the DMA channel number currently occupying the MDIO bus for PHY register access, for software debugging of bus occupancy in multi-channel DMA scenarios; (3) PTP second pulse status register (0x0c): used to capture the status of the output PTP second pulse signal, so that the software can monitor the accuracy of time synchronization and the lock status; (4) MAC Rate Indicator Register (0x20): Used to output the actual operating rate of the current MAC core layer unit for software query and linkage with other modules of the system.

[0067] The core function of the four read-only registers (0x04, 0x08, 0x0c, 0x10, 0x20) is to expose the key status information inside the IP to the software in real time for system-level debugging, monitoring and business logic use, so as to achieve top-level observability of the key status inside the IP, such as the signal values ​​generated by each functional module inside the IP that reflect its current operation status, including PTP time, PPS pulse, MDIO bus occupied channel, MAC working speed, etc., to meet the MCU system-level debugging and monitoring requirements.

[0068] The logic synthesis area of ​​the media access controller is less than 400 kilogates and the power consumption is less than 4 milliwatts.

[0069] This application is based on a customized trimming and encapsulation of Synopsys Ethernet QoS IP, achieving an area of ​​<400K gates (approximately 100K gates) and power consumption of <4mW while supporting full gigabit functionality, making it compatible with highly integrated MCU chips. Through trade-offs such as customized IP interface integration (separate encapsulation of AHB master interface and APB slave interface) and not adding a dedicated AV transmit / receive channel (sharing existing channels), all core functions are retained while resource overhead is controlled within an acceptable range for the MCU, forming a complete Ethernet controller solution that can be directly embedded into the MCU subsystem. Customized integration refers to physically separating and differentially encapsulating the bus interfaces provided by the GMAC subsystem IP core according to their functional characteristics, forming two independent and clearly defined bus paths: the AHB master interface is dedicated to data transport, and the APB slave interface is dedicated to control and status access. This invention fixes AHB as the master interface (actively initiating data transmission) and APB as the slave interface (passively responding to CPU configuration requests), and completely isolates their signals, timing, and address spaces through top-level encapsulation, ensuring no interference. By re-encapsulating the IP interface and independently bringing out the AHB and APB interfaces, they can be directly mounted onto the corresponding AHB and APB buses during SoC integration without the need for additional bus bridging or protocol conversion logic, thus reducing integration complexity. Therefore, based on the use of standard buses to achieve module interconnection, by deeply integrating the functions and signals of each module, the entire link optimization from software configuration, data migration, rate adaptation, clock management to hardware offloading is achieved, forming a directly reusable, highly stable, and low-power integrated Ethernet controller solution.

[0070] The overall design of this application takes into account area, power consumption and performance, supports both standard Ethernet and real-time audio and video transmission, and has high compatibility, high stability and easy integration characteristics.

[0071] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention shall fall within the scope of the technical solution of the present invention.

Claims

1. A gigabit Ethernet media access controller for MCU chip integration, characterized in that, It includes an integrated configuration interface unit, system data bus unit, DMA controller unit, MAC transport layer unit, MAC core layer unit, clock reset unit, and PHY interface and management unit; The configuration interface unit is connected to the processor via the APB bus, and the system data bus unit is connected to the memory and the DMA controller unit via the AHB bus, thus completely physically separating the APB configuration interface and the AHB data interface to achieve isolation between the control path and the data path. The configuration interface unit is also connected to the clock reset unit, the DMA controller unit, and the MAC core layer unit respectively, to realize register configuration, working mode setting, status monitoring and reset control; The DMA controller unit is connected to the MAC transport layer unit to realize data transfer between the memory and the MAC transport layer unit; The MAC transport layer unit is connected to the MAC core layer unit to realize cross-clock domain data forwarding and cache scheduling; The MAC core layer unit is connected to the management unit via the MII / GMII interface and the PHY interface to realize the transmission and reception of Ethernet frames and link interaction; The clock reset unit is connected to the configuration interface unit, the system data bus unit, the MAC core layer unit, and the PHY interface and management unit to provide clock signals and reset signals; the clock reset unit is also connected to the DMA controller unit and the MAC transport layer unit to provide reset signals. The PHY interface and management unit are connected to the configuration interface unit through the MDIO management interface, realizing seamless connection between the MAC core layer unit and the external physical layer.

2. The gigabit Ethernet media access controller for MCU chip integration according to claim 1, characterized in that, The DMA controller unit is configured such that: the control status register of the DMA controller unit configures the starting address of the descriptor, wherein the descriptor is pre-arranged in memory, and the hardware of the DMA controller unit automatically loads the descriptor from memory; The DMA controller unit is further configured to: during transmission, after the DMA controller unit parses the descriptor to obtain the buffer address, automatically read the data to be transmitted from the memory through the AHB bus and continuously write it into the transmit FIFO of the MAC transport layer unit until the entire frame of data has been transferred. The DMA controller unit is further configured to: upon receiving data, after detecting that there is valid data in the receive FIFO of the MAC transport layer unit, automatically initiate a write operation to the AHB bus to move the data to the memory buffer specified by the receive descriptor. The DMA controller unit is further configured to automatically write back the transmission status to the corresponding descriptor control status word after each frame of data has been moved.

3. A gigabit Ethernet media access controller for MCU chip integration according to claim 2, characterized in that, The DMA controller unit is configured to support both ring mode and linked list mode. In ring mode, the DMA controller unit is configured to perform data transmission based on a descriptor ring connected end to end; In linked list mode, the DMA controller unit is configured to perform data transfer based on a linked list of descriptors for discrete storage; Each descriptor is configured to support double buffering mode, wherein each descriptor includes a first buffer pointer and a second buffer pointer, such that each descriptor can point to up to two data buffers.

4. A gigabit Ethernet media access controller for MCU chip integration according to claim 1, characterized in that, On the transmission path, the MAC transport layer unit is configured to operate in threshold forwarding mode or first store-and-forward mode; wherein, in the threshold forwarding mode, when the valid data in the transmission FIFO reaches the threshold, the MAC transport layer unit outputs a transmission enable signal to the MAC core layer unit; in the first store-and-forward mode, after the entire frame of data is written into the transmission FIFO, the MAC transport layer unit outputs a transmission enable signal to the MAC core layer unit. On the receiving path, the MAC transport layer unit is configured to operate in either a pass-through mode or a second store-and-forward mode. In the pass-through mode, when the valid data in the receive FIFO reaches a threshold, the MAC transport layer unit outputs a send enable signal to the MAC core layer unit, and the MAC core layer unit continues to receive subsequent data and write it into the receive FIFO. In the second store-and-forward mode, after the entire frame of data has been written into the receive FIFO, the MAC transport layer unit outputs a send enable signal to the MAC core layer unit. The transmit enable signal is used to trigger the MAC core layer unit to send the entire frame of data to the physical layer.

5. A gigabit Ethernet media access controller for MCU chip integration according to claim 1, characterized in that, On the transmission path, the MAC core layer unit is configured to automatically insert a preamble, frame delimiter, and cyclic redundancy check. On the receiving path, the MAC core layer unit is configured to perform frame synchronization, error detection, address filtering, and flow control frame processing.

6. A gigabit Ethernet media access controller for MCU chip integration according to claim 1, characterized in that, The DMA controller unit is connected to the MAC transport layer unit via a first interface, and the MAC transport layer unit is connected to the MAC core layer unit via a second interface.

7. A gigabit Ethernet media access controller for MCU chip integration according to claim 1, characterized in that, The clock reset unit integrates clock frequency division logic, including a time synchronization clock and a transmission clock; the time synchronization clock is configured to be generated by dividing the APB bus clock. The transmit clock is the clock required by the PHY interface and the management unit. In GMII mode, the transmit clock is configured to be generated by an external 125 MHz crystal oscillator via a clock generation module. In MII mode, the transmit clock is configured to be provided by the PHY interface and the management unit, and then the clock source selection and distribution are automatically completed according to the interface type and rate. The clock reset unit also integrates reset synchronization logic: both the AHB reset signal and the APB reset signal are provided by the system on chip. All functional reset signals are derived from the AHB reset signal and are synchronized to the corresponding clock domain by the internal reset synchronization logic before being released, so as to ensure the reset reliability of cross-clock domain circuits. The clock reset unit also integrates a two-level reset control logic: after the on-chip system bus reset signal arrives and the clock frequency stabilizes, a two-level reset is initiated on the Ethernet core through the kernel reset signal, and the kernel reset signal is revoked after the reset is completed.

8. A gigabit Ethernet media access controller for MCU chip integration according to claim 1, characterized in that, All hardware acceleration functions of the media access controller are integrated into the transmit and receive data path of the MAC core layer unit. When a network packet passes through the hardware processing pipeline once, it can sequentially complete checksum calculation and verification, multi-layer filtering condition matching, audio and video AV timestamp marking and queue scheduling without having to move data between multiple independent modules. All hardware acceleration functions share the same APB register for access, and share the same set of DMA descriptor status words and interrupt lines to report to the processor.

9. A gigabit Ethernet media access controller for MCU chip integration according to claim 1, characterized in that, It also includes a top-level APB extension register; the top-level APB extension register includes: The PTP timestamp high and low 32-bit read-only registers are used to store the 64-bit timestamp value generated by the PTP hardware unit inside the media access controller. Current DMA Channel ID Register: Indicates the DMA channel number currently occupying the MDIO bus for PHY register access; PTP Second Pulse Status Register: Used to capture the status of the output PTP second pulse signal; MAC Rate Indicator Register: Used to output the actual operating rate of the current MAC core layer unit.

10. A gigabit Ethernet media access controller for MCU chip integration according to claim 1, characterized in that, The logic synthesis area of ​​the media access controller is less than 400 kilogates and the power consumption is less than 4 milliwatts.

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