An 8K ultra-high resolution video frame buffer architecture based on AXI Stream video codec IP

Abstract

The application discloses an 8K ultra-high resolution video frame buffer architecture based on an AXI Stream video coding IP. In view of the 8K@30Hz ultra-high resolution video signal with the AXI Stream IP as video coding input and decoding output, a kind of buffer architecture of high resolution high bandwidth concurrent video frame data under the scene that the front and rear stage AXI Stream clock is higher than the AXI4 FULL bus clock is designed and realized. Facing the scene that the timing resource of AXI Stream signal is short, the problems of high bandwidth parallel data caused by difficult control of buffer timing and high resolution are solved. The architecture has the advantages of low complexity and easy deployment, and finally completes the storage, handling, transmission and display output of the 8K resolution Stream video signal stream.

Description

Technical Field

[0001] This invention belongs to the field of video processing and integrated circuit design technology, specifically relating to a frame buffer architecture for 8K ultra-high resolution video signals. It is particularly suitable for high-bandwidth, low-latency video frame data storage and transmission control under high-speed clock conditions using video codec IP based on the AXI Stream interface. This architecture can be widely applied in high-end video processing systems, immersive display devices, and glasses-free 3D display terminals. Background Technology

[0002] With the development of display technology, 8K ultra-high-definition video is gradually becoming the mainstream standard for next-generation display systems. Especially in glasses-free 3D display systems, it is necessary to simultaneously process high-resolution video streams from multiple viewpoints to achieve real-time rendering and output of stereoscopic visual effects. Glasses-free 3D displays typically require at least 4K or even higher resolution image content, while 8K requires even higher bandwidth video data streams. This places extremely high demands on the bandwidth, latency, timing control, and data throughput capabilities of the video frame buffer system.

[0003] In existing technologies, video frame buffers are typically implemented based on HDMI interfaces or the traditional AXI4 bus architecture. However, the HDMI interface includes horizontal and vertical sync signals and their leading and trailing edge timings, facilitating buffer control. In contrast, video codec IPs based on the AXI Stream interface lack similar horizontal and vertical sync auxiliary signals, resulting in extremely limited timing resources. This is especially problematic when the clock frequencies of the preceding and following AXI Stream stages are higher than the AXI4 FULL bus clock, leading to issues such as data conflicts, buffer overflows, and timing convergence difficulties. Furthermore, traditional buffer architectures struggle to efficiently support high-bandwidth parallel data streams at 8K@30Hz resolution, resulting in frame rate drops, image tearing, or display latency in high-throughput applications such as glasses-free 3D.

[0004] Therefore, in response to the practical problems of AXI Stream video codec IP in 8K ultra-high resolution video processing, such as difficulty in controlling buffer timing, complex cross-clock domain design, and low efficiency of high-bandwidth data transfer, there is an urgent need for a frame buffer architecture that is low in complexity, easy to deploy, and has high concurrency processing capabilities, especially suitable for the synchronous buffering and scheduling of multiple high-resolution video streams in naked-eye 3D display systems. Summary of the Invention

[0005] The main problem solved by this invention is that, for AXIStream signals where both the front-end and back-end video codec IPs are high-speed clocks, this type of video signal does not have the leading and trailing edges and synchronization time in the horizontal and vertical signals compared to HDMI signals. This solves the problems of difficult control of buffer timing and difficulty in setting cross-clocking for high-resolution data bandwidth and high throughput in scenarios with tight timing resources.

[0006] To address the aforementioned issues, this application designs an 8K ultra-high resolution video frame buffer architecture based on AXI Stream video codec IP, comprising: an AXI Stream forward asynchronous FIFO module, an AXI4 FULL core module, an AXI Stream backward asynchronous FIFO module, and a frame ID buffer module. Specifically, the AXI Stream forward asynchronous FIFO module is responsible for cross-clock domain processing of the write direction control signal for the video signal input from the preceding stage using the AXI Stream protocol; the AXI4 FULL core module is responsible for converting the signal processed by the forward asynchronous FIFO across clock domains from the AXI Stream protocol to the AXI4 FULL protocol and completing the cross-clock domain transmission of video pixel data; the AXI Stream backward asynchronous FIFO module is responsible for cross-clock domain processing of the read direction control signal for the video signal read from the following stage using the AXI Stream protocol; and the frame ID buffer module uses a "write a full frame before reading" control mechanism to prevent data loss caused by simultaneous video read / write operations, and employs frame counting cross-clock domain buffering technology to avoid the loss of frame flag pulses in register form due to metastability under high-speed clock conditions.

[0007] Correspondingly, the 8K ultra-high resolution video frame buffer architecture based on the AXI Stream video codec IP includes the following interfaces: the AXI Stream forward asynchronous FIFO module interface includes the clock and related protocol signals for the input of the front-end 8K video decoding AXI Stream signal, the output signals for the forward write address asynchronous FIFO, the input of the clear reset request signal from the AXI4 FULL core module, the output of the clear write frame buffer reset signal to the AXI4 FULL core module, and the input of the write frame ID from the frame ID buffer module; the AXI4 FULL core module includes a forward (write direction) address buffer asynchronous FIFO, a forward (write direction) data buffer asynchronous FIFO, a backward (read direction) address buffer asynchronous FIFO, and a backward (read direction) data buffer asynchronous FIFO, and its interface includes all input and output signals of the AXI4 bus, the AXI4 bus clock, all interface signals received from the AXI Stream forward asynchronous FIFO module, all interface signals received from the AXI Stream backward asynchronous FIFO module, and valid data signals from the AXI Stream output to the AXI Stream backward asynchronous FIFO module; AXI The Stream conversion backward asynchronous FIFO module interface includes clock and related protocol signals for the input of the AXI Stream signal for the subsequent 8K video decoding, output signals related to the backward write address asynchronous FIFO, input of the clear reset request signal from the AXI4 FULL core module, output of the clear read frame buffer reset signal to the AXI4 FULL core module, output of the frame field rising edge signal to the frame ID buffer module, and input of the read frame ID from the frame ID buffer module. The frame ID buffer module includes a frame counting buffer asynchronous FIFO, and its interface inputs include forward and backward AXI Stream clocks, input of the write frame falling edge, input of the frame counting FIFO read enable, and output of the write frame ID to the AXI Stream conversion forward asynchronous FIFO module and the read frame ID to the AXI Stream conversion backward asynchronous FIFO module.

[0008] Through the above design, the AXI Stream signals of common 8K video codec physical layers, which are converted from IP inputs and drive outputs via the AXI Stream protocol, can be written into the AXI4 FULL interface memory controller IP that supports high-speed concurrent data processing.

[0009] The introduction of asynchronous FIFOs enables address control signals and data to be processed across clock domains, preventing metastability, between the AXI Stream video clock domain and the AXI4FULL buffer controller clock domain.

[0010] The frame writing uses the falling edge-triggered frame ID buffer, which has the advantage of being more suitable for AXI Stream video signals with extremely short frame intervals than the rising edge-triggered method commonly used in the pure HDMI video protocol. It can reserve more clock cycles for logic operations such as frame buffer reset and clearing.

[0011] In addition, using a frame ID counter buffer instead of a register pulse flag to trigger the frame reading timing can effectively prevent the occasional loss of pulse signals under high-frequency clock conditions.

[0012] Correspondingly, the forward write address asynchronous FIFO in the AXI4 FULL core module uses the clock M AXIS CLK of the preceding AXI Stream video decoding IP for writing and S AXIS CLK of the following AXI Stream video encoding IP for reading. Write enable is the write address request wr request input to the AXI Stream-converted forward asynchronous FIFO module, and write data is the write address input to the AXI Stream-converted forward asynchronous FIFO module. Read enable is triggered by the AXI4 FULL core module state machine control. The read data is sent as the AXI write address to the write address channel of the AXI4 FULL bus as the write address signal. Its advantage is that it separates the address control signal from the data and buffers them across clock domains through asynchronous FIFOs. Its advantage lies in the ability to flexibly rearrange data in the buffer through the address control logic of the top-level user end.

[0013] Correspondingly, in the AXI4 FULL core module, the forward write data asynchronous FIFO has a write clock of M AXIS CLK, the clock of the preceding AXI Stream video decoding IP, and a read clock of S AXIS CLK, the clock of the following AXI Stream video encoding IP. The write enable is the forward valid write data input to the AXI Stream conversion forward asynchronous FIFO module, and the write data is the write valid data input to the AXI Stream conversion forward asynchronous FIFO module. The read enable is triggered by the state machine control of the AXI4 FULL core module, and the read data is sent as the AXI write data to the write data channel of the AXI4 FULL bus as the write data signal.

[0014] Accordingly, the AXI Stream conversion forward asynchronous FIFO module includes the following steps:

[0015] Step 1: Perform asynchronous reset and synchronous release cross-clock domain processing on the initialization signal of the DDR controller IP and the system reset. Accordingly, set the frame buffer start valid flag to a high level. The function is to control this module to trigger all functions after the cross-clock domain reset and DDR initialization are completed simultaneously.

[0016] Step 2: Set the AXI Stream valid data counter to count pixel data, record the last data of each frame, and obtain the falling edge of the write frame signal;

[0017] Step 3: Set up the shift register and corresponding counter to convert the input low-width AXI Stream data into high-width data, and set the data valid signal to high level at the end of each conversion. The data and its valid signal are used to send to the forward data FIFO in the AXI4 FULL core module.

[0018] Step 4: Set a burst transmission counter. Count the number of AXI4 data to be transmitted until the current transmission transaction reaches 4096 bytes, then set the write request signal.

[0019] Step 5: Set a line counter to divide each line of video data into 8 bursts. The line counter returns to zero after counting to 8 times the height of the video line. The advantage of this is that it can avoid the loss of control signals and data caused by crossing the 4K byte boundary in the AXI4 protocol, which could lead to system instability.

[0020] Correspondingly, the burst counter and row counter related logic circuits are characterized in that: for controlling the write address, for the write address to increment automatically, in addition to allocating 4096 bytes of address space for each burst, the address must also be controlled within the range of three frames. After the falling edge of each frame is triggered, the starting address of the current frame is updated. The write request signal and address are used to send to the forward address FIFO in the AXI4 FULL core module.

[0021] Accordingly, the AXI4 FULL core module includes the following steps:

[0022] Step 1: Perform cross-clock domain processing of asynchronous reset and synchronous release under AXI4 FULL clock for system reset, and then trigger all functions of this module;

[0023] Step 2: Set up the write transaction state machine;

[0024] Step 2.1: The state machine is initially in an idle state. When the forward address FIFO is not empty, it immediately jumps to the AXI4 write address state in the next moment.

[0025] Step 2.2: When the state machine is in the AXI4 write address state, after the AXI4 write address valid signal handshake is successful, it immediately jumps to the transmit data state in the next moment.

[0026] Step 2.3: When the state machine is in the data transmission state, when the current data bursts to the last data, it will jump to the end state in the next moment.

[0027] Step 2.4: When the state machine is in the end-of-transmission state, it immediately jumps back to the idle state in the next instant.

[0028] Step 3: When the state is in AXI4 write address state, set the forward address FIFO read enable to high level and read the write address written to the forward address FIFO.

[0029] Step 4: When the state is in the data transmission state, set the read enable of the forward data FIFO to high level and read the write data written to the forward data FIFO.

[0030] Step 5: Set up the read transaction state machine.

[0031] Step 5.1: The state machine is initially in an idle state. When the backward address FIFO is not empty, it immediately jumps to the AXI4 read address state in the next moment.

[0032] Step 5.2: When the state machine is in the AXI4 read address state, it immediately jumps to the receive read data state in the next moment;

[0033] Step 5.3: When the state machine is in the receive / read data state, when the current data bursts to the last data, it will jump to the end state in the next moment.

[0034] Step 5.4: When the state machine is in the end-of-transmission state, it immediately jumps back to the idle state in the next instant.

[0035] Step 6: When the state is in AXI4 read address state, set the read enable of the backward address FIFO to high level and read the read address written to the backward address FIFO.

[0036] Step 7: Receive valid AXI4 data and successfully handshake as write enable for the backward data FIFO, and read data from AXI4 as write data for the backward data FIFO.

[0037] Step 8: Set up the shift register, counter, and valid flag signal for reading data from AXI4, perform the necessary high-to-low bit width conversion on the data read from AXI4, and set the data valid flag to high level when the counter counts that there is a valid data signal in the shift register;

[0038] Step 9: When the backward data FIFO is not empty and all data in the shift register is invalid (shifting is complete), set the read enable of the backward data FIFO, read the data and wait for the bit width conversion output in step 8 to complete the cross-clock domain operation.

[0039] Step 10: Set up a synchronous FIFO. The read data from the backward data FIFO is valid as the write enable of this FIFO, and the data is used as the write data of this FIFO. The S AXIS TVALID of the subsequent AXI Stream is used as the read enable of this FIFO, and the data can be directly output to S AXIS TDATA. Its advantage is that, under the premise that the pre-calculated bandwidth is fully sufficient, the frame buffer design does not need to send back pressure signals to the front-stage video input IP, nor does it need to design complex control logic for the back pressure signals sent by the subsequent video driver IP.

[0040] Accordingly, the AXI Stream conversion backward asynchronous FIFO module includes the following steps:

[0041] Step 1: Perform asynchronous reset and synchronous release cross-clock domain processing on the initialization signal of the DDR controller IP and the system reset. Accordingly, set the frame buffer start valid flag to a high level. The function is to control this module to trigger all functions after the cross-clock domain reset and DDR initialization are completed simultaneously.

[0042] Step 2: Set the AXI Stream valid data counter to count pixel data, record the last data of each frame, and obtain the falling edge of the read frame signal;

[0043] Step 3: Set a line counter to divide each line of video data into 8 bursts of transmission. The line counter will return to zero after counting to 8 times the height of the video lines.

[0044] Step 4: Set up the read control state machine;

[0045] Step 4.1: The state machine is initially in an idle state. When the falling edge of the read frame signal is valid, it immediately jumps to the read reset and clear state in the next moment.

[0046] Step 4.2: When the state machine is in the read reset clear state, it waits for the reset clear counter to count to the set value, and then jumps to the read request state at the next moment.

[0047] Step 4.3: When the state machine is in the read request state, it waits for the line counter to count to the number of bursts multiplied by the number of lines of the video resolution, and for the current read request signal to be validly handshaked. Then, the state machine will jump to the end state in the next moment.

[0048] Step 4.4: When the state machine is in the terminated state, it immediately jumps to return to the idle state in the next moment;

[0049] Step 5: Set the read frame clear reset counter, set a reasonable maximum count value, and complete the reset and clearing of the read buffer FIFO and related control logic;

[0050] Step 6: Design read address update. Its advantage is that it can ensure that read data is output to the subsequent video encoding modules in accordance with the frame rate.

[0051] Correspondingly, the read address update logic is used to control the read address. For the read address auto-increment, in addition to allocating 4096 bytes of address space for each burst, it is also necessary to control the address within the range of three frames. After the falling edge of each frame is triggered, the starting address of the current frame is updated. The read request signal and address are used to send to the backward address FIFO in the AXI4 FULL core module.

[0052] Correspondingly, the frame number buffer module sets up a write frame counter and a FIFO for buffering the frame counter. The write enable of the FIFO of this module is triggered by the last signal of the write frame, i.e., the falling edge of the analog signal. The write frame count is used as the write data of the FIFO.

[0053] Correspondingly, the frame number buffer module, when the falling edge of the frame read signal in step 2 of the AXI Stream conversion to the asynchronous FIFO module is valid, triggers the read enable of the frame number FIFO at the next moment, reads the current frame number and inputs it to the AXI Stream conversion to the asynchronous FIFO module.

[0054] Correspondingly, the AXI Stream conversion pre- and post-conversion asynchronous FIFO modules directly connect the relevant AXI Stream signals for the preceding and following AXI Stream video codec IPs with the same source clock.

[0055] Compared with the prior art, the advantages of the present invention are as follows:

[0056] 1. Compared to common frame buffering schemes that use HDMI signals as input and drive, the frame buffering architecture of this invention is suitable for high-speed encoding and decoding scenarios of ultra-high-definition 8K video, and supports lossless video transmission and buffering control under the AXI Stream interface;

[0057] 2. Compared to the solution of directly using the AXI Stream format for address auto-incrementing caching and not controlling the address but only writing or reading pixel data sequentially to or from DDR in a Stream-like manner, the present invention can independently control the read and write addresses, thereby realizing flexible rearrangement of data in the cache;

[0058] 3. Compared to the existing AXI Stream to AXI4 FULL related IP, which requires complex C encoding logic to control read and write addresses, this invention only requires modifying a few user parameters at the top level of RTL to flexibly configure cache address mapping. Attached Figure Description

[0059] Figure 1 This is a schematic diagram of the integrated connection design of the frame buffer architecture system in the method of the present invention.

[0060] Figure 2 This is the read / write state machine transition diagram of the AXI4 FULL core module in the method of the present invention. Detailed Implementation

[0061] To enhance understanding of the present invention, the following detailed description of the solution is provided in conjunction with the accompanying drawings.

[0062] Example: Figure 1 As shown, an 8K ultra-high resolution video frame buffer architecture based on AXI Stream video codec IP includes: an AXI Stream forward asynchronous FIFO module (axis2fifo), an AXI4 FULL core module (axifull core), an AXI Stream backward asynchronous FIFO module (fifo2axis), and a frame ID buffer module.

[0063] The AXI4 FULL core module includes a front-end address FIFO, a front-end data FIFO, a back-end address FIFO, and a back-end data FIFO. Internally, it uses a separate read / write transaction state machine to control the AXI4 FULL bus, ultimately storing the 8K resolution video transmitted by the front-end decoding IP and outputting it to the back-end video encoding IP module.

[0064] This 8K ultra-high resolution video frame buffer architecture is based on the AXI Stream video codec IP. The AXI Stream forward asynchronous FIFO module interface includes clock and related protocol signals for the front-end 8K video decoding AXI Stream signal input, output signals for the forward write address asynchronous FIFO, input of a clear / reset request signal from the AXI4 FULL core module, output of a clear / reset signal to the AXI4 FULL core module, and input of the write frame ID from the frame ID buffer module. The AXI4FULL core module includes a forward (write direction) address buffer asynchronous FIFO, a forward (write direction) data buffer asynchronous FIFO, a backward (read direction) address buffer asynchronous FIFO, and a backward (read direction) data buffer asynchronous FIFO. Its interface includes input / output signals for all AXI4 buses, the AXI4 bus clock, all interface signals received from the AXI Stream forward asynchronous FIFO module, all interface signals received from the AXI Stream backward asynchronous FIFO module, and valid data signals from the AXI Stream output to the AXI Stream backward asynchronous FIFO module. The interface of the Stream conversion backward asynchronous FIFO module includes clock and related protocol signals for the input of the AXI Stream signal for the subsequent 8K video decoding, output signals related to the backward write address asynchronous FIFO, input of the clear reset request signal from the AXI4 FULL core module, output of the clear read frame buffer reset signal to the AXI4FULL core module, output of the frame field rising edge signal to the frame ID buffer module, and input of the read frame ID from the frame ID buffer module. The frame ID buffer module includes a frame counting buffer asynchronous FIFO, and its interface inputs include forward and backward AXI Stream clock, input of write frame falling edge, input of frame counting FIFO read enable, output of the write frame ID to the AXI Stream conversion forward asynchronous FIFO module, and the read frame ID to the AXI Stream conversion backward asynchronous FIFO module.

[0065] Correspondingly, in the AXI4 FULL core module, the forward write address asynchronous FIFO has the write clock as the clock M AXIS CLK of the preceding AXI Stream video decoding IP, and the read clock as the clock S AXIS CLK of the subsequent AXI Stream video encoding IP. The write enable is the write address request wr request input by the AXI Stream conversion forward asynchronous FIFO module, the write data is the write address input by the AXI Stream conversion forward asynchronous FIFO module, and the read enable is triggered by the state machine control of the AXI4 FULL core module. The read data is sent as the AXI write address to the write address channel of the AXI4 FULL bus as the write address signal.

[0066] Correspondingly, in the AXI4 FULL core module, the forward write data asynchronous FIFO has a write clock of M AXIS CLK, the clock of the preceding AXI Stream video decoding IP, and a read clock of S AXIS CLK, the clock of the following AXI Stream video encoding IP. The write enable is the forward valid write data input to the AXI Stream conversion forward asynchronous FIFO module, and the write data is the write valid data input to the AXI Stream conversion forward asynchronous FIFO module. The read enable is triggered by the state machine control of the AXI4 FULL core module, and the read data is sent as the AXI write data to the write data channel of the AXI4 FULL bus as the write data signal.

[0067] like Figure 2 As shown, an 8K ultra-high resolution video frame buffer architecture based on AXI Stream video codec IP is described, and the steps for writing the state machine of its AXI4 FULL core module are as follows:

[0068] Step 1: The state machine is initially in an idle state. When the forward address FIFO is not empty, it immediately jumps to the AXI4 write address state in the next moment.

[0069] Step 2: When the state machine is in the AXI4 write address state, after the AXI4 write address valid signal handshake is successful, it immediately jumps to the transmit data state in the next moment.

[0070] Step 3: When the state machine is in the data transmission state, when the current data bursts to the last data, the next moment jumps to the end state;

[0071] Step 4: When the state machine is in the end-of-transmission state, it immediately jumps back to the idle state in the next instant.

[0072] The implementation steps for reading the state machine in its AXI4 FULL core module are as follows:

[0073] Step 1: The state machine is initially in an idle state. When the backward address FIFO is not empty, it immediately jumps to the AXI4 read address state in the next moment.

[0074] Step 2: When the state machine is in the AXI4 read address state, it immediately jumps to the receive read data state in the next moment;

[0075] Step 3: When the state machine is in the receive / read data state, when the current data bursts to the last data, it will jump to the end state in the next moment.

[0076] Step 4: When the state machine is in the end-of-transmission state, it immediately jumps back to the idle state in the next instant.

[0077] Accordingly, the AXI Stream conversion forward asynchronous FIFO module includes the following steps:

[0078] Step 1: Perform asynchronous reset and synchronous release cross-clock domain processing on the initialization signal of the DDR controller IP and the system reset. Accordingly, set the frame buffer start valid flag to a high level. The function is to control this module to trigger all functions after the cross-clock domain reset and DDR initialization are completed simultaneously.

[0079] Step 2: Set the AXI Stream valid data counter to count pixel data, record the last data of each frame, and obtain the falling edge of the write frame signal;

[0080] Step 3: Set up the shift register and corresponding counter to convert the input low-width AXI Stream data into high-width data, and set the data valid signal to high level at the end of each conversion. The data and its valid signal are used to send to the forward data FIFO in the AXI4 FULL core module.

[0081] Step 4: Set a burst transmission counter. Count the number of AXI4 data to be transmitted until the current transmission transaction reaches 4096 bytes, then set the write request signal.

[0082] Step 5: Set a line counter to divide each line of video data into 8 bursts of transmission. The line counter will return to zero after counting to 8 times the height of the video lines.

[0083] Correspondingly, the burst counter and row counter related logic circuits are used to control the write address. For the write address to increment automatically, in addition to allocating 4096 bytes of address space for each burst, it is also necessary to control the address within the range of three frames. After the falling edge of each frame is triggered, the starting address of the current frame is updated. The write request signal and address are used to send to the forward address FIFO in the AXI4 FULL core module.

[0084] Accordingly, the AXI4 FULL core module includes the following steps:

[0085] Step 1: Perform cross-clock domain processing of asynchronous reset and synchronous release under AXI4 FULL clock for system reset, and then trigger all functions of this module;

[0086] Step 2: Set up the write transaction state machine;

[0087] Step 2.1: The state machine is initially in an idle state. When the forward address FIFO is not empty, it immediately jumps to the AXI4 write address state in the next moment.

[0088] Step 2.2: When the state machine is in the AXI4 write address state, after the AXI4 write address valid signal handshake is successful, it immediately jumps to the transmit data state in the next moment.

[0089] Step 2.3: When the state machine is in the data transmission state, when the current data bursts to the last data, it will jump to the end state in the next moment.

[0090] Step 2.4: When the state machine is in the end-of-transmission state, it immediately jumps back to the idle state in the next instant.

[0091] Step 3: When the state is in AXI4 write address state, set the forward address FIFO read enable to high level and read the write address written to the forward address FIFO.

[0092] Step 4: When the state is in the data transmission state, set the read enable of the forward data FIFO to high level and read the write data written to the forward data FIFO.

[0093] Step 5: Set up the read transaction state machine.

[0094] Step 5.1: The state machine is initially in an idle state. When the backward address FIFO is not empty, it immediately jumps to the AXI4 read address state in the next moment.

[0095] Step 5.2: When the state machine is in the AXI4 read address state, it immediately jumps to the receive read data state in the next moment;

[0096] Step 5.3: When the state machine is in the receive / read data state, when the current data bursts to the last data, it will jump to the end state in the next moment.

[0097] Step 5.4: When the state machine is in the end-of-transmission state, it immediately jumps back to the idle state in the next instant.

[0098] Step 6: When the state is in AXI4 read address state, set the read enable of the backward address FIFO to high level and read the read address written to the backward address FIFO.

[0099] Step 7: Receive valid AXI4 data and successfully handshake as write enable for the backward data FIFO, and read data from AXI4 as write data for the backward data FIFO.

[0100] Step 8: Set up the shift register, counter, and valid flag signal for reading data from AXI4, perform the necessary high-to-low bit width conversion on the data read from AXI4, and set the data valid flag to high level when the counter counts that there is a valid data signal in the shift register;

[0101] Step 9: When the backward data FIFO is not empty and all data in the shift register is invalid (shifting is complete), set the read enable of the backward data FIFO, read the data and wait for the bit width conversion output in step 8 to complete the cross-clock domain operation.

[0102] Step 10: Set up a synchronous FIFO. Reading valid data from the backward data FIFO serves as the write enable for this FIFO, and the data is used as the write data for this FIFO. The S AXIS TVALID of the subsequent AXI Stream serves as the read enable for this FIFO, and the data can be directly output to S AXIS TDATA.

[0103] Accordingly, the AXI Stream conversion backward asynchronous FIFO module includes the following steps:

[0104] Step 1: Perform asynchronous reset and synchronous release cross-clock domain processing on the initialization signal of the DDR controller IP and the system reset. Accordingly, set the frame buffer start valid flag to a high level. The function is to control this module to trigger all functions after the cross-clock domain reset and DDR initialization are completed simultaneously.

[0105] Step 2: Set the AXI Stream valid data counter to count pixel data, record the last data of each frame, and obtain the falling edge of the read frame signal;

[0106] Step 3: Set a line counter to divide each line of video data into 8 bursts of transmission. The line counter will return to zero after counting to 8 times the height of the video lines.

[0107] Step 4: Set up the read control state machine;

[0108] Step 4.1: The state machine is initially in an idle state. When the falling edge of the read frame signal is valid, it immediately jumps to the read reset and clear state in the next moment.

[0109] Step 4.2: When the state machine is in the read reset clear state, it waits for the reset clear counter to count to the set value, and then jumps to the read request state at the next moment.

[0110] Step 4.3: When the state machine is in the read request state, it waits for the line counter to count to the number of bursts multiplied by the number of lines of the video resolution, and for the current read request signal to be validly handshaked. Then, the state machine will jump to the end state in the next moment.

[0111] Step 4.4: When the state machine is in the terminated state, it immediately jumps to return to the idle state in the next moment;

[0112] Step 5: Set the read frame clear reset counter, set a reasonable maximum count value, and complete the reset and clearing of the read buffer FIFO and related control logic;

[0113] Step 6: Design read address update;

[0114] The read address update logic is used to control the read address. For the read address to increment automatically, in addition to allocating 4096 bytes of address space for each burst, it is also necessary to control the address within the range of three frames. After the falling edge of each frame is triggered, the starting address of the current frame is updated. The read request signal and address are used to send to the backward address FIFO in the AXI4 FULL core module.

[0115] The frame number buffer module sets up a write frame counter and a FIFO for buffering the frame counter. The write enable of the FIFO of this module is triggered by the last signal of the write frame, i.e., the falling edge of the analog signal. The write frame count is used as the write data of the FIFO.

[0116] The frame number buffer module, when the falling edge of the frame read signal in step 2 of the AXI Stream conversion asynchronous FIFO module is valid, triggers the read enable of the frame number FIFO at the next moment, reads the current frame number and inputs it to the AXI Stream conversion asynchronous FIFO module;

[0117] The AXI Stream conversion pre- and post-conversion asynchronous FIFO modules directly connect the relevant AXI Stream signals for AXI Stream video codec IPs with the same clock source.

[0118] It should be noted that the above embodiments are not intended to limit the scope of protection of the present invention. Equivalent transformations or substitutions made based on the above technical solutions all fall within the scope of protection of the claims of the present invention.

Claims

1. An 8K ultra-high resolution video frame buffer architecture based on AXI Stream video codec IP, characterized in that, include: The AXI Stream forward asynchronous FIFO conversion module, the AXI4 FULL core module, the AXI Stream backward asynchronous FIFO conversion module, and the frame ID buffer module; The AXI Stream forward asynchronous FIFO conversion module is responsible for processing the write direction control signal of the video signal input by the previous stage using the AXI Stream protocol across clock domains. The AXI4 FULL core module is responsible for converting the signal processed by the forward asynchronous FIFO across clock domains from the AXI Stream protocol to the AXI4 FULL protocol and completing the cross-clock domain transmission of video pixel data. The AXI Stream backward asynchronous FIFO conversion module is responsible for processing the read direction control signal of the video signal read by the subsequent stage using the AXI Stream protocol across clock domains. The frame ID buffer module prevents data loss caused by simultaneous reading and writing of video through the control mechanism of "writing a full frame before reading out", and adopts frame counting cross-clock domain buffering technology to avoid the loss of the frame flag pulse in register form due to metastability under high-speed clock.

2. The 8K ultra-high resolution video frame buffer architecture based on AXI Stream video codec IP as described in claim 1, characterized in that, The AXI Stream conversion forward asynchronous FIFO module interface includes clock and related protocol signals for the input of the front-end 8K video decoding AXI Stream signal, output forward write address asynchronous FIFO related signals, input of clear reset request signal from the AXI4 FULL core module, output of clear write frame buffer reset signal to the AXI4 FULL core module, and input of write frame ID from the frame ID buffer module; The AXI4 FULL core module includes a forward (write direction) address buffer asynchronous FIFO, a forward (write direction) data buffer asynchronous FIFO, a backward (read direction) address buffer asynchronous FIFO, and a backward (read direction) data buffer asynchronous FIFO. Its interface includes all input and output signals of the AXI4 bus, the AXI4 bus clock, receiving all interface signals from the AXI Stream converted forward asynchronous FIFO module, receiving all interface signals from the AXI Stream converted backward asynchronous FIFO module, and outputting valid data signals from the AXI Stream to the AXI Stream converted backward asynchronous FIFO module. The AXI Stream conversion backward asynchronous FIFO module interface includes clock and related protocol signals for the AXI Stream signal input to the subsequent 8K video decoding, output signals related to the backward write address asynchronous FIFO, input of the clear reset request signal from the AXI4 FULL core module, output of the clear read frame buffer reset signal to the AXI4 FULL core module, output of the frame field rising edge signal to the frame ID buffer module, and input of the read frame ID from the frame ID buffer module. The frame ID buffer module includes a frame count buffer asynchronous FIFO. The interface inputs include forward and backward AXI Stream clocks, input write frame falling edge, input frame count FIFO read enable, and outputs to AXI Stream to convert the write frame ID of the forward asynchronous FIFO module and AXI Stream to convert the read frame ID of the backward asynchronous FIFO module.

3. The 8K ultra-high resolution video frame buffer architecture based on AXI Stream video codec IP as described in claim 2, characterized in that, The forward write address asynchronous FIFO in the AXI4 FULL core module uses the clock M AXIS CLK of the preceding AXI Stream video decoding IP for writing and S AXIS CLK of the following AXI Stream video encoding IP for reading. Write enable is the write address request wr request input to the AXIStream-converted forward asynchronous FIFO module, and write data is the write address input to the AXI Stream-converted forward asynchronous FIFO module. Read enable is triggered by the AXI4 FULL core module state machine control, and the read data is sent as the AXI write address to the write address channel of the AXI4 FULL bus as the write address signal.

4. The 8K ultra-high resolution video frame buffer architecture based on AXI Stream video codec IP as described in claim 2, characterized in that, The forward asynchronous FIFO in the AXI4 FULL core module uses the clock M AXIS CLK of the preceding AXI Stream video decoding IP for writing and S AXIS CLK of the following AXI Stream video encoding IP for reading. Write enable is activated when the write data input to the AXIStream-converted forward asynchronous FIFO module is valid (forward valid), and the write data is the valid write data input to the AXI Stream-converted forward asynchronous FIFO module. Read enable is triggered by the AXI4 FULL core module state machine control, and the read data is sent as AXI write data to the write data channel of the AXI4 FULL bus as the write data signal.

5. The 8K ultra-high resolution video frame buffer architecture based on AXI Stream video codec IP as described in claim 2, characterized in that, The AXI Stream conversion forward asynchronous FIFO module includes the following steps: Step 1: Perform asynchronous reset and synchronous release cross-clock domain processing on the initialization signal of the DDR controller IP and the system reset. Accordingly, set the frame buffer start valid flag to a high level. The function is to control this module to trigger all functions after the cross-clock domain reset and DDR initialization are completed simultaneously. Step 2: Set the AXI Stream valid data counter to count pixel data, record the last data of each frame, and obtain the falling edge of the write frame signal; Step 3: Set up the shift register and corresponding counter to convert the input low-width AXI Stream data into high-width data, and set the data valid signal to high level at the end of each conversion. The data and its valid signal are used to send to the forward data FIFO in the AXI4 FULL core module. Step 4: Set a burst transmission counter. Count the number of AXI4 data to be transmitted until the current transmission transaction reaches 4096 bytes, then set the write request signal. Step 5: Set a line counter to divide each line of video data into 8 bursts of transmission. The line counter will return to zero after counting to 8 times the height of the video lines.

6. The 8K ultra-high resolution video frame buffer architecture based on AXI Stream video codec IP as described in claim 5, characterized in that, The burst counter and row counter related logic circuits are used to control the write address. For the write address to increment automatically, in addition to allocating 4096 bytes of address space for each burst, it is also necessary to control the address within the range of three frames. After the falling edge of each frame is triggered, the start address of the current frame is updated. The write request signal and address are used to send to the forward address FIFO in the AXI4 FULL core module.

7. The 8K ultra-high resolution video frame buffer architecture based on AXI Stream video codec IP as described in claim 5, characterized in that, The AXI4 FULL core module includes the following steps: Step 1: Perform cross-clock domain processing of asynchronous reset and synchronous release under AXI4 FULL clock for system reset, and then trigger all functions of this module; Step 2: Set up the write transaction state machine; Step 2.1: The state machine is initially in an idle state. When the forward address FIFO is not empty, it immediately jumps to the AXI4 write address state in the next moment. Step 2.2: When the state machine is in the AXI4 write address state, after the AXI4 write address valid signal handshake is successful, it immediately jumps to the transmit data state in the next moment. Step 2.3: When the state machine is in the data transmission state, when the current data bursts to the last data, it will jump to the end state in the next moment. Step 2.4: When the state machine is in the end-of-transmission state, it immediately jumps back to the idle state in the next instant. Step 3: When the state is in AXI4 write address state, set the forward address FIFO read enable to high level and read the write address written to the forward address FIFO. Step 4: When the state is in the data transmission state, set the read enable of the forward data FIFO to high level and read the write data written to the forward data FIFO. Step 5: Set up the read transaction state machine. Step 5.1: The state machine is initially in an idle state. When the backward address FIFO is not empty, it immediately jumps to the AXI4 read address state in the next moment. Step 5.2: When the state machine is in the AXI4 read address state, it immediately jumps to the receive read data state in the next moment; Step 5.3: When the state machine is in the receive / read data state, when the current data bursts to the last data, it will jump to the end state in the next moment. Step 5.4: When the state machine is in the end-of-transmission state, it immediately jumps back to the idle state in the next instant. Step 6: When the state is in AXI4 read address state, set the read enable of the backward address FIFO to high level and read the read address written to the backward address FIFO. Step 7: Receive valid AXI4 data and successfully handshake as write enable for the backward data FIFO, and read data from AXI4 as write data for the backward data FIFO. Step 8: Set up the shift register, counter, and valid flag signal for reading data from AXI4, perform the necessary high-to-low bit width conversion on the data read from AXI4, and set the data valid flag to high level when the counter counts that there is a valid data signal in the shift register; Step 9: When the backward data FIFO is not empty and all data in the shift register is invalid (shifting is complete), set the read enable of the backward data FIFO, read the data and wait for the bit width conversion output in step 8 to complete the cross-clock domain operation. Step 10: Set up a synchronous FIFO. The read data from the backward data FIFO is valid as the write enable of the FIFO, and the data is used as the write data of the FIFO. The S AXIS TVALID of the subsequent AXI Stream is used as the read enable of the FIFO, and the data can be directly output to S AXIS TDATA.

8. The 8K ultra-high resolution video frame buffer architecture based on AXI Stream video codec IP as described in claim 5, characterized in that, The AXI Stream conversion backward asynchronous FIFO module includes the following steps: Step 1: Perform asynchronous reset and synchronous release cross-clock domain processing on the initialization signal of the DDR controller IP and the system reset. Accordingly, set the frame buffer start valid flag to a high level. The function is to control this module to trigger all functions after the cross-clock domain reset and DDR initialization are completed simultaneously. Step 2: Set the AXI Stream valid data counter to count pixel data, record the last data of each frame, and obtain the falling edge of the read frame signal; Step 3: Set a line counter to divide each line of video data into 8 bursts of transmission. The line counter will return to zero after counting to 8 times the height of the video lines. Step 4: Set up the read control state machine; Step 4.1: The state machine is initially in an idle state. When the falling edge of the read frame signal is valid, it immediately jumps to the read reset and clear state in the next moment. Step 4.2: When the state machine is in the read reset clear state, it waits for the reset clear counter to count to the set value, and then jumps to the read request state at the next moment. Step 4.3: When the state machine is in the read request state, it waits for the line counter to count to the number of bursts multiplied by the number of lines of the video resolution, and for the current read request signal to be validly handshaked. Then, the state machine will jump to the end state in the next moment. Step 4.4: When the state machine is in the terminated state, it immediately jumps to return to the idle state in the next moment; Step 5: Set the read frame clear reset counter, set a reasonable maximum count value, and complete the reset and clearing of the read buffer FIFO and related control logic; Step 6: Design read address update.

9. The 8K ultra-high resolution video frame buffer architecture based on AXI Stream video codec IP as described in claim 5, characterized in that, The read address update logic is used to control the read address. For the read address to increment automatically, in addition to allocating 4096 bytes of address space for each burst, it is also necessary to control the address within the range of three frames. After the falling edge of each frame is triggered, the starting address of the current frame is updated. The read request signal and address are used to send to the backward address FIFO in the AXI4 FULL core module. The frame number buffer module is configured with a write frame counter and a FIFO for buffering the frame counter. The write enable of the FIFO is triggered by the last signal of the write frame, i.e., the analog falling edge, and the write frame count is used as the write data of the FIFO. The AXI Stream conversion pre- and post-conversion asynchronous FIFO modules directly connect the relevant AXI Stream signals for AXI Stream video codec IPs with the same clock source. The directly connected related AXI Stream signals include: valid signal AXIS TVALID, ready signal AXISTREADY, frame flag signal AXIS TUSER, last line data flag AXIS TLAST, mask AXIS TSTRB, and other signals not related to the data read by the frame buffer module of this invention; The AXI4 FULL core module includes: a write buffer reset and clear trigger signal under the AXI4 clock domain, and an AXI4 write data counter. The AXI4 write data counter is used to count the number of AXI4 write data in the current transaction. When the number of data bytes in a whole frame is reached, the write buffer reset and clear trigger signal is set to a high level and sent to the AXI Stream forward conversion asynchronous FIFO module.

10. The 8K ultra-high resolution video frame buffer architecture based on AXI Stream video codec IP as described in claim 5, characterized in that, The frame number buffer module, when the falling edge of the read frame signal in step 2 of the AXI Stream conversion asynchronous FIFO module is valid, triggers the read enable of the frame number FIFO at the next moment, reads the current read frame number and inputs it to the AXI Stream conversion asynchronous FIFO module.

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