Data acquisition device, data acquisition apparatus, and data acquisition method

Abstract

The present disclosure provides a data acquisition device, a data acquisition equipment and a data acquisition method, and relates to the technical fields of data acquisition and medical treatment. The data acquisition device comprises: an array substrate comprising 2N pixel circuit columns, N being a positive integer; a control circuit electrically connected with the 2N pixel circuit columns and configured to send a control signal to the 2N pixel circuit columns; a plurality of reading circuits, each reading circuit comprising a plurality of reading interfaces, each reading interface being electrically connected with a (2n-1)th pixel circuit column and a 2nth pixel circuit column in the 2N pixel circuit columns, each reading circuit being configured to read a data signal from the (2n-1)th pixel circuit column and a data signal from the 2nth pixel circuit column, wherein the data signals are output by the pixel circuit columns based on the control signal, and 1≤n≤N; and a master control driving circuit electrically connected with the plurality of reading circuits and configured to acquire and splice the plurality of data signals to obtain image data displayed by the array substrate.

Description

Technical Field

[0001] This disclosure relates to the fields of data acquisition and medical technology, and in particular to a data acquisition device, data acquisition equipment and data acquisition method. Background Technology

[0002] With the rapid development of the detector industry, the demand for detectors is increasing, making the requirement for low-cost detectors increasingly urgent. In addition to the design factors such as process and materials affecting costs, the internal circuit design of the detector also leads to changes in the cost. Summary of the Invention

[0003] This disclosure provides a data acquisition device, a data acquisition equipment, and a data acquisition method.

[0004] According to a first aspect, this disclosure provides a data acquisition device, comprising: an array substrate including 2N pixel circuit columns, where N is a positive integer; a control circuit electrically connected to the 2N pixel circuit columns and configured to send control signals to the 2N pixel circuit columns; a plurality of readout circuits, each readout circuit including a plurality of readout interfaces electrically connected to the (2n-1)th pixel circuit column and the 2nth pixel circuit column in the 2N pixel circuit columns, the readout circuits being configured to read data signals from the (2n-1)th pixel circuit column and data signals from the 2nth pixel circuit column, wherein the data signals are output by the pixel circuit columns based on the control signals, and 1≤n≤N; and a main control drive circuit electrically connected to the plurality of readout circuits for acquiring and stitching together the plurality of data signals to obtain image data displayed on the array substrate.

[0005] According to a second aspect, this disclosure provides a data acquisition device, including: a data acquisition apparatus provided in the embodiments of this disclosure; and a processor configured to send instructions to the data acquisition apparatus and receive image data from the data acquisition apparatus.

[0006] According to a third aspect, this disclosure provides a data acquisition method applied to the data acquisition device provided in the embodiments of this disclosure, comprising: a control circuit sending control signals to 2N pixel circuit columns included in the array substrate; the 2N pixel circuit columns generating data signals based on the control signals; multiple read circuits reading data signals of the (2n-1)th pixel circuit column and the 2nth pixel circuit column through their read interfaces; and a main control drive circuit acquiring and splicing multiple data signals to obtain image data displayed on the array substrate. Attached Figure Description

[0007] Figure 1 A schematic diagram of the structure of a data acquisition device according to an embodiment of the present disclosure is shown;

[0008] Figure 2A schematic diagram of the structure of a data acquisition device according to another embodiment of the present disclosure is shown;

[0009] Figure 3 A schematic diagram of the structure of an array substrate according to an embodiment of the present disclosure is shown;

[0010] Figure 4 A timing diagram of control signals according to an embodiment of the present disclosure is shown;

[0011] Figure 5 A partial structural schematic diagram of a data acquisition device according to an embodiment of the present disclosure is shown;

[0012] Figure 6 A schematic diagram of the structure of a data acquisition device according to another embodiment of the present disclosure is shown;

[0013] Figure 7 A schematic diagram of the structure of an array substrate according to another embodiment of the present disclosure is shown;

[0014] Figure 8 A schematic diagram of the structure of a data acquisition device according to another embodiment of the present disclosure is shown;

[0015] Figure 9 A timing diagram of control signals according to another embodiment of the present disclosure is shown;

[0016] Figure 10 A partial structural schematic diagram of a data acquisition device according to another embodiment of the present disclosure is shown;

[0017] Figure 11 A schematic diagram of the structure of a data acquisition device according to another embodiment of the present disclosure is shown;

[0018] Figure 12 A schematic diagram of the main drive circuit according to an embodiment of the present disclosure is shown;

[0019] Figure 13 A schematic diagram of the structure of a data acquisition device according to another embodiment of the present disclosure is shown;

[0020] Figure 14 A schematic diagram of the structure of a data acquisition device according to an embodiment of the present disclosure is shown;

[0021] Figure 15 A flowchart illustrating a data acquisition method according to an embodiment of this disclosure is shown. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. In the following description, some specific embodiments are for descriptive purposes only and should not be construed as limiting this disclosure in any way, but are merely examples of embodiments of this disclosure. Conventional structures or constructions will be omitted where they may cause confusion in understanding this disclosure. It should be noted that the shapes and dimensions of the components in the figures do not reflect actual size and proportion, but are only schematic representations of the contents of the embodiments of this disclosure.

[0023] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0024] Furthermore, in the description of the embodiments disclosed herein, the terms "connected to" or "linked" can refer to a direct connection between two components, or to a connection between two components via one or more other components, wherein the connection method is electrical connection or electrical coupling. Additionally, the two components can also be connected or coupled via wired or wireless means.

[0025] It should be noted that, in the description of the embodiments of this disclosure, the symbol SW1 can represent either the first signal terminal or the first signal provided by the first signal terminal. Similarly, the symbol SW2 can represent either the second signal terminal or the second signal provided by the second signal terminal.

[0026] Figure 1 A schematic diagram of the structure of a data acquisition device according to an embodiment of the present disclosure is shown.

[0027] like Figure 1 As shown, the data acquisition device 100 includes an array substrate 110, a control circuit 120, multiple reading circuits 130, and a main control drive circuit 140.

[0028] In this embodiment of the disclosure, the data acquisition device 100 can be various scanning imaging devices, such as X-ray flat panel detectors and non-destructive testing scanners.

[0029] The array substrate 110 includes 2N pixel circuit columns, where N is a positive integer. The value of N can be determined based on the size of the array substrate 110 and the required image resolution.

[0030] For example, when the data acquisition device 100 scans the object being detected, the array substrate 110 in the data acquisition device 100 can receive the light signal carrying the internal structural information of the object being detected, convert the light signal into an electrical signal, and store the electrical signal as a data signal in 2N pixel circuit columns.

[0031] In this embodiment of the disclosure, the control circuit 120 is electrically connected to 2N pixel circuit columns and is configured to send control signals to the 2N pixel circuit columns.

[0032] In this embodiment of the disclosure, the control signal can control the 2N pixel circuit columns and the multiple readout circuits 130 to be in an on or off state.

[0033] For example, when the control signal controls the 2N pixel circuit columns to be in a conducting state with the multiple readout circuits 130, the multiple readout circuits 130 can read the data signals of the 2N pixel circuit columns.

[0034] In this embodiment of the disclosure, the plurality of readout circuits 130 include readout circuits ROIC1, ..., ROICq, ..., ROICQ. Each readout circuit ROIC1, ..., ROICq, ..., ROICQ includes a plurality of readout interfaces RF. The readout interfaces RF can be electrically connected to the (2n-1)th and the 2nth pixel circuit columns in a 2N pixel circuit column. That is, any readout interface RF in each readout circuit can be electrically connected to an odd-numbered column of pixel circuits and an even-numbered column of pixel circuits.

[0035] For example, one read interface RF in read circuit ROIC1 can be electrically connected to the first pixel circuit column and the second pixel circuit column, another read interface RF in read circuit ROIC1 can be electrically connected to the third pixel circuit column and the fourth pixel circuit column, and so on. One read interface RF in read circuit ROICq can be electrically connected to the 2n-1 pixel circuit column and the 2n pixel circuit column, and so on. One read interface RF in read circuit ROICQ can be electrically connected to the 2N-1 pixel circuit column and the 2N pixel circuit column.

[0036] In this embodiment of the disclosure, each of the read circuits ROIC1, ..., ROICq, ..., ROICQ includes multiple read interfaces RF. Each read interface RF can read the data signal of the (2n-1)th pixel circuit column and the data signal of the 2nth pixel circuit in a 2N pixel circuit column. That is, any read interface RF in each read circuit can read the data signal of an odd-numbered pixel circuit column and the data signal of an even-numbered pixel circuit column.

[0037] For example, one read interface RF in read circuit ROIC1 can read the data signals of the first and second pixel circuit columns; another read interface RF in read circuit ROIC1 can read the data signals of the third and fourth pixel circuit columns; ... one read interface RF in read circuit ROICq can read the data signals of the (2n-1)th and 2nth pixel circuit columns; ... one read interface RF in read circuit ROICQ can read the data signals of the (2N-1)th and 2Nth pixel circuit columns.

[0038] In this embodiment, the main control drive circuit 140 is electrically connected to multiple reading circuits 130 to acquire and splice multiple data signals to obtain image data displayed on the array substrate 110.

[0039] In this embodiment of the disclosure, the main control drive circuit 140 can sequentially acquire multiple data signals read by the reading circuits ROIC1, ..., ROICq, ..., ROICQ, and splice the acquired multiple data signals according to the arrangement order of the 2N pixel circuit columns.

[0040] For example, the data acquisition device 100 can be used as an X-ray flat panel detector in medical imaging diagnostic scenarios. When X-rays penetrate the object being examined, the X-rays carrying tissue density information irradiate the array substrate 110. The array substrate 110 converts the received X-rays into electrical signals of corresponding intensities and stores them in multiple pixel circuit columns. Under the timing control of the control circuit 120, each pixel circuit column outputs data signals to multiple readout circuits 130. The main control drive circuit 140 sequentially acquires the data signals read by each readout circuit ROIC1, ..., ROICq, ..., ROICQ, and stitches the read data signals together according to the arrangement order of the multiple pixel circuit columns, displaying the diagnostic image of the object being examined on the array substrate 110.

[0041] In this embodiment, the data acquisition device 100 electrically connects a read interface RF to two pixel circuit columns, allowing data signals from both pixel circuit columns to be read through a single read interface RF, thus reducing the required number of read interfaces. With a fixed number of read interfaces in each read circuit, the number of read circuits in the data acquisition device 100 can be reduced, simplifying the circuit structure and lowering manufacturing costs.

[0042] Figure 2 A schematic diagram of a data acquisition apparatus according to another embodiment of the present disclosure is shown.

[0043] like Figure 2As shown, the data acquisition device 200 includes an array substrate 210, a control circuit 220, multiple reading circuits 230, and a main control drive circuit 240.

[0044] In this embodiment, the multiple read circuits 230 and the main control drive circuit 240 are similar in structure to the read circuit 130 and the main control drive circuit 140 described above, and will not be repeated for the sake of brevity.

[0045] In this embodiment, the array substrate 210 includes 2N pixel circuit columns, and the 2N pixel circuit columns include M pixel circuit rows, where M is a positive integer. The control circuit 220 is electrically connected to the M pixel circuit rows via 2M control lines LC. Each pixel circuit row in the M pixel circuit rows can be electrically connected to two control lines LC, and the two control lines LC connected to different pixel circuit rows are different. Specifically, the control lines LC are electrically connected to either the (2n-1)th pixel circuit (Pixel) or the 2nth pixel circuit (Pixel) in the pixel circuit row.

[0046] For example, a pixel circuit row is electrically connected to two control lines (LC). One control line (LC) can be electrically connected to multiple pixel circuits (Pixel) located in odd-numbered columns of that pixel circuit row, and the other control line (LC) can be electrically connected to multiple pixel circuits (Pixel) located in even-numbered columns of that pixel circuit row.

[0047] In this embodiment of the disclosure, the control circuit 220 can send control signals to M pixel circuit rows via 2M control traces LC. Specifically, the control circuit 220 can send a first-level control signal to the (2n-1)th pixel circuit or the 2nth pixel circuit in the pixel circuit row via the control traces LC. The first level can be a high level.

[0048] For example, a pixel circuit row is electrically connected to two control lines (LC). Control circuit 220 can send a first-level control signal to multiple pixel circuits (Pixel) located in odd-numbered columns of that pixel circuit row via one of the control lines (LC), causing these pixel circuits to output multiple data signals to multiple readout circuits 240. Control circuit 220 can also send a first-level control signal to multiple pixel circuits (Pixel) located in even-numbered columns of a pixel circuit row via the other control line (LC), causing these pixel circuits to output multiple data signals to multiple readout circuits 240.

[0049] The data acquisition device 100 in this embodiment utilizes 2M control lines (LC) to control the output data signals of pixel circuits in odd-numbered columns and even-numbered columns in M ​​pixel circuit rows. This allows multiple readout circuits 230 to read the data signals of pixel circuits in odd-numbered columns and even-numbered columns through a single readout interface (RF), thereby reducing the required number of readout interfaces. With a fixed number of readout interfaces in each readout circuit, the number of readout circuits in the data acquisition device 200 can be reduced, simplifying the circuit structure and lowering manufacturing costs.

[0050] In this embodiment, the control circuit 220 includes multiple control sub-circuits GIC, and each control sub-circuit GIC includes multiple control interfaces G. Each control interface G is electrically connected to a first control trace LC1 or a second control trace LC2. Specifically, the first control trace LC1 is electrically connected to the (2n-1)th pixel circuit in the same pixel circuit row, and the second control trace LC2 is electrically connected to the 2nth pixel circuit in the same pixel circuit row.

[0051] For example, a first control trace LC1 can be electrically connected to multiple pixel circuits located in odd-numbered columns of a pixel circuit row, and to a control interface G in a control sub-circuit GIC. A second control trace LC2 can be electrically connected to multiple pixel circuits located in even-numbered columns of the same pixel circuit row, and to another control interface G in the control sub-circuit GIC.

[0052] In this embodiment, the first control line LC1 can provide the control signal sent by the control interface G in the control sub-circuit GIC to the (2n-1)th pixel circuit in the pixel circuit row, and the second control line LC2 can provide the control signal sent by the control interface G in the control sub-circuit GIC to the 2nth pixel circuit in the pixel circuit row. Since the first control line LC1 is only electrically connected to the pixel circuits (1st, 3rd, ..., 2n-1st, ..., 2N-1st) in the odd-numbered columns of each pixel circuit row, and the second control line LC2 is only electrically connected to the pixel circuits (2nd, 4th, ..., 2nth, ..., 2Nth) in the even-numbered columns of each pixel circuit row, the control circuit 220 can independently select the pixel circuits in the odd-numbered columns and the pixel circuits in the even-numbered columns.

[0053] For example, a pixel circuit row is electrically connected to a first control line LC1 and a second control line LC2. The first control line LC1 can provide a first-level control signal sent by a control interface G in a control sub-circuit GIC to multiple pixel circuits Pixel located in odd-numbered columns of the pixel circuit row, causing the multiple pixel circuits Pixel located in odd-numbered columns of the pixel circuit row to output multiple data signals to multiple readout circuits 230. The second control line LC2 can provide a first-level control signal sent by another control interface G in the same control sub-circuit GIC to multiple pixel circuits Pixel located in even-numbered columns of the pixel circuit row, causing the multiple pixel circuits Pixel located in even-numbered columns of the pixel circuit row to output multiple data signals to multiple readout circuits 230.

[0054] The data acquisition device 100 in this embodiment utilizes a first control line LC1 and a second control line LC2 to control the output data signals of pixel circuits in odd-numbered columns and even-numbered columns in M ​​pixel circuit rows. This allows multiple read circuits 230 to read the data signals of pixel circuits in odd-numbered columns and even-numbered columns through a single read interface RF, thereby reducing the required number of read interfaces. With a fixed number of read interfaces in each read circuit, the number of read circuits in the data acquisition device 200 can be reduced, simplifying the circuit structure and lowering manufacturing costs.

[0055] Figure 3 A schematic diagram of a data acquisition apparatus according to another embodiment of the present disclosure is shown.

[0056] like Figure 3 As shown, the array substrate 310 includes multiple pixel circuit columns, and each pixel circuit column includes multiple pixel circuits.

[0057] In this embodiment, the pixel circuit includes a photoelectric converter PD and a transistor T. The first terminal of the photoelectric converter PD is electrically connected to a reference power supply Vref, and the second terminal of the photoelectric converter PD is electrically connected to the first electrode of the transistor T. The control electrode of the transistor T is electrically connected to a control interface G, and the second electrode of the transistor T is electrically connected to a readout interface RF. The photoelectric converter PD can be a photodiode, and the transistor T can be an N-type thin-film transistor (TFT).

[0058] In this embodiment of the disclosure, the photoelectric converter PD is configured to convert an optical signal into a data signal and transmit the data signal to a transistor T. The transistor is configured to send the data signal to a readout circuit via a readout interface RF under the control of a control signal.

[0059] For example, when the photoelectric converter PD is illuminated by an external light signal, it can convert the received light signal into a corresponding data signal and transmit the data signal to the transistor T. The control electrode of the transistor T continuously receives control signals from the control interface G. When the control signal is high, the transistor T is turned on, and the data signal is written to the read interface RF through the transistor T.

[0060] In this embodiment, a total of 2M control interfaces G1~G2M are provided. Control interfaces G1~G2M are used to output control signals. Each pixel circuit row includes two pixel circuit sub-rows, and the M pixel circuit rows include 2M pixel circuit sub-rows. The (2M-1)th pixel circuit sub-row represents the pixel circuit located in the odd-numbered column of the Mth pixel circuit row. The 2Mth pixel circuit sub-row represents the pixel circuit located in the even-numbered column of the Mth pixel circuit row.

[0061] In this embodiment of the disclosure, the 2M-1th pixel circuit sub-row is electrically connected to the control interface G2M-1 via the first control trace LC1. The 2Mth pixel circuit sub-row is electrically connected to the control interface 2M via the second control trace LC2.

[0062] For example, the first pixel circuit sub-row can be electrically connected to the control interface G1 through the first control line LC1, the second pixel circuit sub-row can be electrically connected to the control interface G2 through the second control line LC2, the third pixel circuit sub-row can be electrically connected to the control interface G3 through the first control line LC1, and so on. The 2M-1 pixel circuit sub-row can be electrically connected to the control interface G2M-1 through the first control line LC1, and the 2M pixel circuit sub-row can be electrically connected to the control interface G2M through the second control line LC2.

[0063] In this embodiment of the disclosure, the control interface G can send control signals to the transistors T in the electrically connected pixel circuit sub-rows via the first control line LC1 or the second control line LC2.

[0064] For example, control interface G1 can send a control signal to the control electrode of transistor T in the first pixel circuit sub-row through the first control line LC1, control interface G2 can send a control signal to the control electrode of transistor T in the second pixel circuit sub-row through the second control line LC2, and so on. Control interface G2M-1 can send a control signal to the control electrode of transistor T in the 2M-1 pixel circuit sub-row through the first control line LC1, and control interface G2M can send a control signal to the control electrode of transistor T in the 2M pixel circuit sub-row through the second control line LC2.

[0065] Combination Figure 2 and Figure 3 The reading process of the reading circuit 230 is illustrated schematically.

[0066] In this embodiment of the disclosure, the pixel circuit array includes M pixel circuits. The control circuit 220 is configured to send a control signal to the m-th pixel circuit Pixel among the M pixel circuits, where 1 ≤ m < M. The readout circuit 230 is configured to read the data signal of the m-th pixel circuit Pixel among the M pixel circuits when the control signal received by the m-th pixel circuit Pixel is at a first level. Specifically, when the readout circuit 230 reads the data signal of the m-th pixel circuit Pixel, the control circuit 220 provides a control signal with a first level to the (m+1)-th pixel circuit Pixel. The first level can be a high level.

[0067] During data acquisition, control circuit 220 sends high-level control signals to the pixel circuit sub-rows via control interfaces G1~G2M. For example, control circuit 220 sends a high-level control signal to the first pixel circuit sub-row via control interface G1, and readout circuit 230 acquires the data signal of the first pixel circuit sub-row. While readout circuit 230 is acquiring the data signal of the first pixel circuit sub-row, control circuit 220 can send an analog front-end (AFE) signal to the second pixel circuit sub-row via control interface G2 to perform analog control on the second pixel circuit sub-row. After readout circuit 230 completes the data signal acquisition of the first pixel circuit sub-row, since the second pixel circuit sub-row has already undergone analog control, readout circuit 230 does not need to wait for the signal establishment process of the second pixel circuit sub-row and can immediately switch to acquiring the data signal of the second pixel circuit sub-row.

[0068] In this embodiment of the disclosure, when the reading circuit 230 acquires the data signal of the current pixel circuit sub-row, the control circuit 220 can send an AFE signal to the next pixel circuit sub-row to enable the next pixel circuit sub-row to be turned on in advance, eliminating the extra waiting time when switching between pixel circuit sub-rows and improving the acquisition efficiency and display frame rate of line-by-line scanning.

[0069] Figure 4 A signal timing diagram of a data acquisition apparatus according to an embodiment of the present disclosure is shown. Figure 4 The timing waveforms of each control interface G1~G2M for each time period are shown.

[0070] The following is based on Figure 3 Taking the structure of the data acquisition device shown as an example, combined with... Figure 4 The signal timing diagram shown illustrates the operation of the data acquisition device 300 provided in this embodiment of the present disclosure. The data acquisition device 300 includes 2M time periods.

[0071] During the first time period Z1, the control signal output by control interface G1 is at a high level, while the control signals output by control interfaces G2~G2M are at a low level.

[0072] The high-level control signal output by the control interface G1 is provided to the N transistors T in the first pixel circuit sub-row through the first control line LC1. The N transistors T in the first pixel circuit sub-row are turned on, and the transistors T in the other pixel circuit sub-rows are turned off. The data signal is written to the read interfaces RF1~RFN respectively through the N transistors T in the first pixel circuit sub-row.

[0073] During the second time period Z2, the control signal output by control interface G1 is low, the control signal output by control interface G2 is high, and the control signals output by control interfaces G3~G2M are low.

[0074] The high-level control signal output from the control interface G1 is provided to N transistors T in the second pixel circuit sub-row through the first second control line LC2. The N transistors T in the second pixel circuit sub-row are turned on, and the transistors T in the other pixel circuit sub-rows are turned off. The data signal is written to the read interfaces RF1~RFN respectively through the N transistors T in the second pixel circuit sub-row.

[0075] During the third time period Z3, the control signals output by control interfaces G1~G2 are at a low level, the control signals output by control interface G3 are at a high level, and the control signals output by control interfaces G4~G2M are at a low level.

[0076] The high-level control signal output from the control interface G3 is provided to N transistors T in the third pixel circuit sub-row via the second first control line LC1. The N transistors T in the third pixel circuit sub-row are turned on, and the transistors T in the other pixel circuit sub-rows are turned off. The data signal is written to the read interface RF1~RFN respectively via the N transistors T in the third pixel circuit sub-row. This process is repeated to sequentially collect the data signals of the pixel circuit sub-rows until the 2M time period Z2M.

[0077] During the 2M period Z2M, the control signals output by control interfaces G1~G2M-1 are at a low level, while the control signals output by control interface G2M are at a high level.

[0078] The high-level control signal output from the control interface G2M is provided to N transistors T in the 2Mth pixel circuit sub-row via the Mth second control line LC2. The N transistors T in the 2Mth pixel circuit sub-row are turned on, while the transistors T in the remaining pixel circuit sub-rows are turned off. The data signal is then written to the read interfaces RF1~RFN via the N transistors T in the 2Mth pixel circuit sub-row. This completes the data signal acquisition.

[0079] In this embodiment, 2M control signals are used, and by setting the signal timing of the 2M control signals, data signal acquisition of the pixel circuit row can be achieved without additional hardware structure, which can simplify the circuit structure and reduce manufacturing costs.

[0080] In this embodiment of the disclosure, the readout circuit is further configured to: read data from the pixel circuit (Pixel) to obtain a noise signal when the control signal is determined to be at a second level; and read data from the pixel circuit (Pixel) to obtain a mixed signal when the control signal is determined to be at a first level. A data signal is determined based on the difference between the mixed signal and the noise signal. The second level can be a low level.

[0081] For example, before the first time period Z1, the control signal output by the control interface G1 is at a low level.

[0082] The low-level control signal output from control interface G1 is provided to N transistors T in the first pixel circuit sub-row via the first control line LC1, turning off the N transistors T in the first pixel circuit sub-row. In this case, the readout circuit ROIC acquires the noise signal of the N pixel circuits in the first pixel circuit sub-row through readout interfaces RF1~RFN.

[0083] During the first time period Z1, the control signal output by control interface G1 is high. This high-level control signal from control interface G1 is provided to the N transistors T in the first pixel circuit sub-row via the first control trace LC1, turning on the N transistors T in the first pixel circuit sub-row. In this state, the mixed signal generated by the N photoelectric converters in the first pixel circuit sub-row is written to the read interfaces RF1~RFN respectively via the N transistors T in the first pixel circuit sub-row. The read circuit ROIC determines the data signal based on the difference between the acquired mixed signal and the noise signal.

[0084] In this embodiment of the disclosure, the read circuit ROIC determines the data signal based on the difference between the mixed signal and the noise signal, which can effectively eliminate noise interference that may be generated by the read circuit ROIC during the reading process and improve the accuracy of the data signal.

[0085] Figure 5 A schematic diagram of the structure of an array substrate according to an embodiment of the present disclosure is shown.

[0086] like Figure 5 As shown, the array substrate 510 is electrically connected to six readout circuits ROIC1~ROIC6 and eight control sub-circuits GIC1~GIC8.

[0087] In this embodiment of the disclosure, the resolution of the array substrate 510 may be, for example, 3072*2048, indicating that the array substrate 510 contains a total of 3072 pixel circuit columns and 2048 pixel circuit rows.

[0088] In this embodiment, six readout circuits ROIC1 to ROIC6, each with 256 readout interfaces, are arranged around the array substrate 510. Each readout circuit is connected to a pad on the array substrate 510 via a chip-on-film (COF) flexible package. Eight control sub-circuits GIC1 to GIC8, each with 512 control interfaces, are also arranged around the array substrate 510. Each control sub-circuit is connected to a pad on the array substrate 510 via a COF. Since one readout interface RF can be electrically connected to two pixel circuit columns, the number of readout interfaces RF is halved. Therefore, only six readout circuits ROIC1 to ROIC6 with 256 control interfaces are needed to complete the acquisition of all 3072 columns of data signals.

[0089] At the same time, since each pixel circuit row needs to be electrically connected to two control traces, and each control trace needs to be connected to a control interface, eight control sub-circuits with a control interface count of 512 are required to drive each pixel circuit row.

[0090] Figure 6 A schematic diagram showing the connection relationship of the drive circuit according to an embodiment of the present disclosure is provided.

[0091] like Figure 6 As shown, the data acquisition device 600 includes an array substrate 610, a control circuit 620, multiple reading circuits 630, a main control drive circuit 640, a first drive circuit 650, and a second drive circuit 660.

[0092] In this embodiment, the array substrate 610, control circuit 620, multiple read circuits 630 and main control drive circuit 640 are similar in structure to the array substrate 110, control circuit 120, multiple read circuits 130 and main control drive circuit 140 described above, and will not be repeated for the sake of brevity.

[0093] In this embodiment, the first driving circuit 650 includes N transmission interfaces, and the first driving circuit is electrically connected to multiple reading circuits through the N transmission interfaces. The multiple reading circuits 130 include reading circuits ROIC1~ROICQ, each reading circuit including K reading interfaces, and Q reading circuits are electrically connected to the N transmission interfaces via K×Q reading interfaces, where K and Q are positive integers, and K×Q=N.

[0094] In this embodiment, the data acquisition device 600 includes a first driving circuit 650, which serves as an intermediate connection between multiple reading circuits and the main control driving circuit, for collecting and transmitting data signals. The main control driving circuit 640 includes D data interfaces, and the main control driving circuit 640 is electrically connected to the first driving circuit 650 via Q of the D data interfaces. D is a positive integer, and D ≥ Q.

[0095] For example, the array substrate 610 has a horizontal resolution of 3072 columns. The multiple readout circuits comprise six independent readout circuits, denoted as ROIC1, ROIC2, ROIC3, ROIC4, ROIC5, and ROIC6, where Q equals 6. Each readout circuit has 256 readout channels and corresponding 256 readout interfaces RF, where K equals 256. Therefore, the six readout circuits provide a total of 1536 readout interfaces RF.

[0096] The first driving circuit 650 has 1536 transmission interfaces, where N equals 1536. These 1536 transmission interfaces are electrically connected one-to-one with the 1536 read interfaces of the six read circuits. For example, the first to 256th transmission interfaces of the first driving circuit 650 can be electrically connected to the 256 read interfaces of read circuit ROIC1; the 257th to 512th transmission interfaces of the first driving circuit 650 can be electrically connected to the 256 read interfaces of read circuit ROIC2; and so on, the 1281st to 1536th transmission interfaces of the first driving circuit 650 can be electrically connected to the 256 read interfaces of read circuit ROIC6. The first driving circuit 650 receives data signals output by read circuits ROIC1 to ROIC6 through these 1536 transmission interfaces.

[0097] The main control drive circuit 640, for example, has six data interfaces, i.e., D equals 8. Of these eight data interfaces, six are electrically connected to the first drive circuit 650. These six data interfaces are used to receive data signals from six read circuits ROIC, respectively, through the first drive circuit 650. Specifically, one data interface receives a data signal from one read circuit ROIC.

[0098] In this embodiment of the disclosure, the second driving circuit 660 is electrically connected to the control circuit 620 and the main control driving circuit 640, and is configured to generate a control signal based on the timing signal from the main control driving circuit 640, and send the control signal to the control circuit 620.

[0099] In this embodiment, the second driving circuit 660 is electrically connected to the main control driving circuit 640 and the control sub-circuits GIC1~GIC2P. The second driving circuit 660 receives timing signals from the main control driving circuit 640 and converts the timing signals into control signals, which are then sequentially sent to the control sub-circuits GIC1~GIC2P.

[0100] In this embodiment of the disclosure, when the size of the array substrate 610 changes, only the number of transmission interfaces of the first driving circuit 650 and its connection method with the reading circuit ROIC, as well as the connection method between the second driving circuit 660 and the control circuit 620, need to be adjusted. The data interface configuration and internal processing logic of the main control driving circuit 640 can be adapted to the panel requirements of different resolutions without modification, avoiding the need to redesign and replace the main control chip due to changes in panel specifications, and simplifying the design process of panel product lines of different sizes.

[0101] Figure 7 A schematic diagram of a data acquisition apparatus according to another embodiment of the present disclosure is shown.

[0102] like Figure 7As shown, the data acquisition device 700 includes an array substrate 710, a control circuit 720, multiple reading circuits 730, a main control drive circuit 740, and a switching circuit 770.

[0103] In this embodiment, the multiple read circuits 730 and the main control drive circuit 740 are similar in structure to the read circuit 130 and the main control drive circuit 140 described above, and will not be repeated for the sake of brevity.

[0104] In this embodiment, the control circuit 220 includes multiple control sub-circuits GIC, and each control sub-circuit GIC includes multiple control interfaces G. The control interfaces G are electrically connected to a first control trace LC1 and a second control trace LC2. Specifically, the first control trace LC1 is electrically connected to the (2n-1)th pixel circuit in the same pixel circuit row, and the second control trace LC2 is electrically connected to the 2nth pixel circuit in the same pixel circuit row.

[0105] For example, a first control trace LC1 can be electrically connected to multiple pixel circuits located in odd-numbered columns of a pixel circuit row, and to a control interface G in a control sub-circuit GIC. A second control trace LC2 can be electrically connected to multiple pixel circuits located in even-numbered columns of the same pixel circuit row, and to the same control interface G in the control sub-circuit GIC.

[0106] In this embodiment, the first control line LC1 can provide the control signal sent by the control interface G in the control sub-circuit GIC to the (2n-1)th pixel circuit in the pixel circuit row, and the second control line LC2 can provide the control signal sent by the same control interface G in the control sub-circuit GIC to the 2nth pixel circuit in the pixel circuit row. Since the first control line LC1 is only electrically connected to the pixel circuits (1st, 3rd, ..., 2n-1st, ..., 2N-1st) in the odd-numbered columns of each pixel circuit row, and the second control line LC2 is only electrically connected to the pixel circuits (2nd, 4th, ..., 2nth, ..., 2Nth) in the even-numbered columns of each pixel circuit row, the control circuit 720 can independently select the pixel circuits located in the odd-numbered columns and the pixel circuits located in the even-numbered columns.

[0107] For example, a pixel circuit row is electrically connected to a first control line LC1 and a second control line LC2. The first control line LC1 can provide a first-level control signal sent from a control interface G in a control sub-circuit GIC to multiple pixel circuits (Pixels) located in odd-numbered columns of that pixel circuit row, causing these pixel circuits to output multiple data signals to multiple readout circuits 730. The second control line LC2 can provide a first-level control signal sent from the same control interface G in the same control sub-circuit GIC to multiple pixel circuits (Pixels) located in even-numbered columns of that pixel circuit row, causing these pixel circuits to output multiple data signals to multiple readout circuits 730.

[0108] The data acquisition device 700 in this embodiment utilizes a first control line LC1 and a second control line LC2 to control the output data signals of pixel circuits in odd-numbered columns and even-numbered columns in M ​​pixel circuit rows. This allows multiple readout circuits 730 to read the data signals of pixel circuits in odd-numbered columns and even-numbered columns through a single readout interface RF, thereby reducing the required number of readout interfaces. With a fixed number of readout interfaces in each readout circuit, the number of readout circuits in the data acquisition device 200 can be reduced, simplifying the circuit structure and lowering manufacturing costs.

[0109] Furthermore, the data acquisition device 700 in this embodiment can simultaneously control the first control line LC1 and the second control line LC2 using a single control interface G, thereby reducing the requirement for the control interface G. Given a fixed number of control interfaces G included in each control sub-circuit GIC, the number of control sub-circuits GIC in the data acquisition device 700 can be reduced, simplifying the circuit structure and lowering manufacturing costs.

[0110] In this embodiment, the switching circuit 770 is electrically connected to the control interface G, the first control line LC1, the second control line LC2, the first signal terminal SW1, and the second signal terminal SW2. The number of switching circuits 770 is the same as the number of control interfaces G included in the control circuit 720. For example, a pixel circuit row can be electrically connected to the switching circuit 770 via the first control line LC1, and also via the second control line LC2. Each switching circuit 770 is electrically connected to one control interface G, and different switching circuits 770 are connected to different control interfaces G.

[0111] In this embodiment of the disclosure, the switching circuit 770 is configured to control the control interface G to connect with the first control line LC1 or the control interface G to connect with the second control line LC2 under the control of the first signal SW1 from the first signal terminal SW1 and the second signal SW2 from the second signal terminal SW2.

[0112] For example, a pixel circuit row is electrically connected to a first control line LC1 and a second control line LC2. The first control line LC1 and the second control line LC2 are electrically connected to the same control interface G via a switching circuit 770. When the first signal SW1 from the first signal terminal SW1 is high, the switching circuit 770 can control the control interface G to be connected to the first control line LC1. When the control interface G is connected to the first control line LC1, the first control line LC1 can provide the first-level control signal sent by the control interface G to multiple pixel circuits located in odd-numbered columns of the pixel circuit row, causing these multiple pixel circuits to output multiple data signals to multiple readout circuits 730. When the second signal SW2 from the second signal terminal SW2 is high, the switching circuit 770 can control the same control interface G to be connected to the second control line LC2. When the control interface G is connected to the second control line LC2, the second control line LC2 can provide the first-level control signal sent by the control interface G to multiple pixel circuits located in even-numbered columns of the pixel circuit row. This causes the multiple pixel circuits located in even-numbered columns of the pixel circuit row to output multiple data signals to multiple readout circuits 730... and so on, continuing to acquire data signals from alternating odd-numbered and even-numbered columns of the pixel circuit row until the data signals of the last pixel circuit row have been acquired. Note that the first signal SW1 and the second signal SW2 are not both high at the same time.

[0113] In this embodiment, the switching circuit 770 can be selected by the first signal SW1 and the second signal SW2. A single control interface G can simultaneously control the first control line LC1 and the second control line LC2, reducing the need for the control interface G. With a fixed number of control interfaces G included in each control sub-circuit GIC, the number of control sub-circuits GIC in the data acquisition device 700 can be reduced, simplifying the circuit structure and lowering manufacturing costs.

[0114] Figure 8 A schematic diagram of a data acquisition apparatus according to another embodiment of the present disclosure is shown.

[0115] like Figure 8 As shown, the array substrate 810 includes multiple pixel circuit columns, and each pixel circuit column includes multiple pixel circuits.

[0116] In this embodiment, the pixel circuit includes a photoelectric converter PD and a transistor T. The first terminal of the photoelectric converter PD is electrically connected to a reference power supply Vref, and the second terminal of the photoelectric converter PD is electrically connected to the first terminal of the transistor T. The control terminal of the transistor T is electrically connected to a control interface G, and the second terminal of the transistor T is electrically connected to a readout interface RF. The photoelectric converter PD can be a photodiode, and the transistor T can be an N-type TFT.

[0117] In this embodiment of the disclosure, the photoelectric converter PD is configured to convert an optical signal into a data signal and transmit the data signal to a transistor T. The transistor is configured to send the data signal to a readout circuit via a readout interface RF under the control of a control signal.

[0118] For example, when the photoelectric converter PD is illuminated by an external light signal, it can convert the received light signal into a corresponding data signal and transmit the data signal to the transistor T. The control electrode of the transistor T continuously receives control signals from the control interface G. When the control signal is high, the transistor T is turned on, and the data signal is written to the read interface RF through the transistor T.

[0119] In this embodiment, a total of M control interfaces G1~GM are provided. These interfaces are used to output control signals. Each pixel circuit row includes two pixel circuit sub-rows, and the M pixel circuit rows comprise 2M pixel circuit sub-rows. The (2M-1)th pixel circuit sub-row represents the pixel circuit located in the odd-numbered column of the Mth pixel circuit row. The 2Mth pixel circuit sub-row represents the pixel circuit located in the even-numbered column of the Mth pixel circuit row.

[0120] In this embodiment of the disclosure, the (2M-1)th pixel circuit sub-row is electrically connected to the control interface G2M via the first control trace LC1. The 2Mth pixel circuit sub-row is electrically connected to the control interface 2M via the second control trace LC2.

[0121] For example, the first pixel circuit sub-row can be electrically connected to the control interface G1 through the first control line LC1, the second pixel circuit sub-row can be electrically connected to the control interface G1 through the second control line LC2, the third pixel circuit sub-row can be electrically connected to the control interface G2 through the first control line LC1, the fourth pixel circuit sub-row can be electrically connected to the control interface G2 through the second control line LC2, and so on. The 2M-1 pixel circuit sub-row can be electrically connected to the control interface GM through the first control line LC1, and the 2M pixel circuit sub-row can be electrically connected to the control interface GM through the second control line LC2.

[0122] In this embodiment of the disclosure, the control interface G can send control signals to the transistors T in the electrically connected pixel circuit sub-rows via the first control line LC1 and the second control line LC2.

[0123] For example, control interface G1 can send a control signal to the control electrode of transistor T in the first pixel circuit sub-row through the first control line LC1, and control interface G1 can also send a control signal to the control electrode of transistor T in the second pixel circuit sub-row through the second control line LC2... control interface GM can send a control signal to the control electrode of transistor T in the 2M-1 pixel circuit sub-row through the first control line LC1, and control interface GM can also send a control signal to the control electrode of transistor T in the 2M pixel circuit sub-row through the second control line LC2.

[0124] Combination Figure 7 and Figure 8 The reading process of the reading circuit 730 is illustrated schematically.

[0125] In this embodiment of the disclosure, the pixel circuit array includes M pixel circuits. The control circuit 720 is configured to send a control signal to the m-th pixel circuit Pixel among the M pixel circuits, where 1 ≤ m < M. The read circuit 730 is configured to read the data signal of the m-th pixel circuit Pixel among the M pixel circuits when the control signal received by the m-th pixel circuit Pixel is at a first level. Specifically, when the read circuit 730 reads the data signal of the m-th pixel circuit Pixel, the control circuit 720 provides a control signal with a first level to the (m+1)-th pixel circuit Pixel. The first level can be a high level.

[0126] During data acquisition, the control circuit 720 sends high-level control signals to the pixel circuit sub-rows via control interfaces G1~GM. For example, the control circuit 720 sends a high-level control signal to the first pixel circuit sub-row via control interface G1, and the reading circuit 230 acquires the data signal of the first pixel circuit sub-row. After the reading circuit 230 has acquired the data signal of the first pixel circuit sub-row, the control circuit 720 sends a high-level control signal to the second pixel circuit sub-row via control interface G1, and the reading circuit 230 acquires the data signal of the second pixel circuit sub-row.

[0127] While the readout circuit 730 is acquiring the data signal of the second pixel circuit sub-row, the control circuit 720 can send AFE signals to the third and fourth pixel circuit sub-rows via the control interface G2 to perform analog control on the third and fourth pixel circuit sub-rows. After the readout circuit 730 completes the acquisition of the data signal of the second pixel circuit sub-row, since the third pixel circuit sub-row has already undergone analog control, the readout circuit 730 does not need to wait for the signal establishment process of the third pixel circuit sub-row and can immediately switch to acquiring its data signal. Similarly, after the readout circuit 730 completes the acquisition of the data signal of the third pixel circuit sub-row, since the fourth pixel circuit sub-row has already undergone analog control, the readout circuit 730 does not need to wait for the signal establishment process of the fourth pixel circuit sub-row and can immediately switch to acquiring its data signal.

[0128] In this embodiment of the present disclosure, when the reading circuit 730 acquires the data signal of the last pixel circuit sub-row in the current pixel circuit row, the control circuit 720 can send an AFE signal to the next pixel circuit row to enable the next pixel circuit row to be turned on in advance, thereby eliminating the extra waiting time when switching between pixel circuit rows and improving the acquisition efficiency and display frame rate of line-by-line scanning.

[0129] Figure 9 A signal timing diagram of a data acquisition apparatus according to another embodiment of the present disclosure is shown. Figure 9 The timing waveforms of the first and second signal terminals for each time period are shown.

[0130] The following is based on Figure 8 Taking the structure of the data acquisition device shown as an example, combined with... Figure 9 The signal timing diagram shown illustrates the operation of the data acquisition device 800 provided in this embodiment of the present disclosure. The data acquisition device 800 includes 2M time periods.

[0131] During the first time period Z1, the first signal output by the first signal terminal SW1 is at a high level, and the second signal output by the second signal terminal SW2 is at a low level.

[0132] Under the control of the high-level first signal SW1 output from the first signal terminal SW1, the first switching circuit 870 connects the control interface G1 and the first control line LC1. The control signal output from the control interface G1 is provided to the N transistors in the first pixel circuit sub-row through the first control line LC1. The N transistors in the first pixel circuit sub-row are turned on, and the transistors T in the other pixel circuit sub-rows are turned off. The data signal is written to the read interfaces RF1~RFN respectively through the N transistors T in the first pixel circuit sub-row.

[0133] During the second time period Z2, the first signal output by the first signal terminal SW1 is at a low level, and the second signal output by the second signal terminal SW2 is at a high level.

[0134] Under the control of the high-level second signal SW2 output from the second signal terminal SW2, the first switching circuit 870 connects the control interface G1 and the first second control line LC2. The control signal output from the control interface G1 is provided to the N transistors in the second pixel circuit sub-row through the first second control line LC2. The N transistors in the second pixel circuit sub-row are turned on, and the transistors T in the other pixel circuit sub-rows are turned off. The data signal is written to the read interfaces RF1~RFN respectively through the N transistors T in the second pixel circuit sub-row.

[0135] During the third time period Z3, the first signal output by the first signal terminal SW1 is at a high level, and the second signal output by the second signal terminal SW2 is at a low level.

[0136] Under the control of the high-level first signal SW1 output from the first signal terminal SW1, the second switching circuit 870 connects the control interface G2 and the second first control line LC1. The control signal output from the control interface G2 is provided to the N transistors in the third pixel circuit sub-row through the second first control line LC1. The N transistors in the third pixel circuit sub-row are turned on, and the transistors T in the other pixel circuit sub-rows are turned off. The data signal is written to the read interfaces RF1~RFN through the N transistors T in the third pixel circuit sub-row, and so on, sequentially acquiring the data signals of the pixel circuit sub-rows until the 2M time period Z2M.

[0137] During the 2M period Z2M, the first signal output by the first signal terminal SW1 is low level, and the second signal output by the second signal terminal SW2 is high level.

[0138] Under the control of the high-level second signal SW2 output from the second signal terminal SW2, the Mth switching circuit 870 connects the control interface GM and the Mth second control line LC2. The control signal output from the control interface GM is provided to the N transistors in the 2Mth pixel circuit sub-row through the Mth second control line LC2. The N transistors in the 2Mth pixel circuit sub-row are turned on, and the transistors T in the remaining pixel circuit sub-rows are turned off. The data signal is written to the read interfaces RF1~RFN respectively through the N transistors T in the 2Mth pixel circuit sub-row. This completes the data signal acquisition.

[0139] In this embodiment, the two columns of transistors T and photoelectric converter PD in the pixel circuit row are connected to the same readout interface RF, which can reduce the number of readout circuit ROICs and reduce manufacturing costs. Simultaneously, the first signal terminal SW1 and the second signal terminal SW2 control a control interface G to be electrically connected to two control traces LC. By controlling the connection between the control interface G and the two control traces LC through the first signal terminal SW1 and the second signal terminal SW2, the number of control interfaces G can be reduced without increasing the number of readout circuit ROICs, further reducing manufacturing costs.

[0140] Figure 10 A schematic diagram of the structure of an array substrate according to another embodiment of the present disclosure is shown.

[0141] like Figure 10 As shown, the array substrate 1010 is electrically connected to six readout circuits ROIC1~ROIC6 and four control sub-circuits GIC1~GIC4.

[0142] In this embodiment of the disclosure, the resolution of the array substrate 1010 may be, for example, 3072*2048, indicating that the array substrate 1010 contains a total of 3072 pixel circuit columns and 2048 pixel circuit rows.

[0143] In this embodiment, six readout circuits ROIC1 to ROIC6, each with 256 readout interfaces, are arranged around the array substrate 1010. Each readout circuit is connected to a pad on the array substrate 510 via a COF. Four control sub-circuits GIC1 to GIC4, each with 512 control interfaces, are also arranged around the array substrate 510. Each control sub-circuit is connected to a pad on the array substrate 510 via a COF. Since one readout interface RF can be electrically connected to two pixel circuit columns, the number of readout interfaces RF is halved. Therefore, only six readout circuits ROIC1 to ROIC6 with 256 readout interfaces are needed to complete the acquisition of all 3072 columns of data signals.

[0144] Meanwhile, since each pixel circuit row requires two control traces to be electrically connected, and each pair of control traces connects to one control interface, only four control sub-circuits with 512 control interfaces are needed to drive each pixel circuit row.

[0145] Figure 11 A schematic diagram showing the connection relationship of a drive circuit according to another embodiment of the present disclosure is shown.

[0146] like Figure 11As shown, the data acquisition device 1100 includes an array substrate 1110, a control circuit 1120, multiple reading circuits 1130, a main control drive circuit 1140, a first drive circuit 1150, and a second drive circuit 1160.

[0147] In this embodiment, the array substrate 1110, control circuit 1120, multiple read circuits 1130 and main control drive circuit 1140 are similar in structure to the array substrate 110, control circuit 120, multiple read circuits 130 and main control drive circuit 140 described above, and the first drive circuit 1150 is similar in structure to the first drive circuit 650 described above, and will not be described again for the sake of brevity.

[0148] In this embodiment of the disclosure, the second driving circuit 1160 is electrically connected to the control circuit 1120 and the main control driving circuit 1140, and is configured to generate a control signal based on the timing signal from the main control driving circuit 1140, and send the control signal to the control circuit 1120.

[0149] In this embodiment, the second driving circuit 660 is electrically connected to the main control driving circuit 640 and the control sub-circuits GIC1~GICP. The second driving circuit 660 receives timing signals from the main control driving circuit 640 and converts the timing signals into control signals, which are then sequentially sent to the control sub-circuits GIC1~GICP.

[0150] In this embodiment, when the size of the array substrate 1110 changes, only the number of transmission interfaces of the first driving circuit 1150 and its connection with the read circuit ROIC, as well as the connection between the second driving circuit 1160 and the control circuit 1130, need to be adjusted. The data interface configuration and internal processing logic of the main control driving circuit 1140 can be adapted to the panel requirements of different resolutions without modification, avoiding the need to redesign and replace the main control chip due to changes in panel specifications, and simplifying the design process of panel product lines of different sizes.

[0151] Figure 12 A schematic diagram of the main drive circuit according to an embodiment of the present disclosure is shown.

[0152] As shown in Figure 12, the main drive circuit 1240 includes a drive control sub-circuit 1241, a timing sub-circuit 1242, a transmission sub-circuit 1243, a data processing sub-circuit 1244, a power control sub-circuit 1245, and a storage sub-circuit 1246.

[0153] In this embodiment of the disclosure, the drive control sub-circuit 1241 is configured to generate a drive signal and send the drive signal to the read circuit. The drive signal is used to drive the read circuit to read data from the pixel circuit, and to generate a clock signal and send the clock signal to the control circuit. The clock signal is used to control the control circuit to generate a control signal that matches the drive signal.

[0154] In this embodiment, the drive control sub-circuit 1241 is a functional unit in the main drive circuit 1240 responsible for generating execution instructions. The drive control sub-circuit 1241 generates two different types of output signals according to internal timing requirements. The first is a drive signal sent to the readout circuit, which instructs the readout circuit to begin data acquisition from the pixel circuit. The second is a clock signal sent to the control circuit, which causes the control circuit to generate gating pulses according to a timing rhythm matching the drive signal. The drive control sub-circuit 1241 simultaneously transmits these two types of signals to the corresponding receiving devices via internal circuitry. During the acquisition of the entire frame image, the drive control sub-circuit 1241 continuously outputs the aforementioned signals. The drive signal and clock signal maintain a strict temporal correspondence, ensuring that the gating time of the pixel circuit is consistent with the data acquisition time of the readout circuit, thereby ensuring that the data signal of each pixel unit is acquired by the readout circuit at the correct time.

[0155] In this embodiment of the disclosure, the timing sub-circuit 1242 is configured to generate a reference clock signal and a multiplexed signal, and to synchronously reset the data acquisition device based on the reference clock signal and the multiplexed signal.

[0156] In this embodiment, the timing sub-circuit 1242 is a functional unit in the main drive circuit 1240 responsible for establishing a time reference. The timing sub-circuit 1242 internally generates two basic signals: a reference clock signal (125MHz, 100MHz, 200MHz, etc.) and a multiplexed signal. The reference clock signal provides a unified time reference for the entire data acquisition device, and all sub-circuits requiring timing operations use this signal as a time reference. The multiplexed signal is used to identify the switching timing between different data channels. The timing sub-circuit 1242 simultaneously sends the reference clock signal and the multiplexed signal to each circuit within the data acquisition device that needs to operate synchronously. When the device starts up or needs to restart, the timing sub-circuit 1242 uses these two signals to generate a reset command, returning the circuits that need to be reset to their initial state.

[0157] In this embodiment of the disclosure, the transmission sub-circuit 1243 is configured to control data transmission within the data acquisition device and data transmission between the data acquisition device and external devices.

[0158] In this embodiment, the transmission sub-circuit 1243 is a functional unit responsible for data transmission within the main drive circuit 1240. The transmission sub-circuit 1243 manages the data flow between circuits within the data acquisition device, transmitting data from the generation location to the processing location or storage location. It also manages data exchange between the data acquisition device and external devices, sending processed image data to external display devices or storage devices, and can receive instructions or parameters from external devices. During data transmission, the transmission sub-circuit 1243 arranges and buffers the data to be transmitted according to the requirements of the receiving end, ensuring continuous and stable data output. During data reception, the transmission sub-circuit 1243 buffers incoming data and forwards it to other circuits within the data acquisition device. The transmission sub-circuit 1243 can realize gigabit and 10-gigabit network data transmission.

[0159] In this embodiment of the disclosure, the data processing sub-circuit 1244 is configured to perform splicing processing on multiple data signals.

[0160] In this embodiment, the data processing sub-circuit 1244 is a functional unit responsible for signal processing within the main drive circuit 1240. The data processing sub-circuit 1244 receives multiple data signals from the transmission sub-circuit 1243, each corresponding to a pixel circuit in a different column on the array substrate. The data processing sub-circuit 1244 arranges these dispersed data signals sequentially according to the column numbering order of the array substrate, ensuring that the data in adjacent columns are correctly positioned, and ultimately combines the data from all columns into a complete two-dimensional data set. In scenarios requiring image reduction, the data processing sub-circuit 1244 can also perform image merging output using an image merging mode. For example, it can merge the data of multiple adjacent pixels into a single data value to reduce the total data volume. After completing the splicing or merging operation, the data processing sub-circuit 1244 transmits the processing result to the transmission sub-circuit 1243 or the storage sub-circuit 1246.

[0161] In this embodiment of the disclosure, the power control sub-circuit 1245 is configured to power the data acquisition device.

[0162] In this embodiment, the power control sub-circuit 1245 is a functional unit responsible for power supply in the main drive circuit 1240. The power control sub-circuit 1245 receives input voltage from an external power source, converts it into a stable operating voltage required by the data acquisition device, and continuously supplies power to the data acquisition device. The power control sub-circuit 1245 also supports low-power mode switching.

[0163] In this embodiment of the disclosure, the storage sub-circuit 1246 is configured to store a plurality of data signals.

[0164] In this embodiment, the storage sub-circuit 1246 is a functional unit responsible for data storage within the main drive circuit 1240. The storage sub-circuit 1246 is used to temporarily store data signals generated during the acquisition process. After the data is successfully processed or transmitted, the storage sub-circuit 1246 can release the corresponding storage space to receive subsequent new data. The storage sub-circuit 1246 can be a third-generation double-data-rate (DDR3) memory.

[0165] In this embodiment, the main drive circuit 1240 is also electrically connected to a host computer via an Ethernet transmission interface. The host computer sends commands (such as register configuration and acquisition mode settings) to the main drive circuit 1240 via the Ethernet transmission interface. The transmission sub-circuit 1243 inside the main drive circuit 1240 receives these commands from the host computer via the Ethernet transmission interface and engages in bidirectional communication with the host computer. The host computer can also receive acquisition data transmitted back from the main drive circuit 1240 via the Ethernet transmission interface.

[0166] Figure 13 A flow control diagram of the main drive circuit according to an embodiment of the present disclosure is shown.

[0167] like Figure 13 As shown, the data acquisition device 1300 includes an array substrate 1310 and a main control circuit 1340.

[0168] In this embodiment of the disclosure, the main control circuit 1340 includes a drive control sub-circuit 1341, a timing sub-circuit 1342, a transmission sub-circuit 1343, a data processing sub-circuit 1344, a power control sub-circuit 1345, and a storage sub-circuit 1346.

[0169] In this embodiment, the array substrate 1310 has a similar structure to the array substrate 110 described above. The drive control sub-circuit 1341, timing sub-circuit 1342, transmission sub-circuit 1343, data processing sub-circuit 1344, power control sub-circuit 1345, and storage sub-circuit 1346 have similar structures to the main drive circuit 1240 described above, which also includes the drive control sub-circuit 1241, timing sub-circuit 1242, transmission sub-circuit 1243, data processing sub-circuit 1244, power control sub-circuit 1245, and storage sub-circuit 1246. For simplicity, these details will not be repeated. In this embodiment, when the data acquisition device 1300 is started, the timing sub-circuit 1342 can first generate a reference clock signal and a reset signal to synchronously reset all circuits inside the data acquisition device 1300 to their initial state. The gate control subcircuit in the drive control subcircuit 1341 generates a selection pulse and sends it to the array substrate 1310 according to the processing mode of the data acquisition device 1300 and the reference clock signal provided by the timing subcircuit 1342, sequentially selecting the odd-numbered or even-numbered column pixel units of each pixel circuit row. Simultaneously with selection, the source control subcircuit in the drive control subcircuit 1341 sends a drive command to the readout circuit, causing the readout circuit to acquire the data signals of the pixel circuit.

[0170] For example, after the data signal is output from the array substrate 1310, it is digitized by the readout circuit and enters the data processing sub-circuit 1344 through the transmission sub-circuit 1343. The data processing sub-circuit 1344 arranges and splices the data signals from different columns according to the actual positions of each pixel circuit on the array substrate. For example, during the splicing process, all data signals from odd-numbered pixel circuits can be processed first, then all data signals from even-numbered pixel circuits can be processed, and finally the two can be alternately merged according to column number to form a complete image data. The spliced ​​image data can be temporarily stored in the storage sub-circuit 1346, while the transmission sub-circuit 1343 can send the image data to the display terminal or storage device through an external interface, completing the acquisition and output of one frame of image. Throughout the entire operation, the power control sub-circuit 1345 continuously provides a stable voltage supply to each circuit.

[0171] In this embodiment, the data acquisition device 1300 has two processing modes: a dual-control circuit (dual-gate) mode and a multiplexing (MUX) mode. The dual-gate mode can be referred to the preceding text. Figure 3 Description of array substrate 310. MUX mode can be found in the previous text. Figure 8 Description of the array substrate 810.

[0172] Combination Figure 3 A schematic illustration of the dual-GATE mode is provided.

[0173] For the dual-GATE mode, the array substrate 310 employs a row-doubling control method, meaning it controls twice the number of rows required for the target resolution. Specifically, each pixel circuit row is divided into two pixel circuit row sub-rows, each connected to an independent control interface. These two pixel circuit row sub-rows alternately control the selection of odd and even columns. The array substrate 310 achieves the goal of halving the number of read interfaces by increasing the number of control interfaces.

[0174] In this embodiment, for example, the system needs to acquire an image with a resolution of 3072×2048. Each readout circuit contains 256 readout interfaces, and each control subcircuit contains 512 channels. Based on this low-cost dual-gate scheme, only 6 readout circuits need to be configured on the source side, while 8 gate drive circuits need to be configured on the gate side. After the system starts, the analog front-end parameters of the readout circuit are configured first, and odd-numbered column acquisition is performed. At the same time, a row enable signal (CPV), a row scan signal (STV), and an output enable signal (OE) are generated to control the control subcircuit to complete the data reading of the first pixel circuit sub-row. After the first pixel circuit sub-row is acquired, the readout circuit is configured to continue to perform analog front-end configuration and data acquisition for even-numbered columns. The row enable signal (CPV), the row scan signal (STV), and the output enable signal (OE) are generated again to control the control subcircuit to complete the data reading of the second pixel circuit sub-row. The data acquired in the two acquisitions are merged to form a complete image data of 3072 pixels per row. Since the odd and even column data are acquired in a time-division multiplexing manner, the system needs to integrate and stitch the data in an alternating odd and even order. This process is repeated line by line, from the 2nd to the 4096th sub-row, to complete the acquisition of all 2048 rows of image data. Although this scheme increases the number of control interfaces, the overall hardware cost is still significantly reduced because the cost of the control sub-circuit is much lower than that of the reading circuit. By doubling the number of rows and acquiring data line by line with odd and even numbers, the amount of reading circuitry used is effectively reduced, thus lowering manufacturing costs.

[0175] Combination Figure 8 The MUX pattern is illustrated.

[0176] For MUX mode, the array substrate 810 adopts a design architecture that controls odd and even columns separately. Column selection is achieved by inputting first signal SW1 and second signal SW2 through first signal terminal SW1 and second signal terminal SW2. Specifically, the SW1 signal controls the turn-on of the odd-numbered column transistors T, and the SW2 signal controls the turn-on of the even-numbered column transistors T. The array substrate 810 determines the currently active column group based on the high and low levels of these two signals, thereby realizing the multiplexing of the readout channel.

[0177] In this embodiment, for example, if the system needs to acquire images with a resolution of 3072×2048, each readout circuit contains 256 readout interfaces RF, and each control sub-circuit GIC contains 512 control interfaces G. Based on the MUX scheme, six readout circuits are configured on the source side, each connected to 256 pairs of columns (i.e., 512 columns), and four control sub-circuits GIC are configured on the gate side to meet the requirements. After the system starts, the analog front-end parameters of the readout circuit are first configured and odd-numbered column acquisition is performed. SW1 is pulled high and SW2 is pulled low simultaneously, generating a row enable signal CPV and a row scan signal STV to control the gate to jump normally. Then, the output enable signal OE is turned on to release the charge, completing the acquisition of odd-numbered column data. After the odd-numbered column acquisition is completed, the readout circuit is configured to continue to perform analog front-end configuration and data acquisition for even-numbered columns. SW2 is pulled high and SW1 is pulled low. At this time, the row enable signal CPV and the row scan signal STV remain unchanged. Only the output enable signal OE needs to be turned on to release the charge, completing the acquisition of even-numbered column data. This completes the acquisition of 3072 pixels per row. Since the odd and even column data are acquired in a time-division multiplexing manner, the system needs to integrate and stitch the data according to the alternating odd and even order to ensure the accuracy of the image data. This process is repeated for rows 2 through 2048. This solution achieves time-division multiplexing of odd and even columns through an internal MUX design without increasing the number of gate drive circuits, effectively reducing the amount of readout circuitry and lowering manufacturing costs.

[0178] Both of the aforementioned modes result in a decrease in frame rate because the readout circuit needs to perform twice the number of analog front-end control and data acquisition operations. To compensate for this deficiency, the data conversion rate can be increased by raising the acquisition clock frequency of the readout circuit and compressing the time overhead of the related double sampling. This can compensate for the frame rate loss caused by the two modes, ensuring that the system still has the imaging speed to meet the needs of practical applications while reducing costs.

[0179] Figure 14 A schematic diagram of the structure of a data acquisition device according to an embodiment of the present disclosure is shown.

[0180] like Figure 14 As shown, the data acquisition device 14 includes a data acquisition unit 1400 and a processor 1401. The data acquisition unit 1400 can be the data acquisition unit 100, data acquisition unit 200, data acquisition unit 600, data acquisition unit 700, data acquisition unit 1100 and data acquisition unit 1300 described above.

[0181] Figure 15 A flowchart illustrating a data acquisition method according to an embodiment of this disclosure is shown.

[0182] like Figure 15As shown, the data acquisition method of this embodiment includes steps S1510 to S1540.

[0183] In step S1510, the control circuit sends control signals to the 2N pixel circuit columns included in the array substrate.

[0184] In step S1520, the 2N pixel circuit columns generate data signals based on the control signals.

[0185] In step S1530, the reading interfaces of multiple reading circuits read the data signals of the (2n-1)th pixel circuit column and the data signals of the 2nth pixel circuit column.

[0186] In step S1540, the main control drive circuit acquires and splices multiple data signals to obtain image data displayed on the array substrate.

[0187] In this embodiment of the disclosure, operations S1510 to S1540 are similar to the operations performed by the data acquisition devices 100, 200, 600, 700, 1100 and 1300 described above, and will not be repeated here.

[0188] The block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, and combinations of blocks in the block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0189] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined and / or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0190] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A data acquisition device, comprising: The array substrate includes 2N pixel circuit columns, where N is a positive integer; A control circuit, electrically connected to the 2N pixel circuit columns, is configured to send control signals to the 2N pixel circuit columns; Multiple readout circuits, each including multiple readout interfaces, are electrically connected to the (2n-1)th and 2nth pixel circuit columns of the 2N pixel circuit columns. The readout circuits are configured to read data signals from the (2n-1)th and 2nth pixel circuit columns, wherein the data signals are output by the pixel circuit columns based on the control signal, and 1 ≤ n ≤ N. as well as The main control drive circuit is electrically connected to the multiple reading circuits and is used to collect and stitch together multiple data signals to obtain image data displayed on the array substrate.

2. The data acquisition device according to claim 1, wherein, The 2N pixel circuit columns include M pixel circuit rows, where M is a positive integer; the control circuit is electrically connected to the M pixel circuit rows through 2M control lines; The control trace is electrically connected to the (2n-1)th pixel circuit or the 2nth pixel circuit in the pixel circuit row.

3. The data acquisition device according to claim 2, wherein, The control circuit includes multiple control sub-circuits, and each control sub-circuit includes multiple control interfaces. The control interfaces are electrically connected to the first control trace and the second control trace. The first control trace is electrically connected to the (2n-1)th pixel circuit in the pixel circuit row, and the second control trace is electrically connected to the 2nth pixel circuit in the same pixel circuit row.

4. The data acquisition device according to claim 3 further includes: Multiple switching circuits are electrically connected to the control interface, the first control trace, the second control trace, the first signal terminal, and the second signal terminal. The switching circuit is configured to control the control interface to connect to the first control trace or the control interface to connect to the second control trace under the control of a first signal from the first signal terminal and a second signal from the second signal terminal. The number of switching circuits is the same as the number of control interfaces included in the control circuit.

5. The data acquisition device according to claim 2, wherein, The control circuit includes multiple control sub-circuits, and each control sub-circuit includes multiple control interfaces. The control interfaces are electrically connected to a first control trace or a second control trace. The first control trace is electrically connected to the (2n-1)th pixel circuit in the pixel circuit row, and the second control trace is electrically connected to the 2nth pixel circuit in the same pixel circuit row.

6. The data acquisition device according to claim 1, wherein, The pixel circuit array includes multiple pixel circuits, and the pixel circuits include photoelectric converters and transistors; The first terminal of the photoelectric converter is electrically connected to a reference power supply, and the second terminal of the photoelectric converter is electrically connected to the first electrode of the transistor. The control electrode of the transistor is electrically connected to the control circuit, and the second electrode of the transistor is electrically connected to the readout circuit.

7. The data acquisition device according to claim 6, wherein, The photoelectric converter is configured to convert an optical signal into a data signal and transmit the data signal to the transistor; The transistor is configured to send the data signal to the read circuit via the read interface under the control of the control signal.

8. The data acquisition device according to claim 1, further comprising: A first driving circuit includes N transmission interfaces, and the first driving circuit is electrically connected to the plurality of reading circuits through the N transmission interfaces; The plurality of reading circuits include Q reading circuits, each reading circuit includes K reading interfaces, and the Q reading circuits are electrically connected to the N transmission interfaces via K×Q reading interfaces, where K and Q are positive integers, and K×Q=N; The main control drive circuit includes D data interfaces. The main control drive circuit is electrically connected to the first drive circuit through Q of the D data interfaces, where D is a positive integer and D≥Q.

9. The data acquisition device according to claim 1, wherein, The pixel circuit column includes M pixel circuits; The control circuit is configured to send the control signal to the m-th pixel circuit among the M pixel circuits, where 1 ≤ m < M; The reading circuit is configured to read the data signal of the mth pixel circuit among the M pixel circuits when the control signal received by the mth pixel circuit is at a first level. Specifically, when the reading circuit reads the data signal of the m-th pixel circuit, the control circuit provides the control signal with a first level to the (m+1)-th pixel circuit.

10. The data acquisition device according to claim 1, wherein, The read circuit is also configured to: When the control signal is determined to be at the second level, data is read from the pixel circuits in the pixel circuit column to obtain the noise signal. When the control signal is determined to be at the first level, data is read from the pixel circuits in the pixel circuit column to obtain a mixed signal. as well as The data signal is determined based on the difference between the mixed signal and the noise signal.

11. The data acquisition device according to claim 1, further comprising: The second driving circuit, electrically connected to the control circuit and the main control driving circuit, is configured to generate the control signal based on the timing signal from the main control driving circuit, and send the control signal to the control circuit.

12. The data acquisition device according to claim 1, wherein, The main control drive circuit includes: The drive control sub-circuit is configured as follows: A driving signal is generated and sent to the readout circuit, the driving signal being used to drive the readout circuit to read data from the pixel circuit; and A clock signal is generated and sent to the control circuit. The clock signal is used to control the control circuit to generate a control signal that matches the drive signal.

13. The data acquisition device according to claim 1, wherein, The main control drive circuit includes: A timing sub-circuit is configured to generate a reference clock signal and a multiplexed signal, and to synchronously reset the data acquisition device based on the reference clock signal and the multiplexed signal. The transmission sub-circuit is configured to control data transmission within the data acquisition device and data transmission between the data acquisition device and external devices; The data processing sub-circuit is configured to splice multiple of the data signals. The power control sub-circuit is configured to supply power to the data acquisition device; and The storage sub-circuit is configured to store a plurality of the data signals.

14. A data acquisition device, comprising: The data acquisition device according to any one of claims 1-13; as well as The processor is configured to send instructions to the data acquisition device and receive the image data from the data acquisition device.

15. A data acquisition method, applied to the data acquisition device according to claims 1-13, comprising: The control circuit sends control signals to the 2N pixel circuit columns included in the array substrate; The 2N pixel circuit arrays generate data signals based on the control signals; The read interfaces of multiple read circuits read the data signal of the (2n-1)th pixel circuit column and the data signal of the 2nth pixel circuit column; as well as The main control drive circuit acquires and splices multiple data signals to obtain image data displayed on the array substrate.

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