A manufacturing method of an AC-DC power supply PCB via copper plating EMI shielding structure

Abstract

The application discloses a kind of production methods of AC-DC power supply PCB via copper EMI shielding structure. For the defects that the additional device is needed in the existing AC-DC power supply, the consistency of mass production is poor, the parallel resonance is easy to produce in the traditional uniform via shielding wall, and the secondary parasitic coupling is introduced, a single-point connection primary safety shielding copper deposition area is arranged at the gap between the two couplings, a non-uniform shielding via array is arranged along the edge thereof, and an integrated vertical conductive shielding wall is formed by a copper deposition process. The non-metallized slot hole of the shielding copper deposition area suppresses the parallel resonance, and the floating conductive layer in the inner layer of the PCB compensates the parasitic parameters through electric field coupling. The application does not need additional shielding devices, is compatible with standard PCB process, can efficiently block common-mode interference coupling path, eliminate resonance peak, has stable high-frequency shielding performance, low mass production cost, high consistency, and is suitable for various high-frequency switching AC-DC power supply products.

Description

Technical Field

[0001] This invention relates to the field of printed circuit board design technology, and in particular to a method for fabricating an AC-DC power supply PCB via copper plating EMI shielding structure. Background Technology

[0002] In AC-DC power supply products, due to the compact layout of the AC input circuit and high-frequency transformer, high-frequency switching noise is easily conducted through parasitic capacitance and magnetic field coupling, resulting in EMI exceeding the standard.

[0003] Currently, the main solutions for conducted interference coupling between AC input and transformer include: adding external metal shielding, manually mounting conductive copper foil, and adding common-mode chokes and other filtering components. All of these solutions have significant drawbacks: shielding and filtering components increase BOM costs and assembly time; manual copper foil mounting is cumbersome, has low yield, and poor consistency; and its suppression effect is limited at high frequencies (above MHz). In recent years, some solutions have proposed using grounding via arrays on the PCB to form a shielding wall to suppress the propagation of common-mode current and surface waves. However, existing via shielding wall technology still has the following shortcomings: via arrays are usually uniformly arranged, making it impossible to differentiate and optimize for interference intensity in different areas; parallel resonance may form between the shielding structure and the PCB inner ground plane, which may worsen EMI performance at certain frequencies; the introduction of the shielding structure may change the original parasitic parameter distribution, potentially introducing new coupling paths.

[0004] Therefore, there is an urgent need for an AC-DC power supply conduction interference shielding technology that requires no additional components, can be integrated through PCB manufacturing, and offers low cost and high consistency. Summary of the Invention

[0005] This invention aims to provide an EMI shielding solution that requires no additional components and is achieved through a standard PCB copper plating process. It effectively blocks common-mode conducted interference between the AC input area and the high-frequency transformer, while actively avoiding resonance risks and compensating for the negative impact of parasitic parameters, thus balancing shielding effectiveness, mass production cost, and circuit stability.

[0006] To achieve the above objectives, the technical solution adopted by the present invention includes the following steps: S1 Determine the interference frequency band: Based on the switching frequency and voltage change rate of the power switching device, determine the upper limit frequency of the common-mode interference band that needs to be suppressed; S2 Calculate shielding parameters: Based on the upper limit frequency of the common mode interference band and the dielectric constant of the PCB substrate, calculate the maximum allowable center distance of the shielding vias, so that the maximum allowable center distance is less than the preset fraction of the wavelength corresponding to the upper limit frequency of the common mode interference band, and set the actual center distance of the shielding vias to be no greater than the maximum allowable center distance. S3 Define the shielding area: During the PCB substrate layout design stage, a continuous shielding copper plating area is defined at the coupling gap between the AC input area and the high-frequency transformer layout area. The shielding copper plating area is connected to the primary safety ground through a single point. S4 Design Non-uniform Via Array: A shielded via array is arranged at the edge of the shielded copper plating area. The aperture and / or center distance of the shielded vias are non-uniformly distributed along the extension direction of the shielded copper plating area. The via density near the AC input area is greater than the via density away from the AC input area. The shielded vias penetrate the entire PCB substrate. S5 Integrated Copper Plating: Through the copper plating process, the copper layer of the shielded copper plating area and the copper layer of the hole wall of the shielded via are synchronously and electrically integrated into a single process. S6 Resonance Suppression: A non-metallized slot is formed on the shielded copper plating area. The length direction of the non-metallized slot is perpendicular to the expected flow direction of the high-frequency common-mode current, so as to suppress the parallel resonance formed between the shielded copper plating area and the PCB inner layer ground plane. S7 Parasitic Capacitance Compensation: A floating conductive layer is provided on the inner layer of the PCB substrate between the shielded copper plating area and the high-frequency transformer. The floating conductive layer has no direct electrical connection with the shielded copper plating area and the high-frequency transformer. The equivalent parasitic capacitance between the shielded copper plating area and the high-frequency transformer is adjusted by electric field coupling. The floating conductive layer is configured to utilize rather than eliminate the parasitic capacitance to compensate for the additional parasitic parameters introduced by setting the shielded copper plating area.

[0007] Furthermore, the width of the shielded copper plating area is not less than a preset multiple of the minimum safe electrical distance between the AC input area and the high-frequency transformer layout area.

[0008] Furthermore, in the non-uniform via array, the aperture and / or center distance of the shielding vias exhibit a continuous gradual change from the AC input side to the side further away; the single-point grounding point of the shielding copper plating area is located at its geometric center and is connected to the primary safety ground through a grounding via with a size larger than the shielding via.

[0009] Furthermore, the non-metallized slots are configured in multiple ways and are arranged at equal intervals along the extension direction of the shielded copper plating area. The spacing between adjacent slots and the length of the slots themselves are both set according to the center frequency of the common-mode interference band.

[0010] Furthermore, the shielded copper plating area can adopt a grid copper foil structure, with the grid period being less than a preset fraction of the wavelength corresponding to the upper limit frequency of common-mode interference.

[0011] Furthermore, the power switching devices adapted to this method have a switching frequency of not less than 100kHz and a voltage change rate of not less than 50V / ns.

[0012] Another aspect of the present invention provides an AC-DC power supply PCB via copper plating EMI shielding structure, applicable to AC-DC power supplies using power switching devices as main switching transistors, comprising: PCB substrate; The shielded copper plating area is located on the surface of the PCB substrate at the coupling gap between the AC input area and the high-frequency transformer layout area. It is a continuous conductive copper layer and is connected to the primary safety ground through a single point. The shielded via array is arranged at the edge of the shielded copper plating area. The shielded vias penetrate the entire PCB substrate, and the copper layer of the via wall is electrically connected to the copper layer of the shielded copper plating area, together forming a vertical conductive shielding wall.

[0013] Among them, the via density near the AC input area in the shielded via array is greater than the via density far from the AC input area; a floating conductive layer is set in the inner layer of the PCB substrate between the shielded copper plating area and the high-frequency transformer. The floating conductive layer has no direct electrical connection with either of them, and the equivalent parasitic capacitance is adjusted by electric field coupling; the shielded copper plating area and the shielded via array together form a Faraday cage isolation barrier to block the conducted interference coupling path between the AC side and the high-frequency transformer.

[0014] Furthermore, the width of the shielded copper plating area is not less than the width of the coupling gap, completely covering the coupling gap; the shielded via array is arranged in a straight line or arc shape, and the aperture and center distance are preset values.

[0015] Furthermore, the shielded copper plating area has at least one non-metallized slot, the length of which is perpendicular to the expected flow direction of the common-mode current, and the length is 1 / 8 to 1 / 4 of the wavelength corresponding to the center frequency of the common-mode interference band.

[0016] Furthermore, the diameter of the shielding via is 0.2mm~0.5mm, the center distance between adjacent vias is 0.5mm~1.5mm, the width of the shielding copper plating area is ≥2mm, and the single-point grounding point is located at the geometric center of the shielding copper plating area and is connected to the primary safety ground through a grounding via with a diameter larger than the shielding via.

[0017] Explanation of beneficial effects: 1. Differentiated shielding design significantly improves high-frequency suppression capability. By adopting a non-uniform via array layout, the local via density is increased to address the higher interference intensity on the AC input side. Without increasing the overall number of vias, the spatial distribution of interference is matched. The shielding effect of high-frequency common-mode interference above MHz is better than that of traditional uniform via arrays, while also taking into account PCB fabrication.

[0018] 2. Integrated manufacturing process enables significant advantages in mass production cost and consistency. The shielding copper plating area and the copper layer of the via wall are formed simultaneously through the standard PCB copper plating process, without the need for additional shielding covers, manual copper plating or filtering components, and without additional BOM costs and assembly processes. The product has high shielding performance consistency, is fully compatible with existing PCB mass production processes, and is suitable for large-scale production applications.

[0019] 3. Active resonance suppression eliminates the risk of EMI performance degradation. By setting non-metallic slots perpendicular to the direction of common-mode current flow, the parallel resonant circuit between the shielding copper layer and the inner ground plane is cut off, solving the common problem of EMI deterioration at specific frequency points in traditional shielding structures and effectively widening the effective shielding frequency band. Attached Figure Description

[0020] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings: Figure 1 This is a flowchart of the steps involved in manufacturing a via copper plating EMI shielding structure for an AC-DC power supply PCB according to the present invention. Figure 2 This is a schematic diagram of the overall layout of the AC-DC power supply PCB shielding structure. Detailed Implementation

[0021] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0022] Example 1

[0023] This embodiment provides a method for fabricating an AC-DC power supply PCB via copper plating EMI shielding structure. This method can be integrated using standard PCB manufacturing processes, eliminating the need for additional shielding components and manual mounting. It is suitable for various AC-DC switching power supply products that use power switching devices as the main switching transistors, have switching frequencies in the mid-to-high frequency range, and high voltage change rates. This method effectively suppresses common-mode conducted interference coupling between the AC input area and the high-frequency transformer without altering the power supply's main circuit topology and overall layout dimensions. Simultaneously, it avoids the inherent defects of traditional shielding schemes, such as resonance and parasitic parameter degradation.

[0024] Please see Figure 1 As shown, the technical solution of this embodiment will be described in detail below with reference to the complete manufacturing steps: S1 Determine the interference frequency band In the initial stage of shielding scheme design, the frequency range of common-mode interference that needs to be suppressed is first determined based on the main circuit parameters of the target AC-DC power supply, especially the upper limit frequency of the common-mode interference band, so as to provide a frequency reference for the design of all subsequent shielding parameters.

[0025] Common-mode conducted interference in AC-DC power supplies mainly originates from the high-speed switching action of power switching devices: when the switching transistor turns on and off, its drain-source voltage undergoes a rapid transition between high and low levels, resulting in a high voltage change rate. This rapid voltage transition generates displacement current through various parasitic capacitances in the circuit, thereby triggering common-mode interference to propagate to the AC input side. The spectrum distribution of common-mode interference is based on the switching frequency, accompanied by a large number of higher harmonics. The amplitude of the harmonics gradually decreases as the frequency increases, and after reaching a certain upper limit frequency, the interference amplitude decays to a negligible level.

[0026] In this step, the rated switching frequency of the power switching device and the actual voltage change rate during operation are first obtained. The upper limit frequency of common-mode interference is then derived using a classical estimation model for the interference spectrum. Specifically, the rise time of the switching transistor's voltage transition corresponds to the voltage change rate. The voltage rise time can be calculated by the ratio of the voltage change to the voltage change rate, using the following formula: ; In the formula, The rise time of the drain-source voltage of the switching transistor. This represents the voltage jump amplitude during the switching process. This represents the voltage change rate of the power switching device.

[0027] According to the spectral characteristics in the field of electromagnetic compatibility, the high-frequency cutoff frequency of a trapezoidal pulse is inversely proportional to its rise time. The formula for estimating the upper limit frequency is: ; In the formula, This is the upper limit frequency of the common-mode interference band. The value is the spectrum correction coefficient, and its weight ranges from 0.3 to 0.5. In this embodiment, the preferred value is 0.35.

[0028] After calculating the upper limit frequency using the above formula, the complete common-mode interference suppression frequency band can be determined as a continuous band from the fundamental frequency of the switching frequency to the upper limit frequency. In practical applications, for high-frequency switching power supplies with a switching frequency of not less than 100kHz and a voltage change rate of not less than 50V / ns, the upper limit frequency of common-mode interference is usually in the range of several MHz to tens of MHz. This method can achieve good shielding adaptation effect.

[0029] S2 Calculate shielding parameters Based on the determination of the upper limit frequency of common-mode interference, and combined with the dielectric properties of the PCB substrate itself, the maximum allowable center distance of the shielded via array is calculated. This serves as a design constraint for the via arrangement, ensuring the shielding effectiveness in the high-frequency band.

[0030] The shielding mechanism of the via array is based on the surface wave suppression effect of the periodic conductive structure: when the center distance between adjacent vias is much smaller than the wavelength of the interfering electromagnetic wave, the via array can be equivalent to a continuous conductive shielding wall, effectively blocking the propagation path of high-frequency surface waves; if the center distance between the vias is too large, approaching or exceeding a certain proportion of the wavelength, the electromagnetic wave will diffract through the gap between the vias, resulting in a sharp drop in shielding effectiveness.

[0031] This step first calculates the equivalent propagation wavelength of the interfering electromagnetic wave in the PCB substrate. In free space, the relationship between the wavelength and frequency of an electromagnetic wave is: ; In the formula, The free-space wavelength corresponding to the upper limit frequency. The speed of light in a vacuum.

[0032] Because the speed of electromagnetic waves decreases when propagating in the PCB substrate, the equivalent wavelength is correspondingly shortened, requiring correction using the substrate's effective dielectric constant. For surface wiring and shielding structures, electromagnetic waves propagate partly in the dielectric and partly in the air. The effective dielectric constant lies between the air dielectric constant and the substrate material dielectric constant, and its value range can be calculated based on the substrate's relative dielectric constant and the copper foil thickness. In this embodiment, when using a conventional FR-4 substrate, the effective dielectric constant's weight range is 2.8 to 4.2.

[0033] The formula for calculating the equivalent guided wavelength in a medium is: ; In the formula, This represents the equivalent guided wavelength in the PCB substrate corresponding to the upper limit frequency. It is the effective dielectric constant.

[0034] To ensure stable shielding effectiveness of the via array across the entire interference frequency band, the maximum allowable center-to-center distance between shielded vias must be less than a preset fraction of the equivalent guided wave wavelength. The constraint formula is as follows: ; In the formula, To shield the maximum allowable center distance of the via, This is the wavelength scaling factor, and its threshold range is set to 1 / 15 to 1 / 8. In this embodiment, the preferred value is 1 / 10.

[0035] In practical design, the actual center-to-center distance of the shielded vias is set to be no greater than the maximum allowable center-to-center distance mentioned above, thereby ensuring that the via array has effective suppression capability for all interference signals below the upper limit frequency. If the shielded vias are arranged in multiple columns, the spacing between the columns must also meet the above center-to-center distance constraint to form a complete planar shielding barrier.

[0036] S3 Define the shielding area During the PCB layout design phase, a continuous shielded copper plating area is defined as the main structure for EMI shielding, targeting the coupling path between the AC input area and the high-frequency transformer layout area.

[0037] Due to the compact layout, there is strong electric field coupling between the AC input circuit and the primary winding of the high-frequency transformer. The high-frequency switching voltage on the high-frequency transformer winding couples interference to the AC input side through the parasitic capacitance between the winding and the AC traces, which is the main coupling path for conducted interference. The coupling gap between the two is the area where the electric field distribution is most concentrated. Setting a shielding structure here can block the coupling path to the greatest extent and achieve the best shielding effect.

[0038] In this step, the relative positions of the AC input trace area and the high-frequency transformer package area on the PCB are first identified to determine the minimum coupling gap range between them. Then, a continuous shielded copper plating area is delineated along the extension direction of the coupling gap. The overall direction of the shielded copper plating area is consistent with the direction of the coupling gap, completely covering the projection range of the entire coupling gap.

[0039] To ensure adequate shielding and compliance with safety regulations, the width of the shielded copper plating area is set to be no less than a preset multiple of the minimum safe electrical clearance between the AC input area and the high-frequency transformer layout area. This multiple has a threshold range of 1.2 to 2.5, and in this embodiment, it is preferably 1.5 times. This width setting ensures, on the one hand, that the shielded area completely covers the main area of ​​electric field coupling, preventing interference from diffracting from both sides of the shielded area due to insufficient width; on the other hand, it ensures that sufficient safety distances are maintained between the shielded area and the charged areas on both sides, meeting electrical insulation requirements.

[0040] The shielded copper plating area is connected to the primary safety ground via a single point to avoid forming a closed ground loop due to multiple grounding points. Ground loops can generate induced circulating currents under alternating magnetic fields, becoming new sources of interference. Therefore, single-point grounding is a key design feature to ensure shielding effectiveness. The grounding point is preferably located at the geometric center of the shielded copper plating area. This location ensures a relatively balanced current path from each point in the shield to the grounding point, resulting in the lowest equivalent grounding impedance, the fastest common-mode charge discharge, and optimal shielding stability. Grounding is achieved through dedicated grounding vias with a larger diameter than ordinary shielding vias to further reduce parasitic inductance in the grounding path and improve high-frequency grounding performance.

[0041] The relative positions of the AC input area, the high-frequency transformer layout area, and the shielding copper plating area, as well as the overall arrangement of the shielding structure in this step, can be referred to... Figure 2 As shown.

[0042] S4 Design Non-uniform Via Array After defining the shielded copper plating area, a shielded via array is arranged at the edge of the shielded copper plating area. The shielded vias penetrate the entire PCB substrate along the thickness direction, forming a three-dimensional conductive shielding structure in conjunction with the surface shielded copper plating area.

[0043] Traditional via shielding solutions typically employ a uniformly arranged via array, meaning the via diameter and center-to-center distance are exactly the same throughout. However, in real-world scenarios, the distribution of interference field strength along the extension direction of the shielded copper plating area is not uniform: the side closer to the AC input area is closer to the interference propagation exit, resulting in a higher interference field strength and requiring higher shielding effectiveness; the side farther from the AC input area has already experienced natural attenuation of the interference field strength, and the shielding requirement is relatively lower. A uniformly arranged solution, if designed to meet the shielding requirements of the strong interference side, will create design redundancy on the weak interference side, occupying excessive PCB routing space; conversely, if designed according to the weak interference side, the shielding effectiveness on the strong interference side will be insufficient.

[0044] To address the aforementioned issues, this embodiment employs a non-uniform via array design: the aperture and / or center-to-center distance of the shielded vias are non-uniformly distributed along the extension direction of the shielded copper plating area, exhibiting an overall gradient distribution characteristic where the via density near the AC input area is greater than the via density far from the AC input area.

[0045] Specifically, the gradient change in via density can be achieved in two ways, or in combination: one is a gradual change in aperture, where the aperture of the via gradually decreases from the side closer to the AC input area to the side farther away from the AC input area. Under the same center distance, the larger the aperture, the larger the effective area of ​​conductive shielding and the higher the shielding effectiveness. The other is a gradual change in center distance, where the center distance between adjacent vias gradually increases from the side closer to the AC input area to the side farther away from the AC input area. The smaller the center distance, the higher the via density and the stronger the shielding effectiveness.

[0046] The via density gradient matching employs a gradient distribution algorithm based on the attenuation law of interference field strength: along the extension direction of the shielding area, the electric field strength of common-mode interference decreases approximately exponentially; therefore, the via density is also set to an exponentially decreasing distribution law, matching the distribution of shielding effectiveness with the distribution of interference field strength. The ratio of the via density near the AC input side to the via density far from the input side ranges from 1.5 to 3.0, and is preferably 2.0 in this embodiment. This design can improve the overall shielding effect without increasing the total number of vias or occupying additional wiring resources, achieving an optimal balance between shielding effectiveness and wiring space.

[0047] The shielding vias adopt a through-hole design, penetrating all layers of the entire PCB substrate. They can simultaneously block the coupling of electric and magnetic fields between the surface and inner layers, and together with the shielding copper plating area on the surface, they form a vertical conductive shielding wall, creating an isolation effect similar to a Faraday cage, and blocking the conducted interference coupling path between the AC side and the high-frequency transformer in all directions.

[0048] S5 Integrated Copper Plating After the PCB layout design is completed, the surface copper layer of the shielding copper plating area and the copper layer of the shielding via wall are formed simultaneously through the standard PCB copper plating manufacturing process, so as to achieve reliable electrical conduction and form an integrated three-dimensional shielding structure.

[0049] In traditional solutions involving external shielding and manual copper foil mounting, the shielding body and the PCB substrate are mechanically connected, resulting in contact resistance and contact inductance. At high frequencies, the contact impedance increases significantly, leading to a decrease in shielding effectiveness. Furthermore, the poor consistency of manual mounting and the dispersion of contact states can cause fluctuations in the yield of the product's EMI performance.

[0050] This embodiment uses an integrated PCB manufacturing process to achieve the shielding structure, and its process is fully compatible with the standard PCB metallization via process: First, drilling is completed on the PCB substrate according to the design layout, drilling out all shielding vias and grounding vias; then, the vias are metallized, and a thin conductive copper layer is deposited on the via walls and substrate surface through a chemical copper plating process, and then the copper layer is thickened to the design thickness through a full-board electroplating process.

[0051] In this process, the surface copper layer of the shielding copper plating area and the copper layer of the via wall are grown synchronously in the same deposition process. They are connected by a continuous metal crystal structure without any contact interface, resulting in zero contact resistance and excellent conductivity continuity. This ensures stable low impedance characteristics even at high frequencies, guaranteeing the consistency and reliability of shielding effectiveness. Furthermore, this shielding structure is completed simultaneously during PCB manufacturing, eliminating the need for additional materials, assembly processes, and labor costs. Product yield and consistency are entirely guaranteed by the PCB manufacturing process, making it suitable for large-scale mass production applications.

[0052] After copper plating is completed, the shielding copper plating area can be designed as a solid copper sheet or a grid copper sheet structure, depending on actual needs. When using a grid copper sheet, the grid period must meet a preset fractional value less than the equivalent guided wave wavelength corresponding to the upper limit frequency of common-mode interference. The threshold range of this fractional value is consistent with the constraint of the via center distance, usually 1 / 15 to 1 / 8, to ensure that the grid copper sheet does not lose its shielding effect due to excessive gaps. The grid copper sheet structure can reduce the copper foil coverage area, reduce the risk of PCB warping caused by uneven copper distribution, and at the same time take into account a certain degree of heat dissipation and routing flexibility.

[0053] S6 Resonance Suppression Non-metallic slots are made in the shielded copper plating area to suppress the parallel resonance formed between the shielded copper plating area and the PCB inner layer ground plane, and to avoid EMI performance deterioration at specific frequency points.

[0054] The shielding copper plating area is placed on the surface layer of the PCB. The inner layers of the PCB beneath it typically have a large primary ground plane, separated by a dielectric substrate. This creates an equivalent parallel-plate capacitor structure. Simultaneously, the conductive path of the shielding copper plating area itself contains parasitic inductance. This parasitic inductance and parasitic capacitance together form an LC parallel resonant circuit. When the frequency of the interference signal approaches the inherent resonant frequency of this circuit, parallel resonance occurs. At this point, the circuit impedance reaches its maximum value, and the grounding discharge capability of the shielding layer decreases sharply. This not only results in a loss of shielding effectiveness but may even lead to stronger radiation and coupling at the resonant frequency, causing EMI performance to be worse than in the unshielded state.

[0055] To address this issue, this embodiment creates non-metallic slots in the shielded copper plating area. The slots contain no copper layer and are in an insulating dielectric state, which can cut off the flow path of high-frequency common-mode current in the shielded copper plating area, change the equivalent inductance and equivalent capacitance of the current loop, thereby disrupting the original parallel resonance conditions, shifting the resonance frequency out of the target interference frequency band, or directly suppressing the generation of resonance.

[0056] The length direction of the non-metallized slot is perpendicular to the expected flow direction of the high-frequency common-mode current. The common-mode current mainly flows in the direction perpendicular to the coupling gap in the shielded copper plating area, that is, from the side closer to the transformer to the side closer to the AC input. Therefore, the slot is opened along the length extension direction of the shielded area, and its length direction is orthogonal to the current flow direction, which can maximize the current flow path length and effectively change the resonant parameters of the circuit.

[0057] The length parameter of the slot is set according to the center frequency of the common-mode interference band. Its length corresponds to a certain proportion of the equivalent guided wavelength of the center frequency, with a value range of 1 / 8 to 1 / 4. The calculation formula is as follows: ; In the formula, The length of the non-metallized slot. This is the length scaling factor, with a value ranging from 1 / 8 to 1 / 4. This is the equivalent guided wavelength corresponding to the center frequency of the common-mode interference band.

[0058] When multiple non-metallized slots are used, they are arranged at equal intervals along the extension direction of the shielded copper plating area. The spacing between adjacent slots is also set according to the center frequency of the common-mode interference band, and its value ranges from 1 / 4 to 1 / 2 of the equivalent guided wave wavelength corresponding to the center frequency. By distributing multiple slots, resonance suppression can be achieved over a wider frequency range, avoiding the situation where a single slot is only effective for a single frequency point, and ensuring the stability of shielding performance across the entire interference band.

[0059] S7 Parasitic Capacitance Compensation A floating conductive layer is set in the inner layer of the PCB substrate between the shielded copper plating area and the high-frequency transformer to adjust the equivalent parasitic capacitance between the shielded copper plating area and the high-frequency transformer, and to compensate for the additional parasitic parameters introduced by the shielding structure.

[0060] In the original PCB layout without shielding, there is an inherent parasitic capacitance between the AC input area and the high-frequency transformer, which is the main path for common-mode interference coupling. When a shielded copper plating area is introduced, it forms new parasitic capacitances with both the AC input area and the high-frequency transformer, altering the original parasitic parameter distribution. This is equivalent to inserting new capacitor nodes into the coupling path. This parameter change may alter the coupling path and amplitude of interference, and may even create new coupling paths at certain frequencies, affecting the original EMI characteristics of the power supply and the circuit's operating state.

[0061] Traditional solutions typically attempt to reduce parasitic capacitance by shrinking the shielding area and increasing the spacing, but this approach weakens the shielding effect and fails to balance shielding effectiveness with parameter stability. This embodiment employs a floating conductive layer compensation scheme, actively utilizing the coupling effect of parasitic capacitance to compensate for parameter changes introduced by the shielding structure. This ensures that the overall equivalent parasitic parameters match the original state, eliminating the impact of the shielding structure on the original circuit characteristics without sacrificing shielding effectiveness.

[0062] The floating conductive layer is placed in the inner dielectric layer of the PCB, located between the shielded copper plating area and the projected area of ​​the high-frequency transformer. It has no direct electrical connection to either the shielded copper plating area or the high-frequency transformer windings, and is in a floating potential state. The floating conductive layer forms parasitic capacitances with both the shielded copper plating area and the high-frequency transformer. These two capacitances are connected in series, and the formula for calculating its equivalent compensation capacitance is: ; In the formula, The equivalent compensation capacitor introduced for the floating conductive layer. This refers to the parasitic capacitance between the floating conductive layer and the shielded copper plating area. This refers to the parasitic capacitance between the floating conductive layer and the high-frequency transformer.

[0063] By adjusting the area, shape, and position of the floating conductive layer within the dielectric layer, the values ​​of the two parasitic capacitances can be precisely adjusted. This, in turn, adjusts the size of the equivalent compensation capacitance, offsetting the additional parasitic capacitance increase introduced by the shielded copper plating area and achieving overall parasitic parameter balance. This solution does not eliminate parasitic capacitance but actively utilizes the coupling effect of parasitic capacitance to achieve parameter compensation, transforming the original adverse factor into a controllable compensation method. While ensuring the shielding effect, it maintains the stability of the original parasitic parameters of the circuit, avoiding secondary interference problems introduced by the shielding structure.

[0064] Through the complete implementation of the above seven steps, the final AC-DC power supply PCB via copper plating EMI shielding structure is formed by the shielded copper plating area and the shielded via array, which together constitute a Faraday cage-like three-dimensional isolation barrier. This can effectively block the conducted interference coupling path between the AC side and the high-frequency transformer. At the same time, it has resonance suppression and parasitic parameter compensation mechanisms, avoiding the inherent defects of traditional shielding solutions, and has the comprehensive advantages of high shielding efficiency, high mass production consistency and low overall cost.

[0065] Example 2

[0066] This embodiment uses a mass-produced fast-charging AC-DC power supply as the application platform. Based on the actual production line process and EMI laboratory test data, the engineering effect of the shielding structure of this invention is empirically verified. The test sample uses a 4-layer FR-4 substrate with a relative permittivity of 4.0; the rated switching frequency of the main power supply switch is 130kHz, and the switching action voltage change rate is approximately 62V / ns, which meets the high-frequency switching power supply operating conditions applicable to this invention.

[0067] First, test samples were prepared according to the manufacturing method described in this invention. The core design and process parameters were matched to mass production process capabilities, as detailed below: Based on calculations in steps S1-S2, the upper limit frequency of the target common-mode interference is approximately 22MHz, corresponding to an equivalent guided wave wavelength of approximately 9.8mm within the PCB. The shielded copper plating area is 2.5mm wide, completely covering the coupling gap between the AC input area and the high-frequency transformer. It adopts a single-point grounding at the geometric center, and the grounding via diameter is 0.8mm. The shielded vias are arranged in a non-uniform array: the center-to-center distance of the vias near the AC input side is 0.8 mm and the diameter is 0.3 mm, while the center-to-center distance of the vias away from the AC input side is 1.2 mm and the diameter is 0.25 mm. The overall via density gradient ratio is approximately 1.8:1. Three non-metallized slots are made in the shielded copper plating area. The slot length is 1.5mm and the spacing between adjacent slots is 3mm. The length direction of the slots is perpendicular to the expected direction of common mode current flow. The PCB inner layer features a floating conductive layer made of 0.5 ounce copper foil, covering 70% of the area of ​​the shielded copper plating area, located on the second dielectric layer.

[0068] All samples are integrally formed using standard PCB copper plating process, without additional mounting or post-processing steps.

[0069] Furthermore, the test conditions include: Conducted interference (CE) tests were conducted according to GB / T 17626.6 standard, covering a frequency band of 150kHz to 30MHz. A linear impedance stabilization network was used to collect common-mode interference amplitudes, and the Class B limit was used as the evaluation benchmark to compare the interference levels and EMI margins of different schemes.

[0070] Further, comparative verification 1: comparison of the shielding effects of non-uniform via arrays and uniform via arrays.

[0071] This comparison controlled for a single variable: both groups of samples featured shielded copper plating areas, non-metallized vias, and floating conductive layers, differing only in the via array arrangement. The control group used a conventional uniform via array (1.0 mm center-to-center distance and 0.3 mm aperture), while the experimental group used the non-uniform via array of this invention. The total number of vias was essentially the same in both groups. The test results are shown in the table below: Table 1 Comparison of conducted interference test results for different via array schemes 500kHz 56 52.3 49.7 2.6dB 1MHz 56 50.8 47.2 3.6dB 5MHz 52 48.5 44.9 3.6dB 10MHz 52 47.1 43.3 3.8dB 20MHz 52 46.4 42.1 4.3dB The test data shows that, under the premise of the same total number of vias and PCB space occupied, the non-uniform via array of the present invention has a better shielding effect than the traditional uniform array across the entire test frequency band; and the higher the frequency, the more significant the advantage. At the 20MHz high-frequency point, the interference amplitude is reduced by 4.3dB, which verifies that the gradient arrangement can accurately match the interference field strength distribution and improve the high-frequency shielding performance without increasing the design cost.

[0072] Further, comparative verification 2: the compensation effect of the floating conductive layer on parasitic parameters and resonance.

[0073] This group controlled for a single variable: both groups of samples used non-uniform via arrays and non-metallized slots, differing only in the presence or absence of an inner floating conductive layer. The test results are shown in the table below: Table 2 Comparison of conducted interference test results with and without floating conductive layer 500kHz 56 52.3 49.7 2.6dB 1MHz 56 50.8 47.2 3.6dB 5MHz 52 48.5 44.9 3.6dB 10MHz 52 47.1 43.3 3.8dB 20MHz 52 46.4 42.1 4.3dB Test results show that without the floating conductive layer, the additional parasitic capacitance introduced by the shielding structure causes a significant resonant spike around 8MHz, with the interference amplitude approaching the Class B limit, posing a risk of EMI exceeding the standard. After adding the floating conductive layer, the resonant spike is effectively suppressed, and the interference amplitude across the entire frequency band decreases, with a 6.5dB reduction at the resonant frequency. This verifies that the floating conductive layer can eliminate secondary interference introduced by the shielding structure through parasitic parameter compensation, ensuring the stability of EMI performance.

[0074] Preferably, samples using the shielding solution of this invention, verified by batch sampling on the production line, have an average conducted interference Class B margin of over 6dB and an EMI test yield of 99.2%. Compared with the traditional shielding solution of manually mounting copper foil, the BOM cost per unit is reduced by about 0.12 yuan, assembly time is reduced by about 12%, and the consistency of shielding performance is significantly improved, combining technical effectiveness with the economic benefits of mass production.

[0075] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for fabricating an AC-DC power supply PCB via copper plating EMI shielding structure, characterized in that, Includes the following steps: S1 Determine the interference frequency band: Based on the switching frequency and voltage change rate of the power switching device, determine the upper limit frequency of the common-mode interference band that needs to be suppressed; S2 Calculate shielding parameters: Based on the upper limit frequency of the common mode interference band and the dielectric constant of the PCB substrate, calculate the maximum allowable center distance of the shielding vias, so that the maximum allowable center distance is less than the preset fraction of the wavelength corresponding to the upper limit frequency of the common mode interference band, and set the actual center distance of the shielding vias to be no greater than the maximum allowable center distance. S3 Define the shielding area: During the PCB substrate layout design stage, a continuous shielding copper plating area is defined at the coupling gap between the AC input area and the high-frequency transformer layout area. The shielding copper plating area is connected to the primary safety ground through a single point. S4 Design Non-uniform Via Array: A shielded via array is arranged at the edge of the shielded copper plating area. The aperture and / or center distance of the shielded vias are non-uniformly distributed along the extension direction of the shielded copper plating area. The via density near the AC input area is greater than the via density away from the AC input area. The shielded vias penetrate the entire PCB substrate. S5 Integrated Copper Plating: Through the copper plating process, the copper layer of the shielded copper plating area and the copper layer of the hole wall of the shielded via are synchronously and electrically integrated into a single process. S6 Resonance Suppression: A non-metallized slot is formed on the shielded copper plating area. The length direction of the non-metallized slot is perpendicular to the expected flow direction of the high-frequency common-mode current, so as to suppress the parallel resonance formed between the shielded copper plating area and the PCB inner layer ground plane. S7 Parasitic Capacitance Compensation: A floating conductive layer is provided on the inner layer of the PCB substrate between the shielded copper plating area and the high-frequency transformer. The floating conductive layer has no direct electrical connection with the shielded copper plating area and the high-frequency transformer. The equivalent parasitic capacitance between the shielded copper plating area and the high-frequency transformer is adjusted by electric field coupling. The floating conductive layer is configured to utilize rather than eliminate the parasitic capacitance to compensate for the additional parasitic parameters introduced by setting the shielded copper plating area.

2. The method according to claim 1, characterized in that, The width of the shielded copper plating area is not less than a preset multiple of the minimum safe electrical distance between the AC input area and the high-frequency transformer layout area.

3. The method according to claim 1, characterized in that, In the non-uniform via array design step, the aperture of the shielding via gradually changes from the side closer to the AC input area to the side farther from the AC input area, and / or the center distance of the shielding via gradually changes from the side closer to the AC input area to the side farther from the AC input area; the single-point ground of the shielding copper plating area is located at the geometric center of the shielding copper plating area and is connected to the primary safety ground through a grounding via, and the size of the grounding via is larger than the size of the shielding via.

4. The method according to claim 1, characterized in that, In the resonance suppression step, there are multiple non-metallized slots, which are arranged at equal intervals along the extension direction of the shielded copper plating area. The spacing between adjacent non-metallized slots is set according to the center frequency of the common-mode interference band. The length of the non-metallized slots is set according to the center frequency of the common-mode interference band.

5. The method according to claim 1, characterized in that, The shielded copper plating area is a grid of copper foil; the grid period of the shielded copper plating area is less than a preset fraction of the wavelength corresponding to the upper limit frequency of the common-mode interference band.

6. The method according to claim 1, characterized in that, The switching frequency of the power switching device is not less than 100kHz, and the voltage change rate is not less than 50V / ns.

7. An AC-DC power supply PCB via copper plating EMI shielding structure, wherein the AC-DC power supply uses power switching devices as the main switching transistors, characterized in that... include: PCB substrate; A shielded copper plating area is disposed on the surface of the PCB substrate, located at the coupling gap between the AC input area and the high-frequency transformer layout area. The shielded copper plating area is connected to the primary safety ground through a single point, and the shielded copper plating area is a continuous conductive copper layer. A shielded via array is arranged at the edge of the shielded copper plating area. The shielded vias penetrate the entire PCB substrate. The copper layer of the via wall is electrically connected to the copper layer of the shielded copper plating area, forming a vertical conductive shielding wall. In the shielded via array, the via density near the AC input area is greater than the via density away from the AC input area; A floating conductive layer is provided on the inner layer of the PCB substrate between the shielded copper plating area and the high-frequency transformer. The floating conductive layer has no direct electrical connection with the shielded copper plating area and the high-frequency transformer. The equivalent parasitic capacitance between the shielded copper plating area and the high-frequency transformer is adjusted by electric field coupling. The shielded copper plating area and the shielded via array together form a Faraday cage-like isolation barrier, blocking the conductive interference coupling path between the AC side and the high-frequency transformer.

8. The PCB via copper plating EMI shielding structure according to claim 7, characterized in that, The width of the shielded copper plating area is not less than the width of the coupling gap between the AC input area and the high-frequency transformer layout area, and completely covers the coupling gap; the aperture of the shielded via and the center distance between adjacent shielded vias are preset values, and the shielded via array is arranged in a linear array or an arc array.

9. The PCB via copper plating EMI shielding structure according to claim 7, characterized in that, At least one non-metallized slot is formed on the shielded copper plating area. The length direction of the non-metallized slot is perpendicular to the expected flow direction of the high-frequency common-mode current in the shielded copper plating area. The length of the non-metallized slot is 1 / 8 to 1 / 4 of the wavelength corresponding to the center frequency of the common-mode interference band of the AC-DC power supply.

10. The PCB via copper plating EMI shielding structure according to claim 7, characterized in that, The diameter of the shielding via is 0.2mm to 0.5mm, and the center distance between adjacent shielding vias is 0.5mm to 1.5mm; the width of the shielding copper plating area is ≥2mm; the single-point ground of the shielding copper plating area is located at the geometric center of the shielding copper plating area and is connected to the primary safety ground through a grounding via, and the diameter of the grounding via is larger than the diameter of the shielding via.

Images