Method of manufacturing a semiconductor structure and semiconductor structure thereof
Patent Information
- Application Number
- CN202510936127.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-03-24
- Filing Date
- 2025-07-08
- Publication Date
- 2026-09-25
AI Technical Summary
过度的扭动可能会导致后续形成的金属线出现短路、桥接及意外断裂
[0011]由于在形成位元线之前移除含碳层，因此借由本公开的方法所形成的位元线不具有含碳层的残留物。此外，本公开降低用以对图案层进行图案化的含碳层的高度对宽度的深宽比，其中该图案层包括含有金属氧化物的硬遮罩层。降低深宽比可以使硬遮罩所形成的开口具有较少的扭动。随后，当使用该图案层对目标层进行图案化时，该目标层(包括含氮化物层及位元线堆叠)中的对应的开口同样会更笔直，并且产生更笔直的位元线，从而较不容易发生短路、桥接及意外断裂。
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Figure CN122825432A_ABST
Abstract
Description
Technical Field
[0001] This application claims priority to U.S. Patent Application No. 19 / 087,836 (i.e., priority date "March 24, 2025"), the contents of which are incorporated herein by reference in their entirety.
[0002] This disclosure relates to a method for manufacturing a semiconductor structure and the semiconductor structure manufactured by the method. Specifically, this disclosure relates to a method for manufacturing a semiconductor structure, including forming a hard mask layer between a nitride-containing layer and a carbon-containing layer, and the semiconductor structure formed using the hard mask layer. Background Technology
[0003] Semiconductor components are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Capacitors are used in a broad range of semiconductor circuits. Dynamic Random Access Memory (DRAM) circuits are manufactured by replicating millions of identical circuit elements (called DRAM cells) on a single semiconductor wafer. A DRAM cell is an addressable location that can store one bit (binary) of data. In its most common form, a DRAM cell consists of two circuit elements: a storage capacitor and an access field-effect transistor (FET). In recent years, as the size of DRAM technology nodes has continued to shrink, the conductive structures in DRAM elements have become increasingly close to each other and smaller in size. As a result, the contact resistance of the elements increases, thereby reducing the conduction current and operating speed of the elements.
[0004] To form integrated circuits on a wafer, a lithography process is required. A typical lithography process involves applying photoresist and then defining a pattern on it. The patterned photoresist is defined in a lithography mask layer, and is defined by transparent or opaque portions within the mask layer. The patterned photoresist is then transferred to an underlying film layer via an etching step, where the patterned photoresist is used as a micro-etching mask layer. After the etching step, the patterned photoresist is removed.
[0005] As the demand for smaller electronic components, including integrated circuits, continues to grow, the high aspect ratio stacking of films used in photopatterning techniques results in poor wiggle resistance during the transfer of patterns to underlying films.
[0006] Line twisting occurs when a pattern defined by a mask layer with a high aspect ratio (i.e., a high height-to-width ratio) is transferred onto a patterned film layer underneath. Etching of the patterned film layer using a high aspect ratio mask layer results in excessive twisting of the patterned film layer. Due to this excessive twisting in the patterned film layer, when the underlying target film layer is patterned to form openings for metal lines, both the openings and the resulting metal lines will also exhibit excessive twisting. Excessive twisting can lead to short circuits, bridging, and unexpected breakage of subsequently formed metal lines.
[0007] The discussion in the preceding technical paragraphs is provided for background information only. The statements in the discussion of the preceding technical paragraphs are not an admission that the content disclosed in these paragraphs constitutes prior art of this disclosure, and nothing in the discussion of the preceding technical paragraphs shall be construed as an admission that any part of this application, including the parts in the discussion of the preceding technical paragraphs, constitutes prior art of this disclosure. Summary of the Invention
[0008] This disclosure provides a method for manufacturing a semiconductor structure. The method includes: providing a substrate having an active region, wherein the active region includes an isolation structure and a contact adjacent to the isolation structure; forming a bit line stack on the substrate; forming a nitride-containing layer on the bit line stack; and forming a hard mask layer on the nitride-containing layer, wherein the hard mask layer includes a metal oxide, and the hard mask layer is etched at a rate greater than the nitride-containing layer is etched at the same rate. The method further includes: forming a carbon-containing layer on the hard mask layer; patterning the carbon-containing layer to expose a portion of the hard mask layer; removing the portion of the hard mask layer to form a hard mask with an opening, thereby exposing a portion of the nitride-containing layer; removing the carbon-containing layer after forming the hard mask; and patterning the nitride-containing layer and the bit line stack using the hard mask to form a bit line on the contact and a nitride-containing component on the bit line.
[0009] This disclosure also provides a method for manufacturing a semiconductor structure. The method includes: providing a substrate having an active region, wherein the active region includes a contact; forming a barrier layer on the substrate; forming a conductive layer on the barrier layer; forming a nitride-containing layer on the conductive layer; forming a hard mask layer on the nitride-containing layer, wherein an etch rate of the hard mask layer by means of an etchant is greater than a etch rate of the nitride-containing layer by means of the etchant; and forming a carbon-containing layer on the hard mask layer. The method further includes: patterning the carbon-containing layer and the hard mask layer to form a hard mask having an opening, thereby exposing the nitride-containing layer; removing the carbon-containing layer after forming the hard mask; and patterning the nitride-containing layer, the conductive layer, and the barrier layer using the hard mask to form a bit line and a nitride-containing component located on the bit line, wherein the nitride-containing layer is patterned after the carbon-containing layer is removed.
[0010] This disclosure also provides a semiconductor structure. The semiconductor structure includes: a substrate including an active region; a contact disposed in the active region; and a bit line electrically connected to the contact, wherein the bit line includes a first portion and a second portion disposed above the first portion, wherein a first width of the first portion is substantially equal to a second width of the second portion.
[0011] Because the carbon-containing layer is removed before forming the bit lines, the bit lines formed by the method of this disclosure do not have any carbon-containing layer residue. Furthermore, this disclosure reduces the height-to-width aspect ratio of the carbon-containing layer used to pattern the patterned layer, wherein the patterned layer includes a hard mask layer containing metal oxides. Reducing the aspect ratio allows for less twisting of the openings formed by the hard mask. Subsequently, when the patterned layer is used to pattern a target layer, the corresponding openings in the target layer (including the nitride layer and the bit line stack) will also be straighter, resulting in straighter bit lines, thus reducing the likelihood of short circuits, bridging, and accidental breakage.
[0012] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description
[0013] A more complete understanding of the disclosure of this application can be obtained by referring to the embodiments and claims. This disclosure should also be understood in conjunction with the component symbols in the drawings, which represent similar elements throughout the specification.
[0014] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.
[0015] Figure 2 This is a flowchart illustrating a method for manufacturing a semiconductor structure according to some embodiments of the present disclosure.
[0016] Figures 3 to 9 This is a cross-sectional view illustrating an intermediate stage in the formation process of a semiconductor structure according to some embodiments of the present disclosure.
[0017] The reference numerals in the attached figures are explained as follows:
[0018] 100: Method
[0019] 101: Operation
[0020] 102: Operation
[0021] 103: Operation
[0022] 104: Operation
[0023] 105: Operation
[0024] 106: Operation
[0025] 107: Operation
[0026] 108: Operation
[0027] 109: Operation
[0028] 111:Substrate
[0029] 111a: First surface
[0030] 112: Active Zone
[0031] 114: Isolation Structure
[0032] 116: Contact
[0033] 120: Bit line stacking
[0034] 121: Barrier Layer
[0035] 122: Part One
[0036] 123: Conductive layer
[0037] 124: Part Two
[0038] 125: Nitrogen-containing layer
[0039] 125p: Partial
[0040] 126: Nitride-containing components
[0041] 129: Bitline
[0042] 129s: Sidewall
[0043] 131: Hard mask layer
[0044] 131p: Partial
[0045] 132: Hard Mask
[0046] 133: Carbon-containing layer
[0047] 133p: Partial
[0048] 135: Anti-reflective coating layer
[0049] 137: First masking layer
[0050] 137p: Partial
[0051] 139: Second masking layer
[0052] 141: Opening
[0053] 142: Opening
[0054] 143: Opening
[0055] 200: Method
[0056] 201: Operation
[0057] 202: Operation
[0058] 203: Operation
[0059] 204: Operation
[0060] 205: Operation
[0061] 206: Operation
[0062] 207: Operation
[0063] 208: Operation
[0064] 209: Operation
[0065] 300: Semiconductor Structure
[0066] A1: Area of the first cross-section
[0067] A2: Area of the second cross-section
[0068] D: Depth
[0069] T120: Thickness
[0070] T125: Thickness
[0071] T131: Thickness
[0072] T133: Thickness
[0073] W122: First width
[0074] W124: Second width
[0075] W126: Third width
[0076] W129: Width Detailed Implementation
[0077] The embodiments or examples of this disclosure shown in the drawings are now described using specific language. It should be understood that this is not intended to limit the scope of this disclosure. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as would normally occur to those skilled in the art to which this disclosure pertains. Component symbols may be repeated throughout the embodiments, but this does not necessarily mean that one(s) feature of one embodiment is applicable to another embodiment, even if they share the same component symbols.
[0078] It should be understood that although the terms first, second, third, etc., may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections should not be limited by these terms. Rather, these terms are used only to distinguish one component, part, region, layer, or section from another. Therefore, the first component, part, region, layer, or section discussed below may be referred to as the second component, part, region, layer, or section without departing from the teachings of this disclosure.
[0079] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the concept of the invention. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context otherwise requires. It should be understood that the terms “comprising” and “including,” when used in this specification, indicate the presence of stated features, integers, steps, operations, components, or elements, but do not preclude the presence or addition of a further feature, integer, step, operation, component, element, or group thereof.
[0080] This disclosure provides a semiconductor device and a method for manufacturing a semiconductor device. A semiconductor device includes a bit line, and the method for manufacturing the semiconductor structure includes forming the bit line at a portion of a memory array. To form the bit line, the method includes forming a hard mask layer between a nitride-containing layer and a carbon-containing layer, and transferring a pattern of the carbon-containing layer to the hard mask layer. Compared to methods without a hard mask layer, the thickness of the carbon-containing layer in this disclosure is significantly reduced, and the bit line formed thereby is straighter, thus making it less prone to short circuits, bridging, and accidental breakage.
[0081] According to some embodiments of this disclosure, a method for manufacturing a semiconductor structure is disclosed. Figure 1 This is a flowchart illustrating method 100 according to some embodiments. Method 100 includes multiple operations (operations 101 to 109), and the description and illustration should not be construed as a limitation on the order of these operations. Figure 1 Additional steps are provided before, during, and after the operations shown, and some of the operations described below may be replaced or omitted in other embodiments of method 100. The order of operations may be interchanged.
[0082] See Figure 1 Method 100 begins with operation 101. Operation 101 includes providing a substrate having an active region, wherein the active region includes an isolation structure and a contact adjacent to the isolation structure. Method 100 continues with operations 102 to 109.
[0083] Operation 102 includes forming a bit line stack on a substrate. Operation 103 includes forming a nitride-containing layer on the bit line stack. Operation 104 includes forming a hard mask layer on the nitride-containing layer, wherein the hard mask layer comprises a metal oxide, and the rate at which the hard mask layer is etched with an etchant is greater than the rate at which the nitride-containing layer is etched with the same etchant. Operation 105 includes forming a carbon-containing layer on the hard mask layer. Operation 106 includes patterning the carbon-containing layer to expose a portion of the hard mask layer. Operation 107 includes removing this portion of the hard mask layer to form a hard mask having an opening that exposes a portion of the nitride-containing layer. Operation 108 includes removing the carbon-containing layer after forming the hard mask. Operation 109 includes patterning the nitride-containing layer and the bit line stack using the hard mask to form bit lines on contacts and nitride-containing components on the bit lines.
[0084] According to some embodiments of this disclosure, a method for manufacturing a semiconductor structure is disclosed. Figure 2 This is a flowchart illustrating a method 200 for manufacturing a semiconductor structure according to some embodiments. Method 200 includes multiple operations (operations 201 to 209), and the description and illustration should not be construed as limiting the order of these operations. Figure 2Additional steps are provided before, during, and after the operations shown, and some of the operations described below may be replaced or omitted in other embodiments of method 200. The order of operations may be interchanged. Figures 3 to 9 This is a cross-sectional view illustrating one or more operations of a method 200 for manufacturing a semiconductor structure according to some embodiments of the present disclosure.
[0085] See Figure 2 Method 200 begins with operation 201. Operation 201 includes providing a substrate having an active region, wherein the active region includes a contact. In some embodiments, operation 201 of method 200 is similar to operation 101 of method 100.
[0086] In some embodiments, see Figure 3 A substrate 111 having active regions 112 is provided. In some embodiments, the substrate 111 is a semiconductor layer. In some embodiments, the substrate 111 comprises a semiconductor material. In some embodiments, the substrate 111 is a silicon substrate. In some embodiments, the active regions 112 comprise silicon. In some embodiments, the active regions 112 may serve as channels for electrical connections. In some embodiments, the active regions 112 comprise p-type or n-type implanted dopants. In some embodiments, the substrate 111 is processed to form a plurality of active regions 112. This typically involves several steps, such as forming a thin oxide layer of silicon dioxide (SiO2) on the surface of the substrate 111. This can be achieved by thermal oxidation, in which the substrate 111 is exposed to a high-temperature oxygen-rich environment, or by any suitable deposition process, such as spin coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), stacking, other similar processes, or combinations thereof.
[0087] In some embodiments, a layer of photosensitive material (referred to as photoresist) is applied onto an oxide layer. The photoresist is then exposed to ultraviolet (UV) light by means of an etch mask containing the desired pattern. This step transfers the pattern onto the photoresist. The exposed photoresist is developed using a suitable developing solution. This selectively removes either the exposed areas (positive photoresist) or the unexposed areas (negative photoresist) of the photoresist, leaving the desired pattern. An etching process, such as plasma etching, dry etching, or wet etching, is used to selectively remove the exposed oxide layer at the locations where the active region will be formed. The patterned photoresist acts as a mask to protect the areas requiring oxide. In some embodiments, ion implantation is performed to introduce p-type or n-type dopants into the exposed areas of the substrate 111 where the active element will subsequently be formed. The dopants modify the electrical properties of the substrate 111, thereby creating an active region 112 with the desired conductivity. The implanted dopants are activated by an annealing process, and lattice damage caused during the implantation process is repaired. This step typically involves subjecting the substrate 111 to high temperatures for a specific period of time.
[0088] In some embodiments, substrate 111 includes an isolation structure 114 and a contact 116 adjacent to the isolation structure 114 and located within an active region 112. In some embodiments, active region 112 may include silicon. Isolation structure 114 may include an oxide, such as silicon oxide or other suitable material. Isolation structure 114 may be a shallow trench isolation (STI) structure. In some embodiments, active region 112 includes a plurality of isolation structures 114 and a plurality of contacts 116, wherein each contact 116 is adjacent to a corresponding isolation structure 114.
[0089] In some embodiments, a plurality of isolation structures 114 are also formed between adjacent active regions 112 to achieve electrical isolation. In some embodiments, the plurality of active regions 112 may be separated by corresponding isolation structures 114. In some embodiments, the isolation structures 114 are embedded in a substrate 111. In some embodiments, the isolation structures 114 may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride, silicon nitride oxide (N2OSi2), or other suitable materials.
[0090] The isolation structure 114 can be formed through a series of steps, such as trench formation, etching, substrate deposition, trench filling, and planarization. In some embodiments, a trench pattern is created on the wafer surface using lithography. The trench pattern defines the location and size of the isolation trench. A masking material, such as photoresist, is applied to the wafer surface, and the wafer surface is then exposed to ultraviolet light using a photomask, followed by development to form a photoresist pattern. The exposed areas of the wafer surface are then etched away using a dry or wet etching process to form the isolation trench.
[0091] In some embodiments, a thin oxide layer (referred to as a liner) is deposited on the sidewalls and bottom of the isolation trench. The liner is typically formed of silicon dioxide (SiO2) or other suitable dielectric material. The liner helps improve electrical isolation and prevents contaminants from diffusing into the active region 112. The isolation trench is filled with a dielectric material, such as chemical vapor deposition (CVD) oxide, or a combination of oxide and other materials (e.g., silicon nitride (Si3N4)). Excess filler material is typically removed using a chemical mechanical planarization (CMP) process to flatten the wafer surface. Therefore, wafer surface planarization ensures that the wafer surface is uniform and flat, thereby eliminating any irregularities or morphological variations caused by the trench filling process.
[0092] In some embodiments, a plurality of contacts 116 are formed on the active region 112. In some embodiments, each active region 112 includes a corresponding contact 116. In some embodiments, the plurality of contacts 116 and a plurality of isolation structures 114 are alternately disposed in the substrate 111.
[0093] In some embodiments, in a semiconductor memory array, a plurality of contacts 116 (also referred to as bit line contacts or bit line contact plugs) are key components for establishing electrical connections between bit lines and memory cells or transistors. This configuration allows for the transmission of signals and data between memory cells and bit lines in the memory array. In some embodiments, contacts 116 are configured to form bit lines (not shown). Contacts 116 may include conductive materials such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, combinations thereof, or any metallic material having suitable resistance and caking capabilities.
[0094] In some embodiments, the contact 116 may be formed by a series of steps, such as dielectric layer deposition, lithography, etching, conductive material deposition, or planarization. In some embodiments, a dielectric layer may be deposited over a memory array region. The dielectric layer may serve as an insulating material, providing electrical isolation between different components of the memory array. A layer of photosensitive material (referred to as photoresist) is applied onto the dielectric layer. Lithography is then used to define the locations where the contact 116 is expected to form. Lithography involves exposing the photoresist to ultraviolet light by means of an etch mask containing the desired contact pattern. An etching process is employed to remove the dielectric layer in areas not protected by the photoresist. The etching process creates openings or cavities at the locations where the contact 116 is expected to form.
[0095] In some embodiments, a conductive material, such as a metal or metal alloy, is deposited into the openings or cavities to form a plurality of contacts 116. In some embodiments, the conductive material is polycrystalline silicon, and the plurality of contacts 116 comprise polycrystalline silicon. In some embodiments, a planarization technique, such as chemical mechanical planarization, is performed to remove excess conductive material and ensure that the substrate 111 has a smooth and flat surface. Planarization helps to eliminate any topographic variations and ensures uniformity throughout the semiconductor structure.
[0096] Method 200 continues with operations 202 and 203. See also Figure 2 Operation 202 includes forming a barrier layer on substrate 111, and operation 203 includes forming a conductive layer on the barrier layer. In some embodiments, operations 202 and 203 of method 200 are similar to operation 102 of method 100.
[0097] See Figure 3 In some embodiments, a bitline stack 120 is formed on a substrate 111. The bitline stack 120 is configured to form bitlines (not shown) after further patterning. In some embodiments, a barrier layer 121 of the bitline stack 120 is formed on the substrate 111, and a conductive layer 123 of the bitline stack 120 is formed on the barrier layer 121. In some embodiments, the barrier layer 121 is disposed on and in contact with a plurality of isolation structures 114 and a plurality of contacts 116, and the conductive layer 123 is disposed on and in contact with the barrier layer 121. In some embodiments, the bitline stack 120 is electrically connected to the contacts 116 and electrically isolated from the isolation structures 114 of the substrate 111.
[0098] In some embodiments, the barrier layer 121 comprises titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), manganese dinitride (Mn3N2), or a combination thereof. In some embodiments, the barrier layer 121 comprises titanium nitride. In some embodiments, the conductive layer 123 comprises a metal, such as tungsten, copper, ruthenium, iridium, nickel, osmium, rhodium, aluminum, molybdenum, cobalt, alloys thereof, or a combination thereof. In some embodiments, the conductive layer 123 comprises tungsten.
[0099] In some embodiments, each of the barrier layer 121 and the conductive layer 123 may be formed by any applicable deposition process, such as spin coating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, stacking, other similar processes, or combinations thereof.
[0100] Method 200 continues to operation 204. See also... Figure 2 Operation 204 includes forming a nitride-containing layer on the conductive layer 123. In some embodiments, operation 204 of method 200 is similar to operation 103 of method 100.
[0101] In some embodiments, a nitride-containing layer 125 is formed on a bit line stack 120. In some embodiments, the nitride-containing layer 125 is in contact with a conductive layer 123. In some embodiments, the nitride-containing layer 125 comprises silicon nitride (Si3N4), silicon oxynitride, silicon nitride oxide (N2OSi2), or a combination thereof. In some embodiments, the nitride-containing layer 125 may be formed by any suitable deposition process, such as spin coating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, stacking, other similar processes, or combinations thereof.
[0102] In some embodiments, the thickness T125 of the nitride layer 125 is greater than the thickness T120 of the bit line stack 120.
[0103] Method 200 continues to operation 205. See also... Figure 2 Operation 205 includes forming a hard mask layer on the nitride-containing layer 125, wherein the rate of etching the hard mask layer by means of an etchant is greater than the rate of etching the nitride-containing layer 125 by means of the etchant. In some embodiments, operation 205 of method 200 is similar to operation 104 of method 100.
[0104] In some embodiments, see Figure 3 A hard mask layer 131 is formed on the nitride-containing layer 125. In some embodiments, the first dielectric constant of the nitride-containing layer 125 is different from the second dielectric constant of the hard mask layer 131, thereby providing etch selectivity relative to the nitride-containing layer 125. In some embodiments, the first dielectric constant is smaller than the second dielectric constant.
[0105] In some embodiments, the hard mask layer 131 comprises a metal oxide and does not contain carbon or nitrides, and the rate at which the hard mask layer 131 is etched with an etchant is greater than the rate at which the nitride-containing layer is etched with the same etchant. In some embodiments, the hard mask layer 131 has high etch selectivity relative to the nitride-containing layer 125. In some embodiments, the hard mask layer 131 comprises zirconium dioxide (ZrO2), hafnium dioxide (HfO2), silicon-doped hafnium dioxide (Si-doped HfO2, HSO), lanthanum trioxide (La2O3), lanthanum alumina (LaAlO3), zirconium silicon oxide (ZrSiO4), or combinations thereof. In some embodiments, the hard mask layer 131 comprises zirconium dioxide, hafnium dioxide, or combinations thereof. In some embodiments, the hard mask layer 131 can be formed by any suitable deposition process, such as spin coating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, stacking, other similar processes, or combinations thereof.
[0106] In some embodiments, the thickness T125 of the nitride-containing layer 125 is greater than the thickness T131 of the hard mask layer 131. In some embodiments, the thickness T120 of the bit line stack 120 is greater than the thickness T131 of the hard mask layer 131. In some embodiments, the thickness T131 of the hard mask layer 131 is between... and between.
[0107] Method 200 continues to operation 206. See also... Figure 2 Operation 206 includes forming a carbon-containing layer on the hard mask layer 131. In some embodiments, operation 206 of method 200 is similar to operation 105 of method 100.
[0108] In some embodiments, see Figure 3 A carbon-containing layer 133 is formed on the hard mask layer 131. In some embodiments, a nitride-containing layer 125, a hard mask layer 131, and a carbon-containing layer 133 are sequentially disposed on the bit line stack 120. In some embodiments, the hard mask layer 131 is disposed between the carbon-containing layer 133 and the nitride-containing layer 125. In some embodiments, the third dielectric constant of the carbon-containing layer 133 is different from the second dielectric constant of the hard mask layer 131, thereby providing etch selectivity relative to the hard mask layer 131. In some embodiments, the third dielectric constant is smaller than the second dielectric constant.
[0109] In some embodiments, the carbon-containing layer 133 serves as a protective layer for defining and transferring patterns onto the underlying hard mask layer 131, and the hard mask layer 131 and the nitride-containing layer 125 serve as protective layers for defining and transferring patterns onto the underlying bitline stack during various subsequent operations of method 200. In some embodiments, the carbon-containing layer 133, the hard mask layer 131, and the nitride-containing layer 125 serve as a mask, providing resistance to etching chemicals and helping to ensure accurate pattern transfer and alignment to the underlying layer.
[0110] In some embodiments, the carbon-containing layer 133 may be a carbon-rich layer, while the hard mask layer 131 may be substantially carbon-free. In some embodiments, the carbon-containing layer 133 may be formed by any suitable deposition process, such as spin coating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, stacking, other similar processes, or combinations thereof.
[0111] In some embodiments, the thickness T133 of the carbon-containing layer 133 is less than the thickness T125 of the nitride-containing layer 125. In some embodiments, the thickness T125 of the nitride-containing layer 125 is greater than twice the thickness T133 of the carbon-containing layer 133. In some embodiments, the thickness T125 of the nitride-containing layer 125 is greater than four times the thickness T133 of the carbon-containing layer 133. In some embodiments, the thickness T131 of the hard mask layer 131 is less than the thickness T133 of the carbon-containing layer 133. In some embodiments, the thickness T133 of the carbon-containing layer 133 is between 20 nm and 50 nm. In some embodiments, the thickness T133 of the carbon-containing layer 133 is between 30 nm and 40 nm.
[0112] In some embodiments, see Figure 3 Method 200 further includes forming an antireflective coating layer 135 on the carbon-containing layer 133. In some embodiments, the antireflective coating layer 135 serves as a protective layer for defining a pattern and transferring the pattern onto the underlying carbon-containing layer 133. In some embodiments, forming the antireflective coating layer 135 includes forming a first masking layer 137 comprising oxide on the carbon-containing layer 133, and forming a second masking layer 139 comprising silicon on the first masking layer 137. In some embodiments, the first masking layer 137 is an oxygen-rich layer, and the second masking layer 139 is a silicon-rich layer. In some embodiments, each of the first masking layer 137 and the second masking layer 139 can be formed by any suitable deposition process, such as spin coating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, stacking, other similar processes, or combinations thereof.
[0113] In some embodiments, see Figure 3 Method 200 further includes patterning the second masking layer 139 to expose a portion 137p of the first masking layer 137. In some embodiments, a portion of the second masking layer 139 is removed by an etching operation to expose a portion 137p of the first masking layer 137. The etching operation includes plasma etching, wet chemical etching, and / or other types of etching techniques.
[0114] In some embodiments, see Figure 4 Method 200 further includes patterning the first mask layer 137 to expose a portion 133p of the carbon-containing layer 133. In some embodiments, the first mask layer 137 is etched to form a patterned first mask layer 137. In some embodiments, the first mask layer 137 is etched using a patterned second mask layer 139 as an etching mask, such that the pattern of the patterned second mask layer 139 is transferred to the first mask layer 137 to create the patterned first mask layer 137. The patterned first mask layer 137 has a portion 137p (e.g., ...) formed on the first mask layer 137. Figure 3 (as shown) opening 141. In some embodiments, the second mask layer 139 is consumed during the patterning of the first mask layer 137.
[0115] In some embodiments, a portion 137p of the first masking layer 137 exposed through the second masking layer 139 is removed by an etching operation (e.g., Figure 3 (As shown), to expose portion 133p of the carbon-containing layer 133. Etching operations include plasma etching, wet chemical etching, and / or other types of etching techniques.
[0116] Method 200 continues to operation 207. See also... Figure 2 Operation 207 includes patterning the carbon-containing layer 133 and the hard mask layer 131 to form a hard mask having an opening that exposes a portion of the nitride-containing layer. In some embodiments, operation 207 of method 200 is similar to operations 106 and 107 of method 100.
[0117] In some embodiments, see Figure 5 Operation 207 includes patterning the carbon-containing layer 133. In some embodiments, an antireflective coating layer 135 serves as an etch mask to pattern the carbon-containing layer 133, such that the patterned carbon-containing layer 133 exposes a portion 131p of the hard mask layer 131. In some embodiments, the pattern of the antireflective coating layer 135 is transferred to the carbon-containing layer 133 to create the patterned carbon-containing layer 133. The patterned carbon-containing layer 133 has openings 141 (e.g., ...) Figure 4 (As shown) Extended opening 142.
[0118] In some embodiments, a portion 133p of the carbon-containing layer 133 exposed through the antireflective coating layer 135 is removed by an etching operation (e.g., Figure 4 As shown, a portion 131p of the hard mask layer 131 is exposed. Etching or patterning operations include plasma etching, wet etching, dry etching, and / or other types of etching techniques. In some embodiments, a portion 133p of the carbon-containing layer 133 is removed by a dry etching process. In some embodiments, a dry etchant, such as hydrogen (H2) or nitrogen (N2), may be used in the dry etching process. In some embodiments, a portion 133p of the carbon-containing layer 133 is removed by a wet etching process. The etchant used in the wet etching process may include sulfuric acid (H2SO4), hydrogen peroxide (H2O2), hydrofluoric acid (HF), ammonium hydroxide (NH4OH), or combinations thereof. In some embodiments, after the carbon-containing layer 133 is patterned, the antireflective coating layer 135 is removed.
[0119] In some embodiments, see Figure 6Operation 207 includes patterning the hard mask layer 131 to form a hard mask 132 having an opening 143 exposing the nitride-containing layer 125. In some embodiments, the hard mask layer 131 is etched to form the patterned hard mask 132. In some embodiments, the hard mask layer 131 is etched using a patterned carbon-containing layer 133 as an etching mask, such that the pattern of the carbon-containing layer 133 is transferred onto the hard mask layer 131, thereby forming the patterned hard mask 132. The hard mask 132 has openings 143 (such as...) Figure 5 (as shown) Extended opening 143. In some embodiments, the patterned carbon-containing layer 133 is consumed during the patterning of the hard mask layer 131. In some embodiments, the antireflective coating layer 135 is also completely consumed during the patterning of the hard mask layer 131 if it has not yet been completely consumed.
[0120] In some embodiments, see Figure 5 The carbon-containing layer 133 serves as an etching mask to pattern the hard mask layer 131, and see [reference needed]. Figure 6 A portion 125p of the nitride-containing layer 125 is exposed by the patterned hard mask layer 131. In some embodiments, the portion 131p of the hard mask layer 131 exposed by the patterned carbon-containing layer 133 is removed by an etching operation (e.g., Figure 5 (As shown), to expose a portion 125p of the nitride-containing layer 125. Etching or patterning operations include plasma etching, wet etching, dry etching, and / or other types of etching techniques. In some embodiments, the etching operation used to pattern the hard mask layer 131 to form the hard mask 132 includes a wet etching process. The etchant used in a wet etching process may include sulfuric acid, hydrogen peroxide, hydrofluoric acid, ammonium hydroxide, or combinations thereof.
[0121] In some embodiments, the etching rate of the hard mask layer 131 is greater than the etching rate of the nitride-containing layer 125. In some embodiments, the etching rate of the nitride-containing layer 125 is substantially zero.
[0122] In some embodiments, see Figure 7 The etch rate of the nitride layer 125 is greater than zero. In some embodiments, a breakthrough (BT) etching process is performed to form a hard mask 132. The hard mask 132 is etched using a patterned carbon layer 133 as an etch mask, such that the pattern of the carbon layer 133 is transferred to the top portion of the hard mask 132 and the nitride layer 125. The patterned hard mask 132 has openings 142 (e.g., ...) Figure 5(As shown) an extended opening 143. The breakthrough etching process can include any suitable etching process, such as a wet etching process or a dry etching process. In some embodiments, after the breakthrough etching process, the groove in the opening 143 extends into the nitride-containing layer 125, wherein the depth D of the groove can be between approximately Between approximately 3nm, for example, approximately From approximately 1nm.
[0123] Method 200 continues to operation 208. See also... Figure 2 Operation 208 includes removing the carbon-containing layer 133 after forming the hard mask 132. In some embodiments, operation 208 of method 200 is similar to operation 108 of method 100.
[0124] In some embodiments, see Figure 7 After the hard mask layer 131 is patterned and the hard mask 132 is formed, the patterned carbon-containing layer 133 is removed or stripped. In some embodiments, the patterned carbon-containing layer 133 is completely consumed during the formation of the hard mask 132. In some embodiments, if the patterned carbon-containing layer 133 remains on the hard mask 132, undesirable carbon byproducts may be generated in subsequent processes and may contact the nitride layer 125 and the bit line stack 120. In some embodiments, if the patterned carbon-containing layer 133 remains on the hard mask 132 after its formation, removal of the patterned carbon-containing layer 133 in subsequent processes may cause oxidation of the conductive layer 123, thereby affecting the electrical properties of the formed semiconductor structure.
[0125] Method 200 continues with operation 209. See also... Figure 2 Operation 209 includes patterning the nitride layer 125, the conductive layer 123, and the barrier layer 121 using a hard mask 132 to form bit lines 129 on the contact 116 and nitride-containing components 126 on the bit lines 129. In some embodiments, operation 209 of method 200 is similar to operation 109 of method 100. In some embodiments, a semiconductor structure 300 is formed. In some embodiments, the semiconductor structure 300 is manufactured by method 100 or method 200.
[0126] See Figure 7 and Figure 8 In some embodiments, after removing the patterned carbon-containing layer 133 (e.g., Figure 6 (As shown) Then, a hard mask 132 is used to pattern the nitride layer 125, the conductive layer 123 and the barrier layer 121 to form a plurality of bit lines 129 and a plurality of nitride components 126 disposed on the corresponding bit lines 129.
[0127] In some embodiments, the hard mask 132 serves as an etching mask to pattern the nitride layer 125 and the bit line stack 120, thereby forming a plurality of bit lines 129 and a plurality of nitride-containing components 126, which expose the isolation structure 114 of the substrate 111. In some embodiments, the pattern of the hard mask 132 is transferred to the nitride layer 125 and the bit line stack 120 to form a plurality of bit lines 129 and a plurality of nitride-containing components 126 disposed thereon. In some embodiments, the bit lines 129 are patterned and formed after the patterned carbon layer 133 is removed, and only the hard mask 132 is used as an etching mask to pattern the nitride layer 125 and the bit line stack 120, such that any residue of the patterned carbon layer 133 has no opportunity to contact the bit lines 129 or fall between adjacent bit lines 129. In some embodiments, bit lines 129 and substrate 111 do not have any residue of carbon-containing layer 133 disposed thereon.
[0128] In some embodiments, a portion 125p of the nitride-containing layer 125 exposed by the hard mask 132 is removed by an etching operation, thereby exposing the isolation structure 114 of the substrate 111. The etching operation includes plasma etching, wet etching, dry etching, and / or other types of etching techniques.
[0129] In some embodiments, see Figure 8 Patterning the bit line stack 120 to form bit lines 129 includes forming a plurality of first portions 122 that are electrically and physically connected to contacts 116, and forming a plurality of second portions 124 disposed on the first portions 122. In some embodiments, one of the first portions 122 is in contact with its corresponding second portion 124. In some embodiments, each bit line 129 includes one of the first portions 122 and a corresponding second portion 124, wherein the second portion 124 is formed prior to the formation of the corresponding first portion 122. In some embodiments, each bit line 129 is disposed below its corresponding nitride-containing component 126, and the corresponding second portion 124 of the bit line 129 is disposed between the corresponding first portion 122 of the bit line 129 and the corresponding nitride-containing component 126.
[0130] In some embodiments, the first width W122 of the first portion 122 is substantially equal to the second width W124 of the second portion 124. In some embodiments, the width W129 of the bit line 129 is between 5 nm and 15 nm. In some embodiments, the nitride-containing component 126 has a third width W126, wherein the third width W126 is between 5 nm and 15 nm. In some embodiments, the width W129 of the bit line 129 is substantially equal to the third width W126 of the nitride-containing component 126. In some embodiments, the first width W122 of the first portion 122 is substantially equal to the third width W126 of the nitride-containing component 126, and the second width W124 of the second portion 124 is substantially equal to the third width W126 of the nitride-containing component 126.
[0131] In some embodiments, the first portion 122 has a first cross-sectional area A1, and the second portion 124 has a second cross-sectional area A2, wherein the first cross-sectional area A1 is substantially equal to the second cross-sectional area A2.
[0132] In some embodiments, the first portion 122 and the second portion 124 comprise different materials. In some embodiments, the first portion 122 comprises titanium nitride. In some embodiments, the second portion comprises tungsten.
[0133] In some embodiments, the substrate 111 has a first surface 111a, and a bit line 129 is disposed on the first surface 111a. In some embodiments, the sidewalls 129s of the bit line 129 are substantially perpendicular to the first surface 111a of the substrate 111.
[0134] In some embodiments, see Figure 9 Method 200 further includes removing a hard mask 132 from the semiconductor structure 300 after forming the bit lines 129. In some embodiments, no undercut is formed on the bit lines 129 and the nitride-containing components 126. In some embodiments, the hard mask 132 is removed by a stripping, etching, or patterning operation, including plasma etching, wet etching, dry etching, and / or other types of etching techniques. In some embodiments, the hard mask 132 is removed by a dry etching process. In some embodiments, chemical mechanical planarization (CMP) processes are avoided during the removal of the hard mask 132, so that small particles often generated by CMP processes are less likely to fall into the openings between the bit lines 129, thereby preventing damage to the semiconductor structure 300 during subsequent processes.
[0135] In summary, because the carbon-containing layer is removed before forming the bit lines, the bit lines formed by the method of this disclosure do not have any carbon-containing layer residue. Furthermore, the bit lines are formed by patterning the nitride layer and the bit line stack using a hard mask with a metal oxide, wherein the etch rate of the hard mask layer is greater than the etch rate of the nitride layer. Thus, the semiconductor structure of this disclosure includes bit lines having a first portion and a second portion disposed on the first portion, wherein the first width of the first portion is substantially equal to the second width of the second portion, and good electrical performance and reliability of the semiconductor structure are ensured.
[0136] This disclosure provides a method for manufacturing a semiconductor structure. The method includes: providing a substrate having an active region, wherein the active region includes an isolation structure and a contact adjacent to the isolation structure; forming a bit line stack on the substrate; forming a nitride-containing layer on the bit line stack; and forming a hard mask layer on the nitride-containing layer, wherein the hard mask layer includes a metal oxide, and the hard mask layer is etched at a rate greater than the nitride-containing layer is etched at the same rate. The method further includes: forming a carbon-containing layer on the hard mask layer; patterning the carbon-containing layer to expose a portion of the hard mask layer; removing the portion of the hard mask layer to form a hard mask with an opening, thereby exposing a portion of the nitride-containing layer; removing the carbon-containing layer after forming the hard mask; and patterning the nitride-containing layer and the bit line stack using the hard mask to form a bit line on the contact and a nitride-containing component on the bit line.
[0137] This disclosure also provides a method for manufacturing a semiconductor structure. The method includes: providing a substrate having an active region, wherein the active region includes a contact; forming a barrier layer on the substrate; forming a conductive layer on the barrier layer; forming a nitride-containing layer on the conductive layer; forming a hard mask layer on the nitride-containing layer, wherein an etch rate of the hard mask layer by means of an etchant is greater than a etch rate of the nitride-containing layer by means of the etchant; and forming a carbon-containing layer on the hard mask layer. The method further includes: patterning the carbon-containing layer and the hard mask layer to form a hard mask having an opening, thereby exposing the nitride-containing layer; removing the carbon-containing layer after forming the hard mask; and patterning the nitride-containing layer, the conductive layer, and the barrier layer using the hard mask to form a bit line and a nitride-containing component located on the bit line, wherein the nitride-containing layer is patterned after the carbon-containing layer is removed.
[0138] This disclosure also provides a semiconductor structure. The semiconductor structure includes: a substrate including an active region; a contact disposed in the active region; and a bit line electrically connected to the contact, wherein the bit line includes a first portion and a second portion disposed above the first portion, wherein a first width of the first portion is substantially equal to a second width of the second portion.
[0139] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.
[0140] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.
Claims
1. A method for manufacturing a semiconductor structure, comprising: A substrate is provided having an active region, wherein the active region includes an isolation structure and a contact adjacent to the isolation structure; A single-bit line stack is formed on the substrate; A nitride-containing layer is formed on the stack of these bit lines; A hard mask layer is formed on the nitride-containing layer, wherein the hard mask layer comprises a metal oxide, and the hard mask layer is etched by an etchant at a rate greater than the nitride-containing layer is etched by the etchant. A carbon-containing layer is formed on the hard masking layer; The carbon-containing layer is patterned to expose a portion of the hard mask layer; Remove this portion of the hard mask layer to form a hard mask with an opening, thereby exposing a portion of the nitride-containing layer; After the hard mask is formed, the carbon-containing layer is removed; as well as The nitride layer and the bit line stack are patterned using a hard mask to form a bit line on the contact and a nitride component on the bit line.
2. The method of manufacturing a semiconductor structure as claimed in claim 1, wherein the bit line is formed after the carbon-containing layer is removed.
3. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the hard mask layer does not contain carbon or nitrides.
4. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the hard mask layer comprises a metal oxide.
5. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the hard masking layer comprises zirconium dioxide, hafnium dioxide, silicon-doped hafnium dioxide, lanthanum trioxide, lanthanum aluminum oxide, zirconium silicon oxide, or a combination thereof.
6. The method for manufacturing a semiconductor structure as described in claim 1, further comprising: After the bit line is formed, remove the hard mask.
7. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the thickness of the carbon-containing layer is less than the thickness of the nitride-containing layer.
8. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the thickness of the nitride-containing layer is greater than twice the thickness of the carbon-containing layer.
9. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the thickness of the bit line stack is less than the thickness of the nitride-containing layer.
10. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the thickness of the hard mask layer is less than the thickness of the carbon-containing layer.
11. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein the formation of the bit line stack comprises: A barrier layer is formed on the substrate; as well as A conductive layer is formed on the barrier layer. The nitride-containing layer is formed on the conductive layer.
12. The method for manufacturing a semiconductor structure as claimed in claim 1, wherein patterning the stack of bit lines to form the bit lines comprises: A first portion is formed coupled to the contact; as well as A second part is formed on top of the first part. The second part is formed before the first part, and the first width of the first part is substantially equal to the second width of the second part.
13. The method of manufacturing a semiconductor structure as claimed in claim 12, wherein the first part comprises titanium nitride.
14. The method of manufacturing a semiconductor structure as claimed in claim 12, wherein the second part comprises tungsten.