Semiconductor element having trench capacitor formed on channel structure and method of manufacturing the same

Abstract

A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a substrate, a first bit line disposed on the substrate and extending along a first direction, a first word line disposed on the first bit line and extending along a second direction perpendicular to the first direction, a tunnel structure disposed on the first bit line and penetrating the first word line, and a trench capacitor disposed on the first bit line. The tunnel structure is separated from the first word line by a gate dielectric layer.

Description

Technical Field

[0001] This application claims priority to U.S. Patent Application No. 19 / 087,816 (i.e., priority date "March 24, 2025"), the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor element and a method for manufacturing a semiconductor element, and more specifically, to a semiconductor element having trench capacitance formed on a channel structure. Background Technology

[0003] Oxide semiconductor random-access memory (OSRAM) devices are random access memories that store each bit of data in separate capacitors within an integrated circuit. Typically, OSRAM is configured as an array, where each cell contains a capacitor and a transistor. In current OSRAM architectures, the capacitors are manufactured first. However, recently, OSRAM manufacturers have faced increasing challenges in improving both the performance and yield of memory cell manufacturing. For example, bit line channels may easily come into contact with word lines, potentially causing short circuits due to overlap errors in the lithography process.

[0004] The discussion in the preceding technical paragraphs is provided for background information only. The statements in the discussion in the preceding technical paragraphs are not an admission that the content disclosed in these paragraphs constitutes prior art of this disclosure, and nothing in the discussion in the preceding technical paragraphs shall be construed as an admission that any part of this application, including the parts in the discussion in the preceding technical paragraphs, constitutes prior art of this disclosure. Summary of the Invention

[0005] One aspect of this disclosure provides a semiconductor device. The semiconductor device includes: a substrate having a plurality of active regions; a word line disposed on the substrate and extending along a first direction; a conductive layer disposed on the substrate and electrically connected to the plurality of active regions of the substrate; and a word line contact disposed between the word line and the conductive layer. In a first cross-sectional view along a longitudinal axis of the word line, an upper portion of the word line contact has a tapered cross-sectional profile. A lower portion of the word line contact directly contacts the conductive layer and has a non-tapered cross-sectional profile in the first cross-sectional view. In a second cross-sectional view along a line orthogonal to the longitudinal axis of the word line, the upper portion of the word line contact has a non-tapered cross-sectional profile.

[0006] This disclosure also provides a semiconductor device. The semiconductor device includes: a substrate having a plurality of active regions disposed therein; a channel structure disposed on the substrate; a conductive layer disposed on the substrate and electrically connected to the plurality of active regions of the substrate; a word line disposed on the substrate and surrounding the channel structure; a word line contact including an insulating layer and disposed between the word line and the conductive layer; a first circuit layer disposed on the substrate; and a trench capacitor disposed on the channel structure and located above the substrate. The insulating layer includes an opening to at least partially expose the conductive layer in the first circuit layer.

[0007] This disclosure also provides a method for manufacturing a semiconductor device. The method includes: providing a substrate; forming a plurality of active regions in the substrate; forming a word line on the substrate and extending along a first direction; forming a conductive layer on the substrate and electrically connected to the plurality of active regions of the substrate; forming a word line contact between the word line and the conductive layer; forming a single word line on the substrate and extending along a second direction; forming a channel structure on the word line, wherein the channel structure penetrates the word line; forming a dielectric layer on the substrate; and forming a trench capacitor on the channel structure. The word line includes: a base, a first sidewall, and a second sidewall.

[0008] This disclosure also provides a method for manufacturing a semiconductor device. The method includes: providing a substrate having a plurality of active regions disposed therein; forming a channel structure on the substrate; forming a conductive layer on the substrate and electrically connected to the plurality of active regions of the substrate; forming a word line on the substrate to surround the channel structure; forming a word line contact, wherein the word line contact includes an insulating layer and is located between the word line and the conductive layer; forming a first circuit layer above the substrate; and forming a trench capacitor on the channel structure at a position opposite to the substrate.

[0009] Embodiments of this disclosure provide a semiconductor element for which a capacitor is ultimately formed, thereby differentiating the process and structure of this disclosure from those of the prior art. For example, in the prior art, contacts connecting a memory array to other components are manufactured by stacking several contacts and platforms, while this disclosure provides a single, integrated contact for connecting to the memory array, thus avoiding misaligned (failed) contacts. Furthermore, since the word lines of this disclosure are disposed on the substrate near the lower conductive layer, the connection resistance can be reduced by shortening the electrical path (i.e., due to the shorter word line contacts).

[0010] Regarding potential failures in the channel structure, in some embodiments, the etching process used to fabricate the channel structure may fail to create a channel of sufficient depth. In this case, the bottom surface of the channel structure may contact the word line, causing a short circuit between the channel structure and the word line. In the prior art, since the bit line is disposed on top of the channel structure, a short circuit may occur between the bit line and the word line through the failed channel structure, leading to short circuits in other channel structures connected to this bit line. In contrast, this disclosure provides a semiconductor device in which the capacitor is formed last (i.e., the capacitor is disposed on the channel structure). Due to this configuration, a short circuit may occur between the word line and the capacitor (rather than the bit line) through the failed channel structure, and therefore only one memory cell (i.e., the memory cell containing this failed channel structure) is affected. This improves the manufacturing yield and performance of the semiconductor device.

[0011] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure by modifying or designing other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0012] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the drawings in conjunction with the embodiments and claims, wherein the same element symbols represent similar elements in all the drawings.

[0013] Figure 1A This is a cross-sectional view illustrating semiconductor elements according to some embodiments of the present disclosure.

[0014] Figure 1B This is a magnified image, for example. Figure 1A Region A in the middle.

[0015] Figure 1C This is a top view, exemplified along... Figure 1B The semiconductor element cut off by the section line B-B' in the diagram.

[0016] Figure 1D This is an enlarged view illustrating other embodiments of this disclosure. Figure 1A Region A in the middle.

[0017] Figure 1E This is an enlarged view illustrating other embodiments of this disclosure. Figure 1A Region B in the text.

[0018] Figure 1F This is an enlarged view illustrating other embodiments of this disclosure. Figure 1A Region E in the diagram displays a cross-sectional view along the character line on the X-axis, specifically the vertical axis X-X', and along the Y-axis, specifically the section line Y-Y', which is orthogonal to the vertical axis X-X'.

[0019] Figure 1G This is an enlarged view illustrating other embodiments of this disclosure. Figure 1A Region E in the diagram displays a cross-sectional view along the character line on the X-axis, specifically the vertical axis X-X', and along the Y-axis, specifically the section line Y-Y', which is orthogonal to the vertical axis X-X'.

[0020] Figure 2A This is a cross-sectional view illustrating a semiconductor element according to an embodiment of the present disclosure.

[0021] Figure 2B This is a magnified image, for example. Figure 2A Region C in the middle.

[0022] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G and Figure 3H Examples are one or more operations of a method for manufacturing a semiconductor element according to some embodiments of this disclosure.

[0023] Figure 4 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0024] The reference numerals in the attached figures are explained as follows:

[0025] 1: Semiconductor components

[0026] 2: Semiconductor components

[0027] 40: Operation

[0028] 41: Operation

[0029] 42: Operation

[0030] 43: Operation

[0031] 44: Operation

[0032] 45: Operation

[0033] 46: Operation

[0034] 47: Operation

[0035] 48: Operation

[0036] 49: Operation

[0037] 110: Bit line

[0038] 111: Tungsten layer

[0039] 112: Titanium nitride layer

[0040] 115: Bit line contact

[0041] 120: Character Line

[0042] 121: Base

[0043] 123a: First extension

[0044] 123a': Curved sidewall

[0045] 123b: Second Extension

[0046] 123b': Curved sidewall

[0047] 125: Character line contact

[0048] 125L: Lower part

[0049] 125U: Upper part

[0050] 130: Channel Structure

[0051] 135: Gate dielectric layer

[0052] 140: Lower joint pad

[0053] 145: Titanium nitride layer

[0054] 150: Upper joint pad

[0055] 150W: Top width

[0056] 155: Titanium nitride layer

[0057] 160: Trench capacitor

[0058] 160W: Bottom width

[0059] 161: Conductive layer

[0060] 162: Dielectric layer

[0061] 163: Conductive layer

[0062] 164: Contact Materials

[0063] 164a: Contact layer

[0064] 164s: Sidewall

[0065] 165: Dielectric layer

[0066] 180 conductive layer

[0067] 180s: Sidewall

[0068] 210: Substrate

[0069] 211: Active Zone

[0070] 211B: Liner

[0071] 211C: Air gap

[0072] 212: Isolation Structure

[0073] 213: Air gap structure

[0074] 220: Conductive layer

[0075] 230: Conductive layer

[0076] 231: Bit line conductive segment

[0077] 232: Character line conductive segment

[0078] 240: Dielectric layer

[0079] 240a: Dielectric layer

[0080] 241: Dielectric layer

[0081] 242: Dielectric layer

[0082] 243: Dielectric layer

[0083] 244: Dielectric layer

[0084] 245: Dielectric layer

[0085] 245S: Side surface

[0086] 245TS: Top surface

[0087] 246: Dielectric layer

[0088] 247: Dielectric layer

[0089] 248: Dielectric layer

[0090] 248a: Sidewall

[0091] 250: Contact

[0092] 310: Indium Tin Oxide Layer

[0093] 320: Indium Tin Oxide Layer

[0094] 410: Bit line

[0095] 410t: Open

[0096] 411: Conductive layer

[0097] 412: Conductive layer

[0098] 413: Dielectric layer

[0099] 414: Conductive layer

[0100] 420: Character Line

[0101] 425: Character line contact

[0102] 425a: Partial

[0103] 425b: Partial

[0104] 430: Channel Structure

[0105] 435: Gate dielectric layer

[0106] 440: Joint pad

[0107] 445: Titanium nitride layer

[0108] 460: Trench capacitor

[0109] 461: Conductive layer

[0110] 462: Dielectric layer

[0111] 463: Conductive layer

[0112] 464: Contact Materials

[0113] 510: Substrate

[0114] 511: Conductive Stack

[0115] 512: Isolation Structure

[0116] 520: Conductive layer

[0117] 530: Conductive layer

[0118] 541: Dielectric layer

[0119] 542: Dielectric layer

[0120] 543: Dielectric layer

[0121] 544: Dielectric layer

[0122] 545: Dielectric layer

[0123] 546: Dielectric layer

[0124] 550: Contact

[0125] 551: Column

[0126] 552: Column

[0127] 553: Platform

[0128] 554: Column

[0129] 555: Platform

[0130] 556: Platform

[0131] 557: Platform

[0132] 558: Column

[0133] 570: Nitride layer

[0134] 580: Nitride layer

[0135] 590: Upper conductive layer

[0136] 610: Indium Tin Oxide Layer

[0137] 620: Indium Tin Oxide Layer

[0138] 2411: Dielectric layer

[0139] 2412 dielectric layer

[0140] 5441: Dielectric layer

[0141] 5442: Dielectric layer

[0142] A: Area

[0143] B: Region

[0144] C: Region

[0145] E: Area

[0146] D1: Lower diameter

[0147] D2: Upper diameter

[0148] IL: Insulating layer

[0149] TC: Groove Corner

[0150] VO: Opening

[0151] W1: Width

[0152] W2: Width Detailed Implementation

[0153] The embodiments or examples of this disclosure shown in the drawings are now described using specific language. It should be understood that this is not intended to limit the scope of this disclosure. Any changes or modifications to the described embodiments, and any further application of the principles described herein, should be considered as would normally occur to those skilled in the art to which this disclosure pertains. Component symbols may be repeated throughout the embodiments, but this does not necessarily mean that one(s) feature of one embodiment is applicable to another embodiment, even if they share the same component symbols.

[0154] It should be understood that although the terms first, second, third, etc., may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections should not be limited by these terms. Rather, these terms are used only to distinguish one component, part, region, layer, or section from another. Therefore, the first component, part, region, layer, or section discussed below may be referred to as the second component, part, region, layer, or section without departing from the teachings of this disclosure.

[0155] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the concept of the invention. As used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context otherwise requires. It should be understood that the terms “comprising” and “including,” when used in this specification, indicate the presence of stated features, integers, steps, operations, components, or elements, but do not preclude the presence or addition of a further feature, integer, step, operation, component, element, or group thereof.

[0156] It should be noted that the term "about," used to modify the amount of ingredients, components, or reactants in this disclosure, refers, for example, to numerical variations that may occur through typical measurement and liquid handling procedures used to prepare concentrates or solutions. Furthermore, variations may occur due to unintentional errors in the measurement procedures, differences in the manufacture, source, or purity of the ingredients used to prepare the composition or to carry out the method, etc. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, or 1% of the reported value.

[0157] Figure 1AThis is a cross-sectional view illustrating a semiconductor element 1 according to some embodiments of the present disclosure. Semiconductor element 1 may include a memory, memory element, memory die, memory wafer, or other component. Semiconductor element 1 may be part of a memory, memory element, memory die, or memory wafer. For example, the memory may be dynamic random-access memory (DRAM). In some embodiments, the dynamic random-access memory may be double-data-rate fourth-generation (DDR4) dynamic random-access memory. In some embodiments, the memory may be oxide semiconductor random-access memory (OSRAM). In some embodiments, the memory includes one or more memory cells, memory bits, or memory blocks.

[0158] Semiconductor element 1 includes a substrate 210, conductive layers 220 and 230, dielectric layers 241, 242, 243, 244, 245, 246, and 247, bit lines 110, word lines 120, word line contacts 125, channel structure 130, lower bonding pad 140, upper bonding pad 150, trench capacitor 160, contact layer 164a, conductive layer 180, dielectric layer 248, and contact 250.

[0159] See Figure 1AThe substrate 210 may be a semiconductor substrate, such as a host semiconductor, a semiconductor-on-insulator (SOI) substrate, or a similar substrate. The substrate 210 may include elemental semiconductors, such as single-crystal, polycrystalline, or amorphous silicon or germanium; compound semiconductor materials, including at least one of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and indium antimonide; alloy semiconductor materials, including at least one of silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and gallium indium arsenide phosphide (GaInAsP); any other suitable materials; or combinations thereof. In some embodiments, the alloy semiconductor substrate may be a silicon-germanium alloy having gradient silicon-germanium characteristics, wherein the silicon to germanium composition changes from one ratio at one location of the gradient silicon-germanium characteristics to another ratio at another location. In some embodiments, the silicon-germanium alloy is formed on a silicon substrate. In some embodiments, the silicon-germanium alloy may be mechanically strained by another material in contact with the silicon-germanium alloy. In some embodiments, substrate 210 may be multilayered, or substrate 210 may include a multilayer compound semiconductor structure.

[0160] In some embodiments, the substrate 210 may include an isolation structure 212 and a plurality of active regions. The relative relationship between the isolation structure 212 and the substrate 210 is illustrated in detail in... Figure 3A In some embodiments, the isolation structure 212 may include materials such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon nitride oxide (N2OSi2), or other suitable materials. The active regions may function, for example, as channels for electrical connections. In some embodiments, multiple active regions may be separated by the isolation structure 212.

[0161] A conductive layer 220 may be disposed on a substrate 210. In some embodiments, the conductive layer 220 may be disposed on an isolation structure 212 of the substrate 210. The conductive layer 220 may be electrically connected to an active region (not shown) of the substrate 210. The conductive layer 220 may be patterned to expose a portion of the substrate 210. Figure 1A (not shown).

[0162] The conductive layer 220 may include metals, such as tungsten (W), copper (Cu), ruthenium (Ru), iridium (Ir), nickel (Ni), osmium (Os), rhodium (Rh), aluminum (Al), molybdenum (Mo), cobalt (Co), alloys thereof, combinations thereof, or other metallic materials with suitable resistance and gap-filling capabilities.

[0163] In some embodiments, conductive layer 230 may be formed on conductive layer 220. Conductive layer 230 may be electrically connected to the active region of substrate 210 via conductive layer 220. Conductive layer 230 may be patterned to correspond to the design of conductive layer 220.

[0164] The conductive layer 230 may be formed of a material similar to or the same as that of the conductive layer 220. In some embodiments, the conductive layer 220 may include copper (Cu), while the conductive layer 230 may include tungsten (W).

[0165] Semiconductor element 1 may include a transistor array disposed on substrate 210 (e.g., as shown in region A). The transistor array may include bit line 110, lower bonding pad 140, channel structure 130, word line 120, and upper bonding pad 150.

[0166] For details on the transistor array, please refer to the following. Figure 1A , Figure 1B and Figure 1C . Figure 1B This is a magnified image, for example. Figure 1A Region A in the middle. Figure 1C This is a top view, exemplified along... Figure 1B For clarity, the semiconductor element 1 cut by the cross-section BB in the figure has its channel structure 130 and gate dielectric layer 135 omitted.

[0167] Semiconductor element 1 may include multiple bit lines 110 disposed on substrate 210. The bit lines 110 extend along a Y-axis perpendicular to the X and Z axes. The bit lines 110 may be arranged parallel to each other. In some embodiments, the number of bit lines 110 may be 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, or more. The bit lines 110 may be electrically connected to the active region of substrate 210.

[0168] Bit line 110 may include a conductive material, such as tungsten, copper, aluminum, tantalum, tantalum nitride, titanium, titanium nitride, similar materials, and / or combinations thereof. See also Figure 1B For example, bit line 110 may include a titanium nitride layer 112 and a tungsten layer 111 disposed on the titanium nitride layer 112 and on the opposite side of the substrate 210. The titanium nitride layer 112 may have a minimum thickness. In some embodiments, the thickness of the titanium nitride layer 112 may be less than the thickness of the tungsten layer 111.

[0169] In some embodiments, the bit line 110 may taper towards the channel structure 130. That is, the bit line 110 may have an upper width that is smaller than its lower width. For example, the width of the titanium nitride layer 112 may be greater than the width of the tungsten layer 111.

[0170] During manufacturing, a titanium nitride layer 112 or a tungsten layer 111 can be formed by a removal operation. In some embodiments, the removal operation can be an etching process, such as anisotropic etching or isotropic etching.

[0171] See Figure 1B The lower bonding pads 140 may be disposed on the bit lines 110, wherein each lower bonding pad 140 corresponds to a corresponding bit line 110. In some embodiments, each lower bonding pad 140 may partially cover the corresponding bit line 110. Specifically, the projection of the lower bonding pad 140 on the substrate 210 may partially overlap with the projection of the corresponding bit line 110 on the substrate 210.

[0172] Figure 1C This is a top view, exemplified along... Figure 1B Semiconductor element 1 is shown in section BB. See also... Figure 1C Viewed from the top view, the lower engagement pad 140 may be quadrilateral. In some embodiments, the lower engagement pad 140 may be formed as a parallelogram. For example, the lower engagement pad 140 may have a rhomboid shape. The lower engagement pad 140 may be partially on the bit line 110, which is positioned along the Y-axis. For example, half of each lower engagement pad 140 may overlap with a bit line 110.

[0173] The lower bonding pad 140 may comprise a metal, such as tungsten, copper, ruthenium, iridium, nickel, osmium, rhodium, aluminum, molybdenum, cobalt, alloys thereof, combinations thereof, or other metallic materials having suitable resistance and gap-filling capabilities. Preferably, the lower bonding pad 140 may be formed of tungsten or its alloys.

[0174] See you again Figure 1B The lower bonding pad 140 can contact the bit line 110 via the titanium nitride layer 145. In some embodiments, each lower bonding pad 140 may include a titanium nitride layer 145. Furthermore, the titanium nitride layer 145 may have a minimum thickness such that the thickness of the titanium nitride layer 145 is less than the thickness of the lower bonding pad 140.

[0175] In some embodiments, the lower bonding pad 140 may taper towards the channel structure 130, with the upper width being smaller than the lower width. For example, the width of the titanium nitride layer 145 may be greater than the width of the lower bonding pad 140.

[0176] During manufacturing, the titanium nitride layer 145 or the lower bonding pad 140 can be formed by a removal operation. In some embodiments, the removal operation of the lower bonding pad 140 can be performed partially on the bit line 110. A portion of the bit line 110 can be removed to allow the side surface of the lower bonding pad 140 to smoothly connect to the top surface of the bit line 110. In some embodiments, the bit line 110 having this structure can be separated from adjacent (e.g., left-hand) lower bonding pads 140 to avoid short circuits.

[0177] See Figure 1B An indium tin oxide (ITO) layer 320 may be disposed on the lower bonding pad 140. In some embodiments, the indium tin oxide layer 320 may be disposed between the channel structure 130 and the lower bonding pad 140. Furthermore, the indium tin oxide layer 320 may have a minimum thickness. For example, the thickness of the indium tin oxide layer 320 may be less than the thickness of the lower bonding pad 140.

[0178] The dielectric layer 2411 can be disposed on the substrate 210 and cover the bit line 110, the lower bonding pad 140 and the indium tin oxide layer 320. That is, the bit line 110, the lower bonding pad 140 and the indium tin oxide layer 320 can be surrounded by the dielectric layer 2411.

[0179] In some embodiments, dielectric layer 2411 may include silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low dielectric constant dielectric materials (k<4) or other suitable materials.

[0180] Channel structure 130 may be disposed on lower bonding pad 140 via indium tin oxide layer 320. In some embodiments, channel structure 130 may be disposed on and electrically connected to bit line 110. In some embodiments, channel structure 130 may extend through word line 120. Each channel structure 130 may correspond to a corresponding lower bonding pad 140. In some embodiments, each channel structure 130 may be aligned with the corresponding lower bonding pad 140. Specifically, the projection of channel structure 130 on substrate 210 may overlap with the projection of the corresponding lower bonding pad 140 on substrate 210.

[0181] Each channel structure 130 may correspond to a corresponding bit line 110. In some embodiments, each channel structure 130 may partially cover the corresponding bit line 110. Specifically, the projection of the channel structure 130 on the substrate 210 may partially overlap with the projection of the bit line 110 on the substrate 210.

[0182] In some embodiments, the channel structure 130 may taper towards the bit line 110 and along the Z-axis away from the trench capacitor 160. The channel structure 130 may have an upper diameter D2 adjacent to the upper bonding pad 150, wherein the upper diameter D2 is larger than the lower diameter D1 adjacent to the lower bonding pad 140. For example, the upper diameter D2 of the channel structure 130 may be larger than the lower diameter D1.

[0183] The material of channel structure 130 may include amorphous semiconductors, polycrystalline semiconductors, and / or metal oxides. Semiconductors may include, but are not limited to, germanium (Ge), silicon (Si), tin (Sn), and antimony (Sb). Metal oxides may include, but are not limited to, indium oxide; tin oxide; zinc oxide; two-component metal oxides, such as indium zinc-based oxides (InZn-based), tin zinc-based oxides (SnZn-based), aluminum zinc-based oxides (AlZn-based), zinc magnesium-based oxides (ZnMg-based), tin magnesium-based oxides (SnMg-based), indium magnesium-based oxides (InMg-based), or indium gallium-based oxides (InGa-based); three-component metal oxides, such as indium gallium zinc-based oxides (InGa-based). Indium GaZn-based oxides (also known as IGZO), aluminum gallium zinc oxides (AlGaZn-based oxides), tin aluminum zinc oxides (SnAlZn-based oxides), indium hafnium zinc oxides (InHfZn-based oxides), indium lanthanum zinc oxides (InLaZn-based oxides), indium cerium zinc oxides (InCeZn-based oxides), indium praseodymium zinc oxides (InPrZn-based oxides), indium neodymium zinc oxides (InNdZn-based oxides), indium samarium zinc oxides (InS... Indium europium zinc oxide (InEuZn-based), indium gadolinium zinc oxide (InGdZn-based), indium terbium zinc oxide (InTbZn-based), indium dysprosium zinc oxide (InDyZn-based), indium holmium zinc oxide (InHoZn-based), indium erbium zinc oxide (InErZn-based), indium thallium zinc oxide (InTmZn-based), indium ytterbium zinc oxide (InYbZn-based) The oxides may be indium-zinc oxides or indium-Lu-Zn-based oxides; and four-component metal oxides, such as indium-tin-gallium-zinc oxides (InSnGaZn-based oxides), indium-hafnium-gallium-zinc oxides (InHfGaZn-based oxides), indium-aluminum-gallium-zinc oxides (InAlGaZn-based oxides), indium-tin-aluminum-zinc oxides (InSnAlZn-based oxides), indium-tin-hafnium-zinc oxides (InSnHfZn-based oxides), or indium-hafnium-aluminum-zinc oxides (InHfAlZn-based oxides). However, this disclosure is not limited to this aspect.

[0184] See Figure 1B A gate dielectric layer 135 may surround the channel structure 130. The gate dielectric layer 135 may be formed between the channel structure 130 and the word line 120. In some embodiments, the channel structure 130 may be separated from the word line 120 by the gate dielectric layer 135.

[0185] In some embodiments, the gate dielectric layer 135 may include silicon oxide (SiO2). x ), silicon nitride (Si x N y The gate dielectric layer 135 may include a dielectric material, such as a high-dielectric-constant dielectric material, or a combination thereof. In some embodiments, the gate dielectric layer 135 may include a dielectric material, such as a high-dielectric-constant dielectric material. The high-dielectric-constant dielectric material may have a dielectric constant (k value) greater than 4. The high-dielectric-constant dielectric material may include hafnium dioxide (HfO2), zirconium dioxide (ZrO2), lanthanum trioxide (La2O3), yttrium trioxide (Y2O3), aluminum oxide (Al2O3), titanium dioxide (TiO2), or other suitable materials. Other suitable materials are also within the scope of this disclosure.

[0186] Character line 120 can be disposed on dielectric layer 2411. Character line 120 can extend along the X-axis. See also Figure 1C The character line 120 can extend along a direction perpendicular to the bit line 110 (Y-axis). The character line 120 can overlap with the lower bonding pad 140. Specifically, the character line 120 can overlap with the channel structure 130 (not shown in the diagram). Figure 1C (Middle) overlap, wherein the channel structure 130 is aligned with the lower joint pad 140.

[0187] See Figure 1C Viewed from the top, character lines 120 and bit lines 110 are orthogonal. Each lower bonding pad 140 may overlap with the corresponding character line 120 and may partially overlap with the corresponding bit line 110. The lower bonding pad 140 may have a quadrilateral shape, but is not limited thereto. In some embodiments, the lower bonding pad 140 may also include a triangular, pentagonal, or hexagonal shape.

[0188] See Figure 1B The word line 120 may surround the channel structure 130. The word line 120 may cover the side surface of the channel structure 130. The word line 120 may contact the gate dielectric layer 135. In some embodiments, the semiconductor element 1 may include one or more word lines 120.

[0189] In some embodiments, the etching process used to fabricate the channel structure 130 may fail to create a channel of sufficient depth. In this case, the bottom surface of the channel structure 130 may come into contact with the word line 120, resulting in a short circuit between the channel structure 130 and the word line 120. In a comparative embodiment, if a bit line is provided on the channel structure, a short circuit may occur between the bit line and the word line due to a faulty channel structure, causing other channel structures connected to the same bit line to also fail. In contrast, this disclosure provides a semiconductor device in which the capacitor is formed last (i.e., the capacitor is disposed on the channel structure). With this configuration, a short circuit may occur between the word line 120 and the capacitor 160 due to a faulty channel structure, but only one memory cell (containing the faulty channel structure) will be affected. As a result, the manufacturing yield of the semiconductor device is improved.

[0190] See Figure 1A The word line 120 may extend beyond the transistor array. In some embodiments, the semiconductor element 1 may include a word line contact 125 disposed between the word line 120 and the conductive layer 230. The word line contact 125 may penetrate the dielectric layer 2411 and connect the word line 120 to the conductive layer 230. The word line contact 125 may be separated from the channel structure 130.

[0191] The character line contact 125 may include metals, such as tungsten, copper, ruthenium, iridium, nickel, osmium, rhodium, aluminum, molybdenum, cobalt, their alloys, combinations thereof, or other metallic materials with suitable resistance and gap-filling capabilities.

[0192] Furthermore, according to other embodiments of the present invention, the character line contact 125 may have a different structure than the previously mentioned character line contact 125. Figure 1F and Figure 1G Example Figure 1A A magnified view of region E in the image is used to show these different structures.

[0193] like Figure 1FAs shown, the character line contact 125 may include a base 121, a first extension 123a (or sidewall 123a), and a second extension 123b (or sidewall 123b). The upper portion 125U of the character line contact 125 has a tapered profile in a first cross-sectional view along the longitudinal axis X-X' of the character line 120 in the X-axis, while the lower portion 125L of the character line contact 125 directly contacts the conductive layer 230 and has a non-tapered profile in the first cross-sectional view. Specifically, the tapered profile of the upper portion 125U of the character line contact 125 gradually tapers from the character line 120 toward the conductive layer 230. In other words, the tapered profile of the upper portion 125U of the character line contact 125 includes curved sidewalls 123a' and 123b' that curve inward toward the conductive layer 230. Furthermore, in a second cross-sectional view along line Y-Y', which is orthogonal to the vertical axis X-X' of the character line 120, the upper portion 125U of the character line contact 125 has a non-tapered cross-sectional profile. The width W2 of the conductive layer 230 is greater than the width W1 of the lower portion 125L of the character line contact 125.

[0194] The material of the character line contact 125 is similar to or the same as the material used to form the conductive layer 230, and its description will not be repeated here. In some embodiments, the character line contact 125 may be formed by creating a plurality of openings, a plurality of first grooves, and a plurality of second grooves in the dielectric layer 241; depositing a conductive material on the top surface of the dielectric layer 241 to fill the openings, the first grooves, and the second grooves; and polishing the conductive material to form the character line contact 125. A base 121 may be formed in the opening, a first extension 123a (or sidewall 123a) of the character line contact 125 may be formed in the first groove, and a second extension 123b (or sidewall 123b) may be formed in the second groove. The conductive material may be deposited using chemical vapor deposition, physical vapor deposition, atomic layer deposition, metal-organic chemical vapor deposition, sputtering, electroplating, or other suitable processes. In addition, the conductive material may be polished using a chemical mechanical polishing process.

[0195] like Figure 1G As shown, the structure of character line contact 125 is similar to... Figure 1F The structure of the character line in the middle is similar to that of 125, the difference is that Figure 1G The structure of the character line contact 125 also includes an insulating layer IL that covers the first extension 123a (or sidewall 123a), the second extension 123b (or sidewall 123b), and the side surface of the base 121. The insulating layer IL may include an opening VO to at least partially expose the corresponding conductive layer 230 (e.g., the first circuit layer) in the dielectric layer 241.

[0196] The insulating layer IL can be formed from materials such as silicon oxide, silicon nitride, silicon oxynitride, or tetraethyl orthosilicate. The insulating layer IL can have a thickness between about 50 nm and about 200 nm. Alternatively, in some embodiments, the insulating material IL can be formed from materials such as epoxy resin or poly(p-xylene). The insulating layer IL can have a thickness between about 1 μm and about 5 μm.

[0197] After the opening, the first groove, and the second groove are formed in the dielectric layer 241, and in order to form Figure 1F An insulating layer IL is formed before the deposition of conductive material at the character line contact 125. The insulating layer IL can be formed by compliantly depositing an insulating material within the opening, the first groove, and the second groove. Subsequently, a punchetch process can be performed to remove this insulating material layer formed on the bottom surface of the opening. After the punchetch, this insulating material layer can be transformed into the insulating layer IL. The opening VO can be formed at the bottom of the opening to at least partially expose the corresponding conductive layer 230 (e.g., the first circuit layer) in the dielectric layer 241.

[0198] See Figure 1B An upper bonding pad 150 is disposed on the channel structure 130. Each upper bonding pad 150 may correspond to a corresponding channel structure 130. In some embodiments, each upper bonding pad 150 may be aligned with a corresponding channel structure 130. Specifically, the projection of the upper bonding pad 150 on the substrate 210 may overlap with the projection of the channel structure 130 on the substrate 210.

[0199] In some embodiments, each upper engagement pad 150 may be aligned with a corresponding lower engagement pad 140. In other words, the upper engagement pad 150 may cover the lower engagement pad 140. Furthermore, the upper engagement pad 150 may have a similar shape and / or material to the lower engagement pad 140.

[0200] In some embodiments, the upper bonding pad 150 may be formed of a material similar to that of the lower bonding pad 140.

[0201] In some embodiments, the upper bonding pad 150 may be connected to the channel structure 130 via a titanium nitride layer 155. Each upper bonding pad 150 may have a titanium nitride layer 155. In some embodiments, the titanium nitride layer 155 may be similar to a titanium nitride layer 145.

[0202] In some embodiments, the upper bonding pad 150 may taper gradually from the channel structure 130 toward the trench capacitor 160. Specifically, the upper bonding pad 150 may have an upper width 150W that is smaller than the lower width. For example, the width of the titanium nitride layer 155 may be greater than the width of the upper bonding pad 150.

[0203] During manufacturing, the titanium nitride layer 155 or the upper bonding pad 150 can be formed by a removal operation. In some embodiments, the removal operation can be an etching process, such as anisotropic etching or isotropic etching.

[0204] See Figure 1B An indium tin oxide layer 310 may be disposed on the channel structure 130. In some embodiments, the indium tin oxide layer 310 may be disposed between the channel structure 130 and the upper bonding pad 150. In some embodiments, the indium tin oxide layer 310 may be similar to the indium tin oxide layer 320.

[0205] In some embodiments, the indium tin oxide (ITO) layer 310 and the ITO layer 320 may form a source / drain structure. The channel structure 130 may connect the ITO layer 310 to the ITO layer 320 and be configured to turn on and off in response to signals (e.g., voltage or current) transmitted from the word line 120 through the gate dielectric layer 135.

[0206] Dielectric layer 2412 may be disposed on word line 120 and may cover upper bonding pad 150, indium tin oxide layer 310, and channel structure 130. In other words, upper bonding pad 150, indium tin oxide layer 310, and channel structure 130 may be surrounded by dielectric layer 2412. In some embodiments, channel structure 130 may penetrate dielectric layer 2411, dielectric layer 2412, and word line 120. In some embodiments, dielectric layer 2412 may be the same as or similar to dielectric layer 2411. In some embodiments, such as Figure 1D As shown, dielectric layer 2412 includes an air gap structure 213 disposed between a pair of upper bonding pads 150. Air gap structure 213 has an air gap 211C closed by liner 211B, as... Figure 1D As shown. In some embodiments, the air gap structure 213 can be formed by depositing an energy removable block within the dielectric layer 2412, wherein the energy removable block is formed of an energy removable material. Subsequently, a heat treatment process can be performed to transform the energy removable block into the air gap structure 213, which includes an air gap 211C closed by the liner 211B.

[0207] Dielectric layers 2411 and 2412 can be formed in different manufacturing steps. Dielectric layers 2411 and 2412 can together constitute dielectric layer 241 (e.g., Figure 1A As shown), the transistor array and word line contact 125 are surrounding it.

[0208] See Figure 1A Dielectric layers 242, 243, 244, and 245 may be disposed on dielectric layer 241. Dielectric layers 242, 243, 244, and 245 may be disposed on a transistor array. Dielectric layers 242, 243, 244, and 245 may be formed in different manufacturing steps or in one step. In some embodiments, dielectric layers 242, 243, 244, and 245 may be formed of the same or similar materials. In another embodiment, dielectric layers 242, 243, 244, and 245 may be formed of the same material with different concentrations. Dielectric layers 242, 243, 244, and 245 may be formed of a material similar to dielectric layer 241.

[0209] A trench capacitor 160 may be disposed on the channel structure 130. In some embodiments, the trench capacitor 160 may penetrate dielectric layers 242, 243, 244, and 245 and be connected to the channel structure 130. The trench capacitor 160 may taper towards the channel structure 130. In some embodiments, the trench capacitor 160 may be electrically connected to the channel structure 130 via an upper bonding pad 150 and an indium tin oxide layer 310. In some embodiments, the upper width 150W of the upper bonding pad 150 may be equal to or less than the lower width 160W of the trench capacitor 160 adjacent to the upper bonding pad 150.

[0210] Each trench capacitor 160 can correspond to a corresponding channel structure 130 in the transistor array, which means that the trench capacitors 160 are arranged in an array. In some embodiments, each trench capacitor 160 can be referred to as a capacitor cell.

[0211] See Figure 1B The trench capacitor 160 may include a multilayer stack consisting of conductive layers 161 and 163, a dielectric layer 162, and a contact material 164. During the fabrication of the trench capacitor 160, portions of dielectric layers 242, 243, 244, and 245 may be removed to form multiple trenches. A multilayer stack may then be formed within the trenches, followed by deposition of the contact material 164.

[0212] Conductive layer 161 may be disposed on dielectric layer 245 (see Figure 1AThe conductive layer 161 may cover the side surfaces of dielectric layers 242, 243, 244, and 245. Furthermore, a portion of the conductive layer 161 may be disposed on the upper bonding pad 150. The lower side of the conductive layer 161 may be coplanar with the top surface of the upper bonding pad 150. In some embodiments, the conductive layer 161 may contact the upper bonding pad 150.

[0213] Dielectric layer 162 may be disposed on conductive layer 161. In some embodiments, dielectric layer 162 may be disposed on dielectric layer 245 (see Figure 1A Dielectric layer 162 may be disposed within the trench. Dielectric layer 162 may cover the side surfaces of dielectric layers 242, 243, 244, and 245. A portion of dielectric layer 162 may be disposed on the upper bonding pad 150. In some embodiments, the lower side of dielectric layer 162 may be coplanar with the top surface of conductive layer 161.

[0214] In some embodiments, the conductive layer 163 may be disposed on the dielectric layer 162. The conductive layer 163 may be disposed on the dielectric layer 245 (see [link]). Figure 1A The conductive layer 163 may be disposed within the trench. The conductive layer 163 may cover the side surfaces of dielectric layers 242, 243, 244, and 245. Furthermore, a portion of the conductive layer 163 may be disposed on the upper bonding pad 150. In some embodiments, the lower side of the conductive layer 163 may be coplanar with the top surface of the dielectric layer 162.

[0215] exist Figure 1B The trench capacitor 160 in the above embodiment comprises two conductive layers (conductive layer 161 and conductive layer 163) and a dielectric layer 162. However, in other embodiments, the multilayer stack of the trench capacitor 160 may include additional conductive and dielectric layers. For example, the trench capacitor 160 may have two conductive layers (conductive layer 161 and conductive layer 163) and two dielectric layers (dielectric layer 162 and dielectric layer 165), as shown below. Figure 1E As shown. The trench capacitor 160 is a multilayer stack. Figure 1B and Figure 1E There are many similarities between them; therefore, descriptions of similar features will not be repeated. The main differences are as follows.

[0216] See Figure 1A and Figure 1EIn other embodiments, conductive layer 161 may be disposed within the trench. Conductive layer 161 may cover the side surfaces of dielectric layers 242, 243, and 244, and may partially cover the side surface of dielectric layer 245. Dielectric layer 162 may be disposed above dielectric layer 245 and may cover conductive layer 161 within the trench. Dielectric layer 165 may be disposed above dielectric layer 245 and at a trench corner TC, and may partially cover the top surface 245TS and side surface 245S of dielectric layer 245. Conductive layer 163 may be disposed above dielectric layers 245 and 165, and may cover the side surfaces of dielectric layers 242, 243, 244, and 245.

[0217] See Figure 1B and Figure 1E In some embodiments, conductive layers 161 and 163 may have the same thickness as dielectric layers 162 and 165. In another embodiment, the thicknesses of conductive layers 161 and 163 may differ from those of dielectric layers 162 and 165. The thickness of conductive layer 161 may be equal to or greater than the thickness of dielectric layer 162. The thickness of dielectric layer 162 may be equal to or greater than the thickness of conductive layer 163. The thickness of conductive layer 163 may be equal to or greater than the thickness of dielectric layer 165.

[0218] See Figure 1B and Figure 1E In some embodiments, conductive layers 161 and 163 may be formed of the same material. For example, the material of conductive layers 161 and 163 may include titanium nitride (TiN). In some embodiments, dielectric layers 162 and 165 may be formed of a high dielectric constant dielectric material. For example, dielectric layer 162 may include zirconium oxide (ZrO2), titanium oxide (TiO2), or a combination thereof.

[0219] See Figure 1A , Figure 1B and Figure 1E The contact material 164 of the trench capacitor 160 can be disposed in multiple layers of stack (including...). Figure 1B The conductive layer 161, conductive layer 163, and dielectric layer 162, or including the conductive layer 161, conductive layer 163, and dielectric layer 162, are included in the structure. Figure 1E The conductive layers 161 and 163, and dielectric layers 162 and 165 are disposed on the conductive layers 161 and 163, and dielectric layers 162 and 165, respectively. In some embodiments, contact material 164 may be disposed within a trench defined by the multilayer stack. Contact material 164 may cover the side surface of the conductive layer 163. In some embodiments, contact material 164 may be formed of a semiconductor material. For example, contact material 164 may be formed of polysilicon. In some embodiments, the contact material 164 of the trench capacitor 160 may be configured to receive voltage.

[0220] See Figure 1A The contact material 164 can form a contact layer 164a disposed on the dielectric layer 245. The contact layer 164a can be disposed on the trench capacitor 160, opposite to the channel structure 130. In some embodiments, the contact layer 164a may include sidewalls 164s. The sidewalls 164s may be non-planar. In some embodiments, the sidewalls 164s may be curved.

[0221] In some embodiments, a conductive layer 180 may be disposed on a contact layer 164a. In some embodiments, the lower side of the conductive layer 180 may be coplanar with the top surface of the contact layer 164a. The width of the conductive layer 180 may be greater than the width of the contact layer 164a. The conductive layer 180 may have sidewalls 180s. The sidewalls 164s of the contact layer 164a may be recessed from the sidewalls 180s of the conductive layer 180. In some embodiments, the conductive layer 180 and the contact layer 164a may be configured to receive voltage.

[0222] The conductive layer 180 may include metals, such as tungsten, copper, ruthenium, iridium, nickel, osmium, rhodium, aluminum, molybdenum, cobalt, their alloys, combinations thereof, or other metallic materials with suitable resistance and gap-filling capabilities.

[0223] A dielectric layer 248 may be disposed on the conductive layer 180. The dielectric layer 248 may have the same width as the conductive layer 180. In some embodiments, the dielectric layer 248 may have sidewalls 248a. The sidewalls 248a of the dielectric layer 248 may be coplanar with the sidewalls 180a. In some embodiments, the dielectric layer 248 may be formed of a material similar to that of the dielectric layer 241.

[0224] In some embodiments, the contact layer 164a, conductive layer 180, and dielectric layer 248 may be referred to as a top cell plate (TCP). In some embodiments, after the contact layer 164a, conductive layer 180, and dielectric layer 248 are formed on the dielectric layer 245, the contact layer 164a, conductive layer 180, and dielectric layer 248 may be removed, such that the peripheral regions of the contact layer 164a, conductive layer 180, and dielectric layer 248 (i.e., the regions away from the trench capacitor 160, in other words...) Figure 1A The right side of the text can be removed.

[0225] Dielectric layer 246 may be disposed on dielectric layer 245. Dielectric layer 246 may be disposed on conductive layer 180. Dielectric layer 246 may cover dielectric layer 248, conductive layer 180, and contact layer 164a. That is, the side surfaces of dielectric layer 248, conductive layer 180, and contact layer 164a may be covered by dielectric layer 246. In some embodiments, dielectric layer 246 may be formed of a material similar to dielectric layer 248 (i.e., similar to dielectric layer 241).

[0226] A dielectric layer 247 may be disposed on the dielectric layer 246. In some embodiments, the dielectric layer 247 may be formed of a material similar to that of the dielectric layer 241. In some embodiments, dielectric layers 241, 242, 243, 244, 245, 246, 247, and 248 may be formed of the same material with different concentrations.

[0227] See Figure 1A Contact 250 may be disposed on and electrically connected to conductive layer 230. In some embodiments, contact 250 may penetrate dielectric layers 241, 242, 243, 244, 245, 246, and 247. Contact 250 is separated from channel structure 130. In some embodiments, contact 250 may be a monolithic structure.

[0228] Contact 250 can be electrically connected to character line contact 125 via conductive layers 220 and 230. Character line 120 is electrically connected to contact 250 via character line contact 125 and conductive layers 220 and 230. Contact 250 can connect conductive layer 230 to an upper conductive layer (not shown) for electrical connection.

[0229] In this disclosure, the transistor array (or word lines) is disposed near the lower conductive layer (e.g., conductive layer 220 and conductive layer 230), which can reduce the resistance of the connection by means of the shortened electrical path (i.e., due to the shorter word line contact 125).

[0230] In the comparative embodiment, the contacts connecting the memory array of the semiconductor device to other devices are manufactured by stacking multiple contacts and stages. If one or more contacts and stages are not aligned during manufacturing, a defect known as a "missed contact" may occur. Missed contacts can jeopardize the function of the semiconductor device. On the other hand, this disclosure provides a contact 250, which is a monolithic structure for connecting the memory array to other devices, thus avoiding missed contacts.

[0231] Figure 2AThis is a cross-sectional view illustrating a semiconductor element 2 according to some embodiments of the present disclosure. In some embodiments, the semiconductor element 2 may include a capacitor formed prior to the formation of other elements.

[0232] Semiconductor element 2 includes substrate 510, conductive layers 520 and 530, dielectric layers 541, 542, 543, 544, 545 and 546, bit lines 410, word lines 420, word line contacts 425, channel structures 430, bonding pads 440, trench capacitors 460, contacts 550, and nitride layers 570 and 580.

[0233] See Figure 2A A substrate 510 may be provided. The substrate 510 may be similar to the substrate 210, therefore a detailed description of the substrate 510 is omitted. In some embodiments, the substrate 510 may include a plurality of active regions. The active regions may function appropriately, for example, as channels for electrical connections.

[0234] The substrate 510 may include a conductive stack 511 for connecting to the active regions of the substrate 510. In some embodiments, the substrate 510 may include an isolation structure 512. In some embodiments, a plurality of active regions may be separated by the isolation structure 512.

[0235] A conductive layer 520 may be disposed on a substrate 510. The conductive layer 520 may be a patterned circuit layer. In some embodiments, the conductive layer 520 may be disposed on an isolation structure 512 and on a conductive stack 511 of the substrate 510. In some embodiments, the conductive layer 520 may be electrically connected to an active region (not shown) of the substrate 510. The conductive layer 520 may be similar to conductive layer 220, therefore a detailed description of the conductive layer 520 is omitted.

[0236] The conductive layer 530 may be disposed on the conductive layer 520. The conductive layer 530 may be similar to the conductive layer 230, therefore a detailed description of the conductive layer 530 is omitted.

[0237] A nitride layer 570 may be disposed on the conductive layer 530. In some embodiments, the nitride layer 570 may conform to the conductive layers 520 and 530. That is, the nitride layer 570 may cover the top surfaces of the conductive layers 520 and 530. In some embodiments, the material of the nitride layer 570 may include silicon nitride (SiN).

[0238] In some embodiments, dielectric layers 541, 542, and 543 may be disposed on the nitride layer 570. In some embodiments, dielectric layer 541 may be disposed on the nitride layer 570. Dielectric layer 542 may be disposed on dielectric layer 541. Dielectric layer 543 may be disposed on dielectric layer 542.

[0239] Dielectric layers 541, 542, and 543 may be formed in different manufacturing steps or in a single step. In some embodiments, dielectric layers 541, 542, and 543 may comprise the same or similar materials. In another embodiment, dielectric layers 541, 542, and 543 may comprise the same material with different concentrations. Dielectric layers 541, 542, and 543 may be similar to dielectric layer 241, therefore a detailed description of dielectric layers 541, 542, and 543 is omitted.

[0240] A nitride layer 580 is disposed on the dielectric layer 543. The nitride layer 580 may have an uneven top surface. For example, the nitride layer 580 may have a larger thickness on the left side (near the transistor array) and a smaller thickness on the right side (near the peripheral region).

[0241] A trench capacitor 460 may be disposed on the substrate 510. The trench capacitor 460 may penetrate the nitride layer 580, dielectric layer 541, dielectric layer 542, dielectric layer 543, and nitride layer 570. In some embodiments, the trench capacitor 460 may contact the conductive layer 530.

[0242] Details of the 460 trench capacitor will be provided below. Figure 2A and Figure 2B Please provide an explanation. Figure 2B This is a magnified image, for example. Figure 2A Region C in the middle.

[0243] See Figure 2B The trench capacitor 460 may include a multilayer stack (including conductive layers 461 and 463 and a dielectric layer 462) and contact material 464. During the fabrication of the trench capacitor 460, nitride layer 580, dielectric layer 541, dielectric layer 542 and dielectric layer 543, and nitride layer 570 may be removed to form multiple trenches. The multilayer stack may be formed within the trenches, and then contact material 464 may be deposited within the trenches defined by the multilayer stack.

[0244] The conductive layer 461 and conductive layer 463, dielectric layer 462 and contact material 464 can be similar to the conductive layer 161 and conductive layer 163, dielectric layer 162 and contact material 164 respectively, therefore detailed descriptions of the conductive layer 461 and conductive layer 463, dielectric layer 462 and contact material 464 are omitted.

[0245] In some embodiments, the ITO layer 620 may be disposed on the contact material 464. In some embodiments, the indium tin oxide layer 620 may be deposited in a trench defined by a multilayer stack and in contact with the contact material 464. In some embodiments, the top surface of the indium tin oxide layer 620 may be coplanar with the top surface of the nitride layer 580.

[0246] See Figure 2A Semiconductor element 2 may include a transistor array (e.g., region C) disposed on substrate 510. The transistor array may include bit lines 410, bonding pads 440, channel structures 430, and word lines 420. Details of the transistor array are described below. Figure 2A and Figure 2B Let's have a discussion.

[0247] Dielectric layer 5441 can be disposed on trench capacitor 460. Dielectric layer 5441 can be similar to dielectric layer 2411, therefore a detailed description of dielectric layer 5441 is omitted.

[0248] Character line 420 may be disposed above trench capacitor 460. In some embodiments, character line 420 may be disposed on dielectric layer 5441. Character line 420 may be similar to character line 120, therefore a detailed description of character line 420 is omitted.

[0249] Dielectric layer 5442 may be disposed on word line 420. In some embodiments, word line 420 may be disposed between dielectric layer 5441 and dielectric layer 5442. Dielectric layer 5442 may be similar to dielectric layer 2412, therefore a detailed description of dielectric layer 5442 is omitted.

[0250] Channel structure 430 may be disposed on trench capacitor 460. In some embodiments, channel structure 430 may be disposed on indium tin oxide layer 620. In some embodiments, channel structure 430 may taper towards trench capacitor 460. Each channel structure 430 may correspond to a corresponding trench capacitor 460. Channel structure 430 may be separated from word line 420 by gate dielectric layer 435. Channel structure 430 may be similar to channel structure 130, therefore a detailed description of channel structure 430 is omitted. Gate dielectric layer 435 may be similar to gate dielectric layer 135, therefore a detailed description of gate dielectric layer 435 is omitted.

[0251] See Figure 2B An indium tin oxide layer 610 may be disposed on the channel structure 430. In some embodiments, the indium tin oxide layer 610 may be thinner than the indium tin oxide layer 620.

[0252] In some embodiments, bonding pad 440 may be disposed on ITO layer 610. Bonding pad 440 may contact indium tin oxide layer 610 (or channel structure 430) via titanium nitride layer 445.

[0253] In some embodiments, the bonding pad 440 may taper towards the channel structure 430. In other words, the bonding pad 440 may have an upper width greater than its lower width. For example, the width of the titanium nitride layer 445 may be less than the width of the bonding pad 440.

[0254] Bit lines 410 may be disposed on bonding pads 440. In some embodiments, bit lines 410 may be connected to channel structures 430 via bonding pads 440.

[0255] See Figure 2B The bit line 410 may include a multilayer stack (including conductive layer 411, conductive layer 412, conductive layer 414, and dielectric layer 413). Conductive layer 411 may be disposed on dielectric layer 4142. Conductive layer 412 may be disposed on conductive layer 411. In some embodiments, dielectric layer 413 may be disposed on conductive layer 412. Conductive layer 414 may be disposed on dielectric layer 413.

[0256] Conductive layers 411, 412, and 414 may comprise metals, such as tungsten, copper, ruthenium, iridium, nickel, osmium, rhodium, aluminum, molybdenum, cobalt, alloys thereof, combinations thereof, or other metallic materials having suitable resistance and gap-filling capabilities. For example, conductive layer 411 may comprise tungsten, conductive layer 412 may comprise titanium nitride, and conductive layer 414 may comprise copper. In some embodiments, dielectric layer 413 may comprise a material similar to dielectric layer 544.

[0257] After forming a multilayer stack of bit lines 410, a removal operation can be performed to form a plurality of openings 410t. The openings 410t can separate each bit line 410. In some embodiments, forming the openings 410t may include removing a portion of the bonding pad 440, such that the bonding pad 440 can be separated from the bit line 410.

[0258] A dielectric layer 545 may be disposed on bit line 410 and deposited in opening 410t. In some embodiments, dielectric layer 545 may comprise a material similar to dielectric layer 413.

[0259] In some embodiments, the distance between the bonding pad 440 and the conductive layer 411 of the adjacent bit line 410 may be very small, so a short circuit may occur between the bonding pad 440 and the adjacent bit line 410. Therefore, Figure 1A The present disclosure illustrated in this paper avoids such problems.

[0260] See you again Figure 2A The word line 420 can extend outside the array of transistors. In some embodiments, the semiconductor element 2 may include a word line contact 425 disposed between the word line 420 and the conductive layer 530. In some embodiments, the word line contact 425 may include two portions, such as portion 425a and portion 425b.

[0261] The portion 425b of the character line contact 425 can penetrate the nitride layer 580, dielectric layer 541, dielectric layer 542, dielectric layer 543, and nitride layer 570. In some embodiments, the portion 425b may be disposed on the conductive layer 530.

[0262] A portion 425a of the character line contact 425 can be disposed in the dielectric layer 544, and a portion 425b can be disposed on it. Therefore, the character line contact 425 can connect the character line 420 to the conductive layer 530. The character line contact 425 can be separated from the channel structure 430.

[0263] See Figure 2A Contact 550 may be disposed on and electrically connected to conductive layer 530. In some embodiments, contact 550 may penetrate dielectric layers 541, 542, 543, 544, and 545, as well as nitride layers 570 and 580. Contact 550 is separated from channel structure 430.

[0264] In some embodiments, contact 550 may include a stacked structure. Contact 550 may include pillars 551, 552, 554, and 558, as well as platforms 553, 555, 556, and 557.

[0265] The pillar 551 may penetrate the nitride layer 580, dielectric layer 541, dielectric layer 542, dielectric layer 543, and nitride layer 570. In some embodiments, the pillar 551 may be disposed on the conductive layer 530. In some embodiments, the pillar 551 may be formed in the same process as the formation of the portion 425b of the character line contact 425.

[0266] A pillar 552 may be disposed on a pillar 551. The size of the pillar 552 may be smaller than the size of the pillar 551. For example, the diameter of the pillar 552 may be smaller than the diameter of the pillar 551. In some embodiments, the pillar 552 may be formed in the same process as the portion 425a of the character line contact 425.

[0267] Platform 553 may be disposed on pillar 552. In some embodiments, platform 553 may be disposed within dielectric layer 544. Platform 553 may be horizontally aligned with word line 420. In some embodiments, platform 553 may be formed in the same process as word line 420.

[0268] The pillar 554 may be disposed on the platform 553. In some embodiments, the pillar 554 may be disposed within the dielectric layer 544. The pillar 554 may have a top surface aligned with the top surface of the bonding pad 440.

[0269] Platform 555 may be disposed on pillar 554. In some embodiments, platform 555 may be disposed within dielectric layer 545. Platform 555 may be horizontally aligned with conductive layer 411 of bit line 410. In some embodiments, platform 555 may be formed in the same process as the formation of conductive layer 411 of bit line 410.

[0270] Platform 556 may be disposed on platform 555. In some embodiments, platform 555 may be disposed within dielectric layer 545. Platform 556 may be horizontally aligned with conductive layer 412 of bit line 410. In some embodiments, platform 556 may be formed in the same process as the formation of conductive layer 412 of bit line 410.

[0271] Platform 557 may be disposed on platform 556. In some embodiments, platform 557 may be disposed within dielectric layer 545. Platform 557 may be horizontally aligned with conductive layer 414 of bit line 410. In some embodiments, platform 557 may be formed in the same process as the formation of conductive layer 414 of bit line 410.

[0272] The pillar 558 can pass through platforms 556 and 557, and can be disposed on platform 555. The pillar 558 can be connected to the conductive layer 530 via platforms 555, pillar 554, platform 553, and pillars 552 and 551.

[0273] An upper conductive layer 590 (referred to as layer M1) may be disposed within dielectric layer 546. The upper conductive layer 590 may be disposed on the pillar 558 of contact 550. The bottom surface of the upper conductive layer 590 may include a groove for accommodating the pillar 558. In other words, the pillar 558 may be partially covered by the upper conductive layer 590.

[0274] In some embodiments, contact 550 can electrically connect conductive layer 520 to upper conductive layer 590. Upper conductive layer 590 can provide electrical connection to other components (e.g., external components). In some embodiments, character line 420 can be electrically connected to upper conductive layer 590 via character line contact 425, conductive layer 520 and conductive layer 530, and contact 550.

[0275] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G and Figure 3H Examples are one or more operations of a method for manufacturing a semiconductor element according to some embodiments of this disclosure.

[0276] See Figure 3A A substrate 210 is provided, and a conductive layer 220 may be formed on the substrate 210. In some embodiments, the substrate 210 may be wafer-level or panel-level. The substrate 210 may include an active region 211 and an isolation structure 212 disposed within the active region 211. In some embodiments, the active region 211 may be separated by the isolation structure 212. In some embodiments, the conductive layer 220 may be disposed on the active region 211 of the substrate 210 and connected to the active region 211. The conductive layer 220 may be a patterned circuit layer.

[0277] See Figure 3B The dielectric layer 240a may be formed on the substrate 210, and the conductive layer 230 may be formed on the conductive layer 220 and electrically connected to the conductive layer 220. The conductive layer 230 may include bit line conductive segments 231 and word line conductive segments 232. In some embodiments, the bit line conductive segments 231 may be substantially perpendicular to the word line conductive segments 232.

[0278] See Figure 3C Multiple bit line contacts 115 are formed on the bit line conductive segment 231. In some embodiments, each bit line conductive segment 231 may have one or more bit line contacts 115 disposed thereon. In some embodiments, the bit line contacts 115 may be similar to the word line contacts 125 described above.

[0279] See Figure 3DMultiple bit lines 110 are formed on a substrate 210; multiple lower bonding pads 140 are formed on the bit lines 110; and an indium tin oxide layer 320 is formed on a corresponding lower bonding pad 140. In some embodiments, the bit lines 110 are connected to bit line conductive segments 231 via bit line contacts 115. The bit lines 110 may extend along the Y-axis. In some embodiments, each bit line 110 may include several lower bonding pads 140 disposed thereon. Figure 1C As shown, each lower engagement pad 140 includes a half portion of the cover bit line 110.

[0280] See Figure 3E Multiple character line contacts 125 are formed on the character line conductive segment 232. In some embodiments, each character line conductive segment 232 may have one or more character line contacts 125 disposed thereon.

[0281] See Figure 3F Multiple word lines 120 are formed above bit lines 110, multiple channel structures 130 are formed on bit lines 110, and an indium tin oxide layer 310 is formed on a corresponding channel structure 130. In some embodiments, word lines 120 are connected to word line conductive segments 232 via word line contacts 125. Word lines 120 may extend along the X-axis. In some embodiments, each word line 120 may be penetrated by a plurality of channel structures 130. Channel structures 130 may be formed on a lower bonding pad 140. In some embodiments, each channel structure 130 may correspond to a lower bonding pad 140. In some embodiments, channel structures 130 may have a gate dielectric layer 135 (not shown) formed between the word line 120 and the channel structure 130.

[0282] See Figure 3G Multiple upper bonding pads 150 are formed on the channel structure 130. In some embodiments, the upper bonding pads 150 may be connected to the channel structure 130 via an indium tin oxide layer 310.

[0283] See Figure 3H Multiple trench capacitors 160 are formed on the channel structure 130, a contact layer 164a and a conductive layer 180 are formed on the trench capacitors 160, and a dielectric layer 240 is formed on the dielectric layer 240a. In some embodiments, one trench capacitor 160 may correspond to a corresponding channel structure 130. The dielectric layer 240 may cover elements located above the dielectric layer 240a, such as the channel structure 130, the trench capacitors 160, the contact layer 164a, and the conductive layer 180. In some embodiments, the dielectric layer 240a and the dielectric layer 240 may be formed in several steps (e.g., for forming on...). Figure 1AThe steps of dielectric layers 241, 242, 243, 244, 245, 246, 247, and 248 are illustrated. In this way, a structure is formed as follows: Figure 1A The semiconductor element 1 described and illustrated.

[0284] Figure 4 This is a flowchart illustrating a method for manufacturing a semiconductor device according to some embodiments of this disclosure. In some embodiments, this method can be used to manufacture... Figure 1A Semiconductor element 1 in the middle.

[0285] In operation 40, a substrate is provided. For example, it may be provided in operation 40. Figure 1A Substrate 210.

[0286] In operation 41, a conductive layer (e.g., conductive layer 220 and / or conductive layer 230) is formed on substrate 210.

[0287] In operation 42, a bit line 110 is formed on the substrate 210. The bit line 110 extends along a first direction (Y-axis). In some embodiments, conductive layers 220 and 230 may be disposed between the substrate 210 and the bit line 110.

[0288] In operation 43, a lower bonding pad is formed on the bit line. For example, see Figure 1A In operation 43, a lower bonding pad 140 is formed on bit line 110.

[0289] In operation 44, a word line 120 is formed above the bit line 110. The word line 120 extends along a second direction (X-axis) perpendicular to the first direction. The word line 120 is formed on a first dielectric layer 2411. That is, the first dielectric layer 2411 is formed between the bit line 110 and the word line 120. In some embodiments, a second dielectric layer 2412 is formed on the word line 120. In other words, the first dielectric layer 2411 and the second dielectric layer 2412 may be formed on opposite sides of the word line 120.

[0290] In operation 45, a channel structure 130 is formed on the bit line 110. The channel structure 130 extends through the word line 120 and is formed on the lower bonding pad 140. That is, the lower bonding pad 140 is disposed between the channel structure 130 and the bit line 110.

[0291] In some embodiments, forming the channel structure 130 includes forming an opening through the first dielectric layer 2411, the word line 120, and the second dielectric layer 2412. After forming the opening, a gate dielectric layer 135 may be formed within the opening, and then the channel structure 130 may be formed within the opening defined by the gate dielectric layer 135. In some embodiments, the gate dielectric layer 135 is formed between the word line 120 and the channel structure 130.

[0292] In operation 46, an upper engagement pad 150 is formed on the channel structure 130. That is, the channel structure 130 is located between the upper engagement pad 150 and the lower engagement pad 140.

[0293] In operation 47, a trench capacitor 160 is formed on the channel structure 130. In some embodiments, the trench capacitor 160 is disposed on the upper bonding pad 150. That is, the upper bonding pad 150 is disposed between the trench capacitor 160 and the channel structure 130.

[0294] In operation 48, a conductive layer is formed on the trench capacitor. For example, reference... Figure 1A In operation 48, a conductive layer 180 is formed on the trench capacitor 160.

[0295] In operation 49, a contact 250 is formed on a conductive layer (e.g., conductive layer 220 and / or conductive layer 230). The contact 250 is separated from the channel structure 130.

[0296] This disclosure provides a semiconductor device. The semiconductor device includes: a substrate having a plurality of active regions; a word line disposed on the substrate and extending along a first direction; a conductive layer disposed on the substrate and electrically connected to the plurality of active regions of the substrate; and a word line contact disposed between the word line and the conductive layer. In a first cross-sectional view along a longitudinal axis of the word line, an upper portion of the word line contact has a tapered cross-sectional profile. A lower portion of the word line contact directly contacts the conductive layer and has a non-tapered cross-sectional profile in the first cross-sectional view. In a second cross-sectional view along a line orthogonal to the longitudinal axis of the word line, the upper portion of the word line contact has a non-tapered cross-sectional profile.

[0297] This disclosure also provides a semiconductor device. The semiconductor device includes: a substrate having a plurality of active regions disposed therein; a channel structure disposed on the substrate; a conductive layer disposed on the substrate and electrically connected to the plurality of active regions of the substrate; a word line disposed on the substrate and surrounding the channel structure; a word line contact including an insulating layer and disposed between the word line and the conductive layer; a first circuit layer disposed on the substrate; and a trench capacitor disposed on the channel structure and located above the substrate. The insulating layer includes an opening to at least partially expose the conductive layer in the first circuit layer.

[0298] This disclosure also provides a method for manufacturing a semiconductor device. The method includes: providing a substrate; forming a plurality of active regions in the substrate; forming a word line on the substrate and extending along a first direction; forming a conductive layer on the substrate and electrically connected to the plurality of active regions of the substrate; forming a word line contact between the word line and the conductive layer; forming a single word line on the substrate and extending along a second direction; forming a channel structure on the word line, wherein the channel structure penetrates the word line; forming a dielectric layer on the substrate; and forming a trench capacitor on the channel structure. The word line includes: a base, a first sidewall, and a second sidewall.

[0299] This disclosure also provides a method for manufacturing a semiconductor device. The method includes: providing a substrate having a plurality of active regions disposed therein; forming a channel structure on the substrate; forming a conductive layer on the substrate and electrically connected to the plurality of active regions of the substrate; forming a word line on the substrate to surround the channel structure; forming a word line contact, wherein the word line contact includes an insulating layer and is located between the word line and the conductive layer; forming a first circuit layer above the substrate; and forming a trench capacitor on the channel structure at a position opposite to the substrate.

[0300] Embodiments of this disclosure provide a semiconductor element for which a capacitor is ultimately formed, thereby differentiating the process and structure of this disclosure from those of the prior art. For example, in the prior art, contacts connecting a memory array to other components are manufactured by stacking several contacts and platforms, while this disclosure provides a single, integrated contact for connecting to the memory array, thus avoiding misaligned (failed) contacts. Furthermore, since the word lines of this disclosure are disposed on the substrate near the lower conductive layer, the connection resistance can be reduced by shortening the electrical path (i.e., due to the shorter word line contacts).

[0301] Regarding potential failures in the channel structure, in some embodiments, the etching process used to fabricate the channel structure may fail to create a channel of sufficient depth. In this case, the bottom surface of the channel structure may contact the word line, causing a short circuit between the channel structure and the word line. In the prior art, since the bit line is disposed on top of the channel structure, a short circuit may occur between the bit line and the word line through the failed channel structure, leading to short circuits in other channel structures connected to this bit line. In contrast, this disclosure provides a semiconductor device in which the capacitor is formed last (i.e., the capacitor is disposed on the channel structure). Due to this configuration, a short circuit may occur between the word line and the capacitor (rather than the bit line) through the failed channel structure, and therefore only one memory cell (i.e., the memory cell containing this failed channel structure) is affected. This improves the manufacturing yield and performance of the semiconductor device.

[0302] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0303] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Therefore, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: A substrate with multiple active regions; A character line is disposed on the substrate and extends along a first direction; A conductive layer is disposed on the substrate and electrically connected to the plurality of active regions of the substrate; as well as A character line contact is positioned between the character line and the conductive layer. In a first cross-sectional view along a vertical axis of the character line, the upper portion of the character line in contact with the conductive layer has a tapered profile, the lower portion of the character line in contact with the conductive layer directly contacts the conductive layer and has a non-tapered profile in the first cross-sectional view, and in a second cross-sectional view along a line orthogonal to the vertical axis of the character line, the upper portion of the character line in contact with the conductive layer has a non-tapered profile.

2. The semiconductor device of claim 1, wherein the tapered profile of the upper portion of the character line contact includes curved sidewalls extending inward to the conductive layer.

3. The semiconductor device of claim 1, wherein a width of the conductive layer is greater than a width of the lower portion of the character line contact.

4. The semiconductor element of claim 1, wherein a material of the character line contact is the same as a material of the conductive layer.

5. The semiconductor device of claim 1, further comprising: A bit line is disposed on the substrate and extends along a second direction.

6. The semiconductor device of claim 5, further comprising: A channel structure is disposed on the bit line and extends through the word line, wherein the channel structure is separated from the word line by a gate dielectric layer.

7. The semiconductor device of claim 6, further comprising: A trench capacitor is disposed on this channel structure.

8. The semiconductor device of claim 7, further comprising: A bonding pad is disposed between the channel structure and the bit line.

9. The semiconductor device of claim 8, wherein the bonding pad contacts the bit line via a titanium nitride layer.

10. The semiconductor device of claim 9, further comprising: An indium tin oxide layer is disposed between the channel structure and the bonding pad.

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