Flash memory device and method of manufacturing the same
Patent Information
- Application Number
- CN202610837942.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-10
- Publication Date
- 2026-09-25
AI Technical Summary
[0003]在相关技术中，NOR Flash的衬底上划分有元胞阵列区及外围电路区，参见图1，在元胞阵列区中，元胞器件的漏极（Drain）通过接触孔（Contact，CT）与纵向的金属线连接，纵向的金属线称为位线（Bit Line，BL），元胞器件的控制栅（Control Gate，CG）层通过横向的栅极连接，横向的栅极称为字线（Word Line，WL），元胞阵列区最边缘的元胞器件的自对准源极（Self-Aligned Source，SAS）通过接触孔与金属线连接，横向相邻的元胞器件的源极间由于存在浅沟槽隔离结构（Shallow Trench Isolation，STI），其通过顶部为蛇形的有源区（Active Area，AA）传输电流（参见图2），源极间的传输路径较长，且STI越深，传输路径越长，电阻越大，会影响元胞器件的性能，因此，元胞区的STI不能太深，但外围电路区域因高压器件隔离需求需要较深的STI，为了兼顾元胞区源极串联电阻与外围逻辑器件的隔离需求，常采用分版刻蚀在元胞区及外围电路区形成不同深度的STI，这导致工艺步骤繁琐，成本较高
[0010]有益效果：本申请器件通过在元胞区设置第一沟槽隔离结构，第一沟槽隔离结构包含由元胞区的有源区分隔出的多个子沟槽，可使得横向相邻的元胞器件的源极通过相邻子沟槽隔离结构间的有源区连接，横向相邻的元胞器件的源极之间不存在沟槽隔离结构，可消除沟槽隔离结构的深度对源极串联电阻的影响，沟槽隔离结构的深度可根据外围区的隔离需求进行设计，有利于在满足外围区隔离需求的同时维持元胞器件的良好性能，同时，由于第一沟槽隔离结构的深度对源极串联电阻不产生影响，通过将第一沟槽隔离结构设置成与第二沟槽隔离结构相同的深度，可在器件制造过程中采用一张掩膜版来同步形成第一沟槽隔离结构和第二沟槽隔离结构，有利于简化制造工艺，降低生产成本。
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Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a flash memory device and a method for manufacturing the same. Background Technology
[0002] Non-volatile memory (NVM) is a widely used type of information storage. Its core characteristic is the storage of charge in a floating gate (FG) through electron tunneling or hot electron injection. The charge state captured by the floating gate changes the device's threshold voltage to represent binary data (0 / 1). In NVM memory, NOR flash memory is developed based on the programmable read-only memory tunnel oxide (ETOX) structure proposed by Intel. The structure of ETOX NOR flash is similar to that of a metal-oxide-semiconductor field-effect transistor (MOSFET), achieving non-volatile data storage through a floating gate and corresponding dielectric layers, capturing the charge state through the floating gate.
[0003] In related technologies, the substrate of a NOR Flash memory is divided into a cell array region and a peripheral circuit region. (See [link to relevant documentation]). Figure 1 In the cell array region, the drain of the cell device is connected to the vertical metal line through a contact hole (CT). The vertical metal line is called the bit line (BL). The control gate (CG) layer of the cell device is connected through the horizontal gate, which is called the word line (WL). The self-aligned source (SAS) of the cell device at the outermost edge of the cell array region is connected to the metal line through a contact hole. Due to the presence of a shallow trench isolation structure (STI) between the sources of horizontally adjacent cell devices, current is transferred through the active area (AA) with a serpentine top (see...). Figure 2The transmission path between the source and the source is relatively long, and the deeper the STI (Sequential Transmission Tile), the longer the transmission path and the greater the resistance, which will affect the performance of the cell device. Therefore, the STI in the cell area cannot be too deep. However, the peripheral circuit area requires a deeper STI due to the isolation requirements of high voltage devices. In order to balance the isolation requirements of the source series resistance in the cell area and the peripheral logic device, it is often necessary to form STIs of different depths in the cell area and the peripheral circuit area by separate etching. This results in complicated process steps and high cost. Summary of the Invention
[0004] This application provides a flash memory device and its manufacturing method. The device is not affected by the depth of the trench isolation structure on the source series resistance, and takes into account the isolation requirements of the source series resistance of the cell region and the peripheral logic devices. The method of this application has a simple process and can use a pattern mask to simultaneously form a trench isolation structure in the cell region and the peripheral region, which takes into account the isolation requirements of the source series resistance of the cell region and the peripheral logic devices, thereby reducing production costs.
[0005] On one hand, this application provides a flash memory device, including:
[0006] A substrate, wherein the substrate is divided into cellular regions and peripheral regions;
[0007] A trench isolation structure is formed within a substrate and defines an active region of a cellular region and a peripheral region. The trench isolation structure includes a first trench isolation structure located in the cellular region and a second trench isolation structure located in the peripheral region. The first trench isolation structure includes a plurality of sub-trenches separated by the active region of the cellular region, and the second trench isolation structure has the same depth as the first trench isolation structure.
[0008] A cellular device includes a flash gate structure, a source, and a drain. The flash gate structure is formed on the cellular region and includes, from bottom to top, a tunneling oxide layer, a floating gate layer, an inter-gate dielectric layer, and a control gate layer. The source and drain are located in the substrate on both sides of the flash gate structure.
[0009] In a cell device array, the control gate layers of horizontally adjacent cell devices are connected by word lines, the sources of horizontally adjacent cell devices are connected by the active regions between adjacent sub-trench isolation structures, and the source pins are uniformly led out by cell devices at the edge of the cell region. The drains of vertically adjacent cell devices are connected to the bit lines through contact holes.
[0010] Beneficial effects: The device of this application, by setting a first trench isolation structure in the cell region, the first trench isolation structure includes multiple sub-trenches separated by the active region of the cell region, so that the sources of laterally adjacent cell devices can be connected through the active regions between adjacent sub-trench isolation structures. There is no trench isolation structure between the sources of laterally adjacent cell devices, which can eliminate the influence of the trench isolation structure depth on the source series resistance. The depth of the trench isolation structure can be designed according to the isolation requirements of the peripheral region, which is beneficial to maintain the good performance of the cell device while meeting the isolation requirements of the peripheral region. At the same time, since the depth of the first trench isolation structure does not affect the source series resistance, by setting the first trench isolation structure to the same depth as the second trench isolation structure, the first trench isolation structure and the second trench isolation structure can be formed simultaneously using a mask during the device manufacturing process, which helps to simplify the manufacturing process and reduce production costs.
[0011] Optionally, the active region of the cell region includes a first active region and a second active region connecting the first active region. From a top-down view, the first active region and the second active region form a grid-like structure.
[0012] Optionally, the surface of the second active region is a plane.
[0013] Optionally, the width of the second active region is 5mm-15mm.
[0014] Optionally, the spacing between the second active area and its adjacent word line is 15mm-25mm.
[0015] Optionally, the first trench includes multiple rows of sub-trenches spaced laterally, with the sub-trenches in each row spaced longitudinally.
[0016] Optionally, when viewed from above, the bit line coincides with the first active region.
[0017] Optionally, when viewed from above, the word lines cover the control grid layer.
[0018] Optionally, the inter-gate dielectric layer includes an ONO layer.
[0019] On the other hand, this application provides a method for manufacturing a flash memory device, comprising:
[0020] S1, a substrate is provided, the substrate is divided into a cellular region and a peripheral region, and a photoresist pattern is formed by photolithography to define the active regions of the cellular region and the peripheral region;
[0021] S2, using the photoresist pattern as a mask, perform dry etching to form a first trench in the cell region. The first trench is divided into multiple sub-trenches by the active region of the cell region, and a second trench with the same depth as the first trench is simultaneously formed in the peripheral region.
[0022] S3, fill the first trench and the second trench with an isolation medium to form a first trench isolation structure and a second trench isolation structure;
[0023] S4, a floating gate layer and a control gate layer of a cellular device are formed on the active region of the cellular region. The control gate is formed on the inter-gate dielectric layer, the inter-gate dielectric layer is formed on the floating gate, the floating gate is formed on the tunneling oxide layer, and the tunneling oxide layer is formed on the substrate.
[0024] S5, the source of the cell device is formed in the active region of the cell region. The sources of the laterally adjacent cell devices are connected through the active regions between adjacent sub-trenches, and the source pins are uniformly led out by the cell devices at the edge of the cell region.
[0025] S6 forms word lines, which connect the control gate layers of horizontally adjacent cell devices;
[0026] S7 forms the drain of the cellular device within the active region of the cellular region;
[0027] S8 forms a bit line, which connects to the drain of the vertically adjacent cell device through a contact hole.
[0028] Beneficial effects: The method of this application first forms a photoresist pattern of the active region protecting the cell region and the peripheral region through photolithography, and then etches multiple sub-trenches separated by the active region within the cell region. This allows the sources of laterally adjacent cell devices to be connected through the active region resistance between adjacent sub-trenches. Since there is no trench isolation structure between the sources of laterally adjacent cell devices, the current transmission path between the sources of laterally adjacent cell devices can be reduced, eliminating the influence of the trench isolation structure depth on the cell region source series resistance, which is beneficial to maintaining the good performance of the cell devices. At the same time, since the source series resistance of the cell region is not affected by the trench isolation structure depth, a single patterned mask can be used to simultaneously perform photolithography and etching to form the trench isolation structure in the cell region and the peripheral region. The trench isolation structure depth can be set according to the isolation requirements of the peripheral region, thereby simplifying the manufacturing process, saving a mask, and reducing production costs. Attached Figure Description
[0029] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0030] Figure 1 This is a schematic diagram of the cell layout structure of a flash memory device provided in related technologies;
[0031] Figure 2 yes Figure 1 Scanning Electron Microscope (SEM) image of a section along the X-X' direction;
[0032] Figure 3 This is a layout structure of the cell region of a flash memory device provided in an exemplary embodiment of this application;
[0033] Figure 4 This is a three-dimensional structural diagram of the cell region of a flash memory device provided in an exemplary embodiment of this application;
[0034] Figure 5 This is a process flow diagram of a method for manufacturing a flash memory device provided in an exemplary embodiment of this application;
[0035] Figure 6 This is a top view of a method for manufacturing a flash memory device according to an exemplary embodiment of this application, after forming a first trench in the cell region;
[0036] Figure label:
[0037] 100, Substrate; 110, Sub-trench; 120, First active region; 121, Source; 122, Drain; 130, Second active region;
[0038] 210. Tunneling oxide layer; 220. Floating gate layer; 230. Inter-gate dielectric layer; 240. Control gate layer;
[0039] 300, character line;
[0040] 400, bit line;
[0041] 500, contact hole; Detailed Implementation
[0042] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0043] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0044] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.
[0045] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.
[0046] The following is combined Figures 1 to 6 This describes an embodiment of the present application.
[0047] refer to Figure 3 It illustrates a flash memory device according to an embodiment of this application, including:
[0048] Substrate 100, which is divided into cellular regions and peripheral regions;
[0049] A trench isolation structure is formed within a substrate 100 and defines an active region of a cell region and a peripheral region. The trench isolation structure includes a first trench isolation structure located in the cell region and a second trench isolation structure located in the peripheral region. The first trench isolation structure includes a plurality of sub-trenches 110 separated by the active region of the cell region. The second trench isolation structure has the same depth as the first trench isolation structure.
[0050] The cell device includes a flash gate structure, a source 121 and a drain 122. The flash gate structure is formed on the cell region and includes, from bottom to top, a tunneling oxide layer 210, a floating gate layer 220, an inter-gate dielectric layer 230 and a control gate layer 240. The source 121 and the drain 122 are located in the substrate 100 on both sides of the flash gate structure.
[0051] In the cell device array, the control gate layers 240 of horizontally adjacent cell devices are connected by word lines 300, the sources 121 of horizontally adjacent cell devices are connected by the active regions between the isolation structures of adjacent sub-trench 110, and the source pins 121 are uniformly led out by the cell devices at the edge of the cell region, and the drains 122 of vertically adjacent cell devices are connected to the bit lines through contact holes.
[0052] In related technologies, such as Figure 1 As shown, the substrate of a NOR Flash is divided into a cell array region and a peripheral circuit region. In the cell array region, the drain of the cell device is connected to the vertical metal line through contact holes. The vertical metal line is called the bit line. The control gate layer of the cell device is connected through the horizontal gate, which is called the word line. The source of the cell device at the outermost edge of the cell array region is connected to the metal line through contact holes. Due to the existence of a shallow trench isolation structure (STI) between the sources of horizontally adjacent cell devices, current is transmitted through the active region with a serpentine top (see...). Figure 2 The transmission path between the source and the cell is relatively long, and the deeper the STI (Series Intensity Transmission) is, the longer the transmission path and the greater the resistance, which will affect the performance of the cell device. Therefore, the STI of the cell region cannot be too deep. However, the peripheral circuit region requires a deeper STI due to the isolation requirements of high voltage devices. In order to balance the isolation requirements of the source series resistance in the cell region and the peripheral logic devices, different depths of STI are often formed in the cell region and the peripheral circuit region during the device manufacturing process. This results in complicated process steps and high cost.
[0053] The device of this application incorporates a first trench isolation structure within the cell region. This first trench isolation structure includes multiple sub-trenches 110 separated by the active region of the cell region. This allows the sources 121 of laterally adjacent cell devices to be connected through the active regions between adjacent sub-trench 110 isolation structures. There is no trench isolation structure between the sources 121 of laterally adjacent cell devices, thus eliminating the influence of the trench isolation structure depth on the series resistance of the source 121. The depth of the trench isolation structure can be designed according to the isolation requirements of the peripheral region, which is beneficial to maintaining good performance of the cell device while meeting the isolation requirements of the peripheral region. At the same time, since the depth of the first trench isolation structure does not affect the series resistance of the source 121, by setting the first trench isolation structure to the same depth as the second trench isolation structure, a single mask can be used to simultaneously form the first trench isolation structure and the second trench isolation structure during device manufacturing, which simplifies the manufacturing process and reduces production costs.
[0054] In some embodiments, the active region of the cell region includes a first active region 120 and a second active region 130 connecting the first active region 120. Viewed from a top angle, the first active region 120 and the second active region 130 constitute a grid-like structure.
[0055] For example, the flash gate structure of the cell device is located above the first active region 120, and the source 121 and drain 122 of the cell device are located in the first active regions 120 on both sides of the flash gate structure. The sources 121 of the laterally adjacent cell devices are connected through the second active region 130 between the adjacent sub-trench 110 isolation structures.
[0056] In some embodiments, the surface of the second active region 130 is planar. This topography helps to minimize the transmission path between the sources 121 of laterally adjacent cell devices.
[0057] In some embodiments, the width of the second active region 130 is 5mm-15mm.
[0058] For example, the width of the second active region 130 can be 5mm, 10mm, 15mm, etc.
[0059] In some embodiments, the spacing between the second active region 130 and its adjacent word line 300 is 15mm-25mm.
[0060] For example, the spacing between the second active area and its adjacent word line can be 15mm, 20mm, or 25mm.
[0061] In some embodiments, the first trench includes multiple rows of sub-grooves 110 spaced laterally, with the sub-grooves 110 in each row spaced longitudinally.
[0062] In some embodiments, when viewed from a top view, bit line 400 coincides with the first active region 120.
[0063] In some embodiments, when viewed from above, word lines 300 cover control gate layer 240.
[0064] In some embodiments, the inter-gate dielectric layer 230 includes an oxide-nitride-oxide (ONO) layer.
[0065] refer to Figure 5 It illustrates a method for manufacturing a flash memory device according to an embodiment of this application, including:
[0066] S1, a substrate 100 is provided, the substrate 100 is divided into a cell region and a peripheral region, and a photoresist pattern is formed by photolithography to define the active regions of the cell region and the peripheral region.
[0067] For example, the substrate 100 may be made of silicon, germanium (Ge), gallium arsenide (GaAs), or other materials suitable for semiconductor device fabrication. The photoresist pattern covers and protects the active regions of the cell regions and peripheral regions, exposing the non-active regions on the surface of the substrate 100.
[0068] In some embodiments, the active region of the cell region includes a first active region 120 and a second active region 130 connecting the first active region 120. Viewed from a top angle, the first active region 120 and the second active region 130 constitute a grid-like structure.
[0069] For example, see Figure 3 The first active region 120 extends longitudinally, which is the Y direction in the figure, and the second active region 130 extends laterally, which is the X direction in the figure.
[0070] In some embodiments, the surface of the second active region 130 is planar. This topography helps to minimize the transmission path between the sources 121 of laterally adjacent cell devices.
[0071] In some embodiments, the width of the second active region 130 is 5mm-15mm.
[0072] For example, the width of the second active region 130 can be 5mm, 10mm, 15mm, etc.
[0073] S2, using the photoresist pattern as a mask, performs dry etching to form a first trench in the cell region. The first trench is divided into multiple sub-trenches 110 by the active region of the cell region, and a second trench with the same depth as the first trench is simultaneously formed in the outer region.
[0074] For example, the first trench is divided into a plurality of sub-trenches 110 by a first active region 120 and a second active region 130, wherein the sub-trenches 110 are distributed in multiple rows at lateral intervals, and the sub-trenches 110 in each row are distributed at longitudinal intervals. The etching depth of the first trench and the second trench can be set by the isolation requirements of the peripheral region.
[0075] S3, fill the first trench and the second trench with the isolation medium to form the first trench isolation structure and the second trench isolation structure.
[0076] For example, chemical vapor deposition (CVD) can be used to deposit the isolation medium in the first trench and the second trench until the isolation medium fills the first trench and the second trench. After the isolation medium fills the first trench and the second trench, the surface of the substrate 100 can be planarized by chemical mechanical polishing (CMP) to form the first trench isolation structure and the second trench isolation structure.
[0077] For example, the first trench isolation structure and the second trench isolation structure can be shallow trench isolation structures.
[0078] In some embodiments, the isolation medium may be at least one of silicon oxide and silicon nitride.
[0079] S4, a floating gate layer 220 and a control gate layer 240 of a cellular device are formed on the active region of the cellular region. The control gate layer 240 is formed on the inter-gate dielectric layer 230, the inter-gate dielectric layer 230 is formed on the floating gate layer 220, the floating gate layer 220 is formed on the tunneling oxide layer 210, and the tunneling oxide layer 210 is formed on the substrate 100.
[0080] For example, a floating gate layer 220 and a control gate layer 240 of a cellular device are formed on the first active region 120.
[0081] In some embodiments, the control gate layer 240 includes a control gate polysilicon layer.
[0082] For example, a control gate polysilicon layer is typically deposited on the inter-gate dielectric layer 230 using chemical vapor deposition (CVD).
[0083] In some embodiments, the inter-gate dielectric layer 230 includes, from bottom to top, an oxide layer, a nitride layer, and an oxide layer.
[0084] For example, the inter-gate dielectric layer 230 is an oxide-nitride-oxide (ONO) layer, which is typically formed on the floating gate layer 220 using a combination of thermal oxidation and chemical vapor deposition processes.
[0085] In some embodiments, the floating gate layer 220 includes a floating gate polysilicon layer.
[0086] For example, chemical vapor deposition (CVD) is typically used to deposit the floating gate layer 220 on the tunneling oxide layer 210.
[0087] In some embodiments, the tunneling oxide layer 210 includes a silicon oxide (SiO2) layer.
[0088] For example, a tunnel oxide layer 210 is typically grown on substrate 100 using thermal oxidation (TO).
[0089] S5, the source 121 of the cell device is formed in the active region of the cell region. The source 121 of the laterally adjacent cell devices are connected through the active region between adjacent sub-trenches 110, and the source 121 pin is uniformly led out by the cell devices at the edge of the cell region.
[0090] For example, the source 121 of the cell device is formed in the first active region 120 by a self-aligned source (SAS) process, and the sources 121 of the laterally adjacent cell devices are connected through the second active region 130 between adjacent sub-trenches 110.
[0091] It should be noted that during the process of implanting impurity ions to form the source, the implantation of impurity ions into the second active region can be completed simultaneously.
[0092] S6 forms word line 300, which connects to the control gate layer 240 of the horizontally adjacent cell device.
[0093] For example, see Figure 3 The extension direction of the word line 300 in the cell area is horizontal, that is, the X direction in the figure. The second active area 130 is located between the adjacent word lines 300. The distance between the second active area 130 and its adjacent word lines 300 can be 15mm-25mm, such as 15mm, 20mm, 25mm, etc.
[0094] In some embodiments, when viewed from above, word lines 300 cover control gate layer 240.
[0095] S7, the drain 122 of the cellular device is formed in the first active region 120.
[0096] S8 forms bit line 400, which is connected to the drain 122 of the longitudinally adjacent cell device through contact hole 500.
[0097] For example, see Figure 3 The extension direction of the character line 300 in the cell region is vertical, that is, the Y direction in the figure.
[0098] In some embodiments, when viewed from a top view, bit line 400 coincides with the first active region 120.
[0099] The method of this application first forms a photoresist pattern of the active region protecting the cell region and the peripheral region through photolithography, and then etches multiple sub-trenches 110 separated by the active region within the cell region. This allows the sources 121 of laterally adjacent cell devices to be connected through the active region resistance between adjacent sub-trenches 110. Since there is no trench isolation structure between the sources 121 of laterally adjacent cell devices, the current transmission path between the sources 121 of laterally adjacent cell devices can be reduced, eliminating the influence of the trench isolation structure depth on the series resistance of the cell region source 121, which is beneficial to maintaining the good performance of the cell device. At the same time, since the series resistance of the cell region source 121 is not affected by the trench isolation structure depth, a single patterned mask can be used to simultaneously perform photolithography and etching to form the trench isolation structure in the cell region and the peripheral region. The trench isolation structure depth can be set according to the isolation requirements of the peripheral region, thereby simplifying the manufacturing process, saving a mask, and reducing production costs.
[0100] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.
Claims
1. A flash memory device, characterized in that, include: A substrate, wherein the substrate is divided into cellular regions and peripheral regions; A trench isolation structure is formed within a substrate and defines an active region of a cellular region and a peripheral region. The trench isolation structure includes a first trench isolation structure located in the cellular region and a second trench isolation structure located in the peripheral region. The first trench isolation structure includes a plurality of sub-trenches separated by the active region of the cellular region, and the second trench isolation structure has the same depth as the first trench isolation structure. A cellular device includes a flash gate structure, a source, and a drain. The flash gate structure is formed on the cellular region and includes, from bottom to top, a tunneling oxide layer, a floating gate layer, an inter-gate dielectric layer, and a control gate layer. The source and drain are located in the substrate on both sides of the flash gate structure. In a cell device array, the control gate layers of horizontally adjacent cell devices are connected by word lines, the sources of horizontally adjacent cell devices are connected by the active regions between adjacent sub-trench isolation structures, and the source pins are uniformly led out by cell devices at the edge of the cell region. The drains of vertically adjacent cell devices are connected to the bit lines through contact holes.
2. The device according to claim 1, characterized in that, The active region of a cell includes a first active region and a second active region connecting the first active region. From a top-down view, the first and second active regions form a grid-like structure.
3. The device according to claim 2, characterized in that, The surface of the second active region is planar.
4. The device according to claim 2, characterized in that, The width of the second active region is 5mm-15mm.
5. The device according to claim 2, characterized in that, The spacing between the second active area and its adjacent character line is 15mm-25mm.
6. The device according to claim 1, characterized in that, The first trench comprises multiple rows of sub-trenches spaced laterally, with the sub-trenches in each row spaced longitudinally.
7. The device according to claim 1, characterized in that, Viewed from above, the bit line coincides with the first active region.
8. The device according to claim 1, characterized in that, Viewed from above, the letter lines cover the control grid.
9. The device according to claim 1, characterized in that, The inter-gate dielectric layer includes an ONO layer.
10. A method for manufacturing a flash memory device, characterized in that, include: S1, a substrate is provided, the substrate is divided into a cellular region and a peripheral region, and a photoresist pattern is formed by photolithography to define the active regions of the cellular region and the peripheral region; S2, using the photoresist pattern as a mask, perform dry etching to form a first trench in the cell region. The first trench is divided into multiple sub-trenches by the active region of the cell region, and a second trench with the same depth as the first trench is simultaneously formed in the peripheral region. S3, fill the first trench and the second trench with an isolation medium to form a first trench isolation structure and a second trench isolation structure; S4, a floating gate layer and a control gate layer of a cellular device are formed on the active region of the cellular region. The control gate is formed on the inter-gate dielectric layer, the inter-gate dielectric layer is formed on the floating gate, the floating gate is formed on the tunneling oxide layer, and the tunneling oxide layer is formed on the substrate. S5, the source of the cell device is formed in the active region of the cell region. The sources of the laterally adjacent cell devices are connected through the active regions between adjacent sub-trenches, and the source pins are uniformly led out by the cell devices at the edge of the cell region. S6 forms word lines, which connect the control gate layers of horizontally adjacent cell devices; S7 forms the drain of the cellular device within the active region of the cellular region; S8 forms a bit line, which connects to the drain of the vertically adjacent cell device through a contact hole.