Method of manufacturing a flash memory device

Abstract

The application discloses a manufacturing method of a flash memory device, comprising the following steps: providing a substrate, wherein a region for forming a semiconductor device on the substrate comprises a memory cell region and a logic region, the substrate of the memory cell region is provided with a first gate and a second gate, the substrate of the logic region is provided with a third gate, and the first gate and the second gate are adjacent and have a first opening; forming a first side wall on the first opening and the sidewall of the third gate; forming a second side wall on the sidewall of the first opening; forming a third dielectric layer; etching the third dielectric layer to form a third side wall on the first side wall and the second side wall; forming a reverse ladder-shaped profile with a narrow bottom end and a wide top end between the side walls in the first opening, which comprises the second side wall and the third side wall; and forming an interlayer dielectric layer, thereby solving the problems of a hanging structure and a cavity in the related art.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices and integrated circuit technology, and in particular to a method for manufacturing a flash memory device. Background Technology

[0002] As NOR flash memory technology nodes shrink to 48nm and below, the physical size of the cell region continues to shrink. To increase storage density, the size of the drain space is continuously compressed, which in turn significantly increases the aspect ratio of the inter-layer dielectric (ILD), posing a challenge to defect-free deposition of the ILD.

[0003] Furthermore, during manufacturing, process variations in spacer deposition (spacer dep) and ILD stop layer deposition (ILD stop layer dep) can cause overhangs to form in the depressions of the oxide-nitride-oxide (ONO) stack in the memory cell region. This profile defect not only hinders the uniform filling of the ILD material but also easily induces void formation during deposition. (Reference) Figure 1 This study demonstrates that when the aspect ratio is greater than 2, overhanging structures that impede material coverage are easily formed within the gap, accompanied by voids. These voids may evolve into conductive bridges during subsequent metallization or heat treatment, causing short circuits between adjacent transistors. In mass production testing, this manifests as specific yield losses, directly affecting product yield. Summary of the Invention

[0004] This application provides a solution to the problem of decreased product yield caused by the reduction in aspect ratio due to the shrinkage of storage cells, as well as by overhanging structures and voids in related technologies.

[0005] On one hand, embodiments of this application provide a method for manufacturing a flash memory device, including: A substrate is provided, wherein regions on the substrate for forming a semiconductor device include a memory cell region and a logic region, a first gate and a second gate are formed on the substrate of the memory cell region, and a third gate is formed on the substrate of the logic region, wherein a first opening is provided between adjacent first gates and second gates; A first sidewall is formed on the sidewall of the first opening and the third gate, and the first sidewall includes, from the inside to the outside, an etch stop layer, a first dielectric layer and a second dielectric layer. Remove the second medium layer inside the first opening to form a second sidewall on the sidewall of the first opening; A third dielectric layer is formed, which covers the first opening, the third gate, the first sidewall, the second sidewall, and the surface of the substrate exposed. The third dielectric layer is etched to form a third sidewall on the first sidewall and the second sidewall; The memory cell region is isolated, and a source region and a drain region are formed in the substrate on both sides of the third gate using the third gate and the third sidewall as masks. A stress proximity process is used for transverse etching to create an inverted trapezoidal shape with a narrow bottom and a wide top in the cross-section between the sidewalls, including the second and third sidewalls, within the first opening. An interlayer dielectric layer is formed, which covers the first opening, the third gate, the first sidewall, the second sidewall, the third sidewall, and the area of ​​the exposed substrate.

[0006] In some embodiments, the first gate includes a first gate oxide layer, a first floating gate, a first gate dielectric layer, and a first control gate stacked sequentially from bottom to top; The second gate includes a second gate oxide layer, a second floating gate, a second gate dielectric layer, and a second control gate, which are stacked sequentially from bottom to top.

[0007] In some embodiments, forming a first sidewall at the sidewalls of the first opening and the third gate includes: An etch stop layer, a first dielectric layer, and a second dielectric layer are sequentially formed on the exposed surfaces of the first gate, the second gate, the third gate, and the substrate.

[0008] In some embodiments, after forming the etch stop layer, the first dielectric layer, and the second dielectric layer, the method further includes: The first dielectric layer and the second dielectric layer are etched until the etch stop layer is exposed, and the remaining first dielectric layer, second dielectric layer and etch stop layer on the first opening sidewall and the third gate sidewall form the first sidewall.

[0009] In some embodiments, the material of the etch stop layer includes silicon oxide.

[0010] In some embodiments, the material of the first dielectric layer includes silicon nitride.

[0011] In some embodiments, the material of the second dielectric layer includes silicon oxide.

[0012] In some embodiments, the material of the third dielectric layer includes silicon nitride.

[0013] In some embodiments, the third dielectric layer is etched until the etching stop layer is exposed.

[0014] In some embodiments, during the lateral etching of the sidewalls, in a direction perpendicular to the substrate, the etching rate of the region closer to the substrate is lower than the etching rate of the region farther from the substrate.

[0015] In some embodiments, after lateral etching of the sidewalls of the first opening and the third gate, and before deposition of the interlayer dielectric layer, the method further includes: The logic region is isolated, and a drain region and a source region are formed in the memory cell region using the first gate, the second gate, and the third sidewall as masks. A self-aligned silicide barrier layer is deposited and patterned to expose the third gate and source / drain regions of the logic region, and metal silicides are formed in the source and drain regions.

[0016] The technical solution of this application has at least the following advantages: By removing the second dielectric layer inside the first opening to form a first sidewall inside the first opening, and depositing a third dielectric layer on the third gate sidewall and the first opening sidewall to form a third sidewall, the aspect ratio of the first opening is reduced. By using stress proximity etching for lateral etching, an inverted trapezoidal morphology is formed inside the opening, and a V-shaped morphology is formed after depositing the interlayer dielectric layer. This avoids the generation of overhang structures and voids, eliminates the risk of conductive bridging short circuits, and ensures the yield and reliability of the device. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 It is a cross-sectional view of the device product after filling with ILD material using existing manufacturing methods.

[0019] Figure 2 This is a flowchart of a method for manufacturing a flash memory device provided in an exemplary embodiment of this application.

[0020] Figures 3 to 8 This is a schematic diagram of the manufacture of a flash memory device provided in an exemplary embodiment of this application.

[0021] Figure 9 and Figure 10This is a cross-sectional schematic diagram of a device product manufactured using a flash memory device manufacturing method according to an exemplary embodiment of this application. Detailed Implementation

[0022] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0024] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0025] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0026] refer to Figure 2 It illustrates a flowchart of a method for manufacturing a flash memory device according to an exemplary embodiment of this application, the method comprising: Step S1: Provide a substrate. The regions on the substrate for forming a semiconductor device include a memory cell region and a logic region. A first gate and a second gate are formed on the substrate of the memory cell region, and a third gate is formed on the substrate of the logic region. A first opening is provided between adjacent first gates and second gates.

[0027] refer to Figure 3This illustration shows a cross-sectional schematic diagram of a semiconductor structure provided in an exemplary embodiment of this application. A substrate 200 is provided, and the regions on the substrate for forming semiconductor devices include a memory cell region A and a logic region B. A plurality of first gates 210 and a plurality of second gates 220 are formed on the substrate of the memory cell region A, and a third gate 230 is formed on the substrate of the logic region B. A first opening 310 is provided between adjacent first gates 210 and second gates 220, and a second opening 320 is provided between adjacent second gates.

[0028] Optionally, the first gate 210 includes a first gate oxide layer, a first floating gate, a first gate dielectric layer, and a first control gate (not shown in the figure) stacked sequentially from bottom to top. Optionally, the second gate 220 includes a second gate oxide layer, a second floating gate, a second gate dielectric layer, and a second control gate (not shown in the figure) stacked sequentially from bottom to top.

[0029] Optionally, substrate 200 may include a silicon substrate, a silicon-on-insulator (SOI) substrate, or a silicon substrate with an epitaxial layer grown thereon. The first gate oxide layer and the second gate oxide layer may include silicon oxide (SiO2). The first floating gate and the second floating gate may be made of polycrystalline silicon or silicon nitride (SiN). The first gate dielectric layer and the second gate dielectric layer may be made of an oxide-nitride-oxide (ONO) stack or aluminum oxide (Al2O3). The first control gate and the second control gate may be made of polycrystalline silicon or tungsten (W).

[0030] Step S2: A first sidewall is formed on the sidewall of the first opening and the third gate. The first sidewall includes, from the inside to the outside, an etch stop layer, a first dielectric layer and a second dielectric layer.

[0031] For example, step S2 may include: Step S21: An etch stop layer, a first dielectric layer, and a second dielectric layer are sequentially formed on the first gate, the second gate, the third gate, and the exposed surface of the substrate. Step S22: Etch the first dielectric layer and the second dielectric layer until the etch stop layer is exposed, and form the first sidewall with the remaining first dielectric layer, second dielectric layer and etch stop layer on the first opening sidewall and the third gate sidewall.

[0032] refer to Figure 4This diagram illustrates a cross-sectional view after step S2 in an exemplary embodiment of this application. Optionally, an etch stop layer 240, a first dielectric layer 250, and a second dielectric layer 260 are sequentially formed on the first gate 210, the second gate 220, the third gate 230, and the exposed surface of the substrate, followed by an etching step. The second dielectric layer 260 and the first dielectric layer 250 are etched until the etch stop layer 240 is exposed. The remaining first dielectric layer 250, second dielectric layer 260, and etch stop layer 240 on the sidewalls of the first opening 310 and the third gate 230 form the first sidewall, which includes the etch stop layer 240, the first dielectric layer 250, and the second dielectric layer 260 sequentially from the inside out. Optionally, the second opening 320 is filled with the etch stop layer 240, the first dielectric layer 250, and the second dielectric layer 260.

[0033] Optionally, the etch stop layer 240 may be made of silicon oxide, and the process for forming the etch stop layer 240 may include a high-temperature thermal oxidation process. The first dielectric layer 250 may be made of silicon nitride. The second dielectric layer 260 may be made of silicon oxide, and the process for forming the second dielectric layer 260 may include a furnace tube tetraethyl orthosilicate process.

[0034] Optionally, the first sidewall formed by the sidewall of the first opening 310 includes, from the inside out, an etch stop layer 240 with a thickness ranging from 100 Å to 150 Å, a first dielectric layer 250 with a thickness ranging from 160 Å to 230 Å, and a second dielectric layer 260 with a thickness d1 ranging from 480 Å to 590 Å. Through step S2, the first sidewall is formed at the first opening and the third gate sidewall, respectively.

[0035] Step S3: Remove the second medium layer inside the first opening to form a second sidewall on the sidewall of the first opening.

[0036] refer to Figure 5 The diagram illustrates a cross-sectional view after step S3 in an exemplary embodiment of this application. Optionally, a wet etching process is used to remove the second dielectric layer 260 on the first sidewall of the memory cell region A, thereby forming a second sidewall on the sidewall of the first opening 310. The second sidewall sequentially includes an etch stop layer 240 and a first dielectric layer 250 from the inside out. Through step S3, the first sidewall of the first opening sidewall is transformed into the second sidewall, while the sidewall of the third gate sidewall remains unchanged.

[0037] Step S4: Form a third dielectric layer that covers the first opening, the third gate, the first sidewall, the second sidewall, and the surface of the exposed substrate.

[0038] refer to Figure 6This diagram illustrates a cross-sectional view after step S4 in an exemplary embodiment of this application. Exemplarily, a third dielectric layer 270 is formed on the surfaces of memory cell region A and logic region B. The third dielectric layer 270 covers the first opening 310, the third gate 230, the first sidewall, the second sidewall, and the surface of the exposed substrate. Optionally, the material of the third dielectric layer may include silicon nitride.

[0039] Step S5: Etch the third dielectric layer to form a third sidewall on the first sidewall and the second sidewall.

[0040] refer to Figure 7 The diagram shows a cross-sectional view after step S5 in an exemplary embodiment of this application. Exemplarily, the third dielectric layer 270 is etched until the etch stop layer 240 is exposed, so that a third sidewall is formed on both the second sidewall of the first opening 310 sidewall and the first sidewall of the third gate, the third sidewall including the third dielectric layer 270.

[0041] Optionally, the thickness d2 of the third dielectric layer in the third sidewall ranges from 350 Å to 450 Å. Optionally, the thickness d2 of the third dielectric layer is less than the thickness d1 of the second dielectric layer.

[0042] By performing steps S4 and S5, a sidewall including a second sidewall and a third sidewall is formed in the sidewall of the first opening. Compared with the first sidewall in the first opening, the thickness is reduced, which can reduce the depth-to-width ratio of the opening, which is beneficial to the subsequent deposition of the medium material layer and reduces the probability of void formation.

[0043] Step S6: Isolate the memory cell region, and form the source region and drain region in the substrate on both sides of the third gate using the third gate and the third sidewall as masks.

[0044] Step S7: Use stress proximity process to perform transverse etching so that the sidewalls including the second and third sidewalls in the first opening form an inverted trapezoidal shape with a narrow bottom and a wide top.

[0045] refer to Figure 8The diagram illustrates a cross-sectional view after steps S6 and S7 of an exemplary embodiment of this application. Exemplarily, memory cell region A is isolated, and using the third gate 230 and the third sidewall as masks, the source and drain regions (not shown) of logic region B are formed within the substrate on both sides of the third gate. Subsequently, lateral etching is performed using Stress Proximity Technology (SPT) to create an inverted trapezoidal shape with a narrow bottom and wide top profile between the sidewalls including the second and third sidewalls within the first opening 310. During the lateral etching of the sidewalls including the second and third sidewalls within the first opening, the stress at the top of the sidewall is higher than the stress at the bottom of the sidewall closer to the substrate. Therefore, in the direction perpendicular to the substrate, the etching rate of the region closer to the substrate is lower than the etching rate of the region farther from the substrate; that is, the closer to the top of the sidewall, the more dielectric material is lost from the sidewall. (Reference) Figure 8 The first opening 310 forms an inverted trapezoidal shape with a narrow bottom and a wide top between the side walls.

[0046] Step S8: Form an interlayer dielectric layer that covers the first opening, the third gate, the first sidewall, the second sidewall, the third sidewall, and the area of ​​the exposed substrate.

[0047] Optionally, the material of the interlayer dielectric layer may include silicon oxide, porous silicon dioxide, or carbon-doped oxide (SiOC).

[0048] Optionally, after the lateral etching and before the deposition of the interlayer dielectric layer, the method further includes: isolating the logic region, using the first gate, the second gate, and the third sidewall as masks to form a drain region and a source region in the memory cell region; and forming metal silicides in the source region and drain region of the logic region.

[0049] refer to Figure 9 and Figure 10 The diagram shows a cross-sectional view of a device product manufactured using a flash memory device manufacturing method according to an exemplary embodiment of this application after steps S1-S7 and S1-S8. It can be seen that after step S7, the opening exhibits an inverted trapezoidal morphology. After further deposition to form an interlayer dielectric layer, the opening exhibits a V-shaped morphology.

[0050] In summary, this invention removes the second dielectric layer within the first opening to form a first sidewall within the first opening, and deposits a third dielectric layer on the third gate sidewall and the first opening sidewall to form a third sidewall, thereby reducing the aspect ratio of the first opening. By employing a stress proximity process for lateral etching, an inverted trapezoidal morphology is formed within the opening, and a V-shaped morphology is formed after depositing the interlayer dielectric layer. This avoids the generation of overhanging structures and voids, eliminates the risk of conductive bridging and short circuits, and ensures the yield and reliability of the device.

[0051] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A method for manufacturing a flash memory device, characterized in that, include: A substrate is provided, wherein regions on the substrate for forming a semiconductor device include a memory cell region and a logic region, a first gate and a second gate are formed on the substrate of the memory cell region, and a third gate is formed on the substrate of the logic region, wherein a first opening is provided between adjacent first gates and second gates; A first sidewall is formed on the sidewall of the first opening and the third gate, and the first sidewall includes, from the inside to the outside, an etch stop layer, a first dielectric layer and a second dielectric layer. Remove the second medium layer inside the first opening to form a second sidewall on the sidewall of the first opening; A third dielectric layer is formed, which covers the first opening, the third gate, the first sidewall, the second sidewall, and the surface of the substrate exposed. The third dielectric layer is etched to form a third sidewall on the first sidewall and the second sidewall; The memory cell region is isolated, and a source region and a drain region are formed in the substrate on both sides of the third gate using the third gate and the third sidewall as masks. A stress proximity process is used for transverse etching to create an inverted trapezoidal shape with a narrow bottom and a wide top in the cross-section between the sidewalls, including the second and third sidewalls, within the first opening. An interlayer dielectric layer is formed, which covers the first opening, the third gate, the first sidewall, the second sidewall, the third sidewall, and the area of ​​the exposed substrate.

2. The method according to claim 1, characterized in that, The first gate includes a first gate oxide layer, a first floating gate, a first gate dielectric layer, and a first control gate stacked sequentially from bottom to top; The second gate includes a second gate oxide layer, a second floating gate, a second gate dielectric layer, and a second control gate, which are stacked sequentially from bottom to top.

3. The method according to claim 1, characterized in that, The formation of a first sidewall in the sidewalls of the first opening and the third gate includes: An etch stop layer, a first dielectric layer, and a second dielectric layer are sequentially formed on the exposed surfaces of the first gate, the second gate, the third gate, and the substrate.

4. The method according to claim 3, characterized in that, After forming the etching stop layer, the first dielectric layer, and the second dielectric layer, the method further includes: The first dielectric layer and the second dielectric layer are etched until the etch stop layer is exposed, and the remaining first dielectric layer, second dielectric layer and etch stop layer on the first opening sidewall and the third gate sidewall form the first sidewall.

5. The method according to claim 3 or 4, characterized in that, The material of the etch stop layer includes silicon oxide.

6. The method according to claim 3 or 4, characterized in that, The material of the first dielectric layer includes silicon nitride.

7. The method according to claim 3 or 4, characterized in that, The material of the second dielectric layer includes silicon oxide.

8. The method according to claim 1, characterized in that, The material of the third dielectric layer includes silicon nitride.

9. The method according to claim 8, characterized in that, The third dielectric layer is etched until the etching stop layer is exposed.

10. The method according to claim 1, characterized in that, In the lateral etching of the sidewalls, in the direction perpendicular to the substrate, the etching rate of the region closer to the substrate is lower than the etching rate of the region farther from the substrate.

11. The method according to claim 1, characterized in that, After lateral etching of the sidewalls of the first opening and the third gate, before deposition of the interlayer dielectric layer, the method further includes: The logic region is isolated, and a drain region and a source region are formed in the memory cell region using the first gate, the second gate, and the third sidewall as masks. Metal silicides are formed in the source and drain regions of the logic region.

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