Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The semiconductor device includes a substrate having an active region and an isolation region surrounding the active region; a source region and a drain region disposed in the active region and defining a channel region therebetween; a gate disposed over the channel region; a gate dielectric layer disposed between the gate and the channel region; and an annular silicide block disposed along a periphery of the active region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Embedded flash memory is a type of non-volatile memory that is directly integrated into an integrated circuit (IC) chip.

[0003] Existing medium voltage (MV) components in embedded flash memory devices suffer from poor breakdown voltage uniformity, thus requiring further improvement. Summary of the Invention

[0004] The main objective of this invention is to provide an improved semiconductor device and its manufacturing method to overcome the shortcomings or disadvantages of the prior art.

[0005] The present invention provides a semiconductor device comprising: a substrate having an active region and an isolation region surrounding the active region; a source region and a drain region disposed in the active region and defining a channel region therebetween; a gate disposed above the channel region; a gate dielectric layer disposed between the gate and the channel region; and an annular silicide barrier layer disposed along the periphery of the active region.

[0006] According to an embodiment of the present invention, an annular groove is formed at the boundary between the isolation region and the active region, wherein the annular silicide barrier layer overlaps with the annular groove.

[0007] According to an embodiment of the present invention, the annular silicide barrier layer completely covers the annular groove and extends to the peripheral portion of the active region adjacent to the annular groove.

[0008] According to an embodiment of the present invention, the width of the peripheral portion of the active region ranges from 0 to 0.1 micrometers.

[0009] According to an embodiment of the present invention, the width of the annular silicide barrier layer ranges from 0.2 to 0.4 micrometers.

[0010] According to an embodiment of the present invention, the annular silicide barrier layer comprises silicon oxide, silicon nitride, or a combination thereof.

[0011] According to an embodiment of the present invention, the semiconductor device further includes: a source silicide layer disposed on the source region not covered by the annular silicide barrier layer; a drain silicide layer disposed on the drain region not covered by the annular silicide barrier layer; and a gate silicide layer disposed on the gate not covered by the annular silicide barrier layer.

[0012] According to an embodiment of the present invention, the source silicide layer and the drain silicide layer are not in direct contact with the isolation region.

[0013] According to an embodiment of the present invention, the semiconductor device further includes: a spacer wall disposed on the sidewall of the gate, wherein the annular silicide barrier layer extends to the spacer wall and the gate.

[0014] According to an embodiment of the present invention, the spacer wall comprises silicon nitride.

[0015] Another aspect of the present invention provides a method for forming a semiconductor device, comprising: providing a substrate having an active region and an isolation region surrounding the active region; forming a source region and a drain region in the active region and defining a channel region therebetween; forming a gate over the channel region; forming a gate dielectric layer between the gate and the channel region; and forming an annular silicide barrier layer along the periphery of the active region.

[0016] According to an embodiment of the present invention, an annular groove is formed at the boundary between the isolation region and the active region, wherein the annular silicide barrier layer overlaps with the annular groove.

[0017] According to an embodiment of the present invention, the annular silicide barrier layer completely covers the annular groove and extends to the peripheral portion of the active region adjacent to the annular groove.

[0018] According to an embodiment of the present invention, the width of the peripheral portion of the active region ranges from 0 to 0.1 micrometers.

[0019] According to an embodiment of the present invention, the width of the annular silicide barrier layer ranges from 0.2 to 0.4 micrometers.

[0020] According to an embodiment of the present invention, the annular silicide barrier layer comprises silicon oxide, silicon nitride, or a combination thereof.

[0021] According to an embodiment of the present invention, the method further includes: forming a source silicide layer on the source region not covered by the annular silicide barrier layer; forming a drain silicide layer on the drain region not covered by the annular silicide barrier layer; and forming a gate silicide layer on the gate not covered by the annular silicide barrier layer.

[0022] According to an embodiment of the present invention, the source silicide layer and the drain silicide layer are not in direct contact with the isolation region.

[0023] According to an embodiment of the present invention, the method further includes: forming a gap wall on the sidewall of the gate, wherein the annular silicide barrier layer extends to the gap wall and the gate.

[0024] According to an embodiment of the present invention, the spacer wall comprises silicon nitride. Attached Figure Description

[0025] Figure 1 This is a top view schematic diagram of the semiconductor device shown in an embodiment of the present invention;

[0026] Figure 2 This is a schematic cross-sectional view along the tangent I-I';

[0027] Figure 3 This is a schematic cross-section along tangent II-II';

[0028] Figure 4 This is a schematic diagram of the process for manufacturing a semiconductor device.

[0029] Symbol explanation:

[0030] 1. Semiconductor device

[0031] 100 substrates

[0032] 101 gate

[0033] 102 Source Region

[0034] 103 Drain region

[0035] 110 High-pressure P-type trap

[0036] 200 Ring-shaped silicide barrier layer

[0037] 201 Gate silicide layer

[0038] 202 Source Silice Layer

[0039] 203 Drain silicide layer

[0040] AA Active (Active) Region

[0041] ST Quarantine Zone

[0042] CH channel (channel) region

[0043] GD gate dielectric layer

[0044] SP gap wall

[0045] D Annular Groove

[0046] w width

[0047] s width

[0048] Steps S1~S6 Detailed Implementation

[0049] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and which illustrate specific examples in which the embodiments may be practiced. The embodiments described below are described in sufficient detail to enable those skilled in the art to implement them.

[0050] Of course, other embodiments may be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the following detailed description should not be regarded as limiting; rather, the embodiments included therein will be defined by the appended claims.

[0051] Please see Figures 1 to 3 ,in, Figure 1 This is a top view schematic diagram of a semiconductor device according to an embodiment of the present invention. Figure 2 This is a schematic cross-sectional view along the tangent I-I'. Figure 3 This is a schematic cross-sectional view along tangent II-II'. Figures 1 to 3 As shown, semiconductor device 1 includes a substrate 100 having an active region AA and an isolation region ST surrounding the active region AA. According to embodiments of the present invention, the substrate 100 may be, for example, a P-type silicon substrate, but is not limited thereto. According to embodiments of the present invention, the isolation region ST may be, for example, a shallow trench insulating region. According to embodiments of the present invention, semiconductor device 1 may further include a high-voltage P-type well 110 disposed in the substrate 100.

[0052] According to an embodiment of the present invention, the semiconductor device 1 further includes along... Figure 1 The gate 101 extends along the reference y-axis and spans the active region AA. According to an embodiment of the invention, the gate 101 is, for example, a polysilicon gate, but is not limited thereto.

[0053] According to an embodiment of the present invention, the semiconductor device 1 further includes a source region 102 and a drain region 103 disposed in the active region AA, and defining a channel region CH therebetween. According to an embodiment of the present invention, a gate 101 is disposed above the channel region CH. According to an embodiment of the present invention, the semiconductor device 1 further includes a gate dielectric layer GD disposed between the gate 101 and the channel region CH. According to an embodiment of the present invention, the gate dielectric layer GD is, for example, a silicon dioxide layer, but is not limited thereto.

[0054] According to an embodiment of the present invention, the semiconductor device 1 further includes an annular silicide barrier layer 200 disposed along the periphery of the active region AA. According to an embodiment of the present invention, as... Figure 2 and Figure 3 As shown, an annular groove D is formed at the boundary between the isolation region ST and the active region AA, wherein the annular silicide barrier layer 200 overlaps with the annular groove D.

[0055] According to embodiments of the present invention, the width w of the annular silicide barrier layer 200 is, for example, 0.2 to 0.4 micrometers. According to embodiments of the present invention, the annular silicide barrier layer 200 comprises, for example, silicon oxide, silicon nitride, or a combination thereof.

[0056] According to an embodiment of the present invention, the annular silicide barrier layer 200 completely covers the annular groove D and extends to the peripheral portion of the active region AA adjacent to the annular groove D. According to an embodiment of the present invention, the width s of the peripheral portion of the active region AA overlapping with the annular silicide barrier layer 200 ranges from 0 to 0.1 micrometers.

[0057] According to embodiments of the present invention, such as Figure 3 As shown, the semiconductor device 1 further includes a source silicide layer 202 disposed on the source region 102 not covered by the annular silicide barrier layer 200, a drain silicide layer 203 disposed on the drain region 103 not covered by the annular silicide barrier layer 200, and a gate silicide layer 201 disposed on the gate 101 not covered by the annular silicide barrier layer 200.

[0058] According to an embodiment of the present invention, the source silicide layer 202 and the drain silicide layer 203 are in direct contact with the annular silicide barrier layer 200, but not in direct contact with the isolation region ST, which can effectively improve the breakdown voltage uniformity of the medium voltage (MV) components of the embedded flash memory device.

[0059] According to embodiments of the present invention, such as Figure 2 and Figure 3 As shown, the semiconductor device 1 further includes a spacer wall SP disposed on the sidewall of the gate 101, wherein, as Figure 2 As shown, the annular silicide barrier layer 200 extends onto the spacer wall SP and the gate 101. According to embodiments of the invention, the spacer wall SP may comprise, for example, silicon nitride, but is not limited thereto.

[0060] Please also refer to Figure 4 This illustrates the fabrication process of a semiconductor device. For example... Figures 1 to 4 As shown, firstly, step S1 is performed, providing a substrate 100 having an active region AA and an isolation region ST surrounding the active region AA. According to an embodiment of the present invention, for example, the substrate 100 may be a P-type silicon substrate, but is not limited thereto. According to an embodiment of the present invention, for example, the isolation region ST may be formed using a shallow trench insulation fabrication process.

[0061] According to an embodiment of the present invention, the semiconductor device 1 may further include a high-voltage P-type well 110 disposed in the substrate 100. According to an embodiment of the present invention, as... Figures 2 to 3 As shown, an annular groove D is formed at the boundary between the isolation region ST and the active region AA.

[0062] Next, proceed Figure 4 In step S2, an oxidation or deposition process is performed to form a gate dielectric layer GD on the active region AA. According to embodiments of the present invention, the gate dielectric layer GD is, for example, a silicon dioxide layer, but is not limited thereto.

[0063] Next, proceed Figure 4 In step S3, a gate 101 is formed above the gate dielectric layer GD. According to an embodiment of the present invention, as... Figure 1 As shown, gate 101 along Figure 1 The reference y-axis extends in the direction of the reference y-axis and spans the active region AA. According to an embodiment of the invention, the gate 101 is, for example, a polysilicon gate, but is not limited thereto. According to an embodiment of the invention, such as... Figures 2 to 3 As shown, a spacer wall SP is formed on the sidewall of the gate 101. According to an embodiment of the present invention, the spacer wall SP comprises, for example, silicon nitride.

[0064] Next, proceed Figure 4 In step S4, a source region 102 and a drain region 103 are formed in the active region AA using photolithography and ion implantation processes, and a channel region CH is defined therebetween.

[0065] Next, proceed Figure 4 In step S5, a ring-shaped silicide barrier layer 200 is formed along the periphery of the active region AA using deposition, photolithography, and etching processes. According to an embodiment of the present invention, as... Figures 2 to 3 As shown, an annular silicide barrier layer 200 is formed along an annular groove D at the boundary between the isolation region ST and the active region AA, wherein the annular silicide barrier layer 200 overlaps with the annular groove D.

[0066] According to embodiments of the present invention, such as Figures 2 to 3 As shown, the annular silicide barrier layer 200 completely covers the annular groove D and extends to the peripheral portion of the active region AA adjacent to the annular groove D. According to an embodiment of the present invention, the annular silicide barrier layer 200 comprises, for example, silicon oxide, silicon nitride, or a combination thereof.

[0067] According to an embodiment of the present invention, the width s of the peripheral portion of the active region AA overlapping with the annular silicide barrier layer 200 ranges from 0 to 0.1 micrometers. According to an embodiment of the present invention, the width w of the annular silicide barrier layer 200 ranges from 0.2 to 0.4 micrometers.

[0068] Next, proceed Figure 4In step S6, a metal silicide fabrication process is performed to form a source silicide layer 202 on the source region 102 not covered by the annular silicide barrier layer 200; a drain silicide layer 203 on the drain region 103 not covered by the annular silicide barrier layer 200; and a gate silicide layer 201 on the gate 101 not covered by the annular silicide barrier layer 200.

[0069] According to embodiments of the present invention, such as Figure 3 As shown, the source silicide layer 202 and the drain silicide layer 203 do not directly contact the isolation region ST. According to an embodiment of the present invention, as... Figure 2 As shown, the annular silicide barrier layer 200 extends onto the spacer wall SP and the gate 101.

[0070] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor device comprising: The substrate has an active region and an isolation region surrounding the active region; The source and drain regions are located within the active region, and a channel region is defined therebetween. A gate is disposed above the channel region; A gate dielectric layer is disposed between the gate and the channel region; as well as A ring-shaped silicide barrier layer is disposed along the periphery of the active region.

2. The semiconductor device of claim 1, wherein, An annular groove is formed at the boundary between the isolation region and the active region, wherein the annular silicide barrier layer overlaps with the annular groove.

3. The semiconductor device as claimed in claim 2, wherein, The annular silicide barrier layer completely covers the annular groove and extends to the periphery of the active region adjacent to the annular groove.

4. The semiconductor device of claim 3, wherein, The width of the peripheral portion of the active region ranges from 0 to 0.1 micrometers.

5. The semiconductor device of claim 1, wherein, The width of the annular silicide barrier layer ranges from 0.2 to 0.4 micrometers.

6. The semiconductor device of claim 1, wherein, The annular silicide barrier layer comprises silicon oxide, silicon nitride, or a combination thereof.

7. The semiconductor device of claim 1, further comprising: A source silicide layer is disposed on the source region that is not covered by the annular silicide barrier layer; A drain silicide layer is disposed on the drain region not covered by the annular silicide barrier layer; and A gate silicide layer is disposed on the gate that is not covered by the annular silicide barrier layer.

8. The semiconductor device of claim 7, wherein, The source silicide layer and the drain silicide layer are not in direct contact with the isolation region.

9. The semiconductor device of claim 1, further comprising: A spacer wall is disposed on the sidewall of the gate, wherein, The annular silicide barrier layer extends to the spacer wall and the gate.

10. The semiconductor device of claim 9, wherein, The spacer wall contains silicon nitride.

11. A method of forming a semiconductor device, comprising: A substrate is provided having an active region and an isolation region surrounding the active region; The source and drain regions are formed in this active region, and the channel region is defined in between; A gate is formed above this channel region; A gate dielectric layer is formed between the gate and the channel region; and A ring-shaped silicide barrier layer is formed along the periphery of the active region.

12. The method of claim 11, wherein, An annular groove is formed at the boundary between the isolation region and the active region, wherein the annular silicide barrier layer overlaps with the annular groove.

13. The method of claim 12, wherein, The annular silicide barrier layer completely covers the annular groove and extends to the periphery of the active region adjacent to the annular groove.

14. The method of claim 13, wherein, The width of the peripheral portion of the active region ranges from 0 to 0.1 micrometers.

15. The method of claim 11, wherein, The width of the annular silicide barrier layer ranges from 0.2 to 0.4 micrometers.

16. The method of claim 1, wherein, The annular silicide barrier layer comprises silicon oxide, silicon nitride, or a combination thereof.

17. The method of claim 11, further comprising: A source silicide layer is formed on the source region that is not covered by the annular silicide barrier layer; A drain silicide layer is formed on the drain region not covered by the annular silicide barrier layer; and A gate silicide layer is formed on the gate that is not covered by the annular silicide barrier layer.

18. The method of claim 17, wherein, The source silicide layer and the drain silicide layer are not in direct contact with the isolation region.

19. The method of claim 11, further comprising: A gap wall is formed on the sidewall of the gate, wherein, The annular silicide barrier layer extends to the spacer wall and the gate.

20. The method of claim 19, wherein, The spacer wall contains silicon nitride.

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