Resistive random access memory element

Abstract

A resistive random access memory includes an interlayer dielectric layer disposed on a substrate, a contact plug disposed in the interlayer dielectric layer, a lower electrode disposed on the contact plug, an impedance conversion layer disposed on the lower electrode, and an upper electrode disposed on the impedance conversion layer, wherein the upper electrode includes one or more upper electrodes and the one or more upper electrodes include titanium nitride.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a resistive random access memory device. Background Technology

[0002] Because non-volatile memory (NDRAM) retains data even after power is off, it is essential for many electronic products to maintain normal operation when powered on. Currently, one type of NDRAM being actively developed in the industry is resistive random access memory (RRAM), which offers advantages such as low write operation voltage, short write / erase time, long memory duration, non-destructive reading, multi-state memory, simple structure, and small area requirement. Therefore, it is expected to become one of the most widely used NDRAM components in personal computers and electronic devices in the future.

[0003] In integrated circuit (IC) devices, resistive random access memory (RRAM) is a converged technology for next-generation non-volatile memory devices. Resistive random access memory is a memory structure comprising an array of resistive random access memory cells, each of which stores one bit of data using a resistance value rather than charge. Specifically, each resistive random access memory cell includes a resistive material layer whose resistance value can be adjusted to represent logic "0" or logic "1".

[0004] One way to optimize resistive random access memory cell arrays is to make them smaller and smaller. However, as the size decreases, the manufacturing process becomes more complex and costs increase. Therefore, how to improve the existing manufacturing process while maintaining product yield and reducing costs is a major challenge for the industry. Summary of the Invention

[0005] An embodiment of the present invention discloses a resistive random access memory, which mainly includes an interlayer dielectric layer disposed on a substrate, a contact plug disposed within the interlayer dielectric layer, a lower electrode disposed on the contact plug, an impedance conversion layer disposed on the lower electrode, and an upper electrode disposed on the impedance conversion layer, wherein the upper electrode includes one or more upper electrodes and the one or more upper electrodes include titanium nitride.

[0006] Another embodiment of the present invention discloses a resistive random access memory, comprising an interlayer dielectric layer disposed on a substrate, a contact plug disposed within the interlayer dielectric layer, a lower electrode disposed on the contact plug, an impedance switching layer disposed on the lower electrode, and an upper electrode disposed on the impedance switching layer, wherein the upper electrode comprises titanium nitride with a nitrogen concentration gradient. Attached Figure Description

[0007] Figures 1 to 7 This is a schematic diagram illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0008] Figure 8 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention;

[0009] Figure 9 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention;

[0010] Figure 10 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention;

[0011] Figure 11 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention.

[0012] Symbol explanation:

[0013] 12: Base

[0014] 14: Interlayer dielectric layer

[0015] 16: Gate Structure

[0016] 18: Source / Drain Region

[0017] 20: Contact plug

[0018] 22: Barrier Layer

[0019] 24: Low-resistivity metal layer

[0020] 30: Lower electrode

[0021] 36: Groove

[0022] 44: Impedance Transformation Layer

[0023] 46: Covering layer

[0024] 48: Upper electrode

[0025] 50: Resistive Random Access Memory

[0026] 52: Covering layer

[0027] 54: Intermetallic dielectric layer

[0028] 56: Metal interconnects

[0029] 58: Stop Layer

[0030] 60: Intermetallic dielectric layer

[0031] 62: Metal interconnects

[0032] 64: Contact hole conductor

[0033] 66: Trench conductor

[0034] 68: Stop Layer

[0035] 72: Alignment Mark

[0036] 102: Alignment Marker Area

[0037] 104: Resistive Random Access Memory Area

[0038] 106: Logic Area Detailed Implementation

[0039] Please refer to Figures 1 to 7 , Figures 1 to 7 This is a schematic diagram illustrating a method for fabricating a semiconductor device, or more specifically, a resistive random access memory device, according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of semiconductor material, wherein the semiconductor material can be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and preferably a alignment mark (AM) region 102, a resistive random access memory region 104 and a logic region 106 are defined on the substrate 12.

[0040] The substrate 12 of the resistive random access memory region 104 and the logic region 106 may contain active (active) elements such as metal-oxide-semiconductor (MOS) transistors, passive (passive) elements, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 14 covering the substrate. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor elements, wherein the MOS transistor may include a gate structure 16 (e.g., a metal gate) and source / drain regions 18, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 14 may be disposed on the substrate 12 and cover the MOS transistor, and the interlayer dielectric layer 14 may have multiple contact plugs 20 electrically connecting the gate structure 16 and / or the source / drain regions 18 of the MOS transistor. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here. It should be noted that at this stage, only an interlayer dielectric layer 14 is provided on the substrate 12 of the alignment mark area 102, but preferably no active or passive components are provided.

[0041] In this embodiment, the fabrication of each contact plug 20 can first involve a pattern transfer fabrication process. For example, a patterned mask (not shown) can be used to remove a portion of the interlayer dielectric layer 14 of the resistive random access memory region 104 to form contact holes (not shown) and expose the underlying source / drain regions 18. Then, the desired metal or conductive material is filled into the contact holes, such as a barrier layer 22 comprising titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer 24 selected from low-resistance materials such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or combinations thereof. Next, a planarization fabrication process is performed, such as chemical mechanical polishing (CMP) to remove a portion of the metal material to form contact plugs 20 or metal interconnects electrically connecting the source / drain regions 18 within the contact holes.

[0042] Next, an optional pattern transfer fabrication process can be performed, for example, by removing part of the contact plugs 20 using a patterned mask to form a groove directly above each contact plug 20 and making the top surface of the remaining contact plugs 20 slightly lower than the top surface of the interlayer dielectric layers 14 on both sides. Then, a lower electrode 30 is formed on the interlayer dielectric layer 14 of the alignment mark area 102, the resistive random access memory area 104, and the logic area 106, filling the groove directly above the contact plugs 20. In this embodiment, the lower electrode 30 preferably comprises a metal nitride, such as tantalum nitride (TaN), and its thickness at this stage can be between 100 and 200 angstroms.

[0043] Subsequently, as Figure 2 As shown, a patterned mask 34, for example, a patterned photoresist, is first formed on the lower electrode 30 of the alignment mark region 102, the resistive random access memory region 104, and the logic region 106. The patterned mask 34 has an opening that exposes the surface of the lower electrode 30 of the alignment mark region 102. Then, an etching process is performed using the patterned mask to remove part of the lower electrode 30 and part of the interlayer dielectric layer 14 of the alignment mark region 102 to form a groove 36. This groove 36 can be used as an alignment mark 72 for the alignment mark region 102 in subsequent fabrication processes.

[0044] like Figure 3As shown, the patterned mask 34 is then removed using oxygen to expose the lower electrode 30 again. An impedance switching layer 44, a masking layer 46, and an upper electrode 48 are then sequentially formed on the surface of the lower electrode 30. In this embodiment, the impedance switching layer 44 may comprise a metal oxide layer such as tantalum oxide (TaO) or hafnium oxide (HfO2), the masking layer 46 preferably comprises a metal such as iridium (Ir), and the upper electrode 48 preferably comprises a metal nitride such as titanium nitride (TiN). In this embodiment, the upper electrode 48 is preferably composed of a single-layer structure and is preferably a nitrogen-rich layer. The nitrogen concentration or atomic percentage in the upper electrode 48 is preferably between 30 and 60 at%, and the upper electrode 48 preferably does not contain a nitrogen concentration gradient. In other words, the nitrogen content at any point in the upper electrode 48 is preferably the same concentration, or the nitrogen concentration throughout the layer is preferably evenly distributed.

[0045] It should be noted that in this embodiment, after removing the patterned mask 34 and before forming the impedance conversion layer 44, a pre-clean fabrication process can be selectively performed using, for example, argon plasma to remove the metal oxide layer formed by removing the patterned mask. Then, a planarization process, such as chemical mechanical polishing (CMP), can be performed to remove a portion of the interlayer dielectric layer 14 of the alignment mark region 102, all lower electrodes 30, and a portion of the lower electrodes 30 of the resistive random access memory region 104 and the logic region 106, slightly reducing their thickness. The thickness of the remaining lower electrodes 30 after the planarization process is preferably between 50 and 100 angstroms.

[0046] like Figure 4 As shown, a patterned mask, such as a patterned photoresist, can then be used to perform one or more etching processes to remove all the upper electrodes 48, all the masking layers 46, all the impedance conversion layers 44, and all the lower electrodes 30 of the alignment mark region 102 and the logic region 106. At the same time, some of the upper electrodes 48, some of the masking layers 46, some of the impedance conversion layers 44, and some of the lower electrodes 30 of the resistive random access memory region 104 are removed, thereby exposing the surface of the interlayer dielectric layer 14 of the alignment mark region 102 and the logic region 106, and forming a resistive random access memory 50 by the patterned lower electrode 30, the patterned impedance conversion layer 44, the patterned masking layer 46, and the patterned upper electrode 48 of the resistive random access memory region 104. Then a masking layer 52 is formed on the surface of the interlayer dielectric layer 14 of the alignment mark area 102 and in the groove 36, on the resistive random access memory 50 of the resistive random access memory area 104 and on the surface of the interlayer dielectric layer 14 of the logic area 106.

[0047] It should be noted that when the upper electrode 48, part of the cover layer 46, part of the impedance conversion layer 44, and part of the lower electrode 30 are patterned in this stage to form the resistive random access memory 50, part of the interlayer dielectric layer 14 on both sides of the resistive random access memory 50 may be removed so that the top surface of the remaining interlayer dielectric layer 14 is slightly lower than the bottom surface of the lower electrode 30 or even lower than the top surface of the contact plug 20. Thus, after the cover layer 52 is subsequently formed, the bottom surface of the cover layer 52 on both sides of the resistive random access memory 50 can vary depending on the height of the interlayer dielectric layer 14. For example, the bottom surface of the cover layer 52 on both sides of the resistive random access memory 50 can be flush with or lower than the bottom surface of the lower electrode 30 or lower than the top surface of the contact plug 20, all of which fall within the scope of this invention.

[0048] Furthermore, the masking layer 52 preferably includes a dielectric material such as silicon carbide (SiOC), silicon carbide (SiCN), or silicon nitride (SiN), and the etching process performed to pattern the resistive random access memory 50 in this stage may include reactive ion etching (RIE) and / or ion beam etching (IBE), but is not limited to these.

[0049] Subsequently, as Figure 5 As shown, an intermetallic dielectric layer 54 can be formed using a process such as flowable chemical vapor deposition (FCVD) to fill the grooves 36 in the alignment mark region 102, the resistive random access memory region 104, and the logic region 106, and to cover the resistive random access memory 50 and the interlayer dielectric layer 14. In this embodiment, the intermetallic dielectric layer 54 preferably comprises an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, such as, but not limited to, silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH).

[0050] Then as Figure 6 As shown, a planarization process is performed, for example, by using a chemical mechanical polishing (CMP) process to remove part of the intermetallic dielectric layer 54, so that the top of the intermetallic dielectric layer 54 of the alignment mark region 102, the resistive random access memory region 104 and the logic region 106 is approximately flush with the top surface of the cover layer 52.

[0051] Next, a pattern transfer fabrication process is performed. For example, a patterned mask (not shown) can be used to remove part of the intermetallic dielectric layer 54 and part of the masking layer 52 of the logic region 106 to form contact holes (not shown) to expose the underlying contact plugs 20. Then, the contact holes are filled with the desired metal material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization fabrication process is performed, such as a chemical mechanical polishing process to remove part of the metal material to form contact plugs or metal interconnects 56 that electrically connect the contact plugs 20 below within the contact holes. Then, a stop layer 58 is formed on the alignment mark region 102, the resistive random access memory region 104, and the intermetallic dielectric layer 54 of the logic region 106. The stop layer 58 may include, but is not limited to, a nitrogen-doped carbide (NDC), silicon nitride, silicon carbon nitride (SiCN), or silicon oxynitride (SiON).

[0052] Subsequently, as Figure 7As shown, another intermetallic dielectric layer 60 is formed on the surface of the stop layer 58. Then, one or more photolithography and etching processes are performed to remove portions of the intermetallic dielectric layer 60, the stop layer 58, and the masking layer 52 of the resistive random access memory region 104 and the logic region 106, forming contact holes (not shown). Next, conductive material is filled into the contact holes, and a planarization process such as CMP is used to form metal interconnects 62 connecting the upper electrode 48 below and the metal interconnects 56. Then, another stop layer 68 is formed on the surface of the metal interconnects 62. As with the aforementioned metal interconnects 56, the metal interconnects 62 disposed within the intermetallic dielectric layer 60 can be embedded within the intermetallic dielectric layer 60 using a single damascene fabrication process or a double damascene fabrication process. For example, the metal interconnects 62 of the resistive random access memory area 104 and the logic area 106 may further include via conductors 64 connecting the underlying resistive random access memory 50 and the metal interconnects 56, and the trench conductors 66 are disposed on the via conductors 64. The metal interconnects 62 may further include a barrier layer and a metal layer. The barrier layer may be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer may be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt-tungsten phosphide (CoWP), etc., but is not limited to these.

[0053] In this embodiment, the intermetallic dielectric layer 60 preferably comprises an ultra-low dielectric constant dielectric layer, such as a porous dielectric material, but not limited to silicon oxycarbide (SiOC). The stop layer 68 may comprise, but is not limited to, a nitrogen-doped carbide layer (NDC), silicon nitride (SiN), or silicon nitride carbide (SiCN), and more preferably, silicon nitride, but is not limited thereto. This completes the fabrication of a semiconductor device according to an embodiment of the present invention.

[0054] Please continue to refer to Figure 8 , Figure 8 This is a schematic diagram of a semiconductor device according to an embodiment of the present invention. In order to highlight the various states of the upper electrode 48, the alignment mark region 102 is preferably omitted in this embodiment and subsequent embodiments. Figure 8As shown, compared to the single-layer structure of the upper electrode 48 in the previous embodiment, the upper electrode 48 in this embodiment can be composed of one or more layers, such as a first upper electrode 82 and a second upper electrode 84. The first upper electrode 82, located in the lower contact cover layer 46, comprises a metal nitride such as titanium nitride (TiN), and the upper second upper electrode 84 comprises a metal such as titanium (Ti). The first upper electrode 82 and the second upper electrode 84 can have the same or different thicknesses. (Similar to...) Figure 7 In this embodiment, the upper electrode 48, and the first upper electrode 82, are preferably nitrogen-rich layers, meaning that the nitrogen concentration or atomic percentage in the first upper electrode 82 is preferably between 30 and 60 at%, and the first upper electrode 82 preferably does not contain a nitrogen concentration gradient. In other words, the nitrogen content at any point in the first upper electrode 82 is preferably the same concentration, or the nitrogen concentration throughout the layer is preferably evenly distributed.

[0055] Please continue to refer to Figure 9 , Figure 9 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. Figure 9 As shown, compared to the single or double layer composition of the upper electrode 48 in the previous embodiments, the upper electrode 48 can also be composed of three material layers. For example, it may include a first upper electrode 82 disposed on the cover layer 46, a second upper electrode 84 disposed on the first upper electrode 82, and a third upper electrode 86 disposed on the second upper electrode 84. In this embodiment, the first upper electrode 82 disposed in the lower layer in contact with the cover layer 46 contains a metal nitride such as titanium nitride (TiN), the middle second upper electrode 84 contains a metal such as titanium (Ti), and the upper third upper electrode 86, like the first upper electrode 82, contains a metal nitride such as titanium nitride (TiN). The first upper electrode 82, the second upper electrode 84, and the third upper electrode 86 may have the same or different thicknesses. Figure 7 In this embodiment, the upper electrode 48, the first upper electrode 82, and the third upper electrode 86 are both nitrogen-rich layers. That is, the nitrogen concentration or atomic percentage in the first upper electrode 82 and the third upper electrode 86 is preferably between 30 and 60 at%, and neither the first upper electrode 82 nor the third upper electrode 86 contains a nitrogen concentration gradient. In other words, the nitrogen content at any point in the first upper electrode 82 and the third upper electrode 86 is preferably the same concentration, or the nitrogen concentration throughout the layer is preferably evenly distributed.

[0056] Please continue to refer to Figure 10 , Figure 10 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. Figure 10As shown, the upper electrode 48 in this embodiment comprises only a single-layer structure, wherein the bottom surface of the upper electrode 48 contacts the cover layer 46, the upper electrode 48 comprises a metal nitride such as titanium nitride (TiN), and the upper electrode 48 contains a nitrogen concentration gradient. More specifically, in this embodiment, the nitrogen concentration in the upper electrode 48 is preferably non-uniformly distributed, such that the nitrogen concentration in the upper electrode 48 preferably increases from top to bottom, as shown by the arrow direction in the figure. In other words, there is a higher nitrogen concentration near the bottom surface of the upper electrode 48 and a lower nitrogen concentration near the top surface of the upper electrode 48, or a lower titanium concentration near the bottom surface of the upper electrode 48 and a higher titanium concentration near the top surface of the upper electrode 48. In this embodiment, controlling the nitrogen concentration near the bottom surface of the upper electrode 48 to a higher level avoids titanium oxide (TiO2) concentration. x It undergoes a redox reaction.

[0057] Please continue to refer to Figure 11 , Figure 11 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. Figure 11 As shown, the upper electrode 48 in this embodiment includes a first upper electrode 82 and a second upper electrode 84, wherein the first upper electrode 82 and the second upper electrode 84 may have the same or different thicknesses. The first upper electrode 82, which is disposed on the lower contact cover layer 46, contains a metal nitride such as titanium nitride (TiN), while the upper second upper electrode 84 contains a metal such as titanium (Ti), and the first upper electrode 82 contains a nitrogen concentration gradient. As... Figure 10 In the upper electrode 48, the nitrogen concentration in the first upper electrode 82 in this embodiment is preferably unevenly distributed, such as the nitrogen concentration of the first upper electrode 82 preferably increasing from top to bottom, as shown by the arrow in the figure. In other words, there is a higher nitrogen concentration near the bottom surface of the first upper electrode 82 and a lower nitrogen concentration near the top surface of the first upper electrode 82, or a lower titanium concentration near the bottom surface of the first upper electrode 82 and a higher titanium concentration near the top surface of the first upper electrode 82. As in the previous embodiment, controlling the nitrogen concentration near the bottom surface of the first upper electrode 82 to a higher level can prevent ruthenium dioxide from undergoing a reduction oxidation reaction, and the titanium metal of the upper second upper electrode 84 can be used to reduce the overall component resistance.

[0058] In summary, this invention mainly discloses a method for fabricating a resistive random access memory (RAM) element. The method primarily involves first forming contact plugs 20 within an interlayer dielectric layer 14 to electrically connect or contact the source / drain regions of an active element, such as a MOS transistor, disposed on a substrate. Then, a resistive RAM 50, consisting of at least a lower electrode 30, an impedance conversion layer 44, a cover layer 46, and an upper electrode 48, is formed on the contact plugs. The upper electrode 48 may comprise a single-layer or composite layer structure. Preferably, the upper electrode 48 contains a metal nitride, such as titanium nitride (TiN), and the upper electrode with titanium nitride may contain a nitrogen concentration gradient (e.g., ...). Figures 10 to 11 Examples) or concentration gradients that do not contain oxygen (such as Figures 7 to 9 (Example). According to a preferred embodiment of the present invention, providing a titanium / titanium nitride composite composition or a titanium nitride layer with a nitrogen concentration gradient in the upper electrode as described in the foregoing embodiment can reduce the redox reaction and prevent atoms such as titanium or nitrogen from diffusing downward into the impedance conversion layer, thereby improving the overall performance of the device.

[0059] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A resistive random access memory, characterized in that, Include: An interlayer dielectric layer is disposed on the substrate; Contact plugs are disposed within the interlayer dielectric layer; The lower electrode is located on the contact plug; An impedance conversion layer is disposed on the lower electrode; as well as An upper electrode is disposed on the impedance conversion layer, wherein the upper electrode comprises one or more upper electrodes and the one or more upper electrodes comprises titanium nitride.

2. The resistive random access memory of claim 1, wherein the upper electrode comprises: A first upper electrode is disposed on the impedance conversion layer; and The second upper electrode is disposed on the first upper electrode.

3. The resistive random access memory of claim 2, wherein the first upper electrode comprises titanium nitride and the second upper electrode comprises titanium.

4. The resistive random access memory of claim 1, wherein the upper electrode comprises: The first upper electrode is disposed on the impedance conversion layer; The second upper electrode is disposed on the first upper electrode; and The third upper electrode is disposed on the second upper electrode.

5. The resistive random access memory of claim 4, wherein the first upper electrode comprises titanium nitride.

6. The resistive random access memory of claim 4, wherein the second upper electrode comprises titanium.

7. The resistive random access memory as claimed in claim 4, wherein the third upper electrode comprises titanium nitride.

8. The resistive random access memory as claimed in claim 1, further comprising: A shielding layer is disposed next to the upper electrode; A first intermetallic dielectric layer surrounds the shielding layer; A second intermetallic dielectric layer is disposed on the first intermetallic dielectric layer; and The metal interconnect is located within the second intermetallic dielectric layer and connected to the upper electrode.

9. A resistive random access memory, characterized in that, Include: An interlayer dielectric layer is disposed on the substrate; The contact plug is located within the interlayer dielectric layer; The lower electrode is located on the contact plug; An impedance conversion layer is disposed on the lower electrode; as well as An upper electrode is disposed on the impedance conversion layer, wherein the upper electrode comprises titanium nitride with a nitrogen concentration gradient.

10. The resistive random access memory of claim 9, wherein the upper electrode comprises: A first upper electrode is disposed on the impedance conversion layer; and The second upper electrode is disposed on the first upper electrode.

11. The resistive random access memory of claim 10, wherein the first upper electrode comprises titanium nitride with a nitrogen concentration gradient.

12. The resistive random access memory of claim 11, wherein the bottom surface near the first upper electrode contains a high concentration of nitrogen.

13. The resistive random access memory of claim 12, wherein the second upper electrode comprises titanium.

14. The resistive random access memory of claim 9, wherein the upper electrode comprises a single-layer structure.

15. The resistive random access memory of claim 14, wherein the bottom surface near the upper electrode contains a high concentration of nitrogen.

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