Package structure and method of manufacturing the same

Abstract

The present disclosure provides a packaging structure and a manufacturing method thereof. The packaging structure includes a substrate including a first wiring layer; one or more adapter boards located on a first side of the substrate, each adapter board including a second wiring layer connected to the first wiring layer, the one or more adapter boards including a first adapter board; and one or more stacks located on the first side of the substrate, each stack including one or more chips, the one or more stacks including a first stack connected to the second wiring layer in the first adapter board, wherein an arrangement direction of the one or more stacks is perpendicular to a thickness direction of the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a packaging structure and its manufacturing method. Background Technology

[0002] Chip packaging is a crucial aspect of semiconductor manufacturing. Multiple integrated circuits are packaged into a single package structure to achieve chip integration. Different package structures require different packaging substrate designs. Summary of the Invention

[0003] According to one aspect of this disclosure, a packaging structure is provided, comprising: a substrate including a first wiring layer; one or more adapter plates located on a first side of the substrate, each adapter plate including a second wiring layer connected to the first wiring layer, the one or more adapter plates including the first adapter plate; and one or more stacks located on the first side of the substrate, each stack including one or more chips, the one or more stacks including the first stack, the first stack being connected to the second wiring layer in the first adapter plate, wherein the arrangement direction of the one or more stacks and the one or more adapter plates is perpendicular to the thickness direction of the substrate.

[0004] In some embodiments, the one or more adapter boards further include a second adapter board; the one or more stacks further include a second stack connected to a second wiring layer in the second adapter board.

[0005] In some embodiments, the one or more stacks further include a second stack connected to a second wiring layer in the first adapter board.

[0006] In some embodiments, the substrate further includes a plurality of first pads located between the first wiring layer and the one or more adapter boards and connected to the first wiring layer; each adapter board further includes a plurality of second pads and a plurality of third pads located between the second wiring layer and the substrate, the plurality of second pads being connected to the second wiring layer and connected to the plurality of first pads, the second wiring layer being located between the plurality of third pads and the substrate, and the plurality of third pads being connected to the second wiring layer and the one or more stacks.

[0007] In some embodiments, the package structure further includes: a first lead connected to the plurality of third pads and the one or more stacks.

[0008] In some embodiments, the packaging structure further includes: a packaging layer covering the one or more adapter plates and the one or more stacks; and a plurality of metal bumps located on a second side of the substrate and connected to the first wiring layer, wherein the second side is opposite to the first side.

[0009] In some embodiments, the adapter board includes a printed circuit board, an interposer, or another substrate.

[0010] According to another aspect of this disclosure, a packaging structure is provided, comprising: a substrate including a first wiring layer; one or more adapter plates located on a first side of the substrate, each adapter plate including a second wiring layer connected to the first wiring layer, the one or more adapter plates including a first adapter plate; one or more stacks located on the first side of the substrate, each stack including one or more first chips, the one or more stacks including a first stack, the first stack being connected to a second wiring layer in the first adapter plate, wherein the arrangement direction of the one or more stacks and the one or more adapter plates is perpendicular to the thickness direction of the substrate; and a second chip connected to the second wiring layer in the first adapter plate, wherein the first adapter plate is located between the second chip and the substrate.

[0011] In some embodiments, the one or more adapter boards further include a second adapter board; the one or more stacks further include a second stack connected to a second wiring layer in the second adapter board.

[0012] In some embodiments, the one or more stacks further include a second stack connected to a second wiring layer in the first adapter board.

[0013] In some embodiments, the substrate further includes a plurality of first pads located between the first wiring layer and the one or more adapter boards and connected to the first wiring layer; each adapter board further includes a plurality of second pads and a plurality of third pads located between the second wiring layer and the substrate, the plurality of second pads being connected to the second wiring layer and connected to the plurality of first pads, the second wiring layer being located between the plurality of third pads and the substrate, and the plurality of third pads being connected to the second wiring layer and the one or more stacks.

[0014] In some embodiments, the package structure further includes: a first lead connected to the plurality of third pads and the one or more stacks.

[0015] In some embodiments, the package structure further includes a second lead connected to a second wiring layer in the second chip and the first adapter board.

[0016] In some embodiments, the packaging structure further includes a flip-chip structure located between the second chip and the first adapter board, and connected to a second wiring layer in the second chip and the first adapter board.

[0017] In some embodiments, the flip-chip structure includes: a fourth pad located between the second chip and a second wiring layer in the first adapter board; and a filler layer filling the area around the fourth pad.

[0018] In some embodiments, the packaging structure further includes: a packaging layer covering the one or more adapter boards, the one or more stacks and the second chip; and a plurality of metal bumps located on a second side of the substrate and connected to the first wiring layer, wherein the second side is opposite to the first side.

[0019] In some embodiments, the first chip is a memory chip; the second chip is a control chip.

[0020] According to another aspect of this disclosure, a method for manufacturing a package structure is provided, comprising: obtaining a substrate and one or more adapter plates, wherein the substrate includes a first wiring layer, each adapter plate includes a second wiring layer, and the one or more adapter plates include a first adapter plate; disposing the one or more adapter plates on a first side of the substrate, wherein the second wiring layer is connected to the first wiring layer; disposing one or more stacks on the first side of the substrate, each stack including one or more first chips, the one or more stacks including a first stack, wherein the arrangement direction of the one or more stacks and the one or more adapter plates is perpendicular to the thickness direction of the substrate; and connecting the first stack to the second wiring layer in the first adapter plate.

[0021] In some embodiments, connecting the first stack to the second wiring layer in the first adapter board includes: connecting the first stack to the second wiring layer in the first adapter board using a first lead.

[0022] In some embodiments, the manufacturing method further includes: disposing a second chip on the side of the first adapter board away from the substrate, and connecting the second chip to a second wiring layer of the first adapter board.

[0023] In some embodiments, connecting the second chip to the second wiring layer of the first adapter board includes: connecting the second chip to the second wiring layer of the first adapter board using a second lead or a flip-chip structure.

[0024] In some embodiments, the manufacturing method further includes: forming an encapsulation layer covering the one or more adapter boards and the one or more stacks; and distributing a plurality of metal bumps on a second side of the substrate, wherein the plurality of metal bumps are connected to the first wiring layer, and the second side is opposite to the first side.

[0025] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0026] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0027] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0028] Figure 1A This is a schematic cross-sectional view illustrating a packaging structure according to some embodiments of the present disclosure;

[0029] Figure 1B This is a schematic enlarged cross-sectional view of an adapter plate according to some embodiments of the present disclosure;

[0030] Figure 2 This is a schematic cross-sectional view illustrating a packaging structure according to other embodiments of the present disclosure;

[0031] Figure 3 This is a schematic cross-sectional view illustrating a packaging structure according to other embodiments of the present disclosure;

[0032] Figure 4 This is a schematic cross-sectional view illustrating a packaging structure according to other embodiments of the present disclosure;

[0033] Figure 5 This is a schematic cross-sectional view illustrating a packaging structure according to other embodiments of the present disclosure;

[0034] Figure 6 This is a schematic cross-sectional view illustrating a packaging structure according to other embodiments of the present disclosure;

[0035] Figure 7 This is a flowchart illustrating a method for manufacturing a packaging structure according to some embodiments of the present disclosure;

[0036] Figure 8A This is a schematic cross-sectional view illustrating a stage in the manufacturing process of a packaging structure according to some embodiments of the present disclosure;

[0037] Figure 8BThis is a top view schematically illustrating a stage in the manufacturing process of a packaging structure according to some embodiments of the present disclosure;

[0038] Figure 8C This is a schematic cross-sectional view illustrating one stage of the manufacturing process of a packaging structure according to some embodiments of the present disclosure;

[0039] Figure 8D This is a top view schematically illustrating one stage of the manufacturing process of a packaging structure according to some embodiments of the present disclosure;

[0040] Figure 9 This is a schematic cross-sectional view illustrating another stage of the manufacturing process of a packaging structure according to some embodiments of the present disclosure;

[0041] Figure 10 This is a schematic cross-sectional view illustrating another stage of the manufacturing process of a packaging structure according to some embodiments of the present disclosure;

[0042] Figure 11 This is a schematic cross-sectional view illustrating another stage of the manufacturing process of a packaging structure according to some embodiments of the present disclosure;

[0043] Figure 12 This is a schematic cross-sectional view illustrating another stage of the manufacturing process of a packaging structure according to some embodiments of the present disclosure;

[0044] Figure 13A This is a schematic cross-sectional view illustrating a stage in the manufacturing process of a packaging structure according to other embodiments of the present disclosure;

[0045] Figure 13B This is a top view schematically illustrating a stage in the manufacturing process of a packaging structure according to other embodiments of the present disclosure;

[0046] Figure 13C This is a schematic cross-sectional view illustrating one stage of the manufacturing process of a packaging structure according to other embodiments of the present disclosure;

[0047] Figure 13D This is a top view schematically illustrating one stage of the manufacturing process of a packaging structure according to other embodiments of the present disclosure;

[0048] Figure 14A This is a schematic cross-sectional view illustrating another stage of the manufacturing process of the packaging structure according to other embodiments of the present disclosure;

[0049] Figure 14BThis is a top view schematically illustrating another stage of the manufacturing process of the packaging structure according to other embodiments of this disclosure;

[0050] Figure 15 This is a schematic cross-sectional view illustrating another stage of the manufacturing process of the packaging structure according to other embodiments of the present disclosure;

[0051] Figure 16 This is a schematic cross-sectional view illustrating another stage of the manufacturing process of the packaging structure according to other embodiments of the present disclosure;

[0052] Figure 17 This is a schematic cross-sectional view illustrating another stage of the manufacturing process of the packaging structure according to other embodiments of the present disclosure.

[0053] It should be understood that the dimensions of the various parts shown in the accompanying drawings are not drawn to actual scale. Furthermore, the same or similar reference numerals denote the same or similar components. Detailed Implementation

[0054] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The descriptions of the exemplary embodiments are merely illustrative and are in no way intended to limit the present disclosure or its application or use. The present disclosure may be implemented in many different forms and is not limited to the embodiments described herein. These embodiments are provided so that the present disclosure will be thorough and complete, and will fully express the scope of the disclosure to those skilled in the art. It should be noted that, unless specifically stated otherwise, the relative arrangement of components and steps, the composition of materials, numerical expressions, and values ​​set forth in these embodiments should be interpreted as exemplary only and not as limiting.

[0055] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different parts. Words such as "including" or "contains" mean that the element preceding the word encompasses the element listed after it, and do not exclude the possibility of encompassing other elements as well. Terms such as "above," "below," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, this relative positional relationship may also change accordingly.

[0056] In this disclosure, when a specific device is described as being located between a first device and a second device, an intermediary device may or may not be present between the specific device and the first or second device. When a specific device is described as being connected to other devices, the specific device may be directly connected to the other devices without an intermediary device, or it may be not directly connected to the other devices but have an intermediary device. Here, the connections involved in this disclosure may include conductive connections.

[0057] All terms used in this disclosure (including technical or scientific terms) have the same meaning as understood by one of ordinary skill in the art to which this disclosure pertains, unless otherwise specifically defined. It should also be understood that terms defined in a general dictionary, such as a dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or highly formalized meaning, unless expressly defined herein.

[0058] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0059] The inventors of this disclosure have discovered that different packaging structures require different packaging substrate designs. That is, in the packaging process, a custom-designed substrate is used, which leads to a longer design cycle and increases production costs due to the inability to share molds.

[0060] In view of this, embodiments of the present disclosure provide a packaging structure to shorten the design cycle and reduce production costs.

[0061] Figure 1A This is a schematic cross-sectional view illustrating a packaging structure according to some embodiments of the present disclosure. Figure 1B This is a schematic enlarged cross-sectional view of an adapter plate according to some embodiments of the present disclosure.

[0062] like Figure 1A As shown, the packaging structure includes a substrate 10. The substrate 10 includes a first wiring layer 11. For example, the substrate 10 may also include a first insulating layer 101, a second insulating layer 102, and a third insulating layer 103. The first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 surround the first wiring layer 11. For example, the materials of the first insulating layer 101 and the third insulating layer 103 include ink. The first and third insulating layers can serve as insulation and protection. For example, the material of the second insulating layer 102 includes a dielectric material (e.g., resin and / or glass fiber, etc.). Figure 1A As shown, the substrate 10 includes a first surface 10a and a second surface 10b opposite to the first surface 10a. Here, the substrate can be a universally designed substrate. This universally designed substrate can be used in different generations of memory products, such as memory products with increased NAND layers or memory products with different control chips.

[0063] like Figure 1AAs shown, the packaging structure also includes one or more adapter plates 20. These one or more adapter plates 20 are located on a first side of the substrate 10. That is, the one or more adapter plates 20 are located on the first surface 10a of the substrate 10. Figure 1A and Figure 1B As shown, each adapter board 20 includes a second wiring layer 22. The second wiring layer 22 is connected to the first wiring layer 11. The adapter board includes a first adapter board. For example, Figure 1A The diagram shows two adapter plates 20a and 20b. Adapter plate 20a can be referred to as the first adapter plate, and adapter plate 20b can be referred to as the second adapter plate. Figure 1A and Figure 1B As shown, the first adapter board 20a includes a second wiring layer 22a, and the second adapter board 20b includes a second wiring layer 22b. Figure 1B A first adapter board 20a is schematically shown. For example, the adapter board 20 may include a printed circuit board, an interposer, or a substrate. For instance, the circuit wiring structure of the substrate used as the adapter board may differ from that of the general-purpose substrate (i.e., substrate 10), but the material of the adapter board may be the same as that of the general-purpose substrate. The adapter board may also be a silicon interposer layer, etc. The adapter board can be designed according to product requirements; that is, a customized adapter board may be used. The adapter board can be adaptively adjusted according to the characteristics of the actual product; for example, the internal circuit structure of the adapter board may be adjusted.

[0064] like Figure 1A As shown, the packaging structure also includes one or more stacks 30. These stacks 30 are located on the first side of the substrate 10, specifically on the first surface 10a of the substrate 10. Each stack includes one or more chips 310. Here, multiple chips 310 are stacked in each stack. For example, the number of stacked chips in each stack can be 4, 8, 16, etc. It should also be noted that a stack including only one chip 310 can be considered a special stacking configuration. Each stack can be stepped. The chip 310 is a memory chip. For example, the chip 310 is a NAND (e.g., rNAND (rawNAND)) chip or a DRAM (Dynamic Random Access Memory) chip. Here, rNAND refers to a NAND product that has a NAND chip but no other chips (e.g., a control chip). The stack includes a first stack 31, which is connected to the second wiring layer 22a in the first adapter board 20a.

[0065] For example, Figure 1AThe diagram shows two stacks, 31 and 32. Stack 31 can be referred to as the first stack, and stack 32 as the second stack. One or more chips 310 included in the first stack 31 are connected to the second wiring layer 22a in the first adapter board 20a. One or more chips 310 included in the second stack 32 are connected to the second wiring layer 22b in the second adapter board 20b.

[0066] Here, the arrangement direction of one or more stacked bodies 30 and one or more adapter plates 20 is perpendicular to the thickness direction of the substrate 10. For example... Figure 1A As shown, the stack and the adapter plate are arranged in the X direction, which is parallel to the first surface 10a of the substrate 10; the thickness direction of the substrate 10 is the Y direction, which is perpendicular to the first surface 10a of the substrate 10. Here, the stack 30 and the adapter plate 20 are arranged perpendicular to the thickness direction of the substrate 10. That is, the stack 30 and the adapter plate 20 are laid flat on the first surface 10a of the substrate. This reduces the overall thickness of the packaging structure, which is beneficial for achieving a thinner and lighter packaging design.

[0067] This provides a packaging structure according to some embodiments of the present disclosure. The packaging structure includes: a substrate including a first wiring layer; one or more adapter plates located on a first side of the substrate, each adapter plate including a second wiring layer connected to the first wiring layer, the one or more adapter plates including the first adapter plate; and one or more stacks located on the first side of the substrate, each stack including one or more chips, the one or more stacks including the first stack, the first stack being connected to the second wiring layer in the first adapter plate, wherein the arrangement direction of the one or more stacks and the one or more adapter plates is perpendicular to the thickness direction of the substrate. In this packaging structure, the stacks are electrically connected to the substrate through adapter plates. Different adapter plates can be used for different products, while the substrate can be a general-purpose substrate. Therefore, this packaging structure can shorten the design cycle, has a simple structure and process, and reduce production costs.

[0068] Here, the wiring structure inside the universal substrate can meet the connection requirements of different generations of memory products to other devices. For example, metal bumps that meet standard layout requirements can be set on the universal substrate for connection with other devices. The wiring structure inside the adapter board can meet the connection requirements of memory products of the same generation with the universal substrate. Different adapter boards can be used for different generations of memory products. In this way, when designing the package structure, it is necessary to design the corresponding adapter board, but it is not necessary to redesign the universal substrate. Therefore, the design cycle can be shortened, the structural process is simplified, and the production cost is reduced.

[0069] As mentioned above, Figure 1AAs shown, one or more adapter boards include a first adapter board 20a and a second adapter board 20b. In some embodiments, the structure of the second wiring layer 22a in the first adapter board 20a is the same as the structure of the second wiring layer 22b in the second adapter board 20b. Here, the structure of the second wiring layer is the wiring structure of the second wiring layer.

[0070] For example, in an rNAND product, the rNAND product has multiple adapter boards, and the wiring structure of the second wiring layer of any two adapter boards is the same.

[0071] As mentioned above, Figure 1A As shown, one or more stacks include a first stack 31 and a second stack 32. In some embodiments, the number and type of chips in the first stack 31 are the same as the number and type of chips in the second stack 32. For example, the number of chips in both the first stack 31 and the second stack 32 is 4, and the type of chips in both the first stack 31 and the second stack 32 is rNAND chips.

[0072] The first stack 31 is connected to the second wiring layer 22a in the first adapter board 20a, and the second stack 32 is connected to the second wiring layer 22b in the second adapter board 20b. For example, multiple stacks are connected to multiple adapter boards in a one-to-one correspondence. In this way, multiple stacks can be connected to multiple adapter boards on the same substrate.

[0073] like Figure 1A As shown, the substrate 10 may further include a plurality of first pads 12. These first pads 12 are located between the first wiring layer 11 and one or more adapter boards 20. The plurality of first pads 12 are connected to the first wiring layer 11. By providing the first pads, the connection between the substrate and the adapter board can be facilitated.

[0074] like Figure 1A and Figure 1B As shown, each adapter board 20 may further include a plurality of second pads 21 and a plurality of third pads 24. The plurality of second pads 21 are located between the second wiring layer 22 and the substrate 10. The plurality of second pads 21 are connected to the second wiring layer 22 and to the aforementioned plurality of first pads 12. For example, the plurality of second pads 21 are connected to the plurality of first pads 12 in a one-to-one correspondence. The plurality of third pads 24 are located on the side of the second wiring layer 22 away from the substrate. That is, the second wiring layer 22 is located between the plurality of third pads 24 and the substrate 10. The plurality of third pads 24 are connected to the second wiring layer 22 and one or more stacks 30. Here, by providing the second pads, the connection between the adapter board and the substrate can be facilitated; by providing the third pads, the connection between the adapter board and the stack can be facilitated.

[0075] In some embodiments, the first pad 12, the second pad 21, and the third pad 24 may be circular, elliptical, square, or other shapes, respectively. It should be noted that the scope of this disclosure is not limited to the specific shapes of these pads.

[0076] like Figure 1A and Figure 1B As shown, the third pad 24 in the first adapter plate 20a is connected to the first stack 31, and the third pad 24 in the second adapter plate 20b is connected to the second stack 32. The first stack 31 and the second stack 32 are located between the first adapter plate 20a and the second adapter plate 20b. In a direction parallel to the first surface 10a of the substrate 10 (i.e., the X direction), the first end (e.g., the right end) 2011 of the first adapter plate 20a is closer to the first stack 31 than the second end (e.g., the left end) 2012 of the first adapter plate 20a. At this time, the aforementioned plurality of third pads 24 in the first adapter plate 20a are closer to the first end 2011 of the first adapter plate 20a than the second end 2012 of the first adapter plate 20a. In a direction parallel to the first surface 10a of the substrate 10 (i.e., the X direction), the first end (e.g., the left end) 2013 of the second adapter plate 20b is closer to the second stack 32 than the second end (e.g., the right end) 2014 of the second adapter plate 20b. At this time, the aforementioned plurality of third pads 24 in the second adapter plate 20b are closer to the first end 2013 of the second adapter plate 20b than the second end 2014 of the second adapter plate 20b. By designing the position of the third pads on each adapter plate in this way, the connection between the adapter plate and the stack can be facilitated.

[0077] like Figure 1A and Figure 1B As shown, the adapter board 20 may further include a fourth insulating layer 201, a fifth insulating layer 202, and a sixth insulating layer 203. The fourth insulating layer 201, the fifth insulating layer 202, and the sixth insulating layer 203 surround the second wiring layer 22. For example, the materials of the fourth insulating layer 201 and the sixth insulating layer 203 include ink. These fourth and sixth insulating layers can serve as insulation and protection. The material of the fifth insulating layer 202 includes a dielectric material (e.g., resin and / or glass fiber, etc.).

[0078] like Figure 1A As shown, the package structure may further include a first lead 41. The first lead 41 is connected to the aforementioned plurality of third pads 24 of the adapter board and the aforementioned one or more stacks 30. That is, the stacks are connected to the adapter board via the first lead 41. In this embodiment, one or more chips 310 in the stack are connected to the corresponding adapter board via the first lead 41, and the adapter board is connected to the substrate, thus realizing the electrical connection between the stack and the substrate.

[0079] In some embodiments, the material of the first lead 41 includes metals such as gold. It should be noted that the scope of this disclosure is not limited to the specific material of the first lead.

[0080] like Figure 1A As shown, the encapsulation structure also includes an encapsulation layer 50. This encapsulation layer 50 covers one or more adapter boards 20 and one or more stacks 30. The encapsulation layer 50 is located on the first surface 10a of the substrate 10. For example, the material of the encapsulation layer includes epoxy molding compound, etc. This encapsulation layer enables the sealing of the adapter boards and stacks.

[0081] like Figure 1A As shown, the package structure also includes a plurality of metal bumps 60. These metal bumps 60 are located on a second side of the substrate 10. Here, the second side of the substrate 10 is opposite to the first side of the substrate 10. In other words, the plurality of metal bumps 60 are located on the second surface 10b of the substrate 10. Furthermore, the plurality of metal bumps 60 are connected to the first wiring layer 11. For example, the metal bumps include solder balls. Through these metal bumps, the package structure can be connected to other devices.

[0082] Figure 2 This is a schematic cross-sectional view illustrating a packaging structure according to other embodiments of the present disclosure.

[0083] and Figure 1A Compared to the packaging structure shown, Figure 2 The difference in the packaging structure shown is that multiple stacked units can be connected to the same adapter board. For example, as... Figure 2 The packaging structure shown can be applied to products such as rNAND.

[0084] like Figure 2 As shown, the packaging structure includes a substrate 10, one or more adapter boards 20, and one or more stacks 30. The one or more adapter boards 20 include a first adapter board 20, which includes a second wiring layer 22. The one or more stacks 30 include a first stack 31 and a second stack 32. The first stack 31 is connected to the second wiring layer 22 in the first adapter board 20, and the second stack 32 is also connected to the second wiring layer 22 in the first adapter board 20. The number and type of chips in the first stack 31 are the same as the number and type of chips in the second stack 32. By connecting multiple stacks to the same adapter board, the sharing of the adapter board by multiple stacks is achieved, which can reduce the number of adapter boards and lower production costs.

[0085] As can be seen from the description above, the number of adapter boards can be set according to actual needs. For example, for... Figure 1AThe packaging structure shown can include at least two adapter boards (e.g., the number of adapter boards equals the number of stacked components). For example, for a package like... Figure 2 The packaging structure shown can be configured with an adapter board, allowing multiple stacks to share the same adapter board.

[0086] and Figure 1A The packaging structure shown is similar, in Figure 2 In the illustrated package structure, the substrate 10 may include a plurality of first pads 12, and the first adapter board 20 may include a plurality of second pads 21 and a plurality of third pads 24. The plurality of second pads 21 are connected to the second wiring layer 22 and to the plurality of first pads 12. The plurality of third pads 24 are connected to the second wiring layer 22 and to the plurality of stacks 30.

[0087] like Figure 2 As shown, a first portion of the plurality of third pads 24 in the first adapter board 20 is connected to the first stack 31, and a second portion of the plurality of third pads 24 in the first adapter board 20 is connected to the second stack 32. The first portion of the pads is closer to the first stack 31 than the second portion of the pads. The second portion of the pads is closer to the second stack 32 than the first portion of the pads. This arrangement of the third pad positions facilitates the connection of multiple stacks to the same pad.

[0088] in addition, Figure 2 The packaging structure shown has the same as Figure 1A Components with the same or similar packaging structure as those shown can be referred to in the previous section. Figure 1A The descriptions of the same or similar components in the package structure shown will not be repeated here.

[0089] Figure 3 This is a schematic cross-sectional view illustrating a packaging structure according to other embodiments of the present disclosure.

[0090] like Figure 3 As shown, the package structure includes a substrate 10. The substrate 10 includes a first wiring layer 11. Similar to the previous description, the substrate 10 may also include a first insulating layer 101, a second insulating layer 102, and a third insulating layer 103 surrounding the first wiring layer 11. Figure 3 As shown, the substrate 10 includes a first surface 10a and a second surface 10b opposite to the first surface 10a. Here, the substrate can be a substrate of a general design.

[0091] like Figure 3As shown, the packaging structure also includes one or more adapter boards 20. These adapter boards 20 are located on a first side of the substrate 10. That is, the one or more adapter boards 20 are located on a first surface 10a of the substrate 10. Each adapter board includes a second wiring layer 22. The second wiring layer 22 is connected to a first wiring layer 11. The adapter board includes a first adapter board 20. For example, the adapter board 20 may include a printed circuit board, an interposer, or a substrate. For example, the circuit wiring structure of the substrate used as the adapter board may differ from the circuit wiring structure of the general substrate (i.e., substrate 10), but the material of the adapter board may be the same as that of the general substrate. The adapter board can be designed according to product requirements; that is, the adapter board may be a customized adapter board.

[0092] like Figure 3 As shown, the packaging structure also includes one or more stacks 30. These stacks 30 are located on a first side of the substrate 10. They are located on a first surface 10a of the substrate 10. Each stack includes one or more first chips 310. For example, in each stack, the number of stacked first chips can be 4, 8, 16, etc. Here, the first chip 310 is a memory chip. For example, the first chip is a NAND (e.g., mNAND (manage NAND)) chip or a DRAM chip. Here, mNAND is a NAND product having a NAND chip and a control chip. The one or more stacks include a first stack 31. The first stack 31 is connected to a second wiring layer 22 in the first adapter plate 20. Similar to the previous description, the arrangement direction of the one or more stacks 30 and the one or more adapter plates is perpendicular to the thickness direction of the substrate 10.

[0093] like Figure 3 As shown, the package structure also includes a second chip 70. The second chip 70 is connected to the second wiring layer 22 in the first adapter board 20. The second chip 70 is located on the side of the first adapter board 20 away from the substrate 10. That is, the first adapter board 20 is located between the second chip 70 and the substrate 10. Here, the second chip is a control chip.

[0094] This provides a packaging structure according to other embodiments of the present disclosure. The packaging structure includes: a substrate including a first wiring layer; one or more adapter plates located on a first side of the substrate, each adapter plate including a second wiring layer connected to the first wiring layer, the one or more adapter plates including the first adapter plate; one or more stacks located on the first side of the substrate, each stack including one or more first chips, the one or more stacks including the first stack, the first stack connected to the second wiring layer in the first adapter plate, wherein the arrangement direction of the one or more stacks and the one or more adapter plates is perpendicular to the thickness direction of the substrate; and a second chip connected to the second wiring layer in the first adapter plate, wherein the first adapter plate is located between the second chip and the substrate. In this packaging structure, the stacks are electrically connected to the substrate through adapter plates. Different adapter plates can be used for different products, while a general-purpose substrate can be used. Therefore, this packaging structure can shorten the design cycle, simplify the structural process, and reduce production costs. Moreover, the packaging structure also integrates a second chip, further improving the integration of the packaging structure.

[0095] like Figure 3 As shown, one or more stacks 30 may further include a second stack 32. The second stack 32 is connected to the second wiring layer 22 in the first adapter board 20. That is, in Figure 3 In the packaging structure shown, both the first stack 31 and the second stack 32 are connected to the second wiring layer 22 in the first adapter board 20. That is, multiple stacks can be connected to the same adapter board. This can reduce the number of adapter boards and lower production costs.

[0096] In some embodiments, the number and type of chips in the first stack 31 are the same as the number and type of chips in the second stack 32. For example, both the first stack 31 and the second stack 32 contain four chips, and both are mNAND chips. In such a case, the multiple stacks can share the same adapter board and the same second chip. This reduces the number of adapter boards and the number of second chips, thus lowering production costs.

[0097] In other embodiments, one or more adapter boards may include a second adapter board in addition to a first adapter board, and one or more stacks may include a first stack and a second stack, wherein the first stack is connected to a second wiring layer in the first adapter board, the second stack is connected to a second wiring layer in the second adapter board, and a second chip located on the first adapter board is connected to the second wiring layer in the first adapter board but not to the second wiring layer in the second adapter board.

[0098] In this case, the structure of the second wiring layer in the first adapter board (i.e., the wiring structure) is different from the structure of the second wiring layer in the second adapter board; the number or type of the first chip in the first stack is different from the number or type of the first chip in the second stack. Therefore, the stacks and adapter boards can be configured such that different stacks are connected to different adapter boards. That is, in the package structure, multiple stacks can be connected to different adapter boards.

[0099] Back Figure 3 The substrate 10 may also include a plurality of first pads 12, which are located between the first wiring layer 11 and one or more adapter boards 20 and are connected to the first wiring layer 11.

[0100] like Figure 3 As shown, each adapter board 20 may further include a plurality of second pads 21 and a plurality of third pads 24. The plurality of second pads 21 are located between the second wiring layer 22 and the substrate 10. The plurality of second pads 21 are connected to the second wiring layer 22 and to the aforementioned plurality of first pads 12. The plurality of third pads 24 are located on the side of the second wiring layer 22 away from the substrate 10. That is, the second wiring layer 22 is located between the plurality of third pads 24 and the substrate 10. The plurality of third pads 24 are connected to the second wiring layer 22 and one or more stacks 30. For example, the plurality of third pads 24 are connected to a first stack 31 and a second stack 32.

[0101] like Figure 3 As shown, the first stack 31 is connected to a first portion of the pads among the plurality of third pads 24 in the first adapter board 20, and the second stack 32 is connected to a second portion of the pads among the plurality of third pads 24 in the first adapter board 20. The first portion of the pads is closer to the first stack 31 than the second portion of the pads, and the second portion of the pads is closer to the second stack 32 than the first portion of the pads. This allows multiple stacks to be connected to the same adapter board, reducing the number of adapter boards and lowering production costs.

[0102] In other embodiments, one or more stacks include a first stack and a second stack, and one or more adapter boards include a first adapter board and a second adapter board, wherein a second chip located on the first adapter board is connected to a second wiring layer in the first adapter board but not to a second wiring layer in the second adapter board, a plurality of third pads in the first adapter board are connected to the first stack, and a plurality of third pads in the second adapter board are connected to the second stack. Figure 1A The packaging structure shown similarly has a first end (e.g., the right end, similar to) of the first adapter plate in a direction parallel to the first surface of the substrate (i.e., the X direction). Figure 1A The first end (2011) of the first adapter plate is different from the second end (e.g., the left end, similar to) of the first adapter plate. Figure 1A The second end (2012) is closer to the first stack, and at this time, the plurality of third pads in the first adapter board are closer to the first end of the first adapter board than the second end of the first adapter board; in a direction parallel to the first surface of the substrate (i.e., the X direction), the first end of the second adapter board (e.g., the left end, similar to...) Figure 1A The first end (2013) of the middle plate is different from the second end (e.g., the right end, similar to) of the second adapter plate. Figure 1A The second end (2014) is closer to the second stack, and at this time, multiple third pads in the second adapter board are closer to the first end of the second adapter board than the second end of the second adapter board.

[0103] Back Figure 3 ,and Figure 1A The packaging structure shown is similar, in Figure 3 In the packaging structure shown, the adapter board 20 may further include a fourth insulating layer 201, a fifth insulating layer 202, and a sixth insulating layer 203. The fourth insulating layer 201, the fifth insulating layer 202, and the sixth insulating layer 203 surround the second wiring layer 22.

[0104] like Figure 3 As shown, the package structure may further include a first lead 41. The first lead 41 is connected to a plurality of third pads 24 and one or more stacks 30. That is, the stacks 30 are connected to the plurality of third pads 24 of the first adapter board via the first lead 41. This achieves an electrical connection between the stacks and the adapter board.

[0105] like Figure 3 As shown, the package structure may further include a second lead 42. The second lead 42 is connected to the second chip 70 and the second wiring layer 22 in the first adapter board 20. That is, the second chip 70 is connected to the second wiring layer 22 in the first adapter board 20 through the second lead 42. This achieves an electrical connection between the second chip and the adapter board.

[0106] In some embodiments, the material of the second lead 42 includes metals such as gold. It should be noted that the scope of this disclosure is not limited to the specific material of the first lead.

[0107] like Figure 3 As shown, the packaging structure may further include a packaging layer 50. The packaging layer 50 covers one or more adapter boards 20, one or more stacks 30, and a second chip 70. The packaging layer 50 is located on the first surface 10a of the substrate 10.

[0108] like Figure 3As shown, the package structure may further include a plurality of metal bumps 60. These metal bumps 60 are located on a second side of the substrate, opposite to the first side. That is, the plurality of metal bumps 60 are located on the second surface 10b of the substrate. The plurality of metal bumps 60 are connected to the first wiring layer 11.

[0109] Additionally, it should be noted that, Figure 3 The packaging structure shown also includes other related components. Figure 1A or Figure 2 Components with the same or similar packaging structure shown will not be described in detail again; please refer to the previous section on... Figure 1A or Figure 2 Description of the components of the package structure shown.

[0110] Figure 4 This is a schematic cross-sectional view illustrating a packaging structure according to other embodiments of the present disclosure.

[0111] and Figure 3 Compared to the packaging structure shown, Figure 4 The difference in the packaging structure shown is that: Figure 4 In the packaging structure shown, the second chip is connected to the first adapter board through a flip-chip structure.

[0112] like Figure 4 As shown, the packaging structure includes a flip-chip structure 80. The flip-chip structure 80 is located between the second chip 70 and the first adapter board 20, and is connected to the second wiring layer 22 in both the second chip 70 and the first adapter board 20.

[0113] For example, such as Figure 4 As shown, the flip-chip structure 80 includes a fourth pad 81 and a filler layer 82. The fourth pad 81 is located between the second chip 70 and the second wiring layer 22 in the first adapter board 20. The fourth pad 81 connects to the second chip 70 and the second wiring layer 22, thus achieving an electrical connection between the second chip and the second wiring layer. The filler layer 82 fills around the fourth pad 81. That is, the filler layer 82 surrounds the fourth pad 81. The filler layer 82 can be made of an insulating material such as epoxy resin, which can serve as insulation and support.

[0114] In the above embodiments, the second chip is connected to the first adapter board through a flip-chip structure, which provides another way to connect the second chip to the first adapter board.

[0115] It should be noted that, Figure 4 The packaging structure shown also includes other related components. Figure 3 Components with the same or similar packaging structure shown will not be described in detail again; please refer to the previous section on... Figure 3 Description of the components of the package structure shown.

[0116] Figure 5 This is a schematic cross-sectional view illustrating a packaging structure according to other embodiments of the present disclosure.

[0117] like Figure 5 As shown, the package structure includes a substrate 10. The substrate 10 includes a first wiring layer 11. Similar to the previous description, the substrate 10 may also include a first insulating layer 101, a second insulating layer 102, and a third insulating layer 103 surrounding the first wiring layer 11. Figure 3 As shown, the substrate 10 includes a first surface 10a and a second surface 10b opposite to the first surface 10a. Here, the substrate can be a substrate of a general design.

[0118] In some embodiments, such as Figure 5 As shown, the substrate 10 may also include a support portion 104, which is located on the first side of the first wiring layer 11.

[0119] like Figure 5 As shown, the packaging structure also includes one or more adapter plates 20. The one or more adapter plates 20 are located on a first side of the substrate 10. That is, the one or more adapter plates 20 are located on the first surface 10a of the substrate 10. The adapter plate 20 is stepped. Each adapter plate 20 includes a second wiring layer 22. The second wiring layer 22 is connected to the first wiring layer 11. An adapter plate includes a first adapter plate. For example, Figure 5 The diagram shows two adapter plates 20a and 20b. Adapter plate 20a can be referred to as the first adapter plate, and adapter plate 20b can be referred to as the second adapter plate. Figure 5 As shown, the first adapter board 20a includes a second wiring layer 22a, and the second adapter board 20b includes a second wiring layer 22b. For example, the adapter board 20 may include another substrate, etc. The adapter board can be designed according to product requirements; that is, the adapter board is a customized adapter board.

[0120] like Figure 5 As shown, the adapter board 20 may further include a fourth insulating layer 201, a fifth insulating layer 202, and a sixth insulating layer 203. The fourth insulating layer 201, the fifth insulating layer 202, and the sixth insulating layer 203 surround the second wiring layer 22.

[0121] like Figure 5As shown, the packaging structure also includes one or more stacks 30. These stacks 30 are located on a first side of the substrate 10. For example, the stacks 30 are located on a support portion 104 of the substrate 10. Each stack 30 includes one or more chips 310. Here, in each stack, multiple chips 310 are stacked. For example, in each stack, the number of stacked chips can be 4, 8, 16, etc. It should also be noted that if a stack includes only one chip 310, this can be considered a special stacking configuration. This chip 310 is a memory chip. For example, this chip is a NAND (e.g., rNAND) chip or a DRAM chip. The stack includes a first stack 31, which is connected to a second wiring layer in a first adapter board.

[0122] For example, Figure 5 Two stacks, 31 and 32, are shown. Stack 31 can be referred to as the first stack, and stack 32 as the second stack. For example, the number and type of chips in the first stack 31 are the same as the number and type of chips in the second stack 32. One or more chips 310 included in the first stack 31 are connected to the second wiring layer 22a in the first adapter board 20a. One or more chips 310 included in the second stack 32 are connected to the second wiring layer 22b in the second adapter board 20b.

[0123] Thus, packaging structures according to other embodiments of this disclosure are provided. In this packaging structure, the stack is electrically connected to the substrate via an adapter plate. Different adapter plates can be used for different products, while a general-purpose substrate can be used. Therefore, this packaging structure can shorten the design cycle, and the structural process is simple, reducing production costs.

[0124] In related technologies, the inventors of this disclosure have also discovered that in multi-chip packaging designs, the arc height of the bonding wires occupies a lot of vertical space, making it difficult to achieve thinness and reducing product competitiveness. Moreover, such multi-chip packaging designs may require the chip thickness to be reduced due to the requirement of total package thickness, which will reduce product yield and product performance.

[0125] By employing the packaging structure described in this embodiment, the thickness of the entire packaging structure can be reduced by eliminating the need for leads. This allows for an increase in the thickness of each chip while still meeting the thickness requirements of the packaging structure. Therefore, the packaging structure in this embodiment allows for an increase in the thickness of each chip, thereby improving product yield and performance.

[0126] like Figure 5As shown, the packaging structure includes a connection structure 90 that connects the stack 30 and the adapter plate 20. For example, the connection structure 90 includes a connector 91 between the stack 30 and the adapter plate 20, and a filler layer (which may be referred to as a first filler layer) 92 surrounding the connector 91. The connector is made of a metallic material, and the filler layer 92 is made of an insulating material such as epoxy resin. The connector enables electrical connection between the stack and the adapter plate, and the filler layer provides insulation and support.

[0127] In addition, similar to the previous description, the substrate 10 may also include a plurality of first pads 12, the adapter board 20 may also include a plurality of second pads 21, and the packaging structure may also include a packaging layer 50 and a plurality of metal bumps 60. These first pads 12, second pads 21, packaging layer 50 and metal bumps 60, etc., can be referred to the previous description and will not be repeated here.

[0128] Here, it should be noted that, in Figure 5 In the packaging structure shown, the absence of leads in the packaging structure allows for an increase in the mold cap clearance of the packaging layer (for example, the mold cap clearance can be understood as the distance from the upper surface of the packaging layer to the upper surface of other parts of the packaging structure (e.g., the stack), thereby improving the 3PB (Three-Point Bending) mechanical properties of the product.

[0129] Figure 6 This is a schematic cross-sectional view illustrating a packaging structure according to other embodiments of the present disclosure.

[0130] and Figure 5 Compared to the packaging structure shown, Figure 6 The difference in the packaging structure shown is that: Figure 6 The package structure shown includes a substrate 10, an adapter plate 20, a stack 30, a packaging layer 50, and metal bumps 60, as well as a second chip 70 located on a first side of the substrate 10. For example, this second chip is located above the support portion 104 of the substrate 10. The second chip 70 is connected to the first wiring layer 11 in the substrate 10. Here, the second chip is a control chip.

[0131] In addition, such as Figure 6 As shown, the packaging structure may also include a flip-chip structure 80. The flip-chip structure 80 is located between the second chip 70 and the support portion 104 of the substrate 10. For example, as Figure 6As shown, the flip-chip structure 80 includes a fourth pad 81 and a filler layer (which may be referred to as a second filler layer) 82. The fourth pad 81 is located between the second chip 70 and the support portion 104, and is connected to the second chip and the first wiring layer 11. This achieves the connection between the second chip and the first wiring layer. The filler layer 82 fills around the fourth pad 81. That is, the filler layer 82 surrounds the fourth pad 81. This filler layer 82 is made of an insulating material such as epoxy resin, which can serve as insulation and support.

[0132] Figure 7 This is a flowchart illustrating a method for manufacturing a packaging structure according to some embodiments of the present disclosure. For example... Figure 7 As shown, the manufacturing method includes steps S702 to S708.

[0133] In step S702, a substrate and one or more adapter boards are obtained, wherein the substrate includes a first wiring layer, each adapter board includes a second wiring layer, and the one or more adapter boards include the first adapter board.

[0134] In step S704, one or more adapter boards are disposed on the first side of the substrate, wherein the second wiring layer is connected to the first wiring layer.

[0135] In step S706, one or more stacks are disposed on a first side of the substrate, each stack including one or more first chips, and the one or more stacks including the first stack. The arrangement direction of the one or more stacks and the one or more adapter plates is perpendicular to the thickness direction of the substrate.

[0136] In step S708, the first stack body is connected to the second wiring layer in the first adapter board.

[0137] Thus, a method for manufacturing a packaging structure according to some embodiments of the present disclosure is provided. In this manufacturing method, the stack is electrically connected to the substrate via an adapter plate. Different adapter plates can be used for different products, while a general-purpose substrate can be used. Therefore, the packaging structure formed by this manufacturing method can shorten the design cycle and reduce production costs.

[0138] Figures 8A to 12 This is a schematic diagram illustrating several stages in the manufacturing process of a packaging structure according to some embodiments of the present disclosure. The following is in conjunction with... Figures 8A to 12 as well as Figure 2 A method for manufacturing a packaging structure according to some embodiments of the present disclosure is described in detail.

[0139] like Figure 8A and Figure 8B As shown, substrate 10 is obtained. For example, it can be formed by processes such as deposition, coating, photolithography, and etching. Figure 8A and Figure 8B The substrate 10 shown includes a first wiring layer 11. The substrate 10 also includes a first insulating layer 101, a second insulating layer 102, and a third insulating layer 103. The first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 surround the first wiring layer 11. The substrate 10 also includes a plurality of first pads 12. The plurality of first pads 12 are connected to the first wiring layer 11.

[0140] like Figure 8C and Figure 8D As shown, the adapter plate 20 is obtained. For example, it can be formed through processes such as deposition, coating, photolithography, and etching. Figure 8C and Figure 8D The adapter board 20 shown includes a second wiring layer 22. The adapter board 20 also includes a fourth insulating layer 201, a fifth insulating layer 202, and a sixth insulating layer 203. The fourth insulating layer 201, the fifth insulating layer 202, and the sixth insulating layer 203 surround the second wiring layer 22. The adapter board 20 also includes a plurality of second pads 21 and a plurality of third pads 24. The plurality of second pads 21 and the third pads 24 are all connected to the second wiring layer 22.

[0141] Next, as Figure 9 As shown, the adapter plate 20 is disposed on the first side of the substrate 10. That is, the adapter plate 20 is disposed on the first surface 10a of the substrate 10. The second wiring layer 22 is connected to the first wiring layer 11. For example, by means of a soldering process, the first pad 12 of the substrate 10 and the second pad 21 of the adapter plate 20 are connected correspondingly, thereby connecting the second wiring layer 22 to the first wiring layer 11.

[0142] Next, as Figure 10 As shown, one or more stacks 30 are disposed on the first side of the substrate 10, and each stack includes one or more first chips 310. For example, as Figure 10 As shown, the one or more stacks 30 include a first stack 31 and a second stack 32. The stacks 30 and the adapter plate 20 are arranged in a direction perpendicular to the thickness direction of the substrate 10.

[0143] Next, as Figure 11 As shown, for example, a first stack 31 is connected to a second wiring layer 22 in a first adapter board 20 using a first lead 41 via a wire bonding process. As another example, a second stack 32 can also be connected to a second wiring layer 22 in a first adapter board 20 using another first lead 41 via a wire bonding process. For example, the above wire bonding process may include: forming gold balls, forming first solder joints, forming wire arcs, forming second solder joints, and breaking metal wires, etc. An embodiment of connecting multiple stacks to the same adapter board has been described here.

[0144] In other embodiments, different stacks can be connected to different adapter boards. For example, a first stack can be connected to a first adapter board using a first lead, and a second stack can be connected to a second adapter board using another first lead.

[0145] Next, a packaging layer is formed to cover the adapter board and the stack. For example, as... Figure 12 As shown, an encapsulation layer 50 is formed covering the adapter plate 20, the first stack 31, and the second stack 32. For example, the material of the encapsulation layer 50 includes epoxy molding compound, etc. For example, the epoxy molding compound can be extruded into the mold cavity and the epoxy molding compound can be used to encapsulate the contents of the mold cavity, such as... Figure 11 The structure shown is embedded, and then the epoxy molding compound is cured and molded to form a shape as shown. Figure 12 The structure shown.

[0146] Next, as Figure 2 As shown, a plurality of metal bumps 60 are provided on the second side of the substrate 10. The second side is opposite to the first side. The plurality of metal bumps 60 are connected to the first wiring layer 11. For example, the plurality of metal bumps 60 are formed on the second surface 10b of the substrate 10 by a ball-mounting process.

[0147] Thus, a method for manufacturing a package structure according to some embodiments of the present disclosure is provided. In this manufacturing method, some modules of the substrate in the related art are modified into a substrate that serves as a general part. When the new product has other practical requirements, only the adapter board, which serves as a non-general part, can be modified according to the actual requirements of the new product. During production, the substrate that serves as a general part and the adapter board that serves as a non-general part are soldered together to complete the package production. Through this manufacturing method, a package structure can be formed. This manufacturing method can shorten the design cycle and reduce production costs.

[0148] In some embodiments, the manufacturing method may further include: disposing of a second chip on the side of the first adapter plate away from the substrate, and connecting the second chip to a second wiring layer of the first adapter plate. For example, in Figure 9 Based on the structure shown, in addition to providing one or more stacked bodies 30 on the first side of the substrate 10, a second chip 70 can also be provided on the side of the first adapter plate 20 away from the substrate 10, that is, the second chip 70 is provided on the first adapter plate 20. For example, a second lead (such as...) can be used. Figure 3 The second lead 42 shown) or inverted structure (such as Figure 4 The flip-chip structure 80 shown connects the second chip 70 to the second wiring layer 22 of the first adapter board 20. Thus, after other subsequent process steps, a structure like this can be formed. Figure 3 The packaging structure shown or as Figure 4 The packaging structure shown.

[0149] Figures 13A to 17 This is a schematic diagram illustrating several stages in the manufacturing process of a packaging structure according to other embodiments of the present disclosure. The following is in conjunction with... Figures 13A to 17 as well as Figure 5 A method for manufacturing a packaging structure according to other embodiments of the present disclosure is described in detail.

[0150] like Figure 13A and Figure 13B As shown, substrate 10 is obtained. For example, it can be formed by processes such as deposition, coating, photolithography, and etching. Figure 13A and Figure 13B The substrate 10 shown includes a first wiring layer 11. The substrate 10 also includes a first insulating layer 101, a second insulating layer 102, and a third insulating layer 103. The first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 surround the first wiring layer 11. The substrate 10 also includes a plurality of first pads 12. The plurality of first pads 12 are connected to the first wiring layer 11. The substrate 10 may further include a support portion 104 located on a first side of the first wiring layer 11.

[0151] like Figure 13C and Figure 13D As shown, one or more adapter plates 20 are obtained. For example, they can be formed through processes such as deposition, coating, photolithography, and etching. Figure 13C and Figure 13D The adapter board 20 shown is a second wiring layer 22. The adapter board 20 also includes a fourth insulating layer 201, a fifth insulating layer 202, and a sixth insulating layer 203. The fourth insulating layer 201, the fifth insulating layer 202, and the sixth insulating layer 203 surround the second wiring layer 22. The adapter board 20 is stepped. At the steps, the adapter board can expose a portion of the structure of the second wiring layer 22. The adapter board 20 also includes a plurality of second pads 21. The plurality of second pads 21 are connected to the second wiring layer 22.

[0152] Next, as Figure 14A and Figure 14B As shown, one or more adapter plates 20 are disposed on the first side of the substrate 10. That is, the adapter plates 20 are disposed on the first surface 10a of the substrate 10. For example, the one or more adapter plates 20 may include a first adapter plate 20a and a second adapter plate 20b, and the first adapter plate 20a and the second adapter plate 20b may be disposed on both sides of the support portion 104. The second wiring layer 22a of the first adapter plate 20a and the second wiring layer 22b of the second adapter plate 20b are respectively connected to the first wiring layer 11. For example, by means of a soldering process, the first pad 12 of the substrate 10 and the second pad 21 of each adapter plate are correspondingly connected, thereby connecting the second wiring layer of each adapter plate to the first wiring layer.

[0153] Next, as Figure 15 As shown, one or more stacks 30 are disposed on the support portion 104 of the substrate 10, each stack including one or more first chips 310. For example, as Figure 15 As shown, the one or more stacks 30 include a first stack 31 and a second stack 32. The arrangement direction of the stacks 30 and the adapter plate 20 is perpendicular to the thickness direction of the substrate 10. For example, a connector 91 is provided between the stacks 30 and the corresponding adapter plate 20, and the electrical connection between the stacks and the adapter plate is achieved by the connector 91.

[0154] Next, as Figure 16 As shown, a filler layer 92 is formed around the connector 91. This filler layer serves to provide insulation and support.

[0155] Next, as Figure 17 As shown, an encapsulation layer 50 is formed covering the adapter plate 20 and the stack 30. For example, the material of the encapsulation layer 50 includes epoxy molding compound, etc. For example, the epoxy molding compound can be extruded into the mold cavity and the epoxy molding compound can be used to encapsulate the contents of the mold cavity, such as... Figure 16 The structure shown is embedded, and then the epoxy molding compound is cured and molded to form a shape as shown. Figure 17 The structure shown.

[0156] Next, as Figure 5 As shown, a plurality of metal bumps 60 are provided on the second side of the substrate 10. The second side is opposite to the first side. The plurality of metal bumps 60 are connected to the first wiring layer 11. For example, the plurality of metal bumps 60 are formed on the second surface 10b of the substrate 10 by a ball-mounting process.

[0157] Thus, a method for manufacturing a packaging structure according to other embodiments of the present disclosure is provided. This manufacturing method can form a packaging structure. It can shorten the design cycle, reduce production costs, and improve product yield and performance.

[0158] In other embodiments, the manufacturing method may further include: disposing a second chip 70 on a first side of the substrate 10. For example, the second chip is located above the support portion 104 of the substrate 10. The second chip 70 is connected to a first wiring layer 11 in the substrate 10. Here, the second chip is a control chip.

[0159] For example, using a flip-chip structure 80, a second chip 70 is disposed on a first side of the substrate 10, and the second chip 70 is connected to a first wiring layer 11 in the substrate 10. For example, in Figure 14A and Figure 14BBased on the structure shown, in addition to providing the stack 30 on the support portion 104 of the substrate 10, a flip-chip structure 80 can also be used to place the second chip 70 on the support portion 104 of the substrate 10. For example, the flip-chip structure 80 includes a fourth pad 81 and a filler layer 82. In this way, after subsequent processes or steps, a structure like... Figure 6 The packaging structure shown.

[0160] Thus far, a packaging structure and its manufacturing method according to some embodiments of the present disclosure have been described, which can shorten the design cycle, simplify the structure and process, reduce production costs, and improve product yield and product performance.

[0161] The embodiments of this disclosure have now been described in detail. To avoid obscuring the concept of this disclosure, some details known in the art have not been described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein based on the above description.

[0162] While specific embodiments of this disclosure have been described in detail by way of examples, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments or equivalent substitutions can be made to some technical features without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A packaging structure, comprising: The substrate includes a first wiring layer; One or more adapter boards are located on a first side of the substrate, each adapter board including a second wiring layer connected to the first wiring layer, the one or more adapter boards including a first adapter board; and One or more stacks are located on a first side of the substrate, each stack including one or more chips, the one or more stacks including a first stack connected to a second wiring layer in the first adapter board, wherein the arrangement direction of the one or more stacks and the one or more adapter boards is perpendicular to the thickness direction of the substrate.

2. The packaging structure according to claim 1, wherein: The one or more adapter plates also include a second adapter plate; The one or more stacks further include a second stack, which is connected to a second wiring layer in the second adapter board.

3. The packaging structure according to claim 1, wherein: The one or more stacks further include a second stack, which is connected to a second wiring layer in the first adapter board.

4. The packaging structure according to claim 1, wherein: The substrate further includes a plurality of first pads, which are located between the first wiring layer and the one or more adapter boards and are connected to the first wiring layer; Each adapter board also includes a plurality of second pads and a plurality of third pads, the plurality of second pads being located between the second wiring layer and the substrate, the plurality of second pads being connected to the second wiring layer and to the plurality of first pads, the second wiring layer being located between the plurality of third pads and the substrate, and the plurality of third pads being connected to the second wiring layer and the one or more stacks.

5. The packaging structure according to claim 4 further includes: The first lead is connected to the plurality of third pads and the one or more stacks.

6. The packaging structure according to claim 1, further comprising: An encapsulation layer covering the one or more adapter boards and the one or more stacks; and Multiple metal bumps are located on the second side of the substrate and connected to the first wiring layer, wherein the second side is opposite to the first side.

7. The packaging structure according to claim 1, wherein, The adapter board includes: a printed circuit board, an interposer, or another substrate.

8. A packaging structure, comprising: The substrate includes a first wiring layer; One or more adapter boards are located on a first side of the substrate, each adapter board includes a second wiring layer connected to the first wiring layer, and the one or more adapter boards include a first adapter board; One or more stacks are located on a first side of the substrate, each stack including one or more first chips, the one or more stacks including a first stack connected to a second wiring layer in a first adapter board, wherein the arrangement direction of the one or more stacks and the one or more adapter boards is perpendicular to the thickness direction of the substrate; and The second chip is connected to the second wiring layer in the first adapter board, wherein the first adapter board is located between the second chip and the substrate.

9. The packaging structure according to claim 8, wherein: The one or more adapter plates also include a second adapter plate; The one or more stacks further include a second stack, which is connected to a second wiring layer in the second adapter board.

10. The packaging structure according to claim 8, wherein: The one or more stacks further include a second stack, which is connected to a second wiring layer in the first adapter board.

11. The packaging structure according to claim 8, wherein: The substrate further includes a plurality of first pads, which are located between the first wiring layer and the one or more adapter boards and are connected to the first wiring layer; Each adapter board also includes a plurality of second pads and a plurality of third pads, the plurality of second pads being located between the second wiring layer and the substrate, the plurality of second pads being connected to the second wiring layer and to the plurality of first pads, the second wiring layer being located between the plurality of third pads and the substrate, and the plurality of third pads being connected to the second wiring layer and the one or more stacks.

12. The packaging structure according to claim 11, further comprising: The first lead is connected to the plurality of third pads and the one or more stacks.

13. The packaging structure according to claim 8, further comprising: The second lead is connected to the second wiring layer in the second chip and the first adapter board.

14. The packaging structure according to claim 8, further comprising: A flip-chip structure is located between the second chip and the first adapter board, and is connected to the second wiring layer in both the second chip and the first adapter board.

15. The packaging structure according to claim 14, wherein, The inverted structure includes: The fourth pad is located between the second chip and the second wiring layer in the first adapter board; and A filler layer is applied around the fourth pad.

16. The packaging structure according to claim 8, further comprising: An encapsulation layer covering the one or more adapter boards, the one or more stacks, and the second chip; and Multiple metal bumps are located on the second side of the substrate and connected to the first wiring layer, wherein the second side is opposite to the first side.

17. The packaging structure according to claim 8, wherein: The first chip is a memory chip; The second chip is a control chip.

18. A method for manufacturing a packaging structure, comprising: Obtain a substrate and one or more adapter boards, wherein the substrate includes a first wiring layer, each adapter board includes a second wiring layer, and the one or more adapter boards include a first adapter board; One or more adapter boards are disposed on a first side of the substrate, wherein the second wiring layer is connected to the first wiring layer; One or more stacks are disposed on a first side of the substrate, each stack including one or more first chips, wherein the arrangement direction of the one or more stacks and the one or more adapter plates is perpendicular to the thickness direction of the substrate; and Connect the first stack to the second wiring layer in the first adapter board.

19. The manufacturing method according to claim 18, wherein, Connecting the first stack to the second wiring layer in the first adapter board includes: The first stack is connected to the second wiring layer in the first adapter board using the first lead.

20. The manufacturing method according to claim 18, further comprising: A second chip is disposed on the side of the first adapter board away from the substrate, and the second chip is connected to the second wiring layer of the first adapter board.

21. The manufacturing method according to claim 20, wherein, Connecting the second chip to the second wiring layer of the first adapter board includes: The second chip is connected to the second wiring layer of the first adapter board using a second lead or a flip-chip structure.

22. The manufacturing method according to any one of claims 18 to 21, further comprising: Form an encapsulation layer covering the one or more adapter boards and the one or more stacks; and A plurality of metal bumps are provided on the second side of the substrate, wherein the plurality of metal bumps are connected to the first wiring layer, and the second side is opposite to the first side.

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