A power device, manufacturing method and chip

Abstract

The application discloses a power device, a manufacturing method and a chip, wherein a P-type injection area is arranged in a false gate groove area, the P-type injection area is arranged on both sides and the bottom of the false gate groove and is electrically connected with an emitter metal, the P-type injection area has a lower potential, can effectively shield a large electric field below the false gate groove, significantly reduces the electric field intensity at the bottom of a transition area groove, solves the problem of electric field concentration at the bottom of the transition area groove in a traditional terminal structure, improves the withstand voltage capacity of the device, an N-type hole inhibition area is arranged at an opening at the end of the transition area, can effectively block the flow path of holes along the interface of the terminal area oxide layer, inhibits the hole current density and potential rise below the oxide layer, improves the turn-off reliability of the device, and through the synergistic effect of the P-type injection area and the N-type hole inhibition area, the withstand voltage capacity and long-term reliability of the device are improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a power device, manufacturing method, and chip. Background Technology

[0002] In trench-type power devices, such as trench-gate insulated-gate bipolar transistors (IGBTs) and trench-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), the trench gate structure within the cell region is used to control the switching of the device, while the termination region located outside the cell region is used to withstand reverse voltage. In practical structures, trenches are typically formed in the cell region and the transition region between the cell region and the termination region. The maximum electric field in traditional termination structures usually occurs at the bottom of the trench at the end of this transition region. This electric field concentration problem directly affects the device's withstand voltage capability and long-term reliability. Summary of the Invention

[0003] In view of the above problems, embodiments of the present invention are proposed to provide a power device, manufacturing method and chip that overcomes or at least partially solves the above problems.

[0004] In a first aspect, embodiments of the present invention provide a power device, the power device comprising: N-type drift zone; The P-type terminal injection region is located in the N-type drift region; Multiple trenches are provided within the N-type drift region and located on one side of the P-type terminal injection region; the multiple trenches are arranged laterally at intervals and parallel to each other; the multiple trenches include at least one dummy gate trench and at least one true gate trench, the true gate trench being located on the side of the dummy gate trench away from the P-type terminal injection region; P-type injection regions are located on both sides and the bottom of each dummy gate trench. The P-type injection regions are connected to the P-type terminal injection regions and are connected to the side of the true gate trench that is closest to the dummy gate trench. An N-type carrier storage layer is disposed on both sides of the true gate trench; A P-type well region is located above the N-type carrier storage layer; Multiple P+ regions are provided on both sides of the upper part of each trench, wherein the P+ regions provided on both sides of the upper part of the true gate trench are located above the P-type well region, and both sides of the dummy gate trench are connected to the P+ regions. The N+ region is located above the P-type well region, with one side of the N+ region connected to the P+ region and the other side connected to the side of the true gate trench. An N-type hole suppression region is located within the P-type injection region and connected to the P+ region closest to the P-type terminal injection region; the depth of the N-type hole suppression region is greater than the depth of the P+ region. A polysilicon layer is disposed in each of the trenches, and a gate oxide layer is provided between the polysilicon layer and the inner wall of the trench; A dielectric layer is disposed on the surface of the gate oxide layer, a portion of the surface of the N-type hole suppression region near the P-type terminal injection region, a portion of the surface of the P-type injection region, the surface of the P-type terminal injection region, and a portion of the surface of the N-type drift region; Emitter metal is disposed on the surface of the plurality of P+ regions, the surface of the N+ regions, the surface of the dielectric layer on the surface of the gate oxide layer, a portion of the surface of the N-type hole suppression region, and the surface of the dielectric layer on the surface of the N-type hole suppression region.

[0005] Optionally, the power device further includes: Gate metal, which is disposed on the surface of a dielectric layer on a portion of the surface of the P-type terminal injection region.

[0006] Optionally, the power device further includes: A terminal stop ring is disposed within the N-type drift region and located on the side of the P-type terminal injection region away from the plurality of trenches; the dielectric layer is also disposed on a portion of the surface of the terminal stop ring near the P-type terminal injection region. A stop ring metal is disposed on a portion of the surface of the terminal stop ring and a portion of the surface of the dielectric layer on the terminal stop ring.

[0007] Optionally, the power device further includes: An N-type cutoff layer is disposed below the N-type drift region and connected to the N-type drift region; A P-type collector region is located below the N-type cutoff layer and connected to the N-type cutoff layer; The collector metal is located below the P-type collector region and connected to the P-type collector region.

[0008] Secondly, embodiments of the present invention provide a method for manufacturing a power device, for manufacturing the power device as described in the first aspect, the manufacturing method comprising: Provides an N-type drift zone; P-type ions are injected into the N-type drift region to form a P-type terminal injection region; Multiple trenches are formed by etching in a continuous region from a portion of the P-type terminal injection region to a portion of the N-type drift region; the multiple trenches are arranged laterally at intervals and parallel to each other; the multiple trenches include at least one dummy gate trench and at least one true gate trench, the true gate trench being located on the side of the dummy gate trench away from the P-type terminal injection region. P-type ions are injected into a portion of the N-type drift region between each dummy gate trench and a portion of the P-type terminal injection region connected to the dummy gate trench to form a P-type injection region. The P-type injection region is located on both sides and the bottom of each dummy gate trench. The P-type injection region is connected to the P-type terminal injection region and is connected to the side of the true gate trench closest to the dummy gate trench. N-type ions are injected into both sides of the true gate trench to form an N-type carrier storage layer; P-type ions are injected into the upper region of the N-type carrier storage layer to form a P-type well region; P-type ions are injected on both sides of the upper part of each trench to form multiple P+ regions. The P+ regions located on both sides of the upper part of the true gate trench are located above the P-type well region, and both sides of the dummy gate trench are connected to the P+ regions. N-type ions are implanted above the P-type well region to form an N+ region; one side of the N+ region is connected to the P+ region, and the other side is connected to the side of the true gate trench. N-type ions are injected into the P-type injection region to form an N-type hole suppression region; the N-type hole suppression region is connected to the P+ region closest to the P-type terminal injection region; the depth of the N-type hole suppression region is greater than the depth of the P+ region. A gate oxide layer is formed on the inner wall of each trench, and polysilicon is deposited on the gate oxide layer to form a polysilicon layer; A dielectric layer is formed on the surface of the gate oxide layer, a portion of the surface of the N-type hole suppression region near the P-type terminal injection region, a portion of the surface of the P-type injection region, the surface of the P-type terminal injection region, and a portion of the surface of the N-type drift region. Emitter metal is formed by depositing metal on the surfaces of the plurality of P+ regions, the surfaces of the N+ regions, the surfaces of the dielectric layer on the surface of the gate oxide layer, a portion of the surface of the N-type hole suppression region, and the surface of the dielectric layer on the surface of the N-type hole suppression region.

[0009] Optionally, the step of injecting P-type ions into a portion of the N-type drift region between each dummy gate trench and the P-type terminal injection region connected to the dummy gate trench to form a P-type injection region includes: Before etching to form the plurality of trenches, P-type ions are implanted in a continuous region from a portion of the P-type terminal implantation region to a portion of the N-type drift region to form an unannealed P-type implantation layer. The plurality of trenches are formed by etching in a continuous region where the unannealed P-type implanted layer is implanted and in a portion of the N-type drift region connected to the continuous region. A portion of the unannealed P-type implanted layer is etched away, and the remaining unannealed P-type implanted layer is located between the dummy gate trenches and in the region where the dummy gate trenches are connected to the P-type terminal implanted region. The remaining unannealed P-type implantation layer is annealed to form the P-type implantation region.

[0010] Optionally, the manufacturing method further includes: An emitter metal is formed on a portion of the surface of the N-type hole suppression region and on the surface of the dielectric layer on the surface of the N-type hole suppression region; Metal is deposited on the surface of the dielectric layer on a portion of the surface of the P-type terminal injection region to form gate metal.

[0011] Optionally, the manufacturing method further includes: N-type ions are injected into the N-type drift region to form a terminal stop ring; the terminal stop ring is located on the side of the P-type terminal injection region away from the plurality of trenches; The dielectric layer is formed on a portion of the surface of the terminal cut-off ring near the P-type terminal injection region; Metal is deposited on a portion of the surface of the terminal stop ring and a portion of the surface of the dielectric layer on the terminal stop ring to form the stop ring metal.

[0012] Optionally, the manufacturing method further includes: N-type ions are injected below the N-type drift region to form an N-type cutoff layer; the N-type cutoff layer is connected to the N-type drift region; P-type ions are implanted below the N-type cutoff layer to form a P-type current collector region; the P-type current collector region is connected to the N-type cutoff layer. Metal is deposited below the P-type collector region to form a collector metal; the collector metal is connected to the P-type collector region.

[0013] Thirdly, embodiments of the present invention provide a chip including the power device as described in the first aspect.

[0014] An embodiment of the present invention provides a power device comprising: an N-type drift region; a P-type terminal injection region disposed within the N-type drift region; a plurality of trenches disposed within the N-type drift region and located on one side of the P-type terminal injection region; the plurality of trenches being arranged laterally at intervals and parallel to each other; the plurality of trenches including at least one dummy gate trench and at least one true gate trench, the true gate trench being located on the side of the dummy gate trench away from the P-type terminal injection region; a P-type injection region disposed on both sides and the bottom of each dummy gate trench, the P-type injection region being connected to the P-type terminal injection region and connected to the side of the true gate trench adjacent to the dummy gate trench; an N-type carrier storage layer disposed on both sides of the true gate trench; a P-type well region disposed above the N-type carrier storage layer; and a plurality of P+ regions disposed on the upper sides of each trench, wherein the P+ regions disposed on the upper sides of the true gate trench are located above the P-type well region, and both sides of the dummy gate trench are connected to the P+ regions. An N+ region is located above a P-type well region, with one side of the N+ region connected to the P+ region and the other side connected to the side of the true gate trench; an N-type hole suppression region is located within a P-type injection region and connected to the P+ region closest to the P-type terminal injection region; the depth of the N-type hole suppression region is greater than the depth of the P+ region; a polysilicon layer is located within each trench, with a gate oxide layer between the polysilicon layer and the inner wall of the trench; a dielectric layer is located on the surface of the gate oxide layer, part of the surface of the P-type injection region, the surface of the P-type terminal injection region, and part of the surface of the N-type drift region; and an emitter metal is located on the surfaces of multiple P+ regions, the surface of the N+ region, and the surface of the dielectric layer on the surface of the gate oxide layer. In this embodiment of the invention, a P-type injection region is provided in the dummy gate trench region. The P-type injection region is located on both sides and the bottom of the dummy gate trench and is electrically connected to the emitter metal. Since the P-type injection region has a low potential, it can effectively shield the large electric field below the dummy gate trench and significantly reduce the electric field strength at the bottom of the transition trench. This solves the problem of electric field concentration at the bottom of the trench at the end of the transition region in traditional termination structures and improves the withstand voltage capability of the device. At the same time, an N-type hole suppression region is provided at the opening at the end of the transition region, which can effectively block the flow path of holes along the oxide layer interface of the termination region, suppress the hole current density and potential rise below the oxide layer, and improve the turn-off reliability of the device. Through the synergistic effect of the P-type injection region and the N-type hole suppression region, the withstand voltage capability and long-term reliability of the device are improved.

[0015] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the structure of a power device according to an embodiment of the present invention; Figure 2This is a schematic diagram of the structure of another power device according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the electric field distribution of a power device according to an embodiment of the present invention; Figure 4 This is a schematic diagram comparing the number of holes injected in the terminal area according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the hole extraction path of a power device according to an embodiment of the present invention; Figure 6 This is a schematic diagram of a conventional hole extraction path according to an embodiment of the present invention; Figure 7 A flowchart illustrating the steps of a method for manufacturing a power device according to an embodiment of the present invention; Figure 8 A schematic diagram of the structure for manufacturing a power device according to an embodiment of the present invention; Figure 9 Another schematic diagram of the structure for manufacturing a power device according to an embodiment of the present invention; Figure 10 A schematic diagram of another power device manufacturing structure according to an embodiment of the present invention.

[0017] Reference numerals: N-type drift region 10, P-type terminal injection region 11, trench 12, dummy gate trench 121, real gate trench 122, P-type injection region 13, N-type carrier storage layer 14, P-type well region 15, P+ region 16, N+ region 17, polysilicon layer 18, gate oxide layer 19, dielectric layer 20, emitter metal 21, N-type hole suppression region 22, gate metal 23, terminal cutoff ring 24, cutoff ring metal 25, N-type cutoff layer 26, P-type collector region 27, collector metal 28. Detailed Implementation

[0018] Embodiments of the present invention will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0019] In trench-type power devices, such as trench-gate insulated-gate bipolar transistors (IGBTs) and trench-gate metal-oxide-semiconductor field-effect transistors (MOSFETs), the trench gate structure within the cell region is used to control the switching of the device, while the termination region located outside the cell region is used to withstand reverse voltage. In practical structures, trenches are typically formed in the cell region and the transition region between the cell region and the termination region. The maximum electric field in traditional termination structures usually occurs at the bottom of the trench at the end of this transition region. This electric field concentration problem directly affects the device's withstand voltage capability and long-term reliability.

[0020] One existing termination structure uses a trench with a floating protective ring at the bottom of the trench, replacing the field-limiting ring or junction termination extension (JTE) / variation of lateral doping (VLD) structure in traditional power devices. This solution optimizes the electric field distribution in the termination region. However, this design requires trench etching across the entire termination area, and the spacing between the trenches varies, especially at the termination corners. This places extremely high demands on the etching process precision; even slight deviations can affect the device's breakdown voltage and yield, thus increasing manufacturing difficulty and cost.

[0021] This invention addresses the problem of electric field concentration at the bottom of the transition region trench in traditional termination structures by incorporating a P-type injection region within the dummy gate trench. This region, located on both sides and at the bottom of the trench and electrically connected to the emitter metal, effectively shields the large electric field beneath the dummy gate trench due to its lower potential. This significantly reduces the electric field strength at the bottom of the transition trench, improving the device's withstand voltage. Simultaneously, an N-type hole suppression region is placed at the opening at the end of the transition region, effectively blocking the flow path of holes along the oxide layer interface in the termination region. This suppresses the hole current density and potential rise below the oxide layer, enhancing the device's turn-off reliability. The synergistic effect of the P-type injection region and the N-type hole suppression region further improves the device's withstand voltage and long-term reliability. Furthermore, due to the reduced electric field at the bottom of the transition trench, this invention eliminates the need for the floating protection ring structure required by existing technologies with varying trench spacing and high-precision etching. This reduces the precision requirements of the etching process, lowering manufacturing difficulty and costs.

[0022] Reference Figure 1 The diagram shows a structural schematic of a power device according to an embodiment of the present invention, which specifically includes the following structure: N-type drift zone 10.

[0023] The power device may include a cell region 101, a transition region 102, and a termination region 103, wherein the transition region 102 is located between the cell region 101 and the termination region 103. The cell region 101 is the main operating area of ​​the device, used to control switching and conduction current, and multiple repeating cell structures are formed in this area; the transition region 102 is located on the periphery of the cell region 101, serving as a buffer region between the cell region 101 and the termination region 103, used to smooth the electric field distribution and prevent the electric field from concentrating at the edge of the cell region 101; the termination region 103 is located at the outermost edge region of the chip, used to withstand reverse voltage when the device is turned off, preventing chip edge breakdown.

[0024] The power device can be an IGBT. The N-type drift region 10 serves as the drift region of the IGBT device. It is lightly doped with N-type and is used to withstand reverse voltage and as a carrier transport path when the device is turned on. The N-type drift region 10 extends through the cell region 101, the transition region 102, and the terminal region 103.

[0025] The P-type terminal injection region 11 is located within the N-type drift region 10 and is situated in the terminal region 103. The P-type terminal injection region 11 is a terminal injection region, which can be a junction termination extension (JTE) injection region or a lateral doping (VLD) injection region, used to bear the reverse voltage and alleviate the electric field concentration at the edge of the main junction.

[0026] Multiple trenches 12 are disposed within the N-type drift region 10 and located on one side of the P-type terminal injection region 11; the multiple trenches 12 are arranged laterally at intervals and parallel to each other; the multiple trenches 12 include at least one dummy gate trench 121 and at least one true gate trench 122, the true gate trench 122 being located on the side of the dummy gate trench 121 away from the P-type terminal injection region 11.

[0027] Multiple trenches 12 are located within the transition region 102 and the cell region 101. The trenches closer to the P-type terminal injection region 11, i.e., the trenches located in the transition region 102, are dummy gate trenches 121, and the trenches farther away from the P-type terminal injection region 11, i.e., the trenches located in the cell region 101, are true gate trenches 122. For example, the number of dummy gate trenches 121 can be 3-10.

[0028] P-type injection regions 13 are located on both sides and bottom of each dummy gate trench 121. That is, the P-type injection regions 13 enclose the dummy gate trench 121. The P-type injection regions 13 are connected to the P-type terminal injection regions 11 and are connected to the side of the true gate trench 122 that is closest to the dummy gate trench 121.

[0029] The P-type injection region 13 is located within the transition region 102. The P-type injection region 13 is used to shield the large electric field below the dummy gate trench 121 and reduce the electric field strength at the bottom of the trench in the transition region. The trench enclosed by the P-type injection region 13 is the dummy gate trench 121.

[0030] An N-type carrier storage layer 14 is disposed on both sides of the true gate trench 122. The N-type carrier storage layer 14 is used to store carriers when the device is turned on, thereby reducing the on-state voltage drop. One side of the N-type carrier storage layer 14 located in the transition region 102 is connected to the sidewall of the true gate trench 122, and the other side is connected to the sidewall of the dummy gate trench 121; the side of the N-type carrier storage layer 14 located in the cell region 101 is connected to the sidewall of the true gate trench 122.

[0031] P-type well region 15 is disposed above N-type carrier storage layer 14. P-type well region 15 is used to form a conductive channel under gate voltage control.

[0032] Multiple P+ regions 16 are provided on the upper sides of each trench 12. The P+ regions 16 provided on the upper sides of the true gate trench 122 are located above the P-type well region 15. Both sides of the dummy gate trench 121 are connected to the P+ regions 16.

[0033] The upper two sides of trench 12 refer to the region near the trench opening end along the depth direction (i.e., the vertical direction) of trench 12, and located on both sides (i.e., the left and right sides) of the trench sidewall. For example, trench 12 extends downward from the chip surface into the N-type drift region 10, having a depth. Along this depth direction, trench 12 can be divided into an upper part and a lower part. The upper part is a shallower region near the chip surface, and the lower part is a deeper region near the bottom of the trench. P+ region 16 is a P+ ohmic contact region used to form an ohmic contact with the emitter metal. The P+ regions 16 located on both sides of the upper part of the dummy gate trench 121 are located within the transition region. Multiple P+ regions 16 can have the same depth.

[0034] N+ region 17 is located above P-type well region 15, and one side of N+ region 17 is laterally connected to P+ region 16, while the other side is connected to the side of true gate trench 122. N+ region 17 serves as the emitter region of the device and is used to provide charge carriers.

[0035] An N-type hole suppression region 22 is located within the P-type injection region 13 and connected to the P+ region 16 closest to the P-type terminal injection region 11. The N-type hole suppression region 22 and the P-type terminal injection region 11 are separated by the P-type injection region 13 and are not directly connected. The depth of the N-type hole suppression region 22 is greater than the depth of the P+ region 16. The N-type hole suppression region 22 is used to block the flow path of holes along the oxide layer interface of the terminal region during turn-off, suppressing the concentration of hole current at the end opening of the transition region. The depth of the N-type hole blocking layer is greater than the depth of the P+ region 16 to ensure that it can effectively block the flow path of holes along the oxide layer interface of the terminal region. N-type hole suppression region 22.

[0036] A polysilicon layer 18 is disposed within each trench 12, and a gate oxide layer 19 is provided between the polysilicon layer 18 and the inner wall of the trench 12. Among them, the polysilicon layer 18 located in the true gate trench 122 serves as the gate conductive part for controlling the switching of the device; the polysilicon layer 18 located in the dummy gate trench 121 serves as the dummy conductive part and is connected to the emitter potential.

[0037] The dielectric layer 20 is disposed on the surface of the gate oxide layer 19, a portion of the surface of the N-type hole suppression region 22 near the P-type terminal injection region 11, a portion of the surface of the P-type injection region 13, the surface of the P-type terminal injection region 11, and a portion of the surface of the N-type drift region 10. The material of the dielectric layer 20 can be silicon dioxide, a composite material of silicon nitride and silicon dioxide, used to achieve electrical isolation between the metal layer and the semiconductor layer, for example, to achieve electrical isolation between the gate metal 23 and the N-type hole suppression region 22.

[0038] Emitter metal 21 is disposed on the surfaces of multiple P+ regions 16, the surface of N+ regions 17, the surface of the dielectric layer 20 on the surface of the gate oxide layer 19, a portion of the surface of the N-type hole suppression region 22, and the surface of the dielectric layer 20 on the surface of the N-type hole suppression region 22. Emitter metal 21 is used to form ohmic contacts with the P+ regions 16 and N+ regions 17 as the main current electrode of the device. For example, it can form an ohmic contact with the N-type hole suppression region 22 to fix it to the emitter potential.

[0039] In traditional termination structures, the injection window of the Gring (terminal injection region) typically begins in the transition region. However, due to the low Gring injection dose in JTE or VLD structures, their junction depth and doping concentration are relatively small after annealing, resulting in the Gring not being able to completely cover the bottom of the transition region trench. This makes it impossible to effectively suppress the high electric field at the bottom of the transition region trench, leading to a risk of breakdown due to electric field concentration. Furthermore, an opening is required at the end of the transition region to ground the Gring (terminal injection region). However, during turn-off, holes only flow along the oxide interface of the termination region and concentrate at the opening location at the end of the transition region, causing a potential rise and current concentration below the oxide layer at this opening. In addition, the high dv / dt (voltage change rate) during IGBT turn-off generates displacement current through parasitic capacitance, further exacerbating the potential rise and electric field concentration below the oxide layer. The combined effect of these two factors significantly increases the risk of local electric field and oxide layer breakdown, leading to turn-off reliability failure. Therefore, reducing the electric field strength at the bottom of the transition trench and optimizing the hole current distribution during the turn-off process are the core strategies for improving the turn-off reliability of IGBTs.

[0040] In this embodiment of the invention, a P-type injection region 13 (i.e., a transition region Pring) with higher concentration and deeper junction depth is provided in the transition region 102. The P-type injection region 13 surrounds at least part of the sidewalls and bottom of each dummy gate trench 121. At the same time, the P-type injection region 13 is directly connected to the emitter metal 21 on the surface through the P+ region 16 between the dummy gate trenches 121. Since the emitter metal 21 is grounded, the P-type injection region 13 is also grounded and has a lower potential. Therefore, the P-type injection region 13 can effectively shield the large electric field below the dummy gate trenches 121, avoid the risk of breakdown caused by electric field concentration, and improve the withstand voltage capability and long-term reliability of the device. At the same time, an N-type hole suppression region 22 is added at the opening at the end of the transition region. The N-type hole suppression region 22 can block the flow path of holes on the surface of the P-type terminal injection region 11 (Gring) and prevent holes from flowing to the opening position along the oxide layer interface of the terminal region. Furthermore, the low potential regions of the N-type hole suppression region 22 and the P-type injection region 13 (Pring) work synergistically: the low potential of the P-type injection region 13 actively attracts holes, causing holes during the turn-off process to flow from the drift region to the P-type injection region 13, and then be uniformly extracted through the dummy gate opening, rather than flowing only along the oxide layer interface of the terminal region. Through the synergistic effect of the above structure, this embodiment significantly alleviates the current concentration phenomenon at the end opening of the transition region, suppresses the potential rise and electric field concentration below the oxide layer, thereby effectively reducing the risk of oxide layer breakdown and significantly improving the turn-off reliability and long-term operating stability of the IGBT device.

[0041] Reference Figure 2 The diagram illustrates a structural schematic of another power device according to an embodiment of the present invention. The power device further includes: Gate metal 23 is disposed on the surface of dielectric layer 20 on a portion of the surface of P-type termination injection region 11. Gate metal 23 is a gate metal field plate that covers the dielectric layer 20 on a portion of the surface of P-type termination injection region 11 and is used to modulate the surface electric field of termination region 103.

[0042] In this embodiment of the invention, the power device further includes: The termination stop ring 24 is located within the N-type drift region 10 and on the side of the P-type termination injection region 11 away from the multiple trenches 12, that is, at the outermost edge of the termination region 103. The termination stop ring 24 is heavily doped with N-type to stop the lateral expansion of the depletion layer when the device is turned off, preventing the depletion layer from extending to the edge of the chip dicing track and avoiding breakdown caused by the concentration of the edge electric field.

[0043] The dielectric layer 20 is also disposed on a portion of the surface of the terminal stop ring 24 near the P-type terminal injection region 11, for achieving selective contact between the stop ring metal 25 and the terminal stop ring 24.

[0044] The stop ring metal 25 is disposed on a portion of the surface of the terminal stop ring 24 and a portion of the surface of the dielectric layer 20 on the terminal stop ring 23. The stop ring metal 25 forms an ohmic contact with the terminal stop ring 24 through the opening of the dielectric layer 20, and extends over the dielectric layer 20 to form a field plate structure.

[0045] An N-type heavily doped termination ring 24 is set on the outermost side of the termination region, which can effectively block the lateral expansion of the depletion layer, prevent the depletion layer from extending to the edge of the chip dicing channel, avoid edge breakdown, and improve the device's withstand voltage capability. At the same time, the stop ring metal 25 is in ohmic contact with the termination ring 24 and extends to form a field plate structure. Through the capacitive coupling effect, the surface electric field at the edge of the termination region is modulated, further suppressing electric field concentration and improving the breakdown voltage.

[0046] In this embodiment of the invention, the power device further includes: An N-type cutoff layer 26 is disposed below and connected to the N-type drift region 10. The N-type cutoff layer 26 is an N-type heavily doped layer, also known as a field stop (FS layer), used to prevent the depletion layer from extending to the collector side when the device is turned off, and to prevent the depletion layer from penetrating to the P-type collector region 27, thereby reducing turn-off loss.

[0047] The P-type collector region 27 is located below and connected to the N-type cutoff layer 26. The P-type collector region 27 is a heavily doped P-type layer. As the collector region of the IGBT, it is used to inject holes into the drift region when the device is turned on, forming a conductivity modulation effect and reducing the on-state voltage drop.

[0048] Collector metal 28 is located below and connected to the P-type collector region 27, serving as the collector electrode of the device for connection to external circuitry.

[0049] An N-type cutoff layer 26 (field cutoff layer) is set below the N-type drift region 10, which can effectively prevent the depletion layer from expanding and reduce turn-off loss. A P-type collector region 27 is set to inject holes to form a conductivity modulation effect when the device is turned on, thereby reducing the on-state voltage drop. The combination of the two achieves a good trade-off between the on-state voltage drop and the turn-off loss, and improves the overall performance of the device.

[0050] In traditional terminal structures, the maximum electric field occurs at the bottom of the trench at the end of the transition region. This invention addresses this by providing a P-type injection region 13 (Pring) connected to the emitter metal 21. The P-type injection region 13 encloses the bottom and sidewalls of the dummy gate trench 121, forming a low-potential shielding layer. Simulation results show that this invention completely eliminates the electric field at the bottom of the trench in the transition region, while maintaining the same electric field distribution in the terminal region as traditional terminals, ensuring the same withstand voltage capability. Therefore, this invention effectively reduces the electric field strength at the bottom of the trench in the transition region while ensuring withstand voltage, which is beneficial for improving the reliability of the IGBT.

[0051] Reference Figure 3 This diagram illustrates the electric field distribution of a power device according to an embodiment of the present invention. The doping concentration of the P-type injection region 13 is significantly higher than that of the cell region and the terminal region. Since the P-type injection region 13 is connected to the emitter metal 21 through the P+ region 16, it has the lowest potential in the entire chip. Therefore, the electric field lines radially point from all sides towards the P-type injection region 13, forming a convergent electric field distribution centered on the P-type injection region 13. During the IGBT turn-on process, the P-type collector region 27 on the back side injects holes into the N-type drift region 10, and the N+ region 17 on the front side injects electrons into the N-type drift region 10. Due to the above-mentioned electric field distribution, the movement of charge carriers follows the following pattern: electrons (negative charges) move against the direction of the electric field lines, that is, they move from the P-type injection region 13 to the periphery. Therefore, electrons injected by the emitter of the cell region migrate away from the terminal region under the drive of the electric field, resulting in a decrease in the electron current density in the terminal region. Holes (positive charges) move with the direction of the electric field lines, that is, they converge from the periphery to the P-type injection region 13. Therefore, holes injected by the P-type collector region 27 on the back side preferentially flow away through the P-type injection region 13 rather than diffuse towards the terminal region.

[0052] Through the synergistic effect of the aforementioned electric field distribution and carrier motion law, the structure of this invention effectively suppresses the injection and storage of holes in the terminal region. Electrons migrate away from the terminal region under the influence of the electric field, reducing the electronic current component in the terminal region; holes preferentially flow to the P-type injection region 13 and are extracted through the emitter metal 21 under the influence of the electric field, reducing the accumulation of holes in the terminal region; since both the injection and storage of holes in the terminal region are significantly reduced, the problems of current concentration and electric field rise caused by hole extraction during the turn-off process are effectively alleviated.

[0053] Reference Figure 4 This diagram illustrates a comparison of hole injection quantities in the terminal region according to an embodiment of the present invention. Specifically, when the IGBT is turned on, along... Figure 2 The comparison shows the number of holes injected into the terminal region at the A-A1 tangent. The horizontal axis (Distance) represents the lateral distance, referring to the lateral position extending from the cell region towards the terminal region, i.e., at the A-A1 tangent; the vertical axis (HoleDensity) represents the hole density. The results show that the structure of this embodiment has a lower hole density at the bottom of the drift region of the terminal than the traditional structure, and this structure can suppress hole injection in the terminal region.

[0054] In traditional terminal structures, a contact hole is required at the end of the transition region to ground the Gring (terminal injection region). During IGBT turn-off, holes in the terminal region can only flow along the oxide layer interface and eventually concentrate at the opening at the end of the transition region, forming a single extraction path. This single extraction path results in extremely high hole current density at the opening, causing a potential rise and local electric field concentration beneath the oxide layer, increasing the risk of oxide layer breakdown and, in severe cases, leading to turn-off reliability failure.

[0055] Reference Figure 5 This diagram illustrates a hole extraction path for a power device according to an embodiment of the present invention. Figure 6 A schematic diagram of a traditional hole extraction path is shown. It can be seen that the current concentration phenomenon in the traditional structure is because the holes flow laterally along the oxide layer interface on the terminal region and finally concentrate at the last opening at the end of the trench. Compared with the single extraction path in the traditional structure where the holes concentrate at the opening at the end of the transition region, the present invention disperses the hole current between the dummy gate trenches for extraction. By dispersing the hole extraction path, the current concentration problem at the end of the transition region is effectively alleviated, and the turn-off reliability of the IGBT chip is improved.

[0056] This invention provides an N-type hole suppression region 22 at the opening position at the end of the transition region. The N-type hole suppression region 22 can block the flow path of holes along the oxide layer interface of the terminal region. The N-type hole suppression region 22 is located within the P-type injection region 13 (Pring) and is connected to the P+ region 16 closest to the P-type terminal injection region 11. Due to its N-type doping characteristics, it can effectively block the path of holes flowing along the oxide layer interface of the terminal region to the opening position, suppressing the hole current density and potential rise below the oxide layer. It can also work with the P-type injection region 13 to attract holes. The P-type injection region 13 is connected to the emitter through the P+ region 16. The metal 21 connection has the lowest potential in the entire chip. This low potential characteristic actively attracts holes, causing them to preferentially flow from the N-type drift region 10 to the P-type injection region 13 during the turn-off process. It can also disperse the hole extraction path: the holes attracted to the P-type injection region 13 are no longer extracted only through a single opening at the end of the transition region, but are uniformly extracted through the Mesa region (i.e., the mesa region between the dummy gate trenches) in the P-type injection region 13. Thus, the hole extraction path is transformed from a single concentrated path in the traditional structure into multiple dispersed extraction paths.

[0057] Reference Figure 7 The diagram illustrates a step-by-step flowchart of a method for manufacturing a power device according to an embodiment of the present invention. The method for manufacturing the power device specifically includes the following steps: Step 101, provide the N-type drift zone; Step 102: P-type ions are injected into the N-type drift region to form a P-type terminal injection region.

[0058] Step 103: Etching is performed in a continuous region from a portion of the P-type terminal injection region to a portion of the N-type drift region to form multiple trenches; the multiple trenches are arranged laterally at intervals and parallel to each other; the multiple trenches include at least one dummy gate trench and at least one true gate trench, the true gate trench being located on the side of the dummy gate trench away from the P-type terminal injection region.

[0059] Step 104: P-type ions are injected into a portion of the N-type drift region between each dummy gate trench and the P-type terminal injection region connected to the dummy gate trench to form a P-type injection region. The P-type injection region is located on both sides and the bottom of each dummy gate trench. The P-type injection region is connected to the P-type terminal injection region and is also connected to the side of the true gate trench that is closest to the dummy gate trench.

[0060] Step 105: Inject N-type ions into both sides of the true gate trench to form an N-type carrier storage layer. Step 106: P-type ions are injected into the upper region of the N-type carrier storage layer to form a P-type well region.

[0061] Step 107: P-type ions are injected into the upper sides of each trench to form multiple P+ regions. The P+ regions located on the upper sides of the true gate trench are above the P-type well region, and both sides of the dummy gate trench are connected to the P+ regions.

[0062] Step 108: N-type ions are implanted above the P-type trap region to form an N+ region; one side of the N+ region is connected to the P+ region, and the other side is connected to the side of the true gate trench.

[0063] Step 109: Inject N-type ions into the P-type injection region to form an N-type hole suppression region; the N-type hole suppression region is connected to the P+ region closest to the P-type terminal injection region; the depth of the N-type hole suppression region is greater than the depth of the P+ region.

[0064] Step 110: A gate oxide layer is formed on the inner wall of each trench, and polysilicon is deposited on the gate oxide layer to form a polysilicon layer.

[0065] Step 111: A dielectric layer is formed on the surface of the gate oxide layer, a portion of the surface of the N-type hole suppression region near the P-type terminal injection region, a portion of the surface of the P-type injection region, the surface of the P-type terminal injection region, and a portion of the surface of the N-type drift region.

[0066] Step 112: Deposit metal on the surfaces of multiple P+ regions, the surface of N+ regions, the surface of the dielectric layer on the gate oxide layer, a portion of the surface of the N-type hole suppression region, and the surface of the dielectric layer on the surface of the N-type hole suppression region to form an emitter metal.

[0067] An embodiment of the present invention provides a power device comprising: an N-type drift region; a P-type terminal injection region disposed within the N-type drift region; a plurality of trenches disposed within the N-type drift region and located on one side of the P-type terminal injection region; the plurality of trenches being arranged laterally at intervals and parallel to each other; the plurality of trenches including at least one dummy gate trench and at least one true gate trench, the true gate trench being located on the side of the dummy gate trench away from the P-type terminal injection region; a P-type injection region disposed on both sides and the bottom of each dummy gate trench, the P-type injection region being connected to the P-type terminal injection region and connected to the side of the true gate trench adjacent to the dummy gate trench; an N-type carrier storage layer disposed on both sides of the true gate trench; a P-type well region disposed above the N-type carrier storage layer; and a plurality of P+ regions disposed on the upper sides of each trench, wherein the P+ regions disposed on the upper sides of the true gate trench are located above the P-type well region, and both sides of the dummy gate trench are connected to the P+ regions. An N+ region is located above a P-type well region, with one side of the N+ region connected to the P+ region and the other side connected to the side of the true gate trench; an N-type hole suppression region is located within a P-type injection region and connected to the P+ region closest to the P-type terminal injection region; the depth of the N-type hole suppression region is greater than the depth of the P+ region; a polysilicon layer is located within each trench, with a gate oxide layer between the polysilicon layer and the inner wall of the trench; a dielectric layer is located on the surface of the gate oxide layer, part of the surface of the P-type injection region, the surface of the P-type terminal injection region, and part of the surface of the N-type drift region; and an emitter metal is located on the surfaces of multiple P+ regions, the surface of the N+ region, and the surface of the dielectric layer on the surface of the gate oxide layer. In this embodiment of the invention, a P-type injection region is provided in the dummy gate trench region. The P-type injection region is located on both sides and the bottom of the dummy gate trench and is electrically connected to the emitter metal. Since the P-type injection region has a low potential, it can effectively shield the large electric field below the dummy gate trench and significantly reduce the electric field strength at the bottom of the transition trench. This solves the problem of electric field concentration at the bottom of the trench at the end of the transition region in traditional termination structures and improves the withstand voltage capability of the device. At the same time, an N-type hole suppression region is provided at the opening at the end of the transition region, which can effectively block the flow path of holes along the oxide layer interface of the termination region, suppress the hole current density and potential rise below the oxide layer, and improve the turn-off reliability of the device. Through the synergistic effect of the P-type injection region and the N-type hole suppression region, the withstand voltage capability and long-term reliability of the device are improved.

[0068] In this embodiment of the invention, step 104 may include the following sub-steps: Before etching to form multiple trenches, P-type ions are implanted in a continuous region from a portion of the P-type terminal implantation region to a portion of the N-type drift region to form an unannealed P-type implantation layer. Multiple trenches are formed by etching in a continuous region where an unannealed P-type implanted layer is implanted and in a portion of the N-type drift region connected to the continuous region. A portion of the unannealed P-type implanted layer is etched away, and the remaining unannealed P-type implanted layer is located between the dummy gate trenches and in the region where the dummy gate trenches are connected to the P-type terminal implanted region. The remaining unannealed P-type implantation layer is annealed to form the P-type implantation region.

[0069] In this embodiment of the invention, the manufacturing method further includes: Metal is deposited on the surface of the dielectric layer on a portion of the surface of the P-type terminal injection region to form the gate metal.

[0070] In this embodiment of the invention, the manufacturing method further includes: N-type ions are injected into the N-type drift region to form a terminal stop ring; the terminal stop ring is located on the side of the P-type terminal injection region away from multiple trenches; A dielectric layer is formed on a portion of the surface of the terminal cutoff ring near the P-type terminal injection region; Metal is deposited on a portion of the surface of the terminal stop ring and a portion of the surface of the dielectric layer on the terminal stop ring to form the stop ring metal.

[0071] In this embodiment of the invention, the manufacturing method further includes: N-type ions are injected below the N-type drift region to form an N-type cutoff layer; the N-type cutoff layer is connected to the N-type drift region; P-type ions are implanted below the N-type cutoff layer to form a P-type current collector region; the P-type current collector region is connected to the N-type cutoff layer. Metal is deposited below the P-type collector region to form the collector metal; the collector metal is connected to the P-type collector region.

[0072] Reference Figure 8 In the N-type drift region 10 of the terminal region 103, P-type ions are implanted and annealed at high temperature to form a GRing region (i.e., P-type terminal implantation region 11) with JTE (junction terminal extension) or VLD (lateral variable doping) termination. This high-temperature annealing process fully activates and diffuses the implanted P-type impurities, forming a P-type terminal implantation region 11 with a specific doping concentration distribution and junction depth, which is used to bear the reverse voltage and alleviate the electric field concentration at the edge of the main junction.

[0073] After the Gring region is formed, Pring implantation is performed. P-type ions are implanted in a predetermined region of the transition region and a portion of the adjacent P-type terminal implantation region 11 to form the Pring implantation layer (i.e., the subsequent P-type implantation region 13). At this time, the Pring has not yet undergone annealing, and the implanted P-type impurities are mainly distributed on the surface region of the semiconductor substrate, with a shallow junction depth, and the final doping distribution has not yet been formed.

[0074] Reference Figure 9 Silicon etching is performed in a continuous region containing an unannealed P-type implanted layer and in a portion of the N-type drift region 10 connected to the continuous region to form multiple trenches 12. This etching process simultaneously forms true gate trenches 122 located in the cell region and dummy gate trenches 121 located in the transition region. Since the etching removes the silicon material at the location of the trenches, the unannealed P-type implanted layer originally located in the trench region is also removed during etching. After etching, the unannealed P-type implanted layer is only retained in the region between the trenches (i.e., between the dummy gate trenches 121 and in the region where the dummy gate trenches 121 connect to the P-type terminal implanted region 11).

[0075] Reference Figure 10 The remaining unannealed P-type implanted layer is then annealed. During the high-temperature annealing process, P-type impurities are activated and undergo lateral and longitudinal diffusion. After annealing, the junction depth of the P-type implanted layer is significantly increased, the doping concentration distribution is more uniform, and a morphology is formed that envelops the pseudo-gate trench 121 in the transition region, that is, the P-type implanted region 13 envelops at least part of the sidewalls and bottom of the pseudo-gate trench 121.

[0076] N-type ions are selectively implanted into the P-type implantation region 13 to form an N-type hole suppression region 22. After implantation, annealing is performed to activate and diffuse the N-type impurities, forming an N-type doped region with a predetermined depth and concentration, namely the N-type hole suppression region 22. The N-type hole suppression region 22 is not connected to the P-type terminal implantation region 11.

[0077] N-type ions are selectively implanted into the N-type drift region 10 to form a terminal stop ring 24. The terminal stop ring 24 is located on the side of the P-type terminal implantation region 11 away from the multiple trenches 12 (i.e., the outermost edge of the terminal region). After implantation, annealing is performed to activate and diffuse the N-type impurities, forming N... + Heavily doped region. The termination ring 24 is used to stop the lateral expansion of the depletion layer when the device is turned off, preventing the depletion layer from extending to the edge of the chip dicing track.

[0078] After the implantation and annealing of the aforementioned N-type hole blocking layer and CR cutoff ring, gate oxide and polysilicon deposition and etching are performed, followed by implantation and annealing of the N-type carrier storage layer 14 and the P-type well region 15. A gate oxide layer is formed on the inner wall of each trench, and then polysilicon is deposited on the gate oxide layer and etched to form a polysilicon layer. Next, N-type carrier storage layer 14 is implanted, with N-type ions implanted on both sides of the true gate trench to form an N-type carrier storage layer. Then, P-type ions are implanted in the upper region of the N-type carrier storage layer to form a P-type well region. After the above implantation is completed, annealing is performed to activate and diffuse the implanted impurities, forming a doped region with a predetermined doping concentration and junction depth.

[0079] Subsequently, the N+ emitter region and P+ ohmic contact region are implanted and annealed, the front side is deposited and etched, and the back side N-type cutoff layer and P-type collector region are implanted and annealed, and the back side is deposited.

[0080] In this embodiment of the invention, a high-concentration, deep-junction P-type implantation region 13 is provided in the dummy gate trench region of the transition region. The P-type implantation region 13 covers at least part of the sidewalls and bottom of the dummy gate trench 121, serving as a protective ring for the transition region trench, and is connected to the emitter metal 21 through the P+ region 16 between the dummy gate trenches 121, thus having the lowest potential in the entire chip. Due to the low potential characteristics of the P-type implantation region 13, the electric field lines near it point radially towards the P-type implantation region 13 from all sides. This structure can effectively shield the large electric field below the dummy gate trench 121, significantly reduce the electric field strength at the bottom of the transition region trench, thereby improving the reliability of the transition region.

[0081] When the IGBT is turned on, electrons are injected into the N+ region 17 of the cell, and holes are injected into the P-type collector region 27 on the back. Influenced by the distribution of electric field lines in the low-potential region of the P-type injection region 13, electrons (negative charges) move against the electric field lines, migrating away from the terminal region; while holes (positive charges) move with the electric field lines and are attracted and extracted by the P-type injection region 13. This mechanism effectively reduces the hole injection efficiency in the terminal region, decreases the amount of holes stored in the terminal region, and lays the foundation for improved reliability during the turn-off phase.

[0082] To address the problem in traditional terminal structures where holes flow only along the oxide layer interface of the terminal region and concentrate at the end opening of the transition region, this invention provides an N-type hole suppression region 22 below the end opening of the transition region. This N-type hole suppression region 22 is located within the P-type injection region 13 and is connected to the P+ region 16 closest to the P-type terminal injection region 11, with a depth greater than that of the P+ region 16. The N-type hole blocking layer effectively blocks the flow path of holes below the oxide layer, suppressing the rise in hole current density and potential below the oxide layer.

[0083] Through the combined action of the low potential region of the P-type injection region 13 and the N-type hole suppression region 22, this invention achieves comprehensive optimization of the hole current path. On the one hand, the low potential of the P-type injection region 13 actively attracts holes, causing holes during the turn-off process to flow from the drift region to the Pring region; on the other hand, the N-type hole suppression region 22 cuts off the traditional path of holes along the oxide layer interface of the terminal region to the opening at the end of the transition region. After being attracted to the P-type injection region 13, the holes are uniformly extracted through the Mesa region (i.e., the mesa region between the dummy gate trenches) within the P-type injection region 13, forming multiple dispersed extraction paths.

[0084] This invention also provides a chip, including the power device described above.

[0085] The terms "first" and "second" in the specification and claims of this invention may explicitly or implicitly include one or more of those features. In the description of this invention, unless otherwise stated, "a plurality of" means two or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0086] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0087] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0088] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0089] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A power device, characterized in that, The power device includes: N-type drift zone; The P-type terminal injection region is located in the N-type drift region; Multiple trenches are provided within the N-type drift region and located on one side of the P-type terminal injection region; the multiple trenches are arranged laterally at intervals and parallel to each other; the multiple trenches include at least one dummy gate trench and at least one true gate trench, the true gate trench being located on the side of the dummy gate trench away from the P-type terminal injection region; P-type injection regions are located on both sides and the bottom of each dummy gate trench. The P-type injection regions are connected to the P-type terminal injection regions and are connected to the side of the true gate trench that is closest to the dummy gate trench. An N-type carrier storage layer is disposed on both sides of the true gate trench; A P-type well region is located above the N-type carrier storage layer; Multiple P+ regions are provided on both sides of the upper part of each trench, wherein the P+ regions provided on both sides of the upper part of the true gate trench are located above the P-type well region, and both sides of the dummy gate trench are connected to the P+ regions. The N+ region is located above the P-type well region, with one side of the N+ region connected to the P+ region and the other side connected to the side of the true gate trench. An N-type hole suppression region is located within the P-type injection region and connected to the P+ region closest to the P-type terminal injection region; the depth of the N-type hole suppression region is greater than the depth of the P+ region. A polysilicon layer is disposed in each of the trenches, and a gate oxide layer is provided between the polysilicon layer and the inner wall of the trench; A dielectric layer is disposed on the surface of the gate oxide layer, a portion of the surface of the N-type hole suppression region near the P-type terminal injection region, a portion of the surface of the P-type injection region, the surface of the P-type terminal injection region, and a portion of the surface of the N-type drift region; Emitter metal is disposed on the surface of the plurality of P+ regions, the surface of the N+ regions, the surface of the dielectric layer on the surface of the gate oxide layer, a portion of the surface of the N-type hole suppression region, and the surface of the dielectric layer on the surface of the N-type hole suppression region.

2. The power device according to claim 1, characterized in that, The power device further includes: Gate metal, which is disposed on the surface of a dielectric layer on a portion of the surface of the P-type terminal injection region.

3. The power device according to claim 1, characterized in that, The power device further includes: A terminal stop ring is disposed within the N-type drift region and located on the side of the P-type terminal injection region away from the plurality of trenches; the dielectric layer is also disposed on a portion of the surface of the terminal stop ring near the P-type terminal injection region. A stop ring metal is disposed on a portion of the surface of the terminal stop ring and a portion of the surface of the dielectric layer on the terminal stop ring.

4. The power device according to claim 1, characterized in that, The power device further includes: An N-type cutoff layer is disposed below the N-type drift region and connected to the N-type drift region; A P-type collector region is located below the N-type cutoff layer and connected to the N-type cutoff layer; The collector metal is located below the P-type collector region and connected to the P-type collector region.

5. A method for manufacturing a power device, characterized in that, The manufacturing method for manufacturing the power device as described in any one of claims 1 to 4 includes: Provides an N-type drift zone; P-type ions are injected into the N-type drift region to form a P-type terminal injection region; Multiple trenches are formed by etching in a continuous region from a portion of the P-type terminal injection region to a portion of the N-type drift region; the multiple trenches are arranged laterally at intervals and parallel to each other; the multiple trenches include at least one dummy gate trench and at least one true gate trench, the true gate trench being located on the side of the dummy gate trench away from the P-type terminal injection region. P-type ions are injected into a portion of the N-type drift region between each dummy gate trench and a portion of the P-type terminal injection region connected to the dummy gate trench to form a P-type injection region. The P-type injection region is located on both sides and the bottom of each dummy gate trench. The P-type injection region is connected to the P-type terminal injection region and is connected to the side of the true gate trench closest to the dummy gate trench. N-type ions are injected into both sides of the true gate trench to form an N-type carrier storage layer; P-type ions are injected into the upper region of the N-type carrier storage layer to form a P-type well region; P-type ions are injected on both sides of the upper part of each trench to form multiple P+ regions. The P+ regions located on both sides of the upper part of the true gate trench are located above the P-type well region, and both sides of the dummy gate trench are connected to the P+ regions. N-type ions are implanted above the P-type well region to form an N+ region; one side of the N+ region is connected to the P+ region, and the other side is connected to the side of the true gate trench. N-type ions are injected into the P-type injection region to form an N-type hole suppression region; the N-type hole suppression region is connected to the P+ region closest to the P-type terminal injection region; the depth of the N-type hole suppression region is greater than the depth of the P+ region. A gate oxide layer is formed on the inner wall of each trench, and polysilicon is deposited on the gate oxide layer to form a polysilicon layer; A dielectric layer is formed on the surface of the gate oxide layer, a portion of the surface of the N-type hole suppression region near the P-type terminal injection region, a portion of the surface of the P-type injection region, the surface of the P-type terminal injection region, and a portion of the surface of the N-type drift region. Emitter metal is formed by depositing metal on the surfaces of the plurality of P+ regions, the surfaces of the N+ regions, the surfaces of the dielectric layer on the surface of the gate oxide layer, a portion of the surface of the N-type hole suppression region, and the surface of the dielectric layer on the surface of the N-type hole suppression region.

6. The manufacturing method according to claim 5, characterized in that, The step of injecting P-type ions into a portion of the N-type drift region between each dummy gate trench and a portion of the P-type terminal injection region connected to the dummy gate trench to form a P-type injection region includes: Before etching to form the plurality of trenches, P-type ions are implanted in a continuous region from a portion of the P-type terminal implantation region to a portion of the N-type drift region to form an unannealed P-type implantation layer. The plurality of trenches are formed by etching in a continuous region where the unannealed P-type implanted layer is implanted and in a portion of the N-type drift region connected to the continuous region. A portion of the unannealed P-type implanted layer is etched away, and the remaining unannealed P-type implanted layer is located between the dummy gate trenches and in the region where the dummy gate trenches are connected to the P-type terminal implanted region. The remaining unannealed P-type injection layer is annealed to form the P-type injection region.

7. The manufacturing method according to claim 5, characterized in that, The manufacturing method further includes: Metal is deposited on the surface of the dielectric layer on a portion of the surface of the P-type terminal injection region to form gate metal.

8. The manufacturing method according to claim 5, characterized in that, The manufacturing method further includes: N-type ions are injected into the N-type drift region to form a terminal stop ring; the terminal stop ring is located on the side of the P-type terminal injection region away from the plurality of trenches; The dielectric layer is formed on a portion of the surface of the terminal cut-off ring near the P-type terminal injection region; Metal is deposited on a portion of the surface of the terminal stop ring and a portion of the surface of the dielectric layer on the terminal stop ring to form the stop ring metal.

9. The manufacturing method according to claim 5, characterized in that, The manufacturing method further includes: N-type ions are injected below the N-type drift region to form an N-type cutoff layer; the N-type cutoff layer is connected to the N-type drift region; P-type ions are implanted below the N-type cutoff layer to form a P-type current collector region; the P-type current collector region is connected to the N-type cutoff layer. Metal is deposited below the P-type collector region to form a collector metal; the collector metal is connected to the P-type collector region.

10. A chip, characterized in that, Includes the power device as described in any one of claims 1 to 4.

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