Semiconductor device and manufacturing method thereof, electronic device

Abstract

The application relates to the technical field of semiconductor device preparation, in particular to a semiconductor device and a manufacturing method thereof, an electronic device, and a transistor device region, wherein the transistor device region comprises a gate, a channel region, and source / drain regions located on both sides of the channel region along the length direction; a first isolation part is arranged directly below the channel region; a semiconductor layer is arranged directly below the source / drain regions, and the upper surface of the semiconductor layer is in direct contact with the bottom surface of the source / drain regions. According to the application, the first isolation part is arranged directly below the channel, and a continuous single-crystal semiconductor layer is reserved below the source / drain regions, so that the channel bottom parasitic leakage is effectively blocked by the bottom dielectric isolation, and the stress transmission path from the source / drain epitaxial layer to the channel is opened by the semiconductor layer, the stress loss defect of the full BDI structure is compensated, and the channel carrier mobility and the device conduction current are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication technology, and in particular to a semiconductor device and its manufacturing method, as well as an electronic device. Background Technology

[0002] Gate-All-Around (GAA) transistors, with their advantage of fully enclosed gate control, can effectively suppress short-channel effects and are the mainstream device architecture for advanced process logic devices and high-density SRAM cells at 3nm and below.

[0003] To address the issue of bottom parasitic leakage current between the channel and the silicon substrate at the nanoscale, current technologies generally employ a method of completely embedding an insulating dielectric layer beneath the entire layer of the GAA nanosheet channel and the active regions of the source / drain. This insulating dielectric layer isolates the silicon connectivity pathway between the source / drain, the channel, and the silicon substrate, physically blocking the bottom leakage current induced by the substrate. This significantly reduces the device's subthreshold leakage current and parasitic substrate capacitance, effectively improving the device's leakage characteristics and power consumption performance.

[0004] However, in practical applications, filling the entire area below the source / drain region with insulating dielectric completely cuts off the continuous silicon conduction path extending downward from the source / drain epitaxial region. As a result, the source / drain stress cannot be effectively transferred to the interior of the GAA nanosheet channel through the silicon substrate, causing insufficient channel stress recovery. This directly leads to the decay of carrier mobility and a decrease in the device's saturation conduction current, sacrificing the upper limit of the electrical performance of the GAA device.

[0005] Meanwhile, existing conventional back-side contact fabrication processes require wafer flipping and substrate thinning to remove the original silicon substrate after the front-side device fabrication is completed on the wafer. Then, back-side photolithography is used for pattern overlay, windowing to create contact holes, and filling with contact metal. However, due to the influence of wafer thinning, back-side grinding, wafer bonding, and other processes, the wafer is prone to warping deformation, resulting in significant overlay errors between the back-side photolithography and the front-side active area pattern. This makes it difficult to accurately align the back-side contact holes with the source / drain active areas. Contact alignment deviations not only cause significant fluctuations in device contact resistance and a decrease in device yield, but in extreme cases, contact metal may also accidentally touch the gate structure, inducing gate-source / leakage currents.

[0006] In view of this, the present invention is proposed. Summary of the Invention

[0007] The purpose of this invention is to provide a semiconductor device that, while taking into account the low leakage current advantage of BDI, overcomes the shortcomings of the electrical performance degradation of traditional full-bottom dielectric isolation devices, achieving a balance between low leakage and high driving performance.

[0008] In a first aspect, the present invention provides a semiconductor device, comprising: A transistor device region, the transistor device region including a gate, a channel region and source / drain regions located on both sides of the channel region along its length; The first isolation section is located directly below the trench area; A semiconductor layer is disposed directly below the source / drain region, and the upper surface of the semiconductor layer is in direct contact with the bottom surface of the source / drain region.

[0009] As a preferred embodiment of this technical solution, it further includes a first source / drain contact portion, which is disposed on the back side of the semiconductor device and extends vertically from the back side of the semiconductor device to the lower surface of the semiconductor layer.

[0010] As a preferred embodiment of this technical solution, it further includes a second source / drain contact portion, which is disposed on the side of the first source / drain contact portion away from the semiconductor layer, and a second isolation portion is disposed between the second source / drain contacts.

[0011] As a preferred embodiment of this technical solution, the first source / drain contact portion is isolated from each other by the first isolation portion.

[0012] As a preferred embodiment of this technical solution, the lateral boundary of the first isolation section does not exceed the projection range of the channel area.

[0013] In a preferred embodiment of this technical solution, the surface of the first isolation portion near the channel region is located on the same plane as the surface of the semiconductor layer near the source / drain region.

[0014] As a preferred embodiment of this technical solution, the lateral sides of the first isolation portion are located on the same plane as the inner side of the semiconductor layer.

[0015] In a preferred embodiment of this technical solution, the thickness of the first isolation portion is greater than the thickness of the semiconductor layer.

[0016] As a preferred embodiment of this technical solution, the semiconductor layer is single-crystal silicon with a thickness of 4-30nm.

[0017] As a preferred embodiment of this technical solution, the first isolation portion and the second isolation portion are one or more composite dielectric layers selected from silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric.

[0018] As a preferred embodiment of this technical solution, the transistor device is a gate-around transistor, and the channel region includes stacked nanosheets or nanowires.

[0019] Secondly, the present invention also discloses a method for manufacturing the above-mentioned semiconductor device, comprising the following steps: Provide semiconductor substrates; Along the direction perpendicular to the thickness of the semiconductor substrate, a site sacrificial layer, a semiconductor layer, and multiple sets of alternately stacked channel sacrificial layers and channel layers are epitaxially grown sequentially, and fins are patterned. This forms a false grid layer and an outer wall; Selectively remove the sacrificial layer beneath the source / drain region and fill the resulting cavity with a spacer material; The fin stack is etched to form a channel stack, and source / drain regions are epitaxially grown on both sides of the channel stack; Etching the channel sacrificial layer and the occupant sacrificial layer below the channel stack forms a trench, and a replacement gate stack is formed in the trench to complete the fabrication of the transistor structure; The semiconductor substrate is wafer-bonded to another semiconductor substrate on the upper surface of the transistor structure. After flipping, the semiconductor substrate is thinned down to the surface of the placer material. Selectively remove the semiconductor layer below the channel region to create a bottom opening below the channel; A dielectric layer is formed above the bottom opening and polished until the placeholder material is exposed; Selectively remove the occupier material and fill the resulting cavity with metal; A back dielectric layer is deposited to form vias and complete the back metal interconnect.

[0020] In a preferred embodiment of this technical solution, when selectively removing the sacrificial layer below the source / drain region, isotropic etching is used, and the etching time is controlled to release only the sacrificial layer below the source / drain region.

[0021] As a preferred embodiment of this technical solution, when etching the fin stack to form a channel stack, only multiple sets of alternately stacked channel sacrificial layers and channel layers in the source / drain regions are removed, while the semiconductor layer below the source / drain regions is retained.

[0022] As a preferred embodiment of this technical solution, when selectively removing the semiconductor layer below the channel region, the semiconductor layer below the source / drain region must be retained.

[0023] In a preferred embodiment of this technical solution, when filling the formed cavity with metal, the metal is kept only within the area defined by the occupant material.

[0024] As a preferred embodiment of this technical solution, the occupier material includes any one of silicon oxide, silicon nitride, silicon carbonitride, or silicon carbide.

[0025] Thirdly, the present invention also discloses electronic devices including the above-mentioned semiconductor devices, the electronic devices including smartphones, personal computers, tablet computers, artificial intelligence devices, wearable devices or power banks.

[0026] The semiconductor device of the present invention has at least the following beneficial effects: This invention differs from conventional full-bottom dielectric isolation (BDI) device structures where the entire channel and source / drain regions have bottom dielectrics. Instead, it places a first isolation section only directly below the channel, while the semiconductor layer remains intact directly below the source / drain regions. By utilizing this first isolation section below the channel region to isolate the channel from residual conductive paths on the substrate, it fundamentally blocks parasitic leakage current from the substrate at the bottom of the channel and suppresses short-channel side effects such as DIBL, achieving low leakage power consumption. Simultaneously, the lattice stress generated by source / drain epitaxy can be completely conducted to the channel direction through the semiconductor layer, completely solving the problem of insufficient channel stress caused by dielectric isolation of the silicon substrate and broken stress transmission paths in full-BDI solutions. This effectively optimizes the channel stress state, significantly improves carrier mobility, and significantly improves the device's saturation conduction current. While maintaining the low leakage advantage of BDI, it overcomes the shortcomings of traditional full-bottom dielectric isolation devices with degraded electrical performance, achieving a balance between low leakage and high drive performance. Attached Figure Description

[0027] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0028] Figure 1 This is a partial structural schematic diagram of the semiconductor device of the present invention; Figure 2 This is a top view of the semiconductor device of the present invention; Figure 3 This is a schematic cross-sectional view along the AA' direction during the fabrication of the semiconductor device of the present invention; Figure 4 This is a schematic cross-sectional view along the AA' direction during the fabrication of the semiconductor device of the present invention; Figure 5 This is a schematic cross-sectional view along the AA' direction during the fabrication of the semiconductor device of the present invention; Figure 6 This is a schematic cross-sectional view along the BB' direction during the fabrication of the semiconductor device of the present invention; Figure 7 This is a schematic cross-sectional view along the BB' direction during the fabrication of the semiconductor device of the present invention; Figure 8 This is a schematic cross-sectional view along the BB' direction during the fabrication of the semiconductor device of the present invention; Figure 9 This is a schematic cross-sectional view along the BB' direction during the fabrication of the semiconductor device of the present invention; Figure 10This is a schematic cross-sectional view along the BB' direction during the fabrication of the semiconductor device of the present invention; Figure 11 This is a schematic cross-sectional view along the BB' direction during the fabrication of the semiconductor device of the present invention; Figure 12 This is a schematic cross-sectional view along the BB' direction during the fabrication of the semiconductor device of the present invention; Figure 13 This is a schematic cross-sectional view along the BB' direction during the fabrication of the semiconductor device of the present invention; Figure 14 This is a schematic cross-sectional view along the BB' direction during the fabrication of the semiconductor device of the present invention; Figure 15 This is a schematic cross-sectional view along the BB' direction during the fabrication of the semiconductor device of the present invention; Figure 16 This is a schematic cross-sectional view along the BB' direction during the fabrication of the semiconductor device of the present invention; Figure 17 This is a schematic cross-sectional view along the BB' direction during the fabrication of the semiconductor device of the present invention; Figure 18 This is a schematic cross-sectional view along the BB' direction during the fabrication of the semiconductor device of the present invention; Figure 19 This is a schematic cross-sectional view along the BB' direction during the fabrication of the semiconductor device of the present invention; Figure 20 This is a schematic cross-sectional view along the BB' direction during the fabrication of the semiconductor device of the present invention; Figure 21 This is a schematic cross-sectional view along the BB' direction during the fabrication of the semiconductor device of the present invention; Figure 22 Stress recovery diagrams of NMOS and PMOS transistors in the semiconductor device of this invention; Figure 23 This invention provides a comparison of the drive current of the semiconductor device with conventional devices (STD) and full BDI devices (BDI); Figure 24 This invention provides a comparison of the characteristics of the semiconductor device of the present invention with those of typical ring array circuits of conventional devices (STD) and full BDI devices (BDI); Figure 25 This invention provides a comparison of the characteristics of the SRAM circuits of the semiconductor device of the present invention with those of conventional devices (STD) and full BDI devices (BDI).

[0029] Explanation of reference numerals in the attached figures: 1: Semiconductor substrate; 2: First isolation region; 3: Second isolation region; 4: First source / drain contact region; 5: Second source / drain contact region; 6: Sacrificial layer; 7: Semiconductor layer; 8: Channel sacrificial layer; 9: Channel layer; 10: Shallow trench isolation structure; 11: Dummy gate stack; 12: Dummy gate hard mask layer; 13: Gate outer wall; 14: Placement material; 15: Lateral groove; 16: Inner wall; 17: Source / drain region; 18: Metal gate; 19: Bottom opening. Detailed Implementation

[0030] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and not intended to limit the scope of the invention. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0031] The accompanying drawings illustrate various structural schematic diagrams according to embodiments of the present invention. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0032] In the context of this invention, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0033] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0034] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0035] While existing solutions that fill the entire area below the source / drain region 17 with insulating dielectric can suppress parasitic leakage current at the bottom of the device, the full dielectric arrangement of the source / drain region 17 cuts off the silicon conduction path, resulting in a lack of channel stress and deterioration of mobility and conduction current.

[0036] To address the aforementioned issues, this invention proposes a semiconductor device in which a first isolation portion 2 is disposed only directly below the channel, while a semiconductor layer 7 is fully retained directly below the source / drain region 17. The first isolation portion 2 below the channel region isolates the channel from the residual conductive path of the substrate, fundamentally blocking substrate parasitic leakage current at the bottom of the channel and suppressing short-channel side effects such as DIBL, thereby achieving low leakage power consumption. The semiconductor layer 7 retained directly below the source / drain region 17 can completely conduct the lattice stress generated by source / drain epitaxy to the channel direction, thoroughly solving the problem of insufficient channel stress caused by dielectric isolation of the silicon substrate and breakage of stress transmission path in the all-BDI scheme, effectively optimizing the channel stress state, significantly improving carrier mobility, and significantly improving the device saturation conduction current.

[0037] Specifically, in a first aspect, embodiments of the present invention provide a semiconductor device. For example... Figure 1 As shown, the semiconductor device provided in this embodiment of the invention includes a transistor device region, a first isolation portion 2, and a semiconductor layer 7. The transistor device region includes a gate, a channel region, and source / drain regions 17 located on both sides of the channel region along its length. The first isolation portion 2 is disposed directly below the channel region, meaning its lateral boundary does not exceed the projection range of the channel region, thereby blocking substrate parasitic leakage at the bottom of the channel and suppressing short-channel side effects such as DIBL. The semiconductor layer 7 is disposed directly below the source / drain regions 17, meaning its lateral boundary is completely defined within its projection range, connecting the source / drain epitaxial regions and the back contact region, thus completely solving the problem of insufficient channel stress caused by dielectric isolation of the silicon substrate and breakage of the stress transmission path in the all-BDI scheme. Therefore, the semiconductor device of this invention achieves a balance between low leakage and high driving performance.

[0038] The transistor device of the present invention is a gate-around transistor, wherein the channel is composed of multiple layers of nanosheets or nanowires stacked and arranged in a vertical direction; the gate material surrounds and covers the entire periphery of each layer of nanosheets / nanowires, realizing 360° all-round gate control, which can effectively suppress short-channel effects and significantly improve the leakage current and gate control capability of the device compared with FinFET.

[0039] With the above technical solution, it is understood that the structure of the present invention, which provides a first isolation part 2 directly below the channel region and a semiconductor layer 7 directly below the source / drain region 17, is adapted to stacked nanosheet / nanowire ring gate devices. The stress generated by the source / drain epitaxy is smoothly transmitted to each channel layer through the semiconductor layer 7 directly below the source / drain region 17, ensuring that the multi-channel channels obtain effective stress regulation simultaneously, stably improving the overall carrier migration and conduction capability, and adapting to the device usage requirements of advanced process low voltage and high performance.

[0040] In this embodiment, the transistor device specifically includes a channel region, a source / drain region 17, and a gate stack structure composed of multiple stacked nanosheets or nanowires. The channel region is located between the source / drain regions 17, and both ends of the channel region along its length are distributed and contact the source / drain regions 17. The gate stack structure includes a gate dielectric layer and a gate electrode. The gate dielectric layer surrounds the outer periphery of at least a portion of the length of each nanosheet or nanowire structure, and the gate electrode is formed on the gate dielectric layer. In some cases, the transistor device further includes an outer gate wall 13 and an inner gate wall 16. The outer gate wall 13 is located on both sides of the upper part of the gate stack structure, and the inner gate wall 16 is located between the gate stack structure and the source / drain regions 17.

[0041] Specifically, in some embodiments, the transistor device of the present invention comprises only a single gate-around transistor, wherein the channel region of the gate-around transistor is composed of multiple stacked nanosheets or nanowires, and the gate completely covers the channel. In this embodiment, a first isolation portion 2 is provided only directly below the single channel region, while a semiconductor layer 7 is provided directly below the source / drain region 17, thereby achieving the effects of suppressing leakage current in the channel dielectric and conducting stress in the source / drain semiconductor layer 7.

[0042] Furthermore, the transistor device of the present invention can be a discrete device structure of a single gate ring transistor as described above, or it can be a transistor array composed of multiple gate ring transistors.

[0043] For example, in some embodiments, the transistor device of the present invention is a conventional lateral GAA device, in which the first gate-around transistor and the second gate-around transistor are arranged laterally side by side, and the internal channel of any transistor is formed by stacking multiple nanosheets / nanowires in a vertical direction, with the gate surrounding and covering each channel layer. The present invention provides a first isolation layer only directly below any single transistor channel region, while retaining a semiconductor layer 7 directly below the source / drain region 17. The first isolation layer blocks leakage current at the bottom of the corresponding transistor channel, and the semiconductor layer 7 completes the conduction of source / drain stress to the stacked nanosheet channel, achieving an optimized effect of low leakage current and high mobility.

[0044] In other embodiments, the transistor device of the present invention is a CFET vertically stacked transistor, wherein the first gate ring transistor and the second gate ring transistor are vertically stacked along the thickness direction of the device, and each transistor is independently configured with a source / drain and a gate ring channel. The present invention can arrange a first isolation portion 2 directly below the channel region of each of the upper and lower gate ring transistors, and retain a corresponding semiconductor layer 7 directly below the source / drain region 17 of each gate ring transistor, thereby realizing bottom leakage current suppression and stress transfer of each channel layer respectively.

[0045] Regarding the first and second gate-ring transistors in the above embodiments, their conductivity types can be the same or different. For example, both the first and second gate-ring transistors can be N-type or P-type gate-ring transistors. Alternatively, the first gate-ring transistor can be an N-type gate-ring transistor, in which case the second transistor is a P-type gate-ring transistor. As another example, the first gate-ring transistor can also be a P-type gate-ring transistor, in which case the second gate-ring transistor is an N-type gate-ring transistor.

[0046] The specific structures of the first and second gate ring transistors can be referenced from those of a single gate ring transistor, and will not be elaborated here.

[0047] Furthermore, regarding the first isolation portion 2, the surface of the first isolation portion 2 near the channel region is on the same plane as the surface of the semiconductor layer 7 near the source / drain region 17, and the lateral sides of the first isolation portion 2 are on the same plane as the inner side of the semiconductor layer 7. That is, the first isolation portion 2 of the present invention is only disposed directly below the channel region, and the semiconductor layer 7 is only disposed directly below the source / drain region 17. The two are adjacent to each other along the channel width direction. The two side walls of the first isolation portion 2 are seamlessly connected to the side walls of the semiconductor layer 7 near the channel and are coplanar and flush. There is no lateral extension of the first isolation portion 2 into the bottom of the source / drain region 17, nor is there any extension of the semiconductor layer 7 to the direct below the channel region that encroaches on the placement area of ​​the first isolation portion 2. The partitioning setting of dielectric isolation directly below the channel and complete retention of the semiconductor layer 7 directly below the source / drain region 17 is strictly achieved. The channel is completely isolated directly below by the first isolation portion 2, completely cutting off the conductive path connecting the channel downwards to the silicon substrate, thus maximizing the effect of the first isolation portion 2 in suppressing parasitic leakage current at the bottom. Meanwhile, the semiconductor layer 7 is completely preserved below the source / drain region 17 without any dielectric interfering, allowing the lattice stress of the source / drain epitaxy to be completely transferred to the channel along the semiconductor layer 7, avoiding the full BDI stress deficiency defect. Furthermore, the two sidewalls of the first isolation portion 2 are coplanar with the sidewalls of the semiconductor layer 7 near the channel, without any staggered recesses or protrusions, and the back isolation dielectric can uniformly cover the boundary position, achieving reliable isolation.

[0048] Based on the above solution, the thickness of the first isolation portion 2 in this invention is greater than the thickness of the semiconductor layer 7. The thicker first isolation portion 2 can significantly improve the insulation withstand voltage performance, completely block the downward conductive path of the channel, and further suppress parasitic leakage current in the substrate at the bottom of the channel. Meanwhile, the thinner semiconductor layer 7 has better silicon lattice continuity, and the stress generated by source / drain epitaxy can be efficiently and non-destructively transmitted to both sides of the channel along the thin silicon structure, stably improving the channel carrier mobility and conduction drive current.

[0049] In one specific embodiment, the semiconductor layer 7 directly beneath the source / drain region 17 of the present invention is single-crystal silicon with a thickness of 4-30 nm and a doping concentration of 1×10⁻⁶. 17 -3×10 21 For P-type devices, boron doping can be used. For N-type devices, phosphorus can be doped.

[0050] In one specific embodiment, the first isolation portion 2 directly below the channel region of the present invention is one or more composite dielectric layers selected from silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric. The present invention does not impose strict limitations on it.

[0051] Based on the above technical solution, the semiconductor device of the present invention further includes a first source / drain contact portion 4 and a second source / drain contact portion 5, wherein the first source / drain contact portion 4 is disposed on the back side of the semiconductor device, the first source / drain contact portion 4 extends vertically from the back side of the semiconductor device to the lower surface of the semiconductor layer 7, and the first source / drain contact portions 4 are isolated from each other by a first isolation portion 2; the second source / drain contact portion 5 is disposed on the side of the first source / drain contact portion 4 away from the semiconductor layer 7, and a second isolation portion 3 is disposed between the second source / drain contact portions 5.

[0052] Regarding the first source / drain contact 4, it is arranged on the inner side of the back of the device, close to the semiconductor layer 7, and extends vertically upward from the back of the device to the lower surface of the semiconductor layer 7. It directly contacts the semiconductor layer 7 to achieve electrical conduction and has a low contact resistance. The first source / drain contact 4 corresponding to the transistor device is laterally limited within the projection range of the semiconductor layer 7. The first source / drain contact 4 is physically isolated and electrically insulated from each other by the first isolation part 2 located directly below the channel.

[0053] The first source / drain contact 4 of this invention is formed by filling the previously occupied cavity with metal after removal, eliminating the need for a back-side photolithography windowing process. This avoids misalignment and misalignment issues caused by wafer warpage, resulting in uniform contact resistance and improved device yield. Simultaneously, the first isolation portion at the bottom of the existing channel serves as the isolation medium for the first source / drain contact 4, eliminating the need for deposition and photolithography of the lower isolation film, reducing the transistor unit size, and facilitating high-density integration. Furthermore, constrained by the lateral boundary of the semiconductor layer 7, the metal will not propagate into the first isolation portion below the channel, preventing gate-source leakage caused by metal contacting the channel.

[0054] Regarding the second source / drain contact 5, it is located on the back side of the first source / drain contact 4 away from the semiconductor layer 7, and corresponds one-to-one with the first source / drain contact 4, and is connected vertically to conduct signals for back-side interconnection of the device; the second source / drain contact 5 is filled with a second isolation portion 3, and the interconnection metal is isolated by the second isolation portion 3.

[0055] This invention utilizes the first isolation portion 2 directly below the channel as the isolation medium for the first source / drain contact portion 4, eliminating the need for additional deposition and photolithography to prepare the lower isolation medium, thus simplifying the back-side fabrication process and reducing the device unit area. The second source / drain contact portion 5 is separately paired with the second isolation portion 3 for interlayer isolation, perfectly matching the self-aligned back-side contact fabrication process.

[0056] The second source / drain contact 5 of the present invention is isolated by an independent second isolation part 3 and is not constrained by the bottom first isolation 2 layout, allowing for flexible arrangement of multiple power and signal lines to adapt to the diverse wiring requirements of standard units.

[0057] In some specific embodiments, the material of the second isolation part 3 of the present invention may be the same as or different from the material of the first isolation part 2. Specifically, it may be one or more composite dielectric layers of silicon oxide, silicon nitride, silicon oxynitride or high-k dielectric. The present invention does not impose strict limitations on it.

[0058] Secondly, embodiments of the present invention provide a method for manufacturing a semiconductor device. The structure of the semiconductor device formed by the manufacturing method provided in the second aspect of the present invention is the same as that of the semiconductor device provided in the first aspect. Therefore, the beneficial effects of the second aspect and its various implementations in the present invention can be analyzed with reference to the beneficial effects in the first aspect and its various implementations, and will not be repeated here.

[0059] The following will be based on Figures 2 to 21 The cross-sectional view shown illustrates the manufacturing process. Specifically, the method for manufacturing this semiconductor device includes the following steps: like Figure 3 As shown, along the direction perpendicular to the thickness of the semiconductor substrate 1, a site sacrificial layer 6, a semiconductor layer 7, and multiple sets of alternately stacked channel sacrificial layers 8 and channel layers 9 are epitaxially grown sequentially, and fins are patterned.

[0060] Specifically, the semiconductor substrate 1 can be a substrate made of any semiconductor material such as silicon, germanium-silicon, or germanium, or it can be a substrate made of insulating material such as silicon oxide or ceramic. This embodiment of the invention does not specifically limit the structure and material of the semiconductor substrate 1, as long as it can be applied to the semiconductor device provided in this embodiment. The bottom sacrificial layer 6 is used to define the position of the subsequent sacrificial structure, the semiconductor layer 7 is used to form the semiconductor layer 7 directly below the subsequent source / drain region 17, and the channel sacrificial layer 8 is used to fill the metal gate 18 after release. The sacrificial layer 6 is a high Ge concentration SiGe layer, for example, Si... 0.5 Ge 0.5 The thickness of the sacrificial layer 6 is 5-25 nm; the semiconductor layer 7 can be made of single-crystal silicon with a thickness of 4-30 nm. For P-type devices, it can be doped with boron, and for N-type devices, it can be doped with phosphorus at a doping concentration of 1×10⁻⁶. 17 -3×10 21 Specifically, in-situ doping can be performed during epitaxy, or implantation doping can be performed after etching the source and drain; the channel sacrificial layer 8 is a low-Ge concentration SiGe layer, for example, Si 0.7 Ge 0.3 The 9th channel layer is a Si layer, with ≥1 Si layer. The Si layer determines the number of subsequent nanowires. The thickness of the Si layer is less than 30nm. The final thickness directly determines the height of the nanosheet channel and its electrical performance.

[0061] In the actual manufacturing process, epitaxy and other processes can be used to form a sacrificial layer 6, a semiconductor layer 7, and multiple sets of alternately stacked channel sacrificial layers 8 and channel layers 9 on a semiconductor substrate 1. Then, a hard mask layer is deposited above the top channel layer 9. After patterning, photolithography and etching processes are used to etch the sacrificial layer 6, the semiconductor layer 7, the multiple sets of alternately stacked channel sacrificial layers 8 and channel layers 9, and part of the semiconductor substrate 1 to form fin stacks on the semiconductor substrate 1.

[0062] Next, as Figure 4 As shown, a shallow trench isolation structure 10 can be formed on a semiconductor substrate 1 using processes such as deposition and etching. The top of the shallow trench isolation structure 10 is flush with the bottom surface of the sacrificial layer 6 to facilitate the precise re-etching of the sacrificial layer 6 in the future.

[0063] Next, as Figure 5 As shown, a dummy gate stack 11 and a dummy gate hard mask layer 12 are sequentially formed on the exposed fin stack surface. Specifically, an oxide layer and polysilicon (or amorphous silicon) are sequentially deposited above the shallow trench isolation structure 10, followed by CMP, and then the dummy gate hard mask layer 12 is deposited. Further, the amorphous or polysilicon dummy gate is anisotropically etched and stopped at the top of the fin stack. After etching, the dummy gate hard mask layer 12 above the dummy gate structure is retained. Then, as... Figure 6 As shown, gate outer wall 13 dielectric is deposited on both sides of the dummy gate structure, and then the gate outer wall 13 dielectric in the horizontal direction is etched, leaving only the dielectric of the dummy gate and the hard mask layer sidewall to form the gate outer wall 13.

[0064] Next, as Figures 6 to 7 As shown, the placeholder sacrificial layer 6 directly below the source / drain region 17 is selectively removed, and the cavity formed is filled with placeholder material 14.

[0065] In the actual manufacturing process, isotropic etching can be used. By controlling the etching time, only the sacrificial layer 6 directly below the source / drain region 17 is released, and excessive lateral etching of the under-gate region is avoided. Subsequently, the cavity formed by the release is filled with the placeholder material 14.

[0066] The spacer material 14 includes any one of silicon oxide, silicon nitride, silicon carbonitride, or silicon carbide, and the present invention does not strictly limit it.

[0067] Next, as Figures 8 to 12 As shown, the fin stack is etched to form a channel stack, and source / drain regions 17 are epitaxially grown on both sides of the channel stack.

[0068] In the actual manufacturing process, firstly, the interface oxide layer on the fin stack surface of the source / drain region 17 is removed. Then, anisotropic etching is used to remove only the multiple sets of alternately stacked channel sacrificial layers 8 and channel layers 9 in the source / drain region 17, retaining a semiconductor layer 7 of a certain thickness below the source / drain region 17, forming a channel stack. Further, isotropic etching is performed to precisely etch the inner sidewalls 16 of low-Ge-concentration SiGe, forming controllable lateral grooves 15. Further, the inner sidewall dielectric 16 is deposited in the lateral grooves 15 and etched to form the inner sidewalls 16, exposing the channel material. Further, source / drain regions 17 are epitaxially grown on both sides of the channel stack using methods such as metal-organic chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth, or combinations thereof.

[0069] Next, as Figures 13 to 14 As shown, the channel sacrificial layer 8 and the occupant sacrificial layer 6 directly below the channel stack are etched to form a trench, and a replacement gate stack is formed in the trench to complete the fabrication of the transistor structure.

[0070] In the actual manufacturing process, firstly, the channel sacrificial layer 8 and the occupancy sacrificial layer 6 directly below the channel stack can be selectively etched to release the SiGe nanowire channel and the occupancy space; then, the gate dielectric layer and the metal gate 18 are sequentially deposited in the trench formed by the release of the SiGe nanowire channel and the occupancy space formed by the release of the occupancy space, and CMP is performed to form the metal gate 18 surrounding the nanowire channel, thus completing the fabrication of the front-end transistor structure.

[0071] Next, as Figure 15 As shown, after the front-end transistor structure is completed and protected by the dielectric layer, semiconductor substrate 1 is wafer-bonded to another semiconductor substrate 1 on the upper surface of the transistor structure. After flipping, semiconductor substrate 1 is gradually removed from the back side and gradually approaches the bottom region of the transistor device structure through mechanical thinning, chemical mechanical polishing and selective etching.

[0072] Next, as Figure 16 As shown, the semiconductor layer 7 below the channel region is selectively removed, so that a bottom opening 19 is formed below the channel.

[0073] In the actual manufacturing process, the semiconductor layer 7 that does not need to be retained below the channel region is removed by selective etching, but the semiconductor layer 7 directly below the source / drain region 17 needs to be retained to avoid it being over-etched, so that the bottom opening 19 is formed below the channel.

[0074] Next, as Figures 17 to 18As shown, a dielectric layer is formed at and above the bottom opening 19, and chemically polished until the placeholder material 14 directly below the source / drain region 17 is exposed. At this point, the remaining dielectric layer at the bottom opening 19 is the first isolation portion 2; subsequently, as... Figure 19 As shown, the spacer material 14 is selectively removed, and metal is filled into the cavity formed. Excess metal is removed by chemical mechanical polishing, so that the metal is retained only in the area defined by the spacer material 14, serving as the first source / drain contact 4. Finally, as Figures 20 to 21 As shown, the back dielectric layer is deposited to form a via and the back metal interconnect is completed, thereby forming a self-aligned back contact structure connected to the source / drain region 17. At this time, the back dielectric layer outside the via is the second isolation part 3, and the metal inside the via is the second source / drain contact part 5.

[0075] To further verify the performance of the semiconductor device of the present invention, the performance of the most preferred semiconductor device in the above embodiments was tested, and the test results are as follows: Figures 22 to 25 As shown.

[0076] Figure 22 This is a diagram showing the stress recovery effect of NMOS and PMOS transistors in the semiconductor device of this invention. Figure 22 It can be seen that the semiconductor device of the present invention has tensile stress of 2.26 GPa and compressive stress of -2.86 GPa in the channel region, respectively, which is significantly recovered from the stress in the full BDI structure (BDI).

[0077] Figure 23 To compare the drive current of the semiconductor device of this invention with that of conventional devices (STD) and full BDI devices (BDI), by Figure 23 It can be seen that, compared with the full BDI structure, the NMOS and PMOS transistor driving circuits of the semiconductor device of the present invention are increased by 18% and 40%, respectively.

[0078] Figure 24 To compare the characteristics of the semiconductor device of this invention with those of typical ring array circuits of conventional devices (STD) and full BDI devices (BDI), the following is presented: Figure 24 It can be seen that, compared with STD and full BDI structures, the semiconductor device of the present invention has a higher frequency at the same voltage and lower dynamic power consumption at the same frequency.

[0079] Figure 25 To compare the characteristics of the SRAM circuits of the semiconductor device of this invention with those of conventional devices (STD) and all-BDI devices (BDI), by Figure 25 It can be seen that, compared with STD and full BDI structures, the semiconductor device of the present invention exhibits advantages in both read / write latency and read / write energy.

[0080] Thirdly, embodiments of the present invention provide an electronic device, which includes a smartphone, a personal computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank. The beneficial effects of the third aspect and its various implementations in the embodiments of the present invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0081] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that layers and regions of the desired shape can be formed using various technical means. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be effectively combined.

[0082] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, include A transistor device region, the transistor device region including a gate, a channel region and source / drain regions located on both sides of the channel region along its length; The first isolation section is located directly below the trench area; A semiconductor layer is disposed directly below the source / drain region, and the upper surface of the semiconductor layer is in direct contact with the bottom surface of the source / drain region.

2. The semiconductor device according to claim 1, characterized in that, It also includes a first source / drain contact portion, which is disposed on the back of the semiconductor device and extends vertically from the back of the semiconductor device to the lower surface of the semiconductor layer.

3. The semiconductor device according to claim 2, characterized in that, It also includes a second source / drain contact portion, which is disposed on the side of the first source / drain contact portion away from the semiconductor layer, and a second isolation portion is disposed between the second source / drain contacts.

4. The semiconductor device according to claim 2, characterized in that, The first source / drain contact portion is isolated from each other by the first isolation portion.

5. The semiconductor device according to claim 1, characterized in that, The lateral boundary of the first isolation section does not exceed the projection range of the channel area.

6. The semiconductor device according to claim 1, characterized in that, The surface of the first isolation portion near the channel region is on the same plane as the surface of the semiconductor layer near the source / drain region.

7. The semiconductor device according to claim 1, characterized in that, The two lateral sides of the first isolation portion are located on the same plane as the inner side of the semiconductor layer.

8. The semiconductor device according to claim 1, characterized in that, The thickness of the first isolation portion is greater than the thickness of the semiconductor layer.

9. The semiconductor device according to claim 1, characterized in that, The semiconductor layer is made of single-crystal silicon with a thickness of 4-30 nm.

10. The semiconductor device according to claim 1, characterized in that, The first isolation portion and the second isolation portion are one or more composite dielectric layers selected from silicon oxide, silicon nitride, silicon oxynitride, or high-k dielectric.

11. The semiconductor device according to claim 1, characterized in that, The transistor device is a gate-around transistor, and the channel region includes stacked nanosheets or nanowires.

12. A method for manufacturing a semiconductor device, characterized in that, Includes the following steps: Provide semiconductor substrates; Along the direction perpendicular to the thickness of the semiconductor substrate, a site sacrificial layer, a semiconductor layer, and multiple sets of alternately stacked channel sacrificial layers and channel layers are epitaxially grown sequentially, and fins are patterned. This forms a false grid layer and an outer wall; Selectively remove the sacrificial layer beneath the source / drain region and fill the resulting cavity with a spacer material; The fin stack is etched to form a channel stack, and source / drain regions are epitaxially grown on both sides of the channel stack; Etching the channel sacrificial layer and the occupant sacrificial layer below the channel stack forms a trench, and a replacement gate stack is formed in the trench to complete the fabrication of the transistor structure; The semiconductor substrate is wafer-bonded to another semiconductor substrate on the upper surface of the transistor structure. After flipping, the semiconductor substrate is thinned down to the surface of the placer material. Selectively remove the semiconductor layer below the channel region to create a bottom opening below the channel; A dielectric layer is formed above the bottom opening and polished until the placeholder material is exposed; Selectively remove the spacer material and fill the resulting cavity with metal; A back dielectric layer is deposited to form vias and complete the back metal interconnect.

13. The manufacturing method according to claim 12, characterized in that, When selectively removing the sacrificial layer below the source / drain region, isotropic etching is used, and the etching time is controlled to release only the sacrificial layer below the source / drain region.

14. The manufacturing method according to claim 12, characterized in that, When etching the fin stack to form a channel stack, only multiple sets of alternately stacked channel sacrificial layers and channel layers in the source / drain regions are removed, while the semiconductor layer below the source / drain regions is retained.

15. The manufacturing method according to claim 12, characterized in that, When selectively removing the semiconductor layer below the channel region, the semiconductor layer below the source / drain region must be retained.

16. The manufacturing method according to claim 12, characterized in that, When filling the formed cavity with metal, the metal is kept only within the area defined by the placeholder material.

17. The manufacturing method according to claim 12, characterized in that, The placeholder material includes any one of silicon oxide, silicon nitride, silicon carbonitride, or silicon carbide.

18. An electronic device, characterized in that, Includes the semiconductor device according to any one of claims 1-11; The electronic devices include smartphones, personal computers, tablets, artificial intelligence devices, wearable devices, or power banks.

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