P-gan power device structure and method of manufacturing the same

Abstract

The application discloses a P-GaN power device structure and a manufacturing method thereof. The method comprises the following steps: sequentially forming a channel layer, a barrier layer and a gate structure on the surface of a substrate; using a first processing process to perform first processing on the exposed surface of the gate structure and the exposed surface of the barrier layer, the first processing process comprising a first processing stage, a second processing stage and a third processing stage which are sequentially performed; the first processing stage uses hydrogen-containing radicals to perform surface reduction and impurity removal, the second processing stage uses first nitrogen-containing radicals to perform surface defect repair, and the third processing stage uses second nitrogen-containing radicals to perform surface sealing and passivation; and forming a passivation layer covering the gate structure on the surface of the barrier layer. The application can reduce interface defects, improve film layer quality and be beneficial to improving the electrical performance of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor processing technology, and in particular to a P-GaN power device structure and its manufacturing method. Background Technology

[0002] GaN power devices possess numerous excellent characteristics, including high breakdown electric field, high electron mobility, and high temperature resistance, making them promising for a wide range of applications. Currently, the mainstream technology for commercial enhancement-mode gallium nitride transistors is the P-type gallium nitride gate enhancement-mode high electron mobility transistor (P-GaN E-HEMT). This is a GaN power device structure that achieves normally-off operation by inserting a P-type doped GaN cap layer (P-GaN gate layer) under the gate on the AlGaN / GaN heterojunction. Due to the numerous stacked film layers in its structure, reducing interface defects and improving film quality to enhance the electrical performance of GaN power devices is a crucial research topic that urgently needs to be addressed. Summary of the Invention

[0003] The purpose of this application is to overcome the above-mentioned problems in the prior art and provide a P-GaN power device structure and its manufacturing method.

[0004] To achieve the above objectives, the technical solution of this application is as follows: According to a first aspect of this application, embodiments of this application provide a method for manufacturing a P-GaN power device structure, including: Provide substrate; A channel layer, a barrier layer, a gate material layer, and a gate contact material layer are sequentially formed on the surface of the substrate. The channel layer includes a GaN layer, the barrier layer includes an AlGaN layer, the gate material layer includes a P-GaN layer, and the gate contact material layer includes a TiN layer. The gate contact material layer and the gate layer material layer are sequentially patterned and etched to form a gate contact layer and a gate layer, respectively, so as to form a gate structure including the gate layer and the gate contact layer on the surface of the barrier layer; A first processing technology is used to perform a first processing on the exposed surface of the gate structure and the exposed surface of the barrier layer. The first processing technology includes a first processing stage, a second processing stage and a third processing stage performed sequentially. The first treatment stage uses hydrogen-containing free radicals for surface reduction and impurity removal; the second treatment stage uses first nitrogen-containing free radicals for surface defect repair; and the third treatment stage uses second nitrogen-containing free radicals for surface sealing and passivation. The hydrogen-containing free radicals, the first nitrogen-containing free radicals, and the second nitrogen-containing free radicals are used sequentially in the first treatment stage, the second treatment stage, and the third treatment stage. A passivation layer is formed on the surface of the barrier layer to cover the gate structure, the passivation layer comprising a first AlN layer.

[0005] In some embodiments, the hydrogen radicals obtained are used as the hydrogen-containing radicals after exciting a first mixture of nitrogen and hydrogen and filtering out charged particles in the formed plasma.

[0006] In some embodiments, after exciting a second mixture of nitrogen and ammonia and filtering out charged particles in the resulting plasma, the resulting NH radicals, NH2 radicals, and N radicals are used as the first nitrogen-containing radicals.

[0007] In some embodiments, the resulting N radical is used as the second nitrogen-containing radical after nitrogen gas is excited and charged particles in the formed plasma are filtered out.

[0008] In some embodiments, hydrogen radicals are used in the first processing stage to process the exposed surfaces of the gate structure and the barrier layer to remove residual chlorine impurities, carbon impurities and organic impurities on the etched surfaces by reduction cleaning, and to perform pre-passivation on the treated surfaces of various materials; before performing the first processing stage, a purge gas is used for pre-purge.

[0009] In some embodiments, the exposed surfaces of the gate structure and the barrier layer are treated by using NH radicals, NH2 radicals and N radicals in the second processing stage to fill N vacancies on the treated surfaces of various materials and repair lattice damage; before the second processing stage, a first purging is performed using a purging gas.

[0010] In some embodiments, the exposed surfaces of the gate structure and the barrier layer are treated with N radicals in the third processing stage to close residual dangling bonds on the treated surfaces of various materials, suppress secondary oxidation, promote surface atomic relaxation, smooth surface unevenness, and reduce surface roughness; a second purging is performed using a purge gas before the third processing stage, and a post-purging is performed using a purge gas after the third processing stage.

[0011] In some embodiments, before forming the gate contact material layer, an interlayer material layer is further formed on the surface of the gate layer material layer. The interlayer material layer includes a second AlN layer. The gate contact material layer, the interlayer material layer, and the gate layer material layer are sequentially patterned and etched to form the gate contact layer, the interlayer, and the gate layer, respectively, so as to form a gate structure including the gate layer, the interlayer, and the gate contact layer on the surface of the barrier layer. When performing a first processing on the exposed surface of the gate structure, the processing includes processing the top surface and sidewalls of the gate contact layer, the sidewalls of the interlayer, and the sidewalls of the gate layer.

[0012] In some embodiments, during the first processing stage, the flow rate of the first mixed gas is 50 SCCM to 800 SCCM, the hydrogen flow rate accounts for 4%, the temperature is 30°C to 400°C, the pressure is 50 mTorr to 300 mTorr, the source power is 100 W to 1000 W, the bias power is 0 W, and the time is 50 s to 150 s.

[0013] In some embodiments, during the second processing stage, the ammonia flow rate is 20 SCCM to 200 SCCM, the nitrogen flow rate is 60 SCCM to 600 SCCM, the temperature is 30°C to 400°C, the pressure is 50 mTorr to 300 mTorr, the source power is 100 W to 1000 W, the bias power is 0 W, and the time is 30 s to 120 s.

[0014] In some embodiments, during the third processing stage, the nitrogen flow rate is 300 SCCM to 1000 SCCM, the temperature is 30°C to 400°C, the pressure is 50 mTorr to 300 mTorr, the source power is 50 W to 500 W, the bias power is 0 W, and the time is 30 s to 300 s.

[0015] In some embodiments, after depositing the passivation layer, the method further includes: performing annealing; and, after annealing, using a second processing technique to perform a second treatment on the surface of the passivation layer, the second processing technique using a third nitrogen-containing free radical to fill and repair the increased N vacancies on the treated surface caused by annealing.

[0016] In some embodiments, during annealing, nitrogen is used as the protective atmosphere, the temperature is 200°C to 400°C, and the holding time is 1 min to 20 min.

[0017] In some embodiments, after exciting nitrogen gas and filtering out charged particles in the formed plasma, the resulting N free radicals are used as the third nitrogen-containing free radicals; during the second treatment, the nitrogen flow rate is 40 SCCM to 60 SCCM, the temperature is 25°C to 50°C, the pressure is 80 mTorr to 120 mTorr, the source power is 50 W to 500 W, the bias power is 0 W, and the time is 30 s to 60 s.

[0018] According to a second aspect of this application, embodiments of this application also provide a P-GaN power device structure, which is obtained using the P-GaN power device structure manufacturing method provided in any of the embodiments of the first aspect above.

[0019] The embodiments of this application may have, or at least have, the following advantages: (1) By using a first processing process that includes a first processing stage, a second processing stage and a third processing stage performed sequentially, the exposed surface of the gate structure and the exposed surface of the barrier layer are segmented in a time sequence, the processing atmosphere is isolated from each other, and the processing function is progressively advanced. In the first processing stage, highly active hydrogen-containing free radicals (hydrogen free radicals) can be used to focus on reducing and removing impurities from various surfaces (the surfaces affected include: the top and sidewalls of the gate contact layer, the sidewalls of the interlayer, the sidewalls of the gate layer, and the surface of the barrier layer). This reaction removes halides such as Ti-Cl, Ga-Cl, and N-Cl that remain after etching the gate structure, completely eliminates the interface leakage trap caused by chlorine, and reacts with amorphous carbon and organic residues to remove stubborn carbon impurities on the sidewalls and temporarily passivate a large number of dangling bonds on the surface, preventing air from entering. The process involves secondary adsorption of trace amounts of oxygen to avoid premature nitriding that could interfere with subsequent precise repair procedures. In the second treatment stage, moderately active nitrogen-containing free radicals (NH radicals, NH2 radicals, and N radicals) are used to repair N vacancies, lattice dislocations, and shallow amorphous damage. This approach focuses on the interfaces of each type of damage (gate sidewalls (numerous Ga vacancies), interlayer sidewalls (high bond energy Al vacancies), and barrier layer surfaces) for adaptive repair, while also addressing the repair of nitrogen-deficient sites on the gate contact layer sidewalls. In the third treatment stage, milder nitrogen-containing free radicals (N radicals) are used for surface sealing, interface stabilization, sidewall roughness optimization, and enhancement of subsequent film adhesion. This approach can uniformly passivate remaining dangling bonds on all treated sidewalls and surfaces, stabilizing the surface state after the first two treatment stages. Therefore, by using a step-by-step isolation process, the problem of gas phase quenching between different free radicals is avoided. The graded process achieves three major functions: impurity removal, lattice repair, and interface passivation. Simultaneously, it improves the etching damage in multiple regions, including the top and sidewalls of the gate contact layer, the sidewalls of the interlayer, the sidewalls of the gate layer, and the surface of the barrier layer. This enhances the uniformity of the device's leakage current characteristics and sidewall etching morphology, thereby effectively improving the quality of each interface. It can also improve the bonding quality with the subsequently deposited passivation layer, significantly improve the gate leakage current, and enhance the device's conduction and breakdown performance.

[0020] (2) By performing annealing after depositing the passivation layer, lattice defects can be repaired and stress can be released; by using nitrogen free radicals (third nitrogen-containing free radicals) obtained by exciting nitrogen gas after annealing to perform a second treatment on the surface of the passivation layer, the N vacancies increased due to the loss of N elements caused by annealing on the treated surface can be filled, thereby achieving the repair of interface defects.

[0021] In summary, the embodiments of this application can reduce interface defects and improve film quality, thereby improving the electrical performance of P-GaN power devices.

[0022] Other advantages of this application will be described in the following detailed description. Attached Figure Description

[0023] Figure 1 This is a flowchart illustrating a preferred embodiment of a P-GaN power device structure manufacturing method provided in this application.

[0024] Figure 2 This is a schematic diagram of the structure of a substrate provided in a preferred embodiment of this application.

[0025] Figure 3 This is a schematic diagram of a structure after a buffer layer, a channel layer and a barrier layer are sequentially formed on the surface of a substrate, according to a preferred embodiment of this application.

[0026] Figure 4 This is a schematic diagram of a structure after a gate layer material layer, a sandwich material layer and a gate contact material layer are sequentially formed on the surface of a barrier layer, according to a preferred embodiment of this application.

[0027] Figure 5 This is a schematic diagram of a gate structure formed by patterning a gate contact material layer, a sandwich material layer and a gate layer material layer, according to a preferred embodiment of this application.

[0028] Figure 6 This is a schematic diagram of a structure after a passivation layer covering a gate structure is formed on the surface of a barrier layer, which is a preferred embodiment of this application.

[0029] In the figure: 10. Substrate; 11. Buffer layer; 12. Channel layer; 13. Barrier layer; 14. Gate layer material layer; 141. Gate layer; 15. Gate contact material layer; 151. Gate contact layer; 16. Sandwich material layer; 161. Sandwich; 17. Gate structure; 18. Passivation layer. Detailed Implementation

[0030] To address the issue of P-GaN power device structures having numerous stacked film layers, and in order to reduce interface defects, improve film quality, and enhance device electrical performance, this application provides a method for manufacturing a P-GaN power device structure, including: Provide substrate; A channel layer, a barrier layer, a gate material layer, and a gate contact material layer are sequentially formed on the surface of the substrate. The channel layer includes a GaN layer, the barrier layer includes an AlGaN layer, the gate material layer includes a P-GaN layer, and the gate contact material layer includes a TiN layer. The gate contact material layer and the gate layer material layer are sequentially patterned and etched to form a gate contact layer and a gate layer, respectively, so as to form a gate structure including the gate layer and the gate contact layer on the surface of the barrier layer; A first processing technology is used to perform a first processing on the exposed surface of the gate structure and the exposed surface of the barrier layer. The first processing technology includes a first processing stage, a second processing stage and a third processing stage performed sequentially. The first treatment stage uses hydrogen-containing free radicals for surface reduction and impurity removal; the second treatment stage uses first nitrogen-containing free radicals for surface defect repair; and the third treatment stage uses second nitrogen-containing free radicals for surface sealing and passivation. The hydrogen-containing free radicals, the first nitrogen-containing free radicals, and the second nitrogen-containing free radicals are used sequentially in the first treatment stage, the second treatment stage, and the third treatment stage. A passivation layer is formed on the surface of the barrier layer to cover the gate structure, the passivation layer comprising a first AlN layer.

[0031] This application embodiment performs a first process that segments the exposed surfaces of the gate structure and the barrier layer in a sequential manner, isolates the processing atmospheres, and progressively advances the processing functions. This step-by-step isolation process avoids the problem of gas phase quenching between different free radicals. The graded processing achieves three major functions: impurity removal, lattice repair, and interface passivation. It can simultaneously improve the etching damage on the surfaces of multiple regions, including the gate structure, and enhance the uniformity of the device's leakage current characteristics and the etching morphology of the gate sidewall. This effectively improves the quality of each interface, enhances the bonding quality between the barrier layer and the subsequently deposited passivation layer, significantly improves the gate leakage current, and improves the device's conduction and breakdown performance.

[0032] This application also provides a P-GaN power device structure, which is obtained using the above-described P-GaN power device structure manufacturing method.

[0033] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0034] refer to Figure 1 In a first aspect, embodiments of this application provide a method for manufacturing a P-GaN power device structure, which may sequentially include the following steps: Step S11: Provide a substrate.

[0035] refer to Figure 2 In some embodiments, a substrate 10 is used for further forming the P-GaN power device structure provided in the embodiments of this application on the substrate 10. The substrate 10 may include any suitable type of semiconductor substrate and material. For example, the substrate 10 may include a silicon (Si) substrate, a silicon carbide (SiC) substrate, or a gallium nitride (GaN) substrate, or similar materials, etc.

[0036] In some embodiments, substrate 10 may include a wafer.

[0037] Step S12: A channel layer, a barrier layer, and a gate structure are sequentially formed on the surface of the substrate.

[0038] refer to Figure 3 In some embodiments, before forming the channel layer, a deposition process, such as metal-organic chemical vapor deposition (MOCVD), can be used to deposit a buffer layer 11 on the surface of the substrate 10. The buffer layer 11 may include an AlN buffer layer (a buffer layer of AlN material) and an AlGaN buffer layer (a buffer layer of AlGaN material) deposited sequentially.

[0039] The purpose of depositing the AlN buffer layer is to address the significant lattice mismatch (approximately 17%) and thermal expansion coefficient mismatch (approximately 54%) between the Si material in the substrate and the GaN material in the channel layer, and to provide high-quality epitaxial seed crystals, suppress cracks, reduce dislocation density, and block interdiffusion between Si and GaN.

[0040] In some embodiments, a separately configured MOCVD epitaxial cavity may be used for the deposition of an AlN buffer layer.

[0041] In some embodiments, when depositing the AlN buffer layer, the temperature is 1000°C to 1100°C, preferably 1065°C, and the pressure is 50 Torr to 70 Torr, preferably 60 Torr. The flow rates of ammonia (NH3) as the nitrogen source gas, hydrogen (H2) as the carrier gas, and the flow rate of the aluminum precursor (TMAl) are kept constant.

[0042] In some embodiments, when depositing the AlN buffer layer, the first flow ratio of ammonia to hydrogen is less than 1.

[0043] In some embodiments, when depositing the AlN buffer layer, the flow ratio of ammonia to hydrogen (first flow ratio) is: ammonia:hydrogen = 6:10 to 7:10, preferably the first flow ratio is: ammonia:hydrogen = 7:10.

[0044] In some embodiments, the thickness of the AlN buffer layer is 50 nm to 400 nm.

[0045] The surface of AlN grown at high temperatures contains numerous Al dangling bonds, intrinsic N vacancies, and trace amounts of surplus Al atom clusters. Simultaneously, the high-temperature epitaxial environment generates defects from the back-diffusion precipitation of Si from the substrate. These interface defects directly lead to the formation of high-density interface states at the AlN buffer layer initiation interface, inducing dislocation climb within the epitaxial layer. Therefore, timely third-stage treatment of the deposited AlN buffer layer surface can improve interface quality.

[0046] In some embodiments, after depositing the AlN buffer layer, the Al precursor is stopped, and the temperature, pressure, and first flow ratio conditions used for depositing the AlN buffer layer are kept constant. Hydrogen gas is continuously introduced, and ammonia gas is cyclically introduced in a pulse-on-off manner to perform a third treatment on the surface of the AlN buffer layer, thereby performing in-situ pulse nitriding modification on the surface of the deposited AlN buffer layer. The pulse-on-off cyclic ammonia gas introduction refers to a pulse-cycle ventilation method in which hydrogen gas is used as the carrier gas, and under continuous hydrogen supply, ammonia gas is introduced and stopped periodically at a fixed time sequence according to the first flow ratio. The ammonia gas flow rate remains constant, and hydrogen gas is continuously introduced at a constant flow rate when ammonia gas is introduced or stopped. When ammonia gas is stopped, hydrogen gas is used for purging.

[0047] In some embodiments, during the third processing, the temperature, pressure, and ammonia and hydrogen gas with a first flow ratio are kept unchanged during the deposition of the AlN buffer layer (the epitaxial cavity is not opened throughout the process, the cavity operating conditions are not changed, and the cavity temperature, pressure, and carrier gas flow rate are kept completely consistent with the AlN growth stage throughout the process). While continuously introducing hydrogen gas at a constant flow rate, ammonia gas at a constant flow rate is cyclically introduced in a pulse on-off manner. This allows for the precise filling of N vacancies on the surface of the deposited AlN buffer layer, passivating the Al dangling bonds at the interface. Thus, by performing in-situ pulsed nitriding modification on the surface of the AlN buffer layer, the overall bonding interface between AlN and the upper film is optimized, improving interface defects from the source, reducing the initial dislocation initiation at the interface, and preventing the upward extension of initial high dislocations.

[0048] When ammonia is cyclically introduced using a pulsed on / off method, each cycle includes a nitriding stage and a purging stage. At high temperatures, a continuous flow of hydrogen carrier gas can rapidly remove the weakly desorbed free Al atoms and trace impurities from the nitriding stage during the pulsed ammonia introduction, preventing Al atom clusters from redepositing on the AlN surface. Furthermore, maintaining a constant hydrogen flow rate ensures stable pressure within the chamber, preventing drastic pressure fluctuations caused by ammonia on / off cycles and thus preventing sudden changes in AlN surface lattice stress and the creation of new vacancy defects. During the hydrogen purging stage, cutting off the ammonia supply and retaining only hydrogen carrier gas allows residual ammonia and nitriding byproducts to be quickly purged from the chamber, preventing over-nitriding due to continuous nitrogen accumulation, which can lead to lattice compressive stress and surface roughness.

[0049] In some embodiments, when ammonia is cyclically introduced in a pulse on / off manner, the cycle time of each cycle is 10s to 20s, preferably 10s.

[0050] In some embodiments, when ammonia is cyclically introduced in a pulse on / off manner, the pulse duty cycle is 60% to 70%, preferably 60%.

[0051] In some embodiments, when ammonia is cyclically introduced in a pulse on / off manner, the number of cycles is 10 to 20, preferably 15.

[0052] In one example, during the third treatment, the temperature was 1065℃, the pressure was 60 Torr, the ammonia flow rate was 7 SLM, and the hydrogen flow rate was 10 SLM. The entire process was conducted without opening the chamber or lowering the temperature, ensuring stable temperature and pressure. The specific timing was as follows: a single cycle time of 10 seconds, including 6 seconds of ammonia introduction and 4 seconds of ammonia purging time, with 15 consecutive cycles of the third treatment completed.

[0053] In some embodiments, the same epitaxial cavity used during the deposition of the AlN buffer layer can be used to epitaxially deposit an AlGaN buffer layer on the surface of the AlN buffer layer. The AlGaN buffer layer may include multiple sub-buffer layers deposited sequentially on the surface of the AlN buffer layer, with the entire stacked sub-buffer layers constituting the AlGaN buffer layer.

[0054] In some embodiments, during the deposition of the AlGaN buffer layer, the ratio of Al precursor (TMAl) to Ga precursor (TMGa) is adjusted accordingly to achieve a gradient decrease in Al content and a gradient increase in Ga content in each sub-buffer layer. That is, there is a certain step difference in Al content and Ga content between each sub-buffer layer. By depositing the AlGaN buffer layer, lattice / thermal stress can be further released, ensuring the integrity of the epitaxial layer, and the gradient decrease in Al content can further reduce dislocations, thereby improving the overall quality of the multilayer material.

[0055] In some embodiments, the number of sub-buffer layers may be 6 to 8.

[0056] In some embodiments, the thickness of the AlGaN buffer layer is 1 μm to 5 μm.

[0057] In some embodiments, the thickness of the AlGaN buffer layer can be evenly divided among the sub-buffer layers.

[0058] In some embodiments, when depositing the AlGaN buffer layer, the temperature, pressure, and ammonia and hydrogen conditions with a first flow ratio can be used in the same way as when depositing the AlN buffer layer. Specifically, when depositing the AlGaN buffer layer, the temperature can be 1000°C to 1100°C, preferably 1065°C, and the pressure can be 50 Torr to 70 Torr, preferably 60 Torr. The flow rates of the nitrogen source gas (NH3) and the carrier gas (H2), as well as the total flow rate of TMAl and TMGa, are kept constant. Only the ratio of TMAl to TMGa is adjusted to keep the growth rate of each sub-buffer layer consistent. When each sub-buffer layer grows to the target thickness, both metal sources (TMAl and TMGa) are turned off, and the main atmosphere (nitrogen source gas and carrier gas) remains unchanged.

[0059] In one example, six sub-buffer layers are formed sequentially on the surface of the AlN buffer layer: the first layer (bottommost sub-buffer layer), the second layer, the third layer, the fourth layer, the fifth layer, and the sixth layer (topmost sub-buffer layer). If we assume that the sum of the Al and Ga content percentages in the sub-buffer layers is 100%, then the first sub-buffer layer can have an Al content percentage of 98%, corresponding to a Ga content percentage of 2% (extremely high TMAl flow rate, extremely low TMGa flow rate); the second sub-buffer layer can have an Al content percentage of 80%, corresponding to a Ga content percentage of 20% (TMAl flow rate slightly decreased); the third sub-buffer layer can have an Al content percentage of 60%, corresponding to a Ga content percentage of 40% (TMAl flow rate accounts for more than half); the fourth sub-buffer layer can have an Al content percentage of 40%, corresponding to a Ga content percentage of 60% (TMGa flow rate accounts for more than half); the fifth sub-buffer layer can have an Al content percentage of 20%, corresponding to a Ga content percentage of 80% (high TMGa flow rate, low TMAl flow rate); and the sixth sub-buffer layer can have an Al content percentage of 2%, corresponding to a Ga content percentage of 98% (almost entirely TMGa). However, it is not limited to these definitions.

[0060] In some embodiments, after each sub-buffer layer is formed on the surface of the AlN buffer layer, the substrate 10 with the deposited sub-buffer layer can be transferred to another independently configured processing chamber for a fourth processing of the surface of each formed sub-buffer layer. A wafer cassette can be used for vacuum wafer transfer between the epitaxial chamber and the processing chamber, eliminating atmospheric exposure, preventing the introduction of additional oxygen impurities, and eliminating the risk of process contamination. This avoids the gas used in the fourth processing from mixing into the epitaxial chamber and causing disturbances that could interfere with epitaxial growth kinetics, thereby enabling precise control of the AlGaN epitaxial composition.

[0061] In this process, after each sub-buffer layer is formed, ammonia and nitrogen gas with a second flow ratio are introduced into the processing chamber through an independently configured gas branch (separate from the main gas path of the epitaxial cavity). The ammonia and nitrogen gas are excited within the processing chamber, causing ionization and forming a plasma containing hydrogen and nitrogen free radicals. Then, charged particles contained in the ammonia and nitrogen plasma are filtered out. The resulting hydrogen and nitrogen free radicals are used to perform a fourth treatment on the surface of each sub-buffer layer. This selectively reduces the primary oxides (Al-O and Ga-O) on the surface of each sub-buffer layer, eliminating secondary interface dislocations induced by the primary oxides, and immediately performing in-situ nitriding and bonding, achieving layer-by-layer interface repair. This reduces interface defects in the AlGaN buffer layer and improves the film quality.

[0062] In some embodiments, during the fourth treatment of each sub-buffer layer, the second flow ratio between ammonia and nitrogen is less than 0.5. This ensures that the flow rate of ammonia is always less than that of nitrogen, so that a high nitrogen partial pressure is provided by sufficient nitrogen in the system to perform immediate in-situ nitriding and sealing of the exposed Al and Ga dangling bonds after reduction, thereby completely eliminating secondary oxidation at the interface.

[0063] In some embodiments, when the surface of each sub-buffer layer is subjected to a fourth treatment in a direction away from the substrate 10, the second flow ratio of ammonia to nitrogen decreases sequentially. That is, when the surface of each sub-buffer layer is subjected to the fourth treatment respectively, the second flow ratio is different for each sub-buffer layer and decreases sequentially.

[0064] In some embodiments, hydrogen radicals generated after ammonia dissociation are used to selectively reduce the native oxides of Ga (Ga-O) and Al (Al-O) present on the surface of the sub-buffer layers. Since Al-O and Ga-O have different reduction capabilities, with Ga-O being more easily reduced, the reduction intensity of hydrogen radicals can be constrained by increasing the nitrogen flow rate to a greater than the ammonia flow rate and gradually decreasing the ammonia-to-nitrogen flow rate ratio with each subsequent treatment. This prevents lattice corrosion and surface roughening caused by excessive surface reduction on the Ga side. Simultaneously, sufficient nitrogen partial pressure improves the efficiency of surface nitriding. By using nitrogen radicals generated after nitrogen dissociation, rapid in-situ nitriding can be performed after Ga-O reduction to seal dangling bonds and prevent secondary oxidation at the interface.

[0065] For example, when the six sub-buffer layers in the above example are subjected to the fourth treatment (a total of 6 times), the ammonia flow rate can be 1800 SCCM, 1550 SCCM, 1280 SCCM, 1000 SCCM, 720 SCCM, and 450 SCCM respectively, and the nitrogen flow rate can be 4000 SCCM, 3690 SCCM, 3200 SCCM, 2780 SCCM, 2250 SCCM, and 1800 SCCM respectively. Alternatively, the ammonia to nitrogen flow rate ratio can be 0.45, 0.42, 0.40, 0.36, 0.32, and 0.25 respectively. Specifically, during the fourth treatment of the first sub-buffer layer, to address the Al-O dominance, the NH3 flow rate was moderately increased to break the high-bond-energy Al-O. During the fourth treatment of the second sub-buffer layer, to address the reduced Al content, the NH3 flow rate was simultaneously slightly reduced while the N2 flow rate was slightly increased. During the fourth treatment of the third sub-buffer layer, to address the coexistence of Al-O and Ga-O, the NH3 flow rate was moderately reduced to achieve a compromise in reduction intensity. During the fourth treatment of the fourth sub-buffer layer, to address the increased Ga content and the ease of Ga-O reduction, the NH3 flow rate was further reduced to prevent over-etching. During the fourth treatment of the fifth sub-buffer layer, to address the high Ga system, the NH3 flow rate was strictly controlled to suppress the etching coarsening of the Ga-N lattice. During the fourth treatment of the sixth sub-buffer layer, to address the almost pure Ga side, an extremely low NH3 flow rate and a sufficient N2 flow rate were used to rapidly nitride the Ga dangling bonds.

[0066] In summary, a small flow rate of NH3 is responsible for precise oxygen removal and reduction, while a large flow rate of N2 is responsible for risk control, bond sealing, and prevention of secondary oxidation. The combination of the two and strict control of NH3 / N2 < 0.5 can not only thoroughly remove oxidation defects at the interface of each sub-buffer layer, but also protect the AlGaN lattice from damage by hydrogen free radicals throughout the process, achieving clean passivation of each layer interface.

[0067] In some embodiments, when performing the fourth process, the temperature is 50°C to 600°C, the pressure is 10 mTorr to 10 Torr, and the time is 30 s to 180 s.

[0068] By performing a fourth process on each sub-buffer layer, oxygen present in the AlGaN buffer layer can be effectively removed, and each sub-buffer layer can have a flat surface without delamination etching pits. This also significantly reduces the overall dislocation density of the AlGaN buffer layer, thus enabling the fabrication of high-quality AlGaN buffer layers.

[0069] refer to Figure 3In some embodiments, a deposition process, such as MOCVD, can be used to sequentially deposit a GaN channel layer 12 and an AlGaN barrier layer 13 on the surface of the fourth-processed AlGaN buffer layer (buffer layer 11).

[0070] In some embodiments, the thickness of the GaN channel layer 12 is 200 nm to 1000 nm.

[0071] In some embodiments, the thickness of the AlGaN barrier layer 13 is 100 nm to 400 nm.

[0072] refer to Figure 4 In some embodiments, an MOCVD process can be used to further epitaxially form a gate material layer 14 and a gate contact material layer 15 on the surface of the barrier layer 13.

[0073] In some embodiments, before forming the gate contact material layer 15, a sandwich material layer 16 may be epitaxially formed on the surface of the gate layer material layer 14, and then the gate contact material layer 15 may be epitaxially formed on the surface of the sandwich material layer 16.

[0074] In some embodiments, the gate layer material layer 14 includes a P-GaN layer (Mg-doped P-type GaN, with a Mg doping concentration of approximately 2 × 10⁻⁶). 19 atm / cm 3 ~3×10 19 atm / cm 3 ).

[0075] In some embodiments, the interlayer material layer 16 includes an AlN layer (a second AlN layer).

[0076] In some embodiments, the gate contact material layer 15 includes a TiN layer.

[0077] In some embodiments, the thickness of the gate material layer 14 is 30 nm to 200 nm.

[0078] In some embodiments, the thickness of the interlayer material layer 16 is 1 nm to 10 nm.

[0079] In some embodiments, the thickness of the gate contact material layer 15 is 50 nm to 200 nm.

[0080] refer to Figure 5In some embodiments, photolithography and etching processes can be used to pattern the gate contact material layer 15 to form a TiN gate contact layer 151 (TiN gate contact layer), and using the gate contact layer 151 as a hard mask, the underlying gate layer material layer 14 can be etched to form a P-GaN gate layer 141 (P-GaN gate layer), and a gate structure 17 including the gate layer 141 and the gate contact layer 151 can be formed on the surface of the barrier layer 13.

[0081] When a sandwich material layer 16 is formed on the surface of the gate material layer 14, the sandwich material layer 16 and the gate material layer 14 below can be etched sequentially using the formed gate contact layer 151 as a hard mask to form an AlN material sandwich layer 161 (AlN sandwich) and a P-GaN material gate layer 141 (P-GaN gate layer), thereby forming a gate structure 17 including the gate layer 141, the sandwich layer 161 and the gate contact layer 151 on the surface of the barrier layer 13 (the following will be described using the gate structure 17 including the gate layer 141, the sandwich layer 161 and the gate contact layer 151 as an example).

[0082] When fabricating the gate structure 17, the gate contact layer 151 serves as both a mask and a gate contact layer. Thus, after etching, the TiN hard mask does not need to be stripped, and it can be directly retained as the gate contact layer 151, avoiding secondary damage and process redundancy. Without an interlayer, the gate contact layer can also serve as the in-situ passivation layer for the gate layer, eliminating the need for an additional passivation process. This achieves mask function reuse, simplifying the process flow while improving the gate layer's resistance to contamination and oxidation (existing gate processes require additional mask stripping and P-GaN surface passivation after P-GaN gate layer etching, which easily causes sidewall roughness and introduces impurities, reducing device yield).

[0083] The sandwich layer 161 can passivate the dangling bonds on the surface of the gate layer 141 of the P-GaN material, suppress surface traps, and solve the problems of GaN current collapse and dynamic on-resistance (R0). on This addresses the degradation issue and allows the use of the interlayer material layer 16 as the etching endpoint layer when patterning the gate contact layer 151, thereby reducing the damage to the gate layer 141 during etching of the gate contact layer 151.

[0084] The TiN gate contact layer 151, together with the AlN interlayer 161 and the P-GaN gate layer 141, forms a rectified Schottky contact, characterized by a high barrier, low reverse leakage current, and suppression of gate leakage. Combined with gate layer 141, it enables E-mode constant off (depletion of 2DEG at zero gate voltage), exhibiting lower reverse leakage current and greater high-temperature stability compared to traditional Ni / Au gates. Furthermore, the TiN material in the gate contact layer 151 allows for fine-tuning of the threshold voltage.

[0085] In some embodiments, when patterning etching to form the gate structure 17, a photoresist mask can first be formed on the surface of the gate contact material layer 15 using a photolithography process. Then, the surface of the gate contact material layer 15 is plasma etched through the photoresist mask to form the gate contact layer 151. After removing the photoresist mask, the lower interlayer material layer 16 and gate layer material layer 14 are sequentially plasma etched using the gate contact layer 151 as a hard mask to form the AlN material interlayer 161 and the P-GaN material gate layer 141.

[0086] In some embodiments, etching the gate contact material layer 15 may include a main etching step and an over-etching step. The main etching step may use Cl2 (flow rate 20%–50%), BCl3 (flow rate less than 10%), Ar (flow rate 30%–40%), and N2 (flow rate approximately 10%) as etching process gases. The total gas flow rate is 50–500 SCCM, the source power is 100 W–500 W, the bias power is 50 W–100 W, the pressure is 5 mTorr–30 mTorr, and the temperature is 10°C–60°C. The over-etching step uses a low-energy plasma atmosphere replenished by a nitrogen source, and may use a mixture of BCl3 (flow rate 30–50 SCCM), Cl2 (flow rate 6–10 SCCM), N2 (flow rate 40–60 SCCM), and NH3 (flow rate 10–20 SCCM) as the etching process gas. The source power is 10W to 100W, the bias power is 2W to 50W, the pressure is 30mTorr to 200mTorr, and the temperature is 10℃ to 60℃. The power of the over-etching step is less than that of the main etching step. When etching the gate contact material layer 15, the interlayer material layer 16 is used as the etching endpoint layer, and the interlayer material layer 16 can be patterned through the over-etching step to form the interlayer 161.

[0087] In some other embodiments, a combination of Cl2, BCl3, N2 and Ar can be used as the etching process gas used in the over-etching step when etching the gate contact material layer 15.

[0088] In some embodiments, after the gate contact layer 151 is formed, the sidewalls of the TiN material gate contact layer 151 can be subjected to a fifth treatment to reduce the sidewall roughness. This fifth treatment can be performed using a nitrogen-containing hydrogen gas introduced into a plasma treatment chamber.

[0089] In some embodiments, the nitrogen-containing hydrogen gas used in the fifth process may include NH3 (ammonia).

[0090] In some embodiments, the flow rate of NH3 used in the fifth process is 50 SCCM to 150 SCCM.

[0091] In some embodiments, during the fifth process, a rare gas (e.g., Ar) may be introduced in addition to the introduction of a nitrogen-containing hydrogen gas (e.g., NH3) to assist in the fifth process. The flow rate of the rare gas may be the same as the flow rate of the nitrogen-containing hydrogen gas.

[0092] In some embodiments, when performing the fifth process, the source power is 100W to 300W, the bias power is 0W to 15W, the pressure is 50mTorr to 200mTorr, the temperature is 100℃ to 300℃, and the time is 15s to 120s.

[0093] In some embodiments, etching the gate material layer 14 may include a main etching step and an over-etching step. The main etching step may use Cl2 (flow rate 60-80 SCCM), BCl3 (flow rate 15-25 SCCM), N2 (flow rate 10-20 SCCM, where N2 acts as sidewall nitriding passivation, suppressing lateral etching and forming steep vertical sidewalls), and Ar (10-20 SCCM) as etching process gases. The source power is 300-400 W, the bias power is 15-25 W, the pressure is 15-20 mTorr, and the temperature is 20-30°C. When the remaining thickness of the gate material layer 14 is 5-10 nm, the over-etching step begins. The over-etching step may use BCl3 (flow rate 25-35 SCCM) and SF6 (flow rate 8-15 SCCM) as etching process gases. The source power is 300W–400W, the bias power is 0W–15W, the pressure is 30mTorr–40mTorr, the temperature is 20℃–40℃, and the over-etching amount is 5%–20%. AlF is generated on the surface of the AlGaN material in barrier layer 13 by reacting with F radicals from SF6. x Passivating the surface of barrier layer 13 can inhibit etching, thereby improving the etching selectivity. (In existing gate etching processes, damage to the AlGaN barrier layer is difficult to control: the etching selectivity between the P-GaN gate layer and the AlGaN barrier layer is low (usually below 10:1). During the etching process, the chemical corrosion caused by the physical bombardment of high-energy ions easily acts on the AlGaN barrier layer, leading to lattice distortion, increased dislocations, and increased defect state density on the AlGaN surface (usually above 5 × 10⁻⁶). 11 cm -2 (The above) severely affects the concentration and mobility of 2DEG, thereby reducing the conduction and breakdown performance of the device.

[0094] In existing gate etching processes, N-vacancy and lattice defects are prominent issues. During dry etching, nitrogen in the P-GaN layer is prone to thermal desorption, forming a large number of N-vacancy defects (typically 3 × 10⁻⁶). 18 cm -3 The above-mentioned factors lead to a decrease in the stability of P-type doping in the P-GaN layer, resulting in severe threshold voltage drift (typically above 0.5V) and affecting the long-term reliability of the device. This application addresses this issue by adding nitrogen to the etching process gas, particularly during over-etching of the gate contact material layer 15, to construct a low-energy plasma etching system with nitrogen source replenishment. By precisely controlling the etching parameters, an ultra-high etching selectivity ratio between P-GaN and AlGaN is achieved, while simultaneously suppressing the generation of N-vacancy defects. This solves the problem of balancing damage and defects in existing processes.

[0095] Step S13: Using a first processing technology, perform a first processing on the exposed surface of the gate structure and the exposed surface of the barrier layer.

[0096] In this embodiment of the application, although the aforementioned corresponding measures are taken to improve etching damage during the patterning of the gate structure, over-etching of the barrier layer 13 during etching of the gate material layer 14 may still cause defects at the interface of the barrier layer 13, thereby deteriorating the bonding quality between the subsequently deposited passivation layer and the barrier layer 13. Furthermore, during etching, ions still bombard the P-GaN sidewalls, causing a large number of N vacancies, lattice dislocations, dangling bonds, and shallow amorphous damage layers in the P-GaN lattice. Chlorine (Cl) impurities (chlorine-based etching products Ti-Cl, Ga-Cl, N-Cl) adsorbed on the P-GaN sidewalls increase leakage current and reduce ohmic contact. In addition, annealing is usually required after the gate structure is formed, but this may also cause the loss of N elements in P-GaN and AlGaN, and increase surface carbon (C). Therefore, after the gate structure 17 is formed, the exposed surface of the gate structure 17 and the exposed surface of the barrier layer 13 can be treated by using a first processing process to improve the above-mentioned problems.

[0097] The first treatment may target the top surface and sidewalls of the gate contact layer 151 of TiN material, the sidewalls of the interlayer 161 of AlN material, the sidewalls of the gate layer 141 of P-GaN material, and the large exposed surface (the surface to be treated) of the barrier layer 13 of AlGaN material. These areas all suffer from ion bombardment lattice damage and residual C / Cl etching byproducts. Therefore, the first treatment is necessary to simultaneously address surface etching damage and impurities of different chemical bond types in these various materials, achieving both impurity removal and defect repair.

[0098] In some embodiments, the first processing step includes a pre-purging stage, a first processing stage, a first purging stage, a second processing stage, a second purging stage, a third processing stage, and a post-purging stage performed sequentially. The first processing stage uses hydrogen-containing free radicals for surface reduction and impurity removal; the second processing stage uses first nitrogen-containing free radicals for surface defect repair; and the third processing stage uses second nitrogen-containing free radicals for surface bonding passivation. The hydrogen-containing free radicals, first nitrogen-containing free radicals, and second nitrogen-containing free radicals are used sequentially in the first, second, and third processing stages to avoid mixing. The pre-purging stage, the first purging stage, the second purging stage, and the post-purging stage are used to purge the cavity with purge gases to remove the original atmosphere and impurities from the cavity, so as to facilitate the corresponding first, second, and third processing stages and the switching of processing gases.

[0099] In some embodiments, the purging gas may include nitrogen.

[0100] In some embodiments, a pre-purging stage is first performed. Nitrogen gas is introduced into the processing chamber for pre-purging to remove moisture, residual oxygen, and impurities, preparing the chamber for the first processing stage.

[0101] Then, the nitrogen gas used for purging is stopped, and the first treatment stage is carried out. By exciting the first mixed gas (FG forming gas (4%H2+96%N2)) composed of nitrogen and hydrogen, and filtering out charged particles in the formed plasma, the surface to be treated is subjected to surface reduction and impurity removal treatment with the obtained hydrogen free radicals (containing hydrogen free radicals). This process removes residual chlorine impurities, carbon impurities, and organic impurities from the etched surface through reduction cleaning, and is suitable for pre-passivation of various materials.

[0102] The first treatment stage relies solely on the dissociation of the first mixed gas to generate highly reactive H radicals, without the involvement of ammonia, focusing solely on reduction and cleaning. Its functions include: (1) Removal of chlorine residue: H free radicals react with halides such as Ti-Cl, Ga-Cl, and N-Cl that are left by etching to generate volatile HCl gas, which is directly carried away by the airflow in the cavity, thus completely eliminating the interface leakage current trap caused by chlorine.

[0103] (2) Removal of carbon residues: H free radicals react with amorphous carbon and organic residues to generate CH4 gas phase desorption, which removes stubborn carbon impurities from the sidewalls.

[0104] (3) Pre-passivation: H free radicals temporarily passivate a large number of dangling bonds on the surface, preventing the secondary adsorption of trace oxygen in the air, while avoiding lattice nitriding repair, thus avoiding interference with the subsequent precise repair process using ammonia.

[0105] Next, the flow of the first mixed gas is stopped, and the first purging stage is performed. By introducing nitrogen into the processing chamber for the first purging, the residual hydrogen in the chamber is purged to prevent hydrogen residue from interfering with the next process (second processing stage).

[0106] Afterwards, the nitrogen gas used for purging is stopped, and the second processing stage is carried out. By exciting a second mixed gas composed of nitrogen and ammonia and filtering out charged particles from the resulting plasma, the resulting NH radicals, NH2 radicals, and N radicals (first nitrogen-containing radicals) are used to treat the surface to be processed. This is suitable for repairing N vacancies, lattice dislocations, and shallow amorphous damage on surfaces of various materials. Using the first nitrogen-containing radicals, the focus is on repairing damaged interfaces such as the sidewalls of the gate layer 141 of P-GaN material (numerous Ga vacancies), the sidewalls of the interlayer 161 of AlN material (high bond energy Al vacancies), and the surface of the barrier layer 13 of AlGaN material. Simultaneously, the repair of nitrogen-deficient sites on the sidewalls of the gate contact layer 151 of TiN material is also addressed.

[0107] The process involves introducing low-concentration ammonia gas diluted with nitrogen, which dissociates to generate highly reactive nitrogen-containing free radicals such as NH radicals, NH2 radicals, and N radicals. The absence of excess H radicals mitigates the risk of Mg acceptor passivation in P-GaN. Its functions include: (1) Filling N vacancies: Nitrogen free radicals can directionally replenish the N atoms lost by the etching ions bombardment, and repair the native N vacancies on the surface of P-GaN, AlN and AlGaN.

[0108] (2) Repairing lattice damage: Highly active amino free radicals can penetrate shallow amorphous damage layers, reconstruct broken Ga-N and Al-N covalent bonds, and repair lattice misalignments.

[0109] (3) Differentiated adaptation to sidewalls of various materials: The amino radical activity is moderate, which can repair the hard lattice damage of AlN with high Al composition, without over-nitriding the P-GaN sidewalls and affecting the gate electrical characteristics.

[0110] Next, the flow of the second mixed gas is stopped, and the second purging stage is performed. Nitrogen gas is introduced into the processing chamber for the second purging to remove residual ammonia and prevent ammonia residue from interfering with the next process (third processing stage).

[0111] Then, the nitrogen gas used for purging is stopped, and the third processing stage is carried out. By exciting only nitrogen gas and filtering out charged particles in the formed plasma, the surface to be treated is subjected to plasma annealing passivation treatment with the obtained N free radicals (second nitrogen-containing free radicals) to adapt to the surface of various materials to perform surface sealing, stabilize the interface, optimize the sidewall roughness, and improve the subsequent film adhesion.

[0112] In this process, nitrogen radicals generated by the dissociation of high-purity nitrogen gas are used to treat all exposed sidewalls and surfaces, uniformly passivating remaining dangling bonds and stabilizing the surface state after the first two treatment stages. The functions include: (1) Closing residual dangling bonds: Using the N free radicals dissociated from high-purity nitrogen, the Ga, Al, and Ti dangling bonds remaining on the surface after the first two stages of treatment are sealed, further reducing the interface state density.

[0113] (2) Suppress secondary oxidation: High concentration of nitrogen increases the nitrogen partial pressure in the cavity, isolates trace amounts of oxygen and water vapor in the cavity, and prevents the regeneration of Al-O, Ga-O, and Ti-O oxides on the surface of the fresh nitride after repair.

[0114] (3) Surface morphology micro-optimization: Using mild nitrogen free radicals, surface atoms are relaxed, the micro-bumps and dents of the sidewalls are smoothed, and the sidewall roughness is further optimized without changing the overall etching morphology of the sidewalls.

[0115] Finally, nitrogen gas is continuously introduced for post-purging. By introducing nitrogen gas into the processing chamber, residual precursors and reaction byproducts (residual ammonia, hydrogen-containing byproducts, etc.) are completely purged from the chamber, preventing residual gases from affecting the subsequent epitaxial deposition process of the passivation layer of AlN material.

[0116] The first processing step does not break the vacuum, has no bias voltage on the substrate, and is free from ion bombardment.

[0117] Conventional surface treatment using a single gas after etching has the following drawbacks: (1) The etching damage and impurity chemical bond types of the surfaces of various materials (TiN / AlN / P-GaN / AlGaN) are different, and a single atmosphere cannot simultaneously take into account impurity removal and defect repair.

[0118] (2) Although the H radicals generated by hydrogen alone have a strong ability to remove Cl / C, the excess H will penetrate into P-GaN, passivate the Mg acceptor, and increase the gate turn-on voltage. When nitriding is performed by ammonia alone, it has a good effect on repairing vacancies, but its removal efficiency for Ti-Cl and organic carbon pollutants is low.

[0119] (3) Due to the lack of zoned matching of free radical ratio in a single atmosphere, if Cl and C remain on the sidewall, it will cause high-density traps at the interface, resulting in problems such as increased gate leakage current and discrete threshold voltage of the device.

[0120] However, if N2 / H2 forming gas, NH3, and N2 are simultaneously introduced into the processing chamber, H radicals, amino radicals, and nitrogen radicals within the chamber will interfere with each other: active H radicals will directly consume highly active NH radicals / NH2 radicals, causing cleaning radicals and lattice repair radicals to cancel each other out. Simultaneously, the overall atmospheric environment is complex, making it impossible to specifically control the reduction and nitriding intensities, and the following problems will arise: (1) Excessive hydrogen reduction: Excessive diffusion of H radicals into the interior of P-GaN will passivate the Mg acceptor and deteriorate the P-type gate conductivity.

[0121] (2) Insufficient nitriding repair: Amino free radicals are consumed, resulting in incomplete repair of shallow amorphous damage to AlN interlayers and AlGaN barrier layers with high Al content.

[0122] (3) Chaotic reaction interface: Impurity removal, vacancy repair and surface passivation occur simultaneously, making it impossible to achieve precise separation of processes, and the consistency of treatment of high aspect ratio sidewalls (narrow AlN interlayer sidewalls) deteriorates.

[0123] To address the aforementioned shortcomings, this application's embodiments employ a three-stage processing approach: time-sequential segmentation, atmosphere isolation, and progressive functional advancement. The entire process is conducted in a vacuum without cavity breakage or atmospheric exposure. Free radicals are gradually switched, sequentially performing hydrogen-based reduction for impurity removal, amino lattice defect repair, and pure nitrogen surface sealing and passivation. Each stage has an independent atmosphere and independent reaction function, with no cross-consumption of free radicals. This approach addresses multi-interface damage after etching by repairing it step by step, adapting to the differentiated repair needs of the treated surfaces (sidewalls) of four different materials: TiN, AlN, P-GaN, and AlGaN. This results in an overall improvement in device performance, significantly outperforming existing single-atmosphere processing schemes or simultaneous ternary gas-purifying processing schemes (which suffer from inherent defects such as mutual consumption of free radicals, continuous action of hydrogen components damaging P-GaN doping, and impurities being easily encapsulated by the nitride layer).

[0124] In this process, by isolating the atmosphere stepwise, the gas-phase quenching loss of H radicals and amino radicals is eliminated, greatly improving the removal efficiency of C and Cl etching residues on the surface and eliminating the source of interface leakage current traps. During the defect repair stage, by completely cutting off the pure hydrogen source, the problems of P-GaN acceptor passivation and lattice N desorption caused by hydrogen atom diffusion are avoided. This significantly reduces the overall surface N vacancy density, allowing for thorough repair of shallow ion-bombarded amorphous damage layers and a significant reduction in the micro-roughness of sidewalls with various materials. This also significantly improves the uniformity and continuity of step coverage during AlN passivation layer deposition. Using the method described in this application, the reverse gate leakage current and ohmic contact resistance of the P-GaN gate layer in the finished device can be significantly reduced, and the inter-wafer threshold voltage dispersion can be significantly improved, resulting in a substantial improvement in device batch consistency and long-term reliability.

[0125] Therefore, by using a step-by-step isolation process, the problem of gas phase quenching between different free radicals is avoided. The graded process achieves three major functions: impurity removal, lattice repair, and interface passivation. Simultaneously, it improves the etching damage in multiple regions, including the top and sidewalls of the gate contact layer, the sidewalls of the interlayer, the sidewalls of the gate layer, and the surface of the barrier layer. This enhances the uniformity of the device's leakage current characteristics and sidewall etching morphology, thereby effectively improving the quality of each interface. It can also improve the bonding quality with the subsequently deposited passivation layer, significantly improve the gate leakage current, and enhance the device's conduction and breakdown performance.

[0126] In some embodiments, during the first processing stage, the flow rate of the first mixed gas is 50 SCCM to 800 SCCM, the flow rate of hydrogen accounts for 4%, the flow rate of nitrogen accounts for 96%, the temperature is 30°C to 400°C, the pressure is 50 mTorr to 300 mTorr, the source power is 100 W to 1000 W, the bias power is 0 W, and the time is 50 s to 150 s.

[0127] In some embodiments, during the second processing stage, the ammonia flow rate is 20 SCCM to 200 SCCM, the nitrogen flow rate is 60 SCCM to 600 SCCM, the temperature is 30°C to 400°C, the pressure is 50 mTorr to 300 mTorr, the source power is 100 W to 1000 W, the bias power is 0 W, and the time is 30 s to 120 s.

[0128] In some embodiments, during the third processing stage, the nitrogen flow rate is 300 SCCM to 1000 SCCM, the temperature is 30°C to 400°C, the pressure is 50 mTorr to 300 mTorr, the source power is 50 W to 500 W, the bias power is 0 W, and the time is 30 s to 300 s.

[0129] In some embodiments, during the pre-purging stage, the flow rate of the purging gas (nitrogen) is 50 SCCM to 800 SCCM, the temperature is 30°C to 400°C, the pressure is 100 mTorr to 500 mTorr, and the time is 3 min to 7 min.

[0130] In some embodiments, during the first purging stage, the flow rate of the purging gas (nitrogen) is 50 SCCM to 800 SCCM, the temperature is 30°C to 400°C, the pressure is 50 mTorr to 300 mTorr, and the time is 20 s to 80 s.

[0131] In some embodiments, during the second purging stage, the flow rate of the purging gas (nitrogen) is 50 SCCM to 800 SCCM, the temperature is 30°C to 400°C, the pressure is 50 mTorr to 300 mTorr, and the time is 20 s to 80 s.

[0132] In some embodiments, during the post-purging stage, the flow rate of the purging gas (nitrogen) is 500 SCCM to 2000 SCCM, the temperature is 30°C to 400°C, the pressure is 190 mTorr to 210 mTorr, and the time is 10 s to 90 s.

[0133] Step S14: Form a passivation layer on the surface of the barrier layer to cover the gate structure.

[0134] refer to Figure 6 In some embodiments, a deposition process is used to form a passivation layer 18 on the surface of the barrier layer 13, and the deposited passivation layer 18 also covers the exposed surface of the gate structure 17.

[0135] In some embodiments, the passivation layer 18 includes a first AlN layer (a passivation layer 18 of AlN material). The passivation layer 18 of AlN material covering the gate structure 17 can be formed on the surface of the barrier layer 13 using a low-temperature plasma-enhanced atomic layer deposition (PE-ALD) process.

[0136] By performing a first treatment on the exposed surfaces of the barrier layer 13 and the gate structure 17, interface defects are eliminated, and the bonding quality between the passivation layer 18 and the barrier layer 13 is improved. Therefore, a high-quality AlN passivation layer film can be prepared, which significantly improves the gate leakage current.

[0137] In some embodiments, the thickness of the passivation layer 18 is 1 nm to 10 nm.

[0138] Step S15: Perform annealing.

[0139] After depositing the passivation layer 18, annealing is performed to repair lattice defects and release stress.

[0140] In some embodiments, nitrogen may be used as a protective atmosphere, and annealing may be performed under a nitrogen atmosphere. During annealing, the temperature is 200°C to 400°C, and the holding time is 1 min to 20 min.

[0141] Step S16: Use the second processing technology to perform a second treatment on the surface of the passivation layer.

[0142] Considering that annealing may cause the loss of N elements inside the passivation layer 18 of AlN material, a second processing process can be used after annealing, and a third nitrogen-containing free radical can be used to perform a second treatment on the surface of the passivation layer 18 to fill the increased N vacancies on the treated surface caused by annealing, thereby repairing the interface defects.

[0143] In some embodiments, during the second treatment, nitrogen free radicals (third nitrogen-containing free radicals) obtained by exciting nitrogen gas and filtering out charged particles in the resulting plasma are used to treat the surface of the passivation layer 18. Through the nitriding effect of the second treatment, nitrogen can be replenished by filling N vacancies, improving the surface roughness of the passivation layer 18 and increasing the threshold voltage value (V) of AlN / TiN. th Adjustments are made to the stability of the system.

[0144] In some embodiments, during the second treatment, the nitrogen flow rate is 40 SCCM to 60 SCCM, the temperature is 25°C to 50°C, the pressure is 80 mTorr to 120 mTorr, the source power is 50 W to 500 W, the bias power is 0 W, and the time is 30 s to 60 s.

[0145] In a second aspect, embodiments of this application also provide a P-GaN power device structure, which is obtained using the P-GaN power device structure manufacturing method provided in any of the embodiments of the first aspect above.

[0146] refer to Figure 6 In some embodiments, the P-GaN power device structure is disposed on a substrate 10, including a buffer layer 11, a channel layer 12 and a barrier layer 13 sequentially stacked on the surface of the substrate 10, a gate structure 17 disposed on the surface of the barrier layer 13, and a passivation layer 18 disposed on the surface of the barrier layer 13 and covering the exposed surface of the gate structure 17.

[0147] In some embodiments, the buffer layer 11 may include an AlN buffer layer and an AlGaN buffer layer deposited sequentially, with the AlN buffer layer disposed on the surface of the substrate 10 and the channel layer 12 disposed on the surface of the AlGaN buffer layer.

[0148] In some embodiments, the gate structure 17 may include a gate layer 141 and a gate contact layer 151, forming a gate stack structure.

[0149] In some embodiments, the gate structure 17 may include a gate layer 141, a sandwich layer 161 and a gate contact layer 151, forming a gate stack structure.

[0150] Specifically, by using a first processing process that includes a first processing stage, a second processing stage, and a third processing stage performed sequentially, the exposed surfaces of the gate structure 17 and the barrier layer 13 are segmented in a time sequence, the processing atmospheres are isolated from each other, and the processing functions are progressively advanced. The first processing achieves three major functions: impurity removal, lattice repair, and interface passivation through hierarchical processing. This simultaneously improves the etching damage in multiple regions, including the top and sidewalls of the gate contact layer 151, the sidewalls of the interlayer 161, the sidewalls of the gate layer 141, and the surface of the barrier layer 13. It also improves the uniformity of the device's leakage current characteristics and the sidewall etching morphology, thereby effectively improving the quality of each interface. This enhances the bonding quality with the subsequently deposited passivation layer 18, significantly improves the gate leakage current, and improves the device's conduction and breakdown performance.

[0151] By performing a second processing step after depositing the passivation layer 18 and annealing, the surface of the passivation layer 18 is treated with a second processing step. This process can fill the N vacancies that are increased due to the loss of N elements caused by annealing on the treated surface, thereby repairing the interface defects.

[0152] In a third aspect, embodiments of this application also provide a plasma processing apparatus for performing the P-GaN power device structure manufacturing method corresponding to the above embodiments to form the P-GaN power device structure corresponding to the above embodiments. The plasma processing apparatus includes inductively coupled plasma (ICP) processing equipment or capacitively coupled plasma (CCP) processing equipment, etc.

[0153] In other aspects, embodiments of this application also provide an electronic device, including a P-GaN power device structure obtained using the P-GaN power device structure manufacturing method of the above embodiments. The electronic device can be a storage device, mobile phone, computer, tablet computer, electronic instrument, television, artificial intelligence device, etc.

[0154] In summary, the embodiments of this application utilize a first processing technology comprising a first processing stage, a second processing stage, and a third processing stage performed sequentially. This first processing involves time-sequential segmentation, mutual isolation of processing atmospheres, and progressive advancement of processing functions on the exposed surfaces of the gate structure 17 and the barrier layer 13. By implementing step-by-step isolation processing, the problem of gas phase quenching between different free radicals can be avoided. Through graded processing, three major functions—impurity removal, lattice repair, and interface passivation—can be achieved. This simultaneously improves the etching damage on the surfaces of multiple regions, including the gate structure 17, and enhances the uniformity of device leakage current characteristics and gate sidewall etching morphology. Consequently, the quality of each interface is effectively improved, enhancing the bonding quality between the barrier layer 13 and the subsequently deposited passivation layer 18. This significantly improves the gate leakage current, thereby improving the electrical performance of the P-GaN power device by enhancing the film quality.

[0155] The above are merely preferred embodiments of this application. These embodiments are not intended to limit the scope of protection of this application. Therefore, any equivalent changes made based on the description and drawings of this application should also be included within the scope of protection of this application.

Claims

1. A method for manufacturing a P-GaN power device structure, characterized in that, include: Provide substrate; A channel layer, a barrier layer, a gate material layer, and a gate contact material layer are sequentially formed on the surface of the substrate. The channel layer includes a GaN layer, the barrier layer includes an AlGaN layer, the gate material layer includes a P-GaN layer, and the gate contact material layer includes a TiN layer. The gate contact material layer and the gate layer material layer are sequentially patterned and etched to form a gate contact layer and a gate layer, respectively, so as to form a gate structure including the gate layer and the gate contact layer on the surface of the barrier layer; A first processing technology is used to perform a first processing on the exposed surface of the gate structure and the exposed surface of the barrier layer. The first processing technology includes a first processing stage, a second processing stage and a third processing stage performed sequentially. The first treatment stage uses hydrogen-containing free radicals for surface reduction and impurity removal; the second treatment stage uses first nitrogen-containing free radicals for surface defect repair; and the third treatment stage uses second nitrogen-containing free radicals for surface sealing and passivation. The hydrogen-containing free radicals, the first nitrogen-containing free radicals, and the second nitrogen-containing free radicals are used sequentially in the first treatment stage, the second treatment stage, and the third treatment stage. A passivation layer is formed on the surface of the barrier layer to cover the gate structure, the passivation layer comprising a first AlN layer.

2. The method for manufacturing a P-GaN power device structure according to claim 1, characterized in that, The hydrogen radicals obtained by exciting a first mixture of nitrogen and hydrogen and filtering out charged particles in the resulting plasma are used as the hydrogen-containing radicals; and / or, the NH radicals, NH2 radicals, and N radicals obtained by exciting a second mixture of nitrogen and ammonia and filtering out charged particles in the resulting plasma are used as the first nitrogen-containing radicals; and / or, the N radicals obtained by exciting nitrogen and filtering out charged particles in the resulting plasma are used as the second nitrogen-containing radicals.

3. The method for manufacturing a P-GaN power device structure according to claim 2, characterized in that, By using hydrogen radicals in the first processing stage, the exposed surfaces of the gate structure and the barrier layer are processed to remove residual chlorine impurities, carbon impurities and organic impurities on the etched surfaces through reduction cleaning, and to perform pre-passivation on the surfaces to be processed for various materials; before performing the first processing stage, a purge gas is used for pre-purge.

4. The method for manufacturing a P-GaN power device structure according to claim 2, characterized in that, The exposed surfaces of the gate structure and the barrier layer are treated by using NH radicals, NH2 radicals and N radicals in the second processing stage to fill N vacancies on the treated surfaces of various materials and repair lattice damage; before the second processing stage, a first purging is performed using a purging gas.

5. The method for manufacturing a P-GaN power device structure according to claim 2, characterized in that, By using N free radicals in the third processing stage to treat the exposed surfaces of the gate structure and the barrier layer, residual dangling bonds are sealed on the treated surfaces of various materials, secondary oxidation is suppressed, surface atomic relaxation is promoted, and surface unevenness is smoothed to reduce surface roughness. Before the third processing stage, a second purging is performed using a purge gas, and after the third processing stage, a post-purging is performed using a purge gas.

6. The method for manufacturing a P-GaN power device structure according to claim 1, characterized in that, Before forming the gate contact material layer, an interlayer material layer is formed on the surface of the gate layer material layer. The interlayer material layer includes a second AlN layer. The gate contact material layer, the interlayer material layer, and the gate layer material layer are sequentially patterned and etched to form the gate contact layer, the interlayer, and the gate layer, respectively, so as to form a gate structure including the gate layer, the interlayer, and the gate contact layer on the surface of the barrier layer. When performing the first processing on the exposed surface of the gate structure, the top surface and sidewalls of the gate contact layer, the sidewalls of the interlayer, and the sidewalls of the gate layer are processed.

7. The method for manufacturing a P-GaN power device structure according to claim 2, characterized in that, During the first treatment stage, the flow rate of the first mixed gas is 50 SCCM to 800 SCCM, the hydrogen flow rate accounts for 4%, the temperature is 30°C to 400°C, the pressure is 50 mTorr to 300 mTorr, the source power is 100 W to 1000 W, the bias power is 0 W, and the time is 50 s to 150 s; and / or, during the second treatment stage, the ammonia flow rate is 20 SCCM to 200 SCCM, and the nitrogen flow rate is 60 SCCM to 600 SCCM. The temperature is 30℃~400℃, the pressure is 50mTorr~300mTorr, the source power is 100W~1000W, the bias power is 0W, and the time is 30s~120s; and / or, during the third treatment stage, the nitrogen flow rate is 300SCCM~1000SCCM, the temperature is 30℃~400℃, the pressure is 50mTorr~300mTorr, the source power is 50W~500W, the bias power is 0W, and the time is 30s~300s.

8. The method for manufacturing a P-GaN power device structure according to claim 1, characterized in that, After depositing the passivation layer, the process further includes: performing annealing; and, after annealing, using a second processing technique to perform a second treatment on the surface of the passivation layer, wherein the second processing technique uses a third nitrogen-containing free radical to fill and repair the increased N vacancies on the treated surface caused by annealing.

9. The method for manufacturing a P-GaN power device structure according to claim 8, characterized in that, During annealing, nitrogen is used as the protective atmosphere, the temperature is 200℃~400℃, and the holding time is 1min~20min; and / or, by exciting nitrogen and filtering out charged particles in the formed plasma, the resulting N free radicals are used as the third nitrogen-containing free radicals; during the second treatment, the nitrogen flow rate is 40SCCM~60SCCM, the temperature is 25℃~50℃, the pressure is 80mTorr~120mTorr, the source power is 50W~500W, the bias power is 0W, and the time is 30s~60s.

10. A P-GaN power device structure, characterized in that, It is obtained using the P-GaN power device structure fabrication method as described in any one of claims 1-9.

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