Power semiconductor device

Abstract

The application provides a power semiconductor device, for example comprising: a substrate, an epitaxial layer, a plurality of first doped regions, a plurality of second doped regions and a gate. The epitaxial layer is disposed on one side of the substrate; the plurality of first doped regions are formed on a part of the epitaxial layer and located on the side of the epitaxial layer away from the substrate, the epitaxial layer is configured with a trench recessed between two adjacent first doped regions, each first doped region has a plurality of fin structures protruding relative to the bottom surface of the trench, and the plurality of fin structures comprise a first fin structure closest to the trench; each second doped region is formed on a part of the corresponding first doped region and is spaced apart from the trench by the first fin structure in the first doped region, each second doped region has a first end surface away from the substrate, and the first fin structure has a second end surface away from the substrate, the first end surface is lower than the second end surface; the gate is disposed on the side of the epitaxial layer away from the substrate. The embodiment of the application can increase the gate control capability of the device and improve the gate oxide reliability.

Description

Technical Field

[0001] This invention relates to the field of power electronic device technology, and more particularly to a power semiconductor device. Background Technology

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC) have become ideal choices for high-voltage, high-temperature, high-frequency, high-power, and low-switching-loss power electronic devices due to their advantages such as high critical breakdown electric field, high thermal conductivity, and high electron saturation velocity. SiC planar DMOSFETs (Double-diffused MOSFETs) have relatively simple processes and high reliability, but the SiC / SiO2 interface has a high interface state density, resulting in low channel mobility and weak gate control capability. Typically, channel mobility needs to be improved by reducing the gate oxide thickness or increasing the gate voltage, but these measures severely affect the gate oxide reliability of SiC planar DMOSFETs, leading to increased leakage current and degraded device performance. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a power semiconductor device to increase the device's gate control capability and improve gate oxide reliability.

[0004] Specifically, an embodiment of the present invention provides a power semiconductor device, including, for example, a substrate, an epitaxial layer, a plurality of first doped regions, a plurality of second doped regions, and a gate; the epitaxial layer is disposed on the substrate and has a first conductivity type; the plurality of first doped regions are formed on a portion of the epitaxial layer and located on the side of the epitaxial layer opposite to the substrate, wherein the plurality of first doped regions have a second conductivity type different from the first conductivity type; the epitaxial layer is configured with trenches recessed between two adjacent first doped regions; each first doped region has a plurality of fin structures protruding relative to the bottom surface of the trench along a first direction, and the plurality of fin structures includes a first fin structure closest to the trench; the first direction is the direction from the substrate to the epitaxial layer; each second doped region... The plurality of second doped regions are formed in a portion of a corresponding first doped region and spaced apart from the trench by the first fin structure within the corresponding first doped region. The plurality of second doped regions have the first conductivity type. Each second doped region has a first end face away from the substrate, and the first fin structure located between the second doped region and the trench has a second end face away from the substrate. The first end face is lower than the second end face in the first direction. The gate is disposed on the side of the epitaxial layer away from the substrate. The gate portion extends into the trench and crosses the first fin structure of each of the two adjacent first doped regions and extends to cover a portion of the first end face of the second doped region located on the side of the first fin structure away from the trench.

[0005] Furthermore, another power semiconductor device provided in this embodiment of the invention includes, for example, a substrate, an epitaxial layer, a first doped region, a second doped region, and a gate; the epitaxial layer is disposed on the substrate and has a first conductivity type; the first doped region is formed on the side of the epitaxial layer away from the substrate, wherein the first doped region has a second conductivity type different from the first conductivity type and has a first fin structure and a second fin structure spaced apart from each other; the second doped region is formed within the first doped region and located between the first fin structure and the second fin structure, the second doped region has the first conductivity type and has a first end face away from the substrate, the first fin structure has a second end face away from the substrate, the first end face is lower than the second end face in a first direction from the substrate to the epitaxial layer, the epitaxial layer has a first surface away from the substrate and located outside the first doped region, the first surface is lower than the second end face in the first direction; the gate is disposed on the side of the epitaxial layer away from the substrate, the gate extends from the first surface across the first fin structure and covers a portion of the first end face of the second doped region.

[0006] The above embodiments of the present invention can have the following beneficial effects: By setting the first fin structure to form a channel, the gate not only covers the second end face (or top face) of the first fin structure, but also wraps around both sides of the first fin structure. This can significantly increase the contact area between the gate and the channel, making the gate's electric field control capability of the channel stronger, thereby enabling more effective regulation of the carrier concentration and current in the channel, that is, increasing the gate control capability. In this way, the gate oxide layer thickness can be increased, which helps to reduce the peak electric field at the corner of the gate oxide layer, and the gate oxide reliability is improved. Furthermore, due to the increased gate control capability, even with a shorter channel length, the short-channel effect can be effectively suppressed to reduce leakage current, the channel utilization is greatly improved, power consumption is low, and even the cell density per unit area can be increased to achieve high integration. Attached Figure Description

[0007] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0008] Figure 1 This is a partial structural cross-sectional schematic diagram of a power semiconductor device provided in an embodiment of the present invention.

[0009] Figure 2 This is a partial structural cross-sectional schematic diagram of another power semiconductor device provided in an embodiment of the present invention.

[0010] Figure 3 This is a partial structural cross-sectional schematic diagram of another power semiconductor device provided in an embodiment of the present invention.

[0011] Figures 4A to 4G This is a partial structural cross-sectional view of a method for fabricating a power semiconductor device according to an embodiment of the present invention.

[0012] [Explanation of Key Figure Markings]

[0013] 11-Substrate; 13-Epiaxial layer; 130-First doped region; 1300-Second doped region; 1302-Third doped region; TR-Trench; 13S-Bottom surface of trench; 13T-First surface of epitaxial layer; 130B-Bottom surface of first doped region; 131a-First fin structure; 131b-Second fin structure; 1300S-First end face; 131S-Second end face; 131E-End face of third doped region; 15-Gate; 151-Gate oxide layer; 153 - Gate electrode layer; H - Gate oxide layer thickness; B1 - First direction; 17 - Interlayer dielectric layer; 19a - First electrode layer; 19b - Second electrode layer; CH - Contact hole; 200 - Patterned masking layer; 201 - First dielectric layer; 202 - Second dielectric layer; SAML - Self-aligned masking layer; ML1 - Patterned self-aligned masking layer; 300 - Patterned masking layer; 301 - Silicon oxide layer; 302 - Polysilicon layer; 303 - Silicon oxide layer; 300H - Opening. Detailed Implementation

[0014] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0015] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0016] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0017] It should also be noted that the division of multiple embodiments in this invention is only for the convenience of description and should not constitute a special limitation. Features in various embodiments can be combined and referenced in each other without contradiction.

[0018] See Figure 1 The present invention provides a power semiconductor device, which includes, for example, a substrate 11, an epitaxial layer 13, a plurality of first doped regions 130, a plurality of second doped regions 1300, and a gate 15.

[0019] The epitaxial layer 13 is disposed on the substrate 11 and has a first conductivity type. For example, the substrate 11 is an N-type SiC substrate, and its doping concentration is, for example, in the range of 1E19 cm⁻¹. -3 -1E20cm -3 .

[0020] The epitaxial layer 13 is an N-type SiC epitaxial layer, and its doping concentration is, for example, in the range of 1E16cm. -3 -1E17cm -3 .

[0021] The plurality of first doped regions 130 are formed in a portion of the epitaxial layer 13 and located on the side of the epitaxial layer 13 facing away from the substrate 11, and the plurality of first doped regions 130 have a second conductivity type different from the first conductivity type. For example, Figure 1 The diagram shows two adjacent first doped regions 130, which are P-type doped regions with doping concentrations, for example, in the range 1E16cm. -3 -1E18cm -3 Furthermore, from Figure 1 It can be understood that the epitaxial layer 13 is configured with a trench TR recessed between two adjacent first doped regions 130. Each first doped region 130 has multiple fin structures, such as 131a and 131b, protruding relative to the bottom surface 13S of the trench TR along a first direction B1. The multiple fin structures, such as 131a and 131b, include the first fin structure 131a closest to the trench TR. The first direction B1 is the direction from the substrate 11 to the epitaxial layer 13. It is worth noting that the multiple fin structures of each first doped region 130 can be understood as meaning that the number of fin structures within a single first doped region 130 is greater than one in the cross-sectional structure of the power semiconductor device. For example... Figure 1 Each first doped region 130 has three fin structures: two first fin structures 131a and one second fin structure 131b. It is understood that in some embodiments... Figure 1 The two first fin structures 131a located in the same first doped region 130 can actually be two strip-shaped fin structures spaced apart from each other, or two different parts of the same annular fin structure.

[0022] As described above, each second doped region 1300 is formed within a portion of a corresponding first doped region 130 and is separated from the trench TR within the corresponding first doped region 130 by the first fin structure 131a. The plurality of second doped regions 1300 have a first conductivity type, such as an N-type doped region, and their doping concentration is, for example, in the range of 1E19cm. -3 -1E20cm -3 Furthermore, each second doped region 1300 has a first end face 1300S facing away from the substrate 11, and the first fin structure 131a located between the second doped region 1300 and the trench TR has a second end face 131S facing away from the substrate 11, wherein the first end face 1300S is lower than the second end face 131S in the first direction B1.

[0023] The gate 15 is disposed on the side of the epitaxial layer 13 facing away from the substrate 11. The gate 15 partially extends into the trench TR and crosses the first fin structure 131a of each of two adjacent first doped regions 130, extending to cover a portion of the first end face 1300S of the second doped region 1300 located on the side of the first fin structure 131a away from the trench TR. Furthermore, the gate 15 is, for example, a multilayer structure, which includes, for example, a gate oxide layer 151 and a gate electrode layer 153. The gate electrode layer 153 is, for example, a polysilicon layer, and the gate oxide layer 151 is, for example, located on the side of the gate electrode layer 153 facing the substrate 11.

[0024] As can be seen from the above, in this embodiment, by setting the first fin structure 131a to form a channel, the gate 15 not only covers the second end face 131S (or top face) of the first fin structure 131a, but also wraps around both sides of the first fin structure 131a. This can significantly increase the contact area between the gate 15 and the channel, making the gate 15 more capable of controlling the electric field of the channel, thereby more effectively regulating the carrier concentration and current in the channel, that is, increasing the gate control capability. In this way, the thickness of the gate oxide layer 151 in the gate 15 can be increased, which helps to reduce the peak electric field at the corner of the gate oxide layer 151, and improves the gate oxide reliability. Furthermore, due to the increased gate control capability, even with a shorter channel length, the short-channel effect can be effectively suppressed to reduce leakage current, the channel utilization is greatly improved, the power consumption is low, and even the cell density per unit area can be increased to achieve high integration.

[0025] In some embodiments, see Figure 1Each of the plurality of fin structures in the first doped region 130 includes a second fin structure 131b, the second fin structure 131b being located on the side of the first fin structure 131a away from the trench TR and spaced apart from the first fin structure 131a by the second doped region 1300. Furthermore, the power semiconductor device, for example, is configured with a plurality of third doped regions 1302. Figure 1 The diagram illustrates two third doped regions 1302 located within two adjacent first doped regions 130 as an illustrative example. Each third doped region 1302 is formed as a part of a corresponding first doped region 130, and the second fin structure 131b of the corresponding first doped region 130 is a component of the third doped region 1302. The plurality of third doped regions 1302 have a second conductivity type, and the doping concentration of each third doped region 1302 is higher than the doping concentration of the corresponding first doped region 130. For example, each third doped region 1302 is a P-type doped region with a doping concentration, for example, in the range 1E18 cm⁻¹. -3 -1E20cm -3 The provision of the third doped region 1302 facilitates the provision of stable electrical connections, such as ohmic contacts, to ensure that current can flow into or out of the device efficiently.

[0026] In some embodiments, see Figure 1 Each of two adjacent first doped regions 130 has a bottom surface 130B facing the substrate 11, and the bottom surface 13S of the trench TR is higher than the bottom surface 130B of each first doped region 130 in the first direction B1. In this way, a shallow trench structure is formed in the JFET (Junction Field-Effect Transistor) region, which is easy to fabricate and has advantages such as strong process capability.

[0027] In some embodiments, see Figure 1 The first end face 1300S of the second doped region 1300 is flush with the bottom face 13S of the trench TR in the first direction B1. This structural design simplifies the device fabrication process.

[0028] In some embodiments, see Figure 2 Each of two adjacent first doped regions 130 has a bottom surface 130B facing the substrate 11, and the bottom surface 13S of the trench TR is flush with the bottom surface 130B of each first doped region 130 in the first direction B1 (e.g., Figure 2(as shown), or below the bottom surface 130B of each first doped region 130 (e.g., a few nanometers or tens of nanometers, such as 30 nanometers, below the bottom surface 130B). In this way, a deep trench structure is formed in the JFET region, resulting in a higher effective channel density and stronger gate control capability, further improving device performance; however, compared to the aforementioned case of forming a shallow trench structure in the JFET region, additional etching steps are usually required.

[0029] In some embodiments, see Figure 1 The thickness H of the gate oxide layer 151 in the gate 15 is in the range of 30nm-300nm. That is, due to the increased gate control capability, the adjustable range of the gate oxide layer 151 is large, thereby reducing the peak electric field at the corner of the gate oxide layer 151 located at the bottom of the trench TR.

[0030] In some embodiments, see Figure 3 The power semiconductor device further includes, for example, an interlayer dielectric layer 17, a first electrode layer 19a, and a second electrode layer 19b. The interlayer dielectric layer 17 is disposed on the side of the gate 15 facing away from the substrate 11 and has a contact hole CH to expose a portion of the second doped region 1300 and a third doped region 1302 of each of two adjacent first doped regions 130. The material of the interlayer dielectric layer 17 is, for example, a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. The first electrode layer 19a is disposed on the side of the interlayer dielectric layer 17 facing away from the substrate 11 and extends into the contact hole CH to form an electrical contact, such as an ohmic contact, with the second doped region 1300 and the third doped region 1302 of each of the two adjacent first doped regions 130. The first electrode layer 19a is, for example, composed of a titanium (Ti) layer, a nickel (Ni) layer, and an aluminum (Al) layer sequentially stacked along the first direction B1. The second electrode layer 19b is disposed on the side of the substrate 11 away from the epitaxial layer 13 and forms an electrical contact, such as an ohmic contact, with the substrate 11. The second electrode layer 19b is, for example, composed of a silver layer and a Ti layer and a Ni layer that are alternately stacked between the silver layer and the substrate 11.

[0031] Please see again. Figure 1Using a single first doped region 130 as the subject of description, an embodiment of the present invention provides a power semiconductor device, for example, comprising: a substrate 11, an epitaxial layer 13, a first doped region 130, a second doped region 1300, and a gate 15. The epitaxial layer 13 is disposed on the substrate 11 and has a first conductivity type, such as N-type. The first doped region 130 is formed on the side of the epitaxial layer 13 facing away from the substrate 11, and has a second conductivity type different from the first conductivity type, such as P-type, and has a first fin structure 131a and a second fin structure 131b spaced apart from each other. The second doped region 1300 is formed within the first doped region 130 and located between the first fin structure 131a and the second fin structure 131b, and has the first conductivity type, such as N-type, and has a first end face 1300S facing away from the substrate 11. The first fin structure 130a... 1a has a second end face 131S facing away from the substrate 11, and a first end face 1300S is lower than the second end face 131S in a first direction B1 from the substrate 11 to the epitaxial layer 13. The epitaxial layer 13 has a first surface 13T (or upper surface) facing away from the substrate 11 and located outside the first doped region 130. The first surface 13T is lower than the second end face 131S in the first direction B1. The gate 15 is disposed on the side of the epitaxial layer 13 facing away from the substrate 11. The gate 15 extends from the first surface 13T across the first fin structure 131a and covers a portion of the first end face 1300S of the second doped region 1300.

[0032] As can be seen from the above, in this embodiment, by setting the first fin structure 131a to form a channel, the gate 15 not only covers the second end face 131S (or top face) of the first fin structure 131a, but also wraps around both sides of the first fin structure 131a. This can significantly increase the contact area between the gate 15 and the channel, making the gate 15 more capable of controlling the electric field of the channel, thereby more effectively adjusting the carrier concentration and current in the channel, that is, increasing the gate control capability. In this way, the thickness of the gate oxide layer in the gate 15 can be increased, which helps to reduce the peak electric field at the corner of the gate oxide layer 151, and the gate oxide reliability is improved. Furthermore, due to the increased gate control capability, even with a shorter channel length, the short-channel effect can be effectively suppressed to reduce leakage current, the channel utilization is greatly improved, the power consumption is low, and even the cell density per unit area can be increased to achieve high integration.

[0033] In some embodiments, see Figure 1The power semiconductor device is configured with a third doped region 1302, which is formed within the first doped region 130, and the second fin structure 131b is a component of the third doped region 1302. The third doped region 1302 has a second conductivity type, such as P-type, and the doping concentration of the third doped region 1302 is higher than that of the first doped region 130. The arrangement of the third doped region 1302 facilitates the provision of stable electrical connections, such as ohmic contacts, to ensure that current can flow into or out of the device efficiently.

[0034] In some embodiments, see Figure 1 The end face 131E of the third doped region 1302 facing away from the substrate 11 is higher than the first end face 1300S of the second doped region 1300 in the first direction B1. This structure mainly depends on the fabrication process steps of the power semiconductor device.

[0035] In some embodiments, see Figure 1 The first surface 13T of the epitaxial layer 13 is flush with the first end face 1300S of the second doped region 1300. This structural design simplifies the fabrication process of power semiconductor devices.

[0036] In some embodiments, see Figure 1 The first surface 13T of the epitaxial layer 13 is higher than the bottom surface 130B of the first doped region 130 facing the substrate 11 in the first direction B1. In this way, a shallow trench structure is formed in the JFET (Junction Field-Effect Transistor) region, which is easy to fabricate and has the advantages of strong process capability.

[0037] In some embodiments, see Figure 2 The first surface 13T of the epitaxial layer 13 is flush with or lower than the bottom surface 130B of the first doped region 130 facing the substrate 11 in the first direction B1 (e.g., a few nanometers or tens of nanometers, such as 30 nanometers, lower than the bottom surface 130B). This forms a deep trench structure in the JFET region, resulting in a higher effective channel density and stronger gate control capability, further improving device performance. However, compared to the aforementioned case of forming a shallow trench structure in the JFET region, additional etching steps are typically required.

[0038] In some embodiments, see Figure 1The gate 15 includes a stacked gate oxide layer 151 and a gate electrode layer 153, with the gate oxide layer 151 located on the side of the gate electrode layer 153 facing the substrate 11. The thickness H of the gate oxide layer 151 is in the range of 30nm-300nm. That is, due to the increased gate control capability, the adjustable range of the gate oxide layer 151 is large, thereby reducing the peak electric field at the corner of the gate oxide layer 151 located at the bottom of the trench TR.

[0039] In some embodiments, see Figure 3 The power semiconductor device further includes, for example, an interlayer dielectric layer 17, a first electrode layer 19a, and a second electrode layer 19b. The interlayer dielectric layer 17 is disposed on the side of the gate 15 facing away from the substrate 11 and has a contact hole CH to expose a portion of the second doped region 1300 and the second fin structure 131b. The material of the interlayer dielectric layer 17 is, for example, a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride. The first electrode layer 19a is disposed on the side of the interlayer dielectric layer 17 facing away from the substrate 11 and extends into the contact hole CH to form an electrical contact, such as an ohmic contact, with the second doped region 1300 and the second fin structure 131b. The first electrode layer 19a is, for example, composed of a titanium (Ti) layer, a nickel (Ni) layer, and an aluminum (Al) layer sequentially stacked along the first direction B1. The second electrode layer 19b is disposed on the side of the substrate 11 away from the epitaxial layer 13 and forms an electrical contact, such as an ohmic contact, with the substrate 11. The second electrode layer 19b is, for example, composed of a silver layer and a Ti layer and a Ni layer that are alternately stacked between the silver layer and the substrate 11.

[0040] To facilitate a clearer understanding of the power semiconductor devices provided in the embodiments of the present invention, the following will be combined with... Figures 4A to 4G Brief description Figure 1 The method for fabricating the power semiconductor device shown may specifically include the following steps.

[0041] First, provide Figure 4AThe initial semiconductor structure shown includes a substrate 11, an epitaxial layer 13 formed on one side of the substrate 11 and having a plurality of first doped regions 130, and a patterned masking layer 200 located on the side of the epitaxial layer 13 opposite to the substrate 11. The substrate 11 is, for example, an N-type SiC substrate, the epitaxial layer 13 is, for example, an N-type SiC epitaxial layer, the plurality of first doped regions 130 are, for example, a plurality of P-type doped regions, and the patterned masking layer 200 exposes the plurality of first doped regions 130. The patterned masking layer 200 includes, for example, a first dielectric layer 201 and a second dielectric layer 202 stacked together. The material of the first dielectric layer 201 is, for example, silicon dioxide, and the material of the second dielectric layer 202 is, for example, silicon oxynitride, silicon oxide, or silicon nitride. Figure 4A The specific implementation method of the initial semiconductor structure shown can refer to the relevant steps in the existing mature SiC planar DMOSFET fabrication process, so it will not be repeated here.

[0042] Next, as Figure 4B As shown, in Figure 4A A self-aligned masking layer SAML, such as a silicon oxide layer, is formed on the initial semiconductor structure shown, with a thickness, for example, in the range of 0.8 μm to 3 μm; the self-aligned masking layer SAML is located on the side of the epitaxial layer 13 opposite to the substrate 11 and covers the patterned masking layer 200 and the plurality of first doped regions 130.

[0043] Subsequently, photoresist is spin-coated, and the self-aligned masking layer (SAML) is patterned by exposure and dry etching (e.g., plasma etching) to obtain the desired result. Figure 4C The patterned self-aligned masking layer ML1 shown is used to expose the region in each first doped region 130 for forming the second doped region 1300; then the exposed region in each first doped region 130 is implanted with N+ type heavy doped ions at a high temperature, such as 500 degrees Celsius, to obtain a plurality of second doped regions 1300.

[0044] Next, the patterned masking layer 200 is removed using wet or dry etching to obtain... Figure 4D The structure shown retains the patterned self-aligned masking layer ML1; wherein the thickness of the retained patterned self-aligned masking layer ML1 is, for example, in the range of 0.3 μm-0.8 μm.

[0045] Then, using the retained patterned self-aligned masking layer ML1 as a mask, the upper surface of the epitaxial layer 13 facing away from the substrate 11 is dry-etched to a certain depth, which does not exceed the depth of the second doped region 1300, thereby forming a trench TR recessed between two adjacent first doped regions 130 in the epitaxial layer 13, such as... Figure 4E As shown. From Figure 4E It can be seen that the epitaxial layer 13 has a first surface 13T (or upper surface) that is away from the substrate 11 and located outside each first doped region 130, and the bottom surface 13S of the trench TR is a part of the first surface 13T of the epitaxial layer 13.

[0046] Next, wet etching is used to remove... Figure 4E The patterned self-aligned masking layer ML1 shown is obtained Figure 4F The structure shown; from Figure 4E It can be seen that each first doped region 130 has a plurality of fin structures protruding relative to the bottom surface 13S of the trench TR, and the plurality of fin structures include, for example, a first fin structure 131a closest to the trench TR and a second fin structure 131b spaced apart from the first fin structure 131a via the second doped region 1300.

[0047] After that, Figure 4F A patterned masking layer 300 is formed on the structure shown; the patterned masking layer 300 covers the first surface 13T, each second doped region 1300, and each first fin structure 131a of the epitaxial layer 13 on the side of the epitaxial layer 13 facing away from the substrate 11, and exposes each second fin structure 131b through openings 300H; then, the region where the exposed second fin structure 131b is located is subjected to P+ type heavy doping (e.g., aluminum ion implantation) at a high temperature, for example, 500 degrees Celsius. Figure 4G As shown, a third doped region 1302 is obtained within each of the first doped regions 130; subsequently, the patterned masking layer 300 is removed, and high-temperature (e.g., around 1800 degrees Celsius) ion activation is performed. The patterned masking layer 300 is, for example, a... Figure 4G The three-layer structure shown consists of a silicon oxide layer 301, a polycrystalline silicon layer 302, and a silicon oxide layer 303 stacked sequentially. Of course, the polycrystalline silicon layer 302 can also be replaced by a silicon oxide layer, a silicon nitride layer, or a silicon nitride layer.

[0048] Then, an initial gate oxide layer and an initial gate electrode layer are sequentially formed on the side of the epitaxial layer 13 facing away from the substrate 11, and the initial gate oxide layer and the initial gate electrode layer are etched to obtain the gate oxide layer 151 and the gate electrode layer 153 of the gate 15, and to expose a portion of the first doped region 1300 and the third doped region 1302 within each first doped region 130, thereby enabling the fabrication of... Figure 1 The power semiconductor device shown.

[0049] Furthermore, it is worth mentioning that, in order to ensure that the first surface 13 of the epitaxial layer 13 or the bottom surface 13S of the trench TR is flush with or lower than the bottom surface 130B of the first doped region 130 facing the substrate 11, it is possible to achieve this by fabricating... Figure 4F Following the structure shown, a deeper etching is performed on the first surface 13T of the epitaxial layer 13 to facilitate the fabrication of... Figure 2 The power semiconductor device shown.

[0050] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A power semiconductor device, characterized in that, include: Substrate; An epitaxial layer disposed on the substrate and having a first conductivity type; A plurality of first doped regions are formed in a portion of the epitaxial layer and located on the side of the epitaxial layer opposite to the substrate, wherein the plurality of first doped regions have a second conductivity type different from the first conductivity type, the epitaxial layer is configured with a trench recessed between two adjacent first doped regions, each first doped region has a plurality of fin structures protruding relative to the bottom surface of the trench along a first direction, and the plurality of fin structures includes a first fin structure closest to the trench, the first direction being the direction from the substrate to the epitaxial layer; A plurality of second doped regions, each second doped region being formed in part of a corresponding first doped region and spaced apart from the trench by the first fin structure within the corresponding first doped region, the plurality of second doped regions having the first conductivity type, each second doped region having a first end face facing away from the substrate, and the first fin structure located between the second doped region and the trench having a second end face facing away from the substrate, the first end face being lower than the second end face in the first direction; as well as A gate is disposed on the side of the epitaxial layer away from the substrate. The gate portion extends into the trench and across the first fin structure of each of the two adjacent first doped regions and extends to cover a portion of the first end face of the second doped region located on the side of the first fin structure away from the trench.

2. The power semiconductor device according to claim 1, characterized in that, The plurality of fin structures in each of the first doped regions includes a second fin structure located on the side of the first fin structure away from the trench and spaced apart from the first fin structure by the second doped region; the power semiconductor device is configured with a plurality of third doped regions, each of the third doped regions being formed as a part of a corresponding first doped region, and the second fin structure of the corresponding first doped region being a component of the third doped region; the plurality of third doped regions have the second conductivity type, and the doping concentration of each third doped region is higher than the doping concentration of the corresponding first doped region.

3. The power semiconductor device according to claim 1, characterized in that, Each of the two adjacent first doped regions has a bottom surface facing the substrate, and the bottom surface of the trench is higher than the bottom surface of each first doped region in the first direction.

4. The power semiconductor device according to claim 1, characterized in that, The first end face is flush with the bottom surface of the groove in the first direction.

5. The power semiconductor device according to claim 1, characterized in that, Each of the two adjacent first doped regions has a bottom surface facing the substrate, and the bottom surface of the trench is either flush with or lower than the bottom surface of each first doped region in the first direction.

6. The power semiconductor device according to claim 1, characterized in that, The gate includes a gate oxide layer and a gate electrode layer stacked together, and the gate oxide layer is located on the side of the gate electrode layer facing the substrate, and the thickness of the gate oxide layer is in the range of 30nm-300nm.

7. The power semiconductor device according to claim 2, characterized in that, Also includes: An interlayer dielectric layer is disposed on the side of the gate opposite to the substrate and has contact holes formed to expose a portion of the second doped region and the third doped region of each of the two adjacent first doped regions; A first electrode layer is disposed on the side of the interlayer dielectric layer away from the substrate and extends into the contact hole to form an electrical contact with the second doped region and the third doped region of each of the two adjacent first doped regions; as well as The second electrode layer is disposed on the side of the substrate opposite to the epitaxial layer and forms an electrical contact with the substrate.

8. A power semiconductor device, characterized in that, include: Substrate; An epitaxial layer disposed on the substrate and having a first conductivity type; A first doped region is formed on the side of the epitaxial layer away from the substrate, wherein the first doped region has a second conductivity type different from the first conductivity type and has a first fin structure and a second fin structure spaced apart from each other. A second doped region is formed within the first doped region and located between the first fin structure and the second fin structure. The second doped region has the first conductivity type and has a first end face away from the substrate. The first fin structure has a second end face away from the substrate. The first end face is lower than the second end face in a first direction from the substrate to the epitaxial layer. The epitaxial layer has a first surface away from the substrate and located outside the first doped region. The first surface is lower than the second end face in the first direction. as well as A gate is disposed on the side of the epitaxial layer opposite to the substrate, the gate extending from the first surface across the first fin structure and covering a portion of the first end face of the second doped region.

9. The power semiconductor device according to claim 8, characterized in that, The power semiconductor device is configured with a third doped region, which is formed within the first doped region and the second fin structure is a component of the third doped region; the third doped region has the second conductivity type and the doping concentration of the third doped region is higher than that of the first doped region.

10. The power semiconductor device according to claim 9, characterized in that, The end face of the third doped region facing away from the substrate is higher than the first end face of the second doped region in the first direction.

11. The power semiconductor device according to claim 8, characterized in that, The first surface of the epitaxial layer is flush with the first end face of the second doped region.

12. The power semiconductor device according to claim 8, characterized in that, The first surface of the epitaxial layer is higher than the bottom surface of the first doped region facing the substrate in the first direction.

13. The power semiconductor device according to claim 8, characterized in that, The first surface of the epitaxial layer is flush with or lower than the bottom surface of the first doped region facing the substrate in the first direction.

14. The power semiconductor device according to claim 8, characterized in that, The gate includes a gate oxide layer and a gate electrode layer stacked together, and the gate oxide layer is located on the side of the gate electrode layer facing the substrate, and the thickness of the gate oxide layer is in the range of 30nm-300nm.

15. The power semiconductor device according to claim 8, characterized in that, Also includes: An interlayer dielectric layer is disposed on the side of the gate opposite to the substrate and has contact holes formed thereon to expose a portion of the second doped region and the second fin structure. The first electrode layer is disposed on the side of the interlayer dielectric layer away from the substrate and extends into the contact hole to form an electrical contact with the second doped region and the second fin structure; as well as The second electrode layer is disposed on the side of the substrate opposite to the epitaxial layer and forms an electrical contact with the substrate.

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