Semiconductor device

Abstract

Embodiments of the present application generally relate to semiconductor devices. A semiconductor device of one embodiment includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of the first conductivity type, a gate electrode, a fourth semiconductor region of the second conductivity type, and a second electrode. The gate electrode faces the second semiconductor region with a gate insulating layer interposed therebetween. The fourth semiconductor region is provided around the second semiconductor region along a first surface perpendicular to a first direction from the first electrode toward the first semiconductor region. The fourth semiconductor region is separated from the second semiconductor region. A distance between the second semiconductor region and the fourth semiconductor region is shorter than a length of the fourth semiconductor region in a second direction from the second semiconductor region toward the fourth semiconductor region. The second electrode is provided over the second semiconductor region, the third semiconductor region, and the gate electrode, and electrically connected to the second semiconductor region and the third semiconductor region.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2025-048590 (filed on March 24, 2025). This application includes all contents of the basic application by reference to that basic application. Technical Field

[0003] Embodiments of the present invention generally relate to semiconductor devices. Background Technology

[0004] Semiconductor devices such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are used, for example, in power conversion applications. Low switching losses are desirable in semiconductor devices. Summary of the Invention

[0005] One embodiment of a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a third semiconductor region of a first conductivity type, a gate electrode, a fourth semiconductor region of a second conductivity type, and a second electrode. The first semiconductor region is disposed on the first electrode. The second semiconductor region is disposed on the first semiconductor region. The third semiconductor region is disposed on the second semiconductor region. The gate electrode is opposite to the second semiconductor region via a gate insulating layer. The fourth semiconductor region is disposed around the second semiconductor region along a first surface perpendicular to a first direction from the first electrode toward the first semiconductor region. The fourth semiconductor region is separated from the second semiconductor region. The distance between the second semiconductor region and the fourth semiconductor region is shorter than the length of the fourth semiconductor region in a second direction from the second semiconductor region toward the fourth semiconductor region. The second electrode is disposed on the second semiconductor region, the third semiconductor region, and the gate electrode, and is electrically connected to the second semiconductor region and the third semiconductor region.

[0006] According to one embodiment, a semiconductor device capable of reducing switching losses can be provided. Attached Figure Description

[0007] Figure 1 This is a top view of a semiconductor device illustrating an implementation method.

[0008] Figure 2 yes Figure 1 Sectional view II-II.

[0009] Figure 3 yes Figure 1 Sectional view III-III.

[0010] Figure 4 yes Figure 1 Sectional view IV-IV.

[0011] Figure 5 This is a top view of a semiconductor device illustrating an implementation method.

[0012] Figure 6 This is a cross-sectional view showing a portion of a semiconductor device for reference.

[0013] Figure 7 It is Figure 2 A magnified sectional view of a portion of the document.

[0014] Figure 8 This is a cross-sectional view showing a portion of a semiconductor device according to a first variation of the embodiment.

[0015] Figure 9 This is a cross-sectional view showing a portion of a semiconductor device in a second variation of the embodiment.

[0016] Figure 10 This is a cross-sectional view showing a portion of a semiconductor device according to a third variation of the embodiment. Detailed Implementation

[0017] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

[0018] The accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between parts, etc., may not be the same as in reality. Even when representing the same part, there may be cases where the dimensions and ratios of each other are represented differently according to the accompanying drawings.

[0019] In this application specification and figures, elements that are the same as those already described are labeled with the same reference numerals and detailed descriptions are omitted where appropriate.

[0020] In the following description and accompanying figures, n + n - The notation "p" indicates the relative levels of impurity concentration. Specifically, a "+" indicates a relatively higher impurity concentration compared to a notation without either "+" or "-", while a "-" indicates a relatively lower impurity concentration compared to a notation without either. When each region contains both p-type and n-type impurities, these notations represent the relative levels of net impurity concentration after these impurities have compensated for each other.

[0021] The embodiments described below can also be implemented by reversing the p-type and n-type of each semiconductor region.

[0022] Figure 1 This is a top view of a semiconductor device illustrating an implementation method. Figures 2-4 They are Figure 1 Sectional views II-II, III-III and IV-IV.

[0023] The semiconductor device 100 in this embodiment is a MOSFET. For example... Figures 1-4 As shown, the semiconductor device 100 includes n - p-type drift region 1 (first semiconductor region), p-type substrate region 2 (second semiconductor region), n ... substrate region 3 (second semiconductor region), n-type substrate region 4 (second semiconductor region), n-type substrate region 5 (second semiconductor region), n-type substrate region 6 (second semiconductor region), n-type substrate region 7 (second semiconductor region), n-type substrate region 8 (second semiconductor region), n-type substrate region 9 + p-type source region 3 (third semiconductor region), p-type semiconductor region 4 (fourth semiconductor region), p-type guard ring region 5 (fifth semiconductor region), n + The circuit includes a drain region 6, a gate electrode 10, a conductive layer 13, an insulating layer 15, a drain electrode 21 (first electrode), a source electrode 22 (second electrode), a gate pad 23 (third electrode), and a resin portion 25. The n-type is an example of the first conductivity type. The p-type is an example of the second conductivity type.

[0024] In the description of the implementation method, an XYZ orthogonal coordinate system is used. The direction from the drain electrode 21 toward n... - The direction of the drift region 1 is defined as the Z direction (first direction). Two directions perpendicular to and orthogonal to the Z direction are defined as the X direction (first perpendicular direction) and the Y direction (second perpendicular direction). Furthermore, for illustration, the direction from the drain electrode 21 towards n... - The direction of the drift region 1 is called "up," and its opposite direction is called "down." These directions are based on the drain electrode 21 and n. - The relative positional relationship of the drift region 1 is independent of the direction of gravity.

[0025] like Figure 1 As shown, the source electrode 22 and the gate pad 23 are disposed on the upper surface of the semiconductor device 100. The source electrode 22 and the gate pad 23 are separated from each other and electrically isolated.

[0026] The gate pad 23 includes a pad portion 23a and a wiring portion 23b. The pad portion 23a extends along the XY plane. For example, in the case where the semiconductor device 100 is mounted externally to a circuit, a wire is bonded to the pad portion 23a. The wiring portion 23b is disposed around the source electrode 22 along the XY plane. In the illustrated example, multiple source electrodes 22 are provided in the Y direction. The source electrodes 22 and the wiring portions 23b extending along the X direction are alternately disposed in the Y direction.

[0027] like Figures 2-4 As shown, the drain electrode 21 is disposed on the lower surface of the semiconductor device 100.+ The drain region 6 is disposed on the drain electrode 21 and is electrically connected to the drain electrode 21.

[0028] n - Type-Drift Region 1 is set in n + Above the drain region 6, via n + The drain region 6 is electrically connected to the drain electrode 21. - The n-type impurity concentration in drift region 1 is higher than that in n + The n-type impurity concentration in the drain region 6 is low.

[0029] like Figure 2 and Figure 3 As shown, the p-type base region 2 is set in n - Above drift region 1. + The source region 3 is disposed on the p-type substrate region 2.

[0030] The gate electrode 10 is disposed on the p-type substrate region 2 through the gate insulating layer 11. The gate electrode 10 is separated from the n-type substrate region 2 by the gate insulating layer 11. + A portion of the p-type source region 3, the p-type substrate region 2, and the n-type source region 3 - A portion of the drift region 1 is relative.

[0031] p-type semiconductor region 4 is located along the XY plane at n + The p-type source region 3 is surrounded by the p-type semiconductor region 4, which is separated from the p-type substrate region 2. The p-type impurity concentration of the p-type semiconductor region 4 can be the same as or lower than that of the p-type substrate region 2.

[0032] The p-type guard ring region 5 is disposed along the XY plane around the p-type semiconductor region 4. The p-type guard ring region 5 is separated from the p-type semiconductor region 4. The p-type impurity concentration of the p-type guard ring region 5 can be the same as or lower than that of the p-type semiconductor region 4.

[0033] Source electrode 22 is located in the p-type substrate region 2, n + Above the p-type source region 3 and the gate electrode 10, and above the p-type substrate region 2 and the n ...10. + The p-type semiconductor region 3 is electrically connected. The source electrode 22 is electrically separated from the gate electrode 10. An insulating layer 15 is disposed between the p-type semiconductor region 4 and the source electrode 22, so that the p-type semiconductor region 4 and the source electrode 22 are not in direct contact. For example, when viewed from the Z direction, the entire p-type semiconductor region 4 is covered by the insulating layer 15.

[0034] like Figure 3 and Figure 4As shown, the gate pad 23 is located above the p-type semiconductor region 4, separated by an insulating layer 15. A conductive layer 13 is disposed within the insulating layer 15. Figure 3 As shown by the dashed line, the gate electrode 10 is electrically connected to the conductive layer 13. The conductive layer 13 is connected to the pad portion 23a of the gate pad 23. That is, the gate electrode 10 is electrically connected to the gate pad 23 via the conductive layer 13.

[0035] like Figures 2-4 As shown, the area between the source electrode 22 and the gate pad 23, as well as the outer periphery of the upper surface of the semiconductor device 100, is covered by a resin portion 25. The resin portion 25 has electrical insulation properties.

[0036] like Figure 2 and Figure 3 As shown, multiple p-type substrate regions 2 and gate electrodes 10 are respectively disposed in the X direction. A pair of n electrodes separated from each other in the X direction are disposed on a p-type substrate region 2. + Type source region 3. Source electrode 22 includes a contact portion 22a extending downward. The lower part of the contact portion 22a is located at a pair of n + Between the source region 3 and the contact portion 22a and the p-type substrate region 2 and a pair of n-type sources. + The source pole region is connected in three phases.

[0037] Figure 5 This is a top view illustrating the implementation of a semiconductor device. Furthermore, in Figure 5 In the text, n is omitted. + The structure includes a source region 3, a gate electrode 10, an insulating layer 15, a source electrode 22, a gate pad 23, and a resin portion 25.

[0038] like Figure 5 As shown, the source electrode 22 is located on a plurality of p-type substrate regions 2 and a portion of a p-type semiconductor region 4. The p-type semiconductor region 4 is disposed around the plurality of p-type substrate regions 2 along the XY plane. A plurality of p-type guard ring regions 5 are disposed in the direction from the p-type semiconductor region 4 toward the p-type guard ring region 5. The plurality of p-type guard ring regions 5 are separated from each other. A portion of the source electrode 22 and the gate pad 23 are located on the p-type semiconductor region 4.

[0039] An example of the materials used in each of the constituent elements will be provided.

[0040] n - Type 1 drift region, p-type base region 2, n + p-type source region 3, p-type semiconductor region 4, p-type guard ring region 5 and n +The drain region 6 contains silicon, silicon carbide, gallium nitride, or gallium arsenide as the semiconductor material. Specifically, from the viewpoint of improving the withstand voltage of the semiconductor device 100 and reducing resistance, silicon carbide is preferred as the semiconductor material. When using silicon carbide as the semiconductor material, nitrogen or phosphorus can be used as the n-type impurity. Aluminum or boron can be used as the p-type impurity. The gate electrode 10 and conductive layer 13 contain polycrystalline silicon with added impurities. The gate insulating layer 11 and insulating layer 15 contain insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The drain electrode 21, source electrode 22, and gate pad 23 contain metallic materials such as aluminum or copper. The resin portion 25 contains an insulating resin such as polyimide.

[0041] The operation of the semiconductor device 100 will be explained.

[0042] When a voltage above a threshold is applied to the gate electrode 10, a channel (inversion layer) is formed in the p-type substrate region 2. When the channel is formed with the potential of the drain electrode 21 higher than that of the source electrode 22, electrons flow from the source electrode 22 to the drain electrode 21 through the channel. As a result, the semiconductor device 100 is turned on. When the voltage applied to the gate electrode 10 becomes lower than the threshold, the channel in the p-type substrate region 2 disappears, and the semiconductor device 100 is turned off.

[0043] like Figure 2 and Figure 3 As shown, the p-type base region 2 may also include a first region 2a, a second region 2b, and a third region 2c. The second region 2b is located between the first region 2a and the contact portion 22a. The third region 2c is located in the n direction in the X direction. + Type source pole region 3 and n - Between the p-type drift regions 1 and 2b, the p-type impurity concentrations of the second region 2b and the third region 2c are higher than those of the first region 2a. By increasing the p-type impurity concentration of the second region 2b, the resistance between the p-type substrate region 2 and the source electrode 22 can be reduced. By increasing the p-type impurity concentration of the third region 2c, the threshold voltage used to switch the semiconductor device 100 to a cutoff state and a turn-on state can be adjusted.

[0044] Figure 6 This is a cross-sectional view showing a portion of a semiconductor device for reference.

[0045] exist Figure 6In the semiconductor device 100r shown, no p-type semiconductor region 4 is provided. A p-type substrate region 2r is provided at the outermost periphery of the plurality of p-type substrate regions 2. The length of the p-type substrate region 2r in the X direction is longer than the length of the other p-type substrate regions 2 in the X direction. The p-type substrate region 2r is electrically connected to the source electrode 22. By providing the p-type substrate region 2r, when the semiconductor device 100r is in the off state, the depletion layer can easily extend from the p-type substrate region 2r to the outer periphery of the semiconductor device 100. This improves the breakdown voltage of the semiconductor device 100r.

[0046] One of the indicators representing the characteristics of a semiconductor device is the output charge quantity (Qoss). The lower the output charge quantity (Qoss), the lower the switching losses of the semiconductor device. The output charge quantity (Qoss) is related to the capacitance (Cds) between the drain electrode 21 and the source electrode 22. The larger the capacitance (Cds), the greater the output charge quantity (Qoss). In the semiconductor device 100r, a p-type substrate region 2r, larger than the p-type substrate region 2, is provided at the outermost periphery of a plurality of p-type substrate regions 2. The p-type substrate region 2r is electrically connected to the source electrode 22. Therefore, the capacitance (Cds) increases by n... - The amount of capacitance between the p-type drift region 1 and the p-type base region 2r.

[0047] In the semiconductor device 100, the p-type semiconductor region 4 is separated from the p-type substrate region 2. Furthermore, an insulating layer 15 is provided between the p-type semiconductor region 4 and the source electrode 22, preventing direct contact between the p-type semiconductor region 4 and the source electrode 22. Therefore, the reduction of n... - The capacitance between the p-type drift region 1 and the p-type semiconductor region 4 contributes to the capacitance Cds. According to semiconductor device 100, compared to semiconductor device 100r, the capacitance Cds can be reduced. As a result, the output charge Qoss can be reduced, and the switching losses of semiconductor device 100 can be reduced.

[0048] Figure 7 It is Figure 2 A magnified sectional view of a portion of the document.

[0049] In the semiconductor device 100 of the embodiment, such as Figure 7 As shown, the distance D1 between the p-type substrate region 2 and the p-type semiconductor region 4 in the X direction is shorter than the length L1 of the p-type semiconductor region 4 in the outward direction (second direction) from the p-type substrate region 2 toward the p-type semiconductor region 4. In other words, in the semiconductor device 100, the p-type substrate region 2 and the p-type semiconductor region 4 are close to each other, such that the distance D1 is less than the length L1. The outward direction... Figure 7The cross-section shown is parallel to the X direction. If the distance D1 is less than the length L1, the potential of the p-type semiconductor region 4 is affected by the potential of the p-type substrate region 2. Even when the semiconductor device 100 is in the off state, it is still possible to [transform the potential from the n-type substrate region 2]. - The pn junction between the p-type drift region 1 and the p-type semiconductor region 4 extends the depletion layer. Therefore, even when the p-type semiconductor region 4 and the p-type substrate region 2 are configured separately, the depletion layer can be promoted to extend toward the outer periphery of the semiconductor device 100, and the reduction of the breakdown voltage of the semiconductor device 100 can be suppressed.

[0050] According to the embodiment, it is possible to suppress the decrease in the withstand voltage of the semiconductor device 100 and reduce the switching loss of the semiconductor device 100.

[0051] For example, from the viewpoint of improving the withstand voltage of the semiconductor device 100, the distance D1 between the p-type substrate region 2 and the p-type semiconductor region 4 is preferably 0.5 μm or more and 1.5 μm or less.

[0052] Preferably, the distance D1 is shorter within the range where the p-type substrate region 2 and the p-type semiconductor region 4 are not in direct contact. The shorter the distance D1, the more strongly the potential of the p-type semiconductor region 4 is affected by the potential of the p-type substrate region 2. As a result, the withstand voltage of the semiconductor device 100 can be further improved. In addition, the region where the p-type semiconductor region 4 is provided is an ineffective region where no current flows. In order to miniaturize the semiconductor device 100, a shorter length L1 is preferred. From the viewpoint of improving withstand voltage and miniaturization, the distance D1 is preferably less than 0.5 times the length L1, more preferably less than 0.3 times.

[0053] Furthermore, the p-type semiconductor region 4 is located below the source electrode 22, separated by the insulating layer 15. By placing the p-type semiconductor region 4 below the source electrode 22, compared to the case where the p-type semiconductor region 4 is not provided, the electric field strength at the outer periphery of the source electrode 22 can be mitigated, and the occurrence of insulation breakdown can be suppressed. In other words, by providing the p-type semiconductor region 4, the occurrence of insulation breakdown near the outer periphery of the source electrode 22 can be suppressed, and the size of the XY plane of the source electrode 22 can be increased. As a result, the resistance of the source electrode 22 can be reduced, and the degree of freedom in the configuration when external terminals (lead frames, wires, etc.) are connected to the source electrode 22 can be increased.

[0054] In the semiconductor device 100, the p-type guard ring region 5 surrounding the p-type semiconductor region 4 may be omitted. However, from the viewpoint of improving breakdown voltage, it is preferable to provide the p-type guard ring region 5. By providing more than one p-type guard ring region 5, the depletion layer can more easily extend towards the outer periphery of the semiconductor device 100. As a result, the breakdown voltage of the semiconductor device 100 can be further improved.

[0055] The length L1 of the p-type semiconductor region 4 in the outward direction is longer than the length L2 of the p-type guard ring region 5 in the outward direction. The p-type semiconductor region 4 is located inside the semiconductor device 100 compared to the p-type guard ring region 5. When the semiconductor device 100 is in the off state, compared to the n... - The pn junction between the p-type drift region 1 and the p-type guard ring region 5, for n - A larger voltage is applied to the pn junction between the p-type drift region 1 and the p-type semiconductor region 4. By making the length L1 longer than the length L2, the p-type semiconductor region 4 is less likely to be completely depleted, and the withstand voltage of the semiconductor device 100 can be made more stable. For example, the length L1 is preferably more than 3 times and less than 20 times the length L2.

[0056] The length L2 of the p-type guard ring region 5 in the outward direction is shorter than the length L1 of the p-type semiconductor region 4. The distance D2 between the p-type semiconductor region 4 and the p-type guard ring region 5 is shorter than the length L1 of the p-type semiconductor region 4.

[0057] The distance D3 between the p-type guard ring regions 5 is shorter than the length L1 of the p-type semiconductor region 4. Distance D3 can be the same as or different from the distance D2 between the p-type semiconductor region 4 and the p-type guard ring region 5. Distance D3 can also be the same as or different from the length L2 of the p-type guard ring region 5.

[0058] The p-type substrate region 2 includes a first end e1 and a second end e2 in the X direction. The first end e1 is located between the second end e2 and the p-type semiconductor region 4 in the X direction. For example, the distance D4 between the contact portion 22a and the first end e1 is shorter than the length L1 of the p-type semiconductor region 4. The distance D1 can be shorter than the distance D4.

[0059] For example, the distance D5 between the contact portion 22a and the p-type semiconductor region 4 is shorter than the length L1 of the p-type semiconductor region 4. The distance D6 between the first end e1 and the second end e2 is shorter than the length L1.

[0060] like Figures 2-4 As shown, n - The p-type drift region 1 may also include a first portion 1a, a second portion 1b, and a third portion 1c. The second portion 1b is disposed around the first portion 1a along the XY plane. The third portion 1c is disposed around the second portion 1b along the XY plane. The p-type substrate region 2 and the gate electrode 10 are located on the first portion 1a. The p-type semiconductor region 4 is located on the second portion 1b. The p-type guard ring region 5 is located on the third portion 1c. The n-type impurity concentration of the first portion 1a is higher than that of the second portion 1b and higher than that of the third portion 1c.

[0061] When the semiconductor device 100 is turned off, breakdown may occur in areas with high electric field strength. During breakdown, electrons are discharged from the drain electrode 21, and holes are discharged from the source electrode 22. If the p-type semiconductor region 4 is not in direct contact with the source electrode 22, and if in the n... - When breakdown occurs near the outer periphery of the p-type drift region 1, holes concentrate and flow towards the outermost p-type substrate region 2. The semiconductor device 100 includes n... - Type 1 drift region, type 2 base region and n + A parasitic transistor exists in the source region 3. If holes concentrate and flow into a portion of the p-type substrate region 2, the potential of the p-type substrate region 2 rises, and the parasitic transistor may operate. When the n-type impurity concentration in the first part 1a is higher than that in the second part 1b, the electric field strength in the first part 1a tends to rise more easily than in the second part 1b. Therefore, breakdown is more likely to occur in the first part 1a than in the second part 1b. When breakdown occurs in the first part 1a, holes flow dispersedly into multiple p-type substrate regions 2. By suppressing the concentrated flow of holes through a portion of the p-type substrate region 2, the operation of the parasitic transistor can be suppressed.

[0062] To facilitate breakdown in the first portion 1a, the n-type impurity concentration of the first portion 1a is preferably at least twice that of the n-type impurity concentration of the second portion 1b. On the other hand, if the n-type impurity concentration of the first portion 1a is too high, the breakdown voltage of the semiconductor device 100 may decrease. Therefore, the n-type impurity concentration of the first portion 1a is preferably at least twice and less than ten times that of the n-type impurity concentration of the second portion 1b.

[0063] The embodiments of the present invention are more suitable for semiconductor devices 100 that use silicon carbide as the semiconductor material. In so-called SiC devices using silicon carbide, higher-speed switching characteristics are required compared to silicon devices. The higher the switching speed, the greater the impact of the output charge QoS, and the higher the switching losses. By applying this embodiment to SiC devices, the switching losses of the semiconductor device 100 can be effectively reduced.

[0064] (First variation)

[0065] Figure 8 This is a cross-sectional view showing a portion of a semiconductor device according to a first variation of the embodiment.

[0066] Figure 8The semiconductor device 110 shown differs from the semiconductor device 100 primarily in the construction of its gate electrode 10. The semiconductor device 100 has a so-called planar construction in which the gate electrode 10 is disposed on a p-type substrate region 2 and extends along the XY plane. In the semiconductor device 110, there is a so-called trench construction in which the gate electrode 10 is disposed in a trench formed in a semiconductor region.

[0067] Specifically, the gate electrode 10 is positioned opposite the p-type substrate region 2 in the X direction, separated by the gate insulating layer 11. A pair of n-type electrodes, separated from each other in the X direction, are disposed on the p-type substrate region 2. + p-type source region 3. For example, a portion of p-type base region 2 is located within a pair of n-type base regions. + Between the p-type source region 3 and the p-type substrate region 2. The p-type impurity concentration in this part of the p-type substrate region 2 is higher than that in other parts of the p-type substrate region 2. This part of the p-type substrate region 2 and a pair of n + The source region 3 is connected to the source electrode 22.

[0068] Other configurations of the semiconductor device 110 can be applied to those of the semiconductor device 100. For example, a source electrode 22 and a gate pad 23 are disposed on the upper surface of the semiconductor device 110, similar to those of the semiconductor device 100. The gate pad 23 is electrically connected to the gate electrode 10 via a conductive layer 13 in the insulating layer 15. An insulating layer 15 is disposed between the p-type semiconductor region 4 and the source electrode 22, so that the p-type semiconductor region 4 and the source electrode 22 are not in direct contact.

[0069] In semiconductor device 110, similarly to semiconductor device 100, the p-type semiconductor region 4 is separated from the p-type substrate region 2. This reduces n... - The capacitance between the p-type drift region 1 and the p-type semiconductor region 4 contributes to the capacitance Cds. As a result, the output charge Qoss can be reduced, and the switching losses of the semiconductor device 110 can be reduced.

[0070] (Second variation)

[0071] Figure 9 This is a cross-sectional view showing a portion of a semiconductor device in a second variation of the embodiment. Figure 9 The semiconductor device 120 shown and Figures 1-5 The p-type semiconductor region 4 has a different structure compared to the semiconductor device 100 shown.

[0072] In semiconductor device 120, p-type semiconductor region 4 includes an outer peripheral portion 4a and an inner peripheral portion 4b. The outer peripheral portion 4a and the inner peripheral portion 4b are located around the p-type substrate region 2 along the XY plane. The inner peripheral portion 4b is located between the p-type substrate region 2 and the outer peripheral portion 4a. The p-type impurity concentration in the outer peripheral portion 4a is lower than the p-type impurity concentration in the inner peripheral portion 4b. Figure 9 As shown, the thickness (dimension in the Z direction) of the outer peripheral portion 4a can also be smaller than the thickness of the inner peripheral portion 4b.

[0073] By providing an outer peripheral portion 4a and an inner peripheral portion 4b with different p-type impurity concentrations, the electric field strength near the outer peripheral end of the p-type semiconductor region 4 can be reduced while extending the depletion layer toward the outer periphery of the semiconductor device 120. According to the second modification, the breakdown voltage of the semiconductor device 120 can be further improved compared to the semiconductor device 100.

[0074] (Third variation)

[0075] Figure 10 This is a cross-sectional view showing a portion of a semiconductor device according to a third variation of the embodiment. Figure 10 The semiconductor device 130 shown and Figures 1-5 The source electrode 22 has a different structure compared to the semiconductor device 100 shown.

[0076] Specifically, in the semiconductor device 130, the source electrode 22 is not provided above the p-type semiconductor region 4. An insulating layer 15 and a resin portion 25 are provided in the region above the p-type semiconductor region 4.

[0077] In the semiconductor device of this embodiment, the p-type semiconductor region 4 is not in contact with the source electrode 22. For example... Figure 6 As shown in the semiconductor device 100r, it is not necessary to place the source electrode 22 on the p-type semiconductor region 4. Therefore, the source electrode 22 can be omitted above the p-type semiconductor region 4.

[0078] The embodiments of the present invention include the following features.

[0079] (Feature 1)

[0080] A semiconductor device comprising:

[0081] First electrode;

[0082] A first semiconductor region of a first conductivity type is disposed on the first electrode;

[0083] A second semiconductor region of a second conductivity type is disposed on the first semiconductor region;

[0084] A third semiconductor region of a first conductivity type is disposed on top of the second semiconductor region;

[0085] The gate electrode is opposite to the second semiconductor region through the gate insulating layer;

[0086] A fourth semiconductor region of a second conductivity type is disposed around the second semiconductor region along a first surface perpendicular to a first direction from the first electrode toward the first semiconductor region, and is separated from the second semiconductor region. The distance between the second semiconductor region and the fourth semiconductor region is shorter than the length of the fourth semiconductor region in the second direction from the second semiconductor region toward the fourth semiconductor region.

[0087] The second electrode is disposed on the second semiconductor region, the third semiconductor region and the gate electrode, and is electrically connected to the second semiconductor region and the third semiconductor region.

[0088] (Feature 2)

[0089] The semiconductor device according to feature 1, wherein...

[0090] The distance between the second semiconductor region and the fourth semiconductor region is less than 0.5 times the length of the fourth semiconductor region.

[0091] (Feature 3)

[0092] The semiconductor device according to feature 1 or 2, wherein,

[0093] It also includes a fifth semiconductor region of a second conductivity type, which is disposed around the fourth semiconductor region along the first surface and is separated from the fourth semiconductor region.

[0094] (Feature 4)

[0095] The semiconductor device according to feature 3, wherein...

[0096] The length of the fifth semiconductor region in the second direction is shorter than the length of the fourth semiconductor region in the second direction.

[0097] (Feature 5)

[0098] The semiconductor device according to feature 3 or 4, wherein...

[0099] The fifth semiconductor region is provided in multiple ways in the second direction.

[0100] (Feature 6)

[0101] The semiconductor device according to feature 5, wherein...

[0102] The distance between adjacent fifth semiconductor regions is shorter than the length of the fourth semiconductor region in the second direction.

[0103] (Feature 7)

[0104] The semiconductor device according to any one of features 1 to 6, wherein,

[0105] The fourth semiconductor region includes an outer peripheral portion located around the second semiconductor region along the first surface, and an inner peripheral portion located between the second semiconductor region and the outer peripheral portion.

[0106] The impurity concentration of the second conductivity type in the outer peripheral portion is lower than the impurity concentration of the second conductivity type in the inner peripheral portion.

[0107] (Feature 8)

[0108] The semiconductor device according to any one of features 1 to 7, wherein...

[0109] It also has a third electrode, which is disposed above the fourth semiconductor region through an insulating layer and is electrically connected to the gate electrode.

[0110] (Feature 9)

[0111] The semiconductor device according to feature 8, wherein...

[0112] A portion of the second electrode is disposed over the fourth semiconductor region through the insulating layer.

[0113] (Feature 10)

[0114] The semiconductor device according to feature 8 or 9, wherein...

[0115] The second electrode has multiple portions disposed in a first perpendicular direction that is perpendicular to the first direction.

[0116] A portion of the third electrode is disposed between the second electrodes.

[0117] A portion of the fourth semiconductor region lies beneath the portion of the third electrode, separated by the insulating layer.

[0118] (Feature 11)

[0119] The semiconductor device according to feature 8 or 9, wherein...

[0120] The second electrode has multiple portions disposed in a first perpendicular direction that is perpendicular to the first direction.

[0121] The third electrode includes a wiring portion extending in a second vertical direction perpendicular to both the first direction and the first vertical direction.

[0122] The second electrode and the wiring portion are alternately arranged in the first vertical direction, and a portion of the fourth semiconductor region is located under the plurality of wiring portions through the insulating layer.

[0123] (Feature 12)

[0124] The semiconductor device according to any one of features 1 to 11, wherein,

[0125] The second semiconductor region and the gate electrode are respectively provided in multiple locations in a second perpendicular direction that is perpendicular to the first direction.

[0126] The fourth semiconductor region is disposed around the plurality of second semiconductor regions along the first surface.

[0127] (Feature 13)

[0128] The semiconductor device according to feature 12, wherein,

[0129] One of the plurality of second semiconductor regions is adjacent to the fourth semiconductor region in the second vertical direction, separated by a portion of the first semiconductor region.

[0130] A pair of third semiconductor regions, separated from each other in the second vertical direction, are disposed on one of the plurality of second semiconductor regions.

[0131] The second electrode includes a contact located between the pair of third semiconductor regions.

[0132] (Feature 14)

[0133] The semiconductor device according to feature 13, wherein...

[0134] One of the plurality of second semiconductor regions includes a first end and a second end in the second vertical direction.

[0135] The first end is located between the fourth semiconductor region and the second end.

[0136] The distance between the contact portion in the second vertical direction and the first end is shorter than the length of the fourth semiconductor region in the second direction.

[0137] (Feature 15)

[0138] The semiconductor device according to feature 14, wherein...

[0139] The distance between the contact portion in the second vertical direction and the fourth semiconductor region is shorter than the length of the fourth semiconductor region in the second direction.

[0140] (Feature 16)

[0141] The semiconductor device according to feature 14 or 15, wherein,

[0142] The distance between the first end and the second end in the second vertical direction is shorter than the length of the fourth semiconductor region in the second direction.

[0143] (Feature 17)

[0144] The semiconductor device according to any one of features 12 to 16, wherein,

[0145] The second electrode is disposed on the plurality of second semiconductor regions and the plurality of fourth semiconductor regions.

[0146] (Feature 18)

[0147] The semiconductor device according to any one of features 1 to 17, wherein,

[0148] The first semiconductor region includes a first portion and a second portion disposed around the first portion along the first surface.

[0149] The second semiconductor region is disposed on the first portion.

[0150] The fourth semiconductor region is disposed on the second portion.

[0151] The impurity concentration of the first conductivity type in the first part is higher than that of the first conductivity type in the second part.

[0152] (Feature 19)

[0153] The semiconductor device according to feature 18, wherein...

[0154] The impurity concentration of the first conductivity type in the first part is more than twice and less than 10 times that of the impurity concentration of the first conductivity type in the second part.

[0155] (Feature 20)

[0156] The semiconductor device according to any one of features 1 to 19, wherein,

[0157] The first to fourth semiconductor regions contain silicon carbide.

[0158] According to the embodiments described above, a semiconductor device is provided that can suppress the decrease in withstand voltage and reduce switching losses.

[0159] In this specification, "or" means that "at least one or more" of the items listed in the text can be used.

[0160] The relative levels of impurity concentrations among the semiconductor regions in the embodiments described above can be confirmed, for example, using scanning electrostatic capacitance microscopy (SCM). Furthermore, the carrier concentration in each semiconductor region can be considered equal to the concentration of impurities activated in each semiconductor region. Therefore, the relative levels of carrier concentrations among the semiconductor regions can also be confirmed using SCM. Additionally, the impurity concentration in each semiconductor region can be measured, for example, by secondary ion mass spectrometry (SIMS).

[0161] While several embodiments of the present invention have been illustrated above, these embodiments are merely examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and are also included within the scope of the invention as described in the claims and its equivalents. Furthermore, the above-described embodiments can be combined with each other for implementation.

Claims

1. A semiconductor device, characterized in that, have: First electrode; A first semiconductor region of a first conductivity type is disposed on the first electrode; A second semiconductor region of a second conductivity type is disposed on the first semiconductor region; A third semiconductor region of a first conductivity type is disposed on top of the second semiconductor region; The gate electrode is opposite to the second semiconductor region through the gate insulating layer; The fourth semiconductor region of the second conductivity type is disposed around the second semiconductor region along a first surface perpendicular to a first direction from the first electrode toward the first semiconductor region, and is separated from the second semiconductor region. The distance between the second semiconductor region and the fourth semiconductor region is shorter than the length of the fourth semiconductor region in the second direction from the second semiconductor region toward the fourth semiconductor region. as well as The second electrode is disposed on the second semiconductor region, the third semiconductor region, and the gate electrode, and is electrically connected to the second semiconductor region and the third semiconductor region.

2. The semiconductor device according to claim 1, characterized in that, The distance between the second semiconductor region and the fourth semiconductor region is less than 0.5 times the length of the fourth semiconductor region.

3. The semiconductor device according to claim 1, characterized in that, It also includes a fifth semiconductor region of a second conductivity type, which is disposed around the fourth semiconductor region along the first surface and is separated from the fourth semiconductor region.

4. The semiconductor device according to claim 3, characterized in that, The length of the fifth semiconductor region in the second direction is shorter than the length of the fourth semiconductor region in the second direction.

5. The semiconductor device according to claim 3, characterized in that, The fifth semiconductor region is provided in multiple ways in the second direction.

6. The semiconductor device according to claim 5, characterized in that, The distance between adjacent fifth semiconductor regions is shorter than the length of the fourth semiconductor region in the second direction.

7. The semiconductor device according to claim 1, characterized in that, The fourth semiconductor region includes an outer peripheral portion located around the second semiconductor region along the first surface, and an inner peripheral portion located between the second semiconductor region and the outer peripheral portion. The impurity concentration of the second conductivity type in the outer peripheral portion is lower than the impurity concentration of the second conductivity type in the inner peripheral portion.

8. The semiconductor device according to claim 1, characterized in that, It also has a third electrode, which is disposed above the fourth semiconductor region through an insulating layer and is electrically connected to the gate electrode.

9. The semiconductor device according to claim 8, characterized in that, A portion of the second electrode is disposed over the fourth semiconductor region through the insulating layer.

10. The semiconductor device according to claim 8, characterized in that, The second electrode has multiple portions disposed in a first perpendicular direction that is perpendicular to the first direction. A portion of the third electrode is disposed between the second electrodes. A portion of the fourth semiconductor region lies beneath the portion of the third electrode, separated by the insulating layer.

11. The semiconductor device according to claim 8, characterized in that, The second electrode has multiple portions disposed in a first perpendicular direction that is perpendicular to the first direction. The third electrode includes a wiring portion extending in a second vertical direction perpendicular to both the first direction and the first vertical direction. The second electrode and the wiring portion are alternately arranged in the first vertical direction. A portion of the fourth semiconductor region is located beneath the plurality of wiring portions, separated by the insulating layer.

12. The semiconductor device according to claim 1, characterized in that, The second semiconductor region and the gate electrode are respectively provided in multiple locations in a second perpendicular direction that is perpendicular to the first direction. The fourth semiconductor region is disposed around the plurality of second semiconductor regions along the first surface.

13. The semiconductor device according to claim 12, characterized in that, One of the plurality of second semiconductor regions is adjacent to the fourth semiconductor region in the second vertical direction, separated by a portion of the first semiconductor region. A pair of third semiconductor regions, separated from each other in the second vertical direction, are disposed on one of the plurality of second semiconductor regions. The second electrode includes a contact located between the pair of third semiconductor regions.

14. The semiconductor device according to claim 13, characterized in that, One of the plurality of second semiconductor regions includes a first end and a second end in the second vertical direction. The first end is located between the fourth semiconductor region and the second end. The distance between the contact portion in the second vertical direction and the first end is shorter than the length of the fourth semiconductor region in the second direction.

15. The semiconductor device according to claim 14, characterized in that, The distance between the contact portion in the second vertical direction and the fourth semiconductor region is shorter than the length of the fourth semiconductor region in the second direction.

16. The semiconductor device according to claim 14, characterized in that, The distance between the first end and the second end in the second vertical direction is shorter than the length of the fourth semiconductor region in the second direction.

17. The semiconductor device according to claim 12, characterized in that, The second electrode is disposed on the plurality of second semiconductor regions and the plurality of fourth semiconductor regions.

18. The semiconductor device according to claim 1, characterized in that, The first semiconductor region includes a first portion and a second portion disposed around the first portion along the first surface. The second semiconductor region is disposed on the first portion. The fourth semiconductor region is disposed on the second portion. The impurity concentration of the first conductivity type in the first part is higher than that of the first conductivity type in the second part.

19. The semiconductor device according to claim 18, characterized in that, The impurity concentration of the first conductivity type in the first part is more than twice and less than 10 times that of the impurity concentration of the first conductivity type in the second part.

20. The semiconductor device according to claim 1, characterized in that, The first to fourth semiconductor regions contain silicon carbide.

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