SiC mosfet device structure and method of manufacturing the same

Abstract

The application provides a SiC MOSFET device structure and a manufacturing method thereof. The SiC MOSFET device structure comprises an N+ type SiC substrate and an N- type drift region formed on the substrate; a P type base region and an N+ source region formed on the upper part of the N- type drift region; a shielding structure formed in the cell, the shielding structure extends into the N- type drift region through the N+ source region and the P type base region in sequence, the shielding structure comprises deep P+ regions located on both sides of the cell and a shallow P+ region located between the two deep P+ regions; the junction depth of the deep P+ region is greater than that of the shallow P+ region; the lateral spacing between the deep P+ region and the adjacent shallow P+ region is smaller than the lateral spacing between the two adjacent deep P+ regions; a trench structure formed in the cell comprises a plurality of trench structures, when the plurality of trenches are arranged from the deep P+ region to the shallow P+ region, the lateral width of each trench gradually decreases, and the longitudinal depth of each trench first decreases and then increases.

Description

Technical Field

[0001] This invention relates to the field of power semiconductors, and more particularly to a trench gate SiC MOSFET structure and its manufacturing method. Background Technology

[0002] Silicon carbide (SiC) materials possess advantages such as wide bandgap, high thermal conductivity, high breakdown field strength, and high saturation velocity, making them ideal for fabricating high-temperature, high-power semiconductor devices. SiC-based power devices can fully leverage their high-temperature, high-frequency, and low-loss characteristics, making them highly promising for applications in high-voltage, high-temperature, high-frequency, high-power, and high-radiation fields. In particular, several manufacturers have already launched commercial SiC power MOSFET devices.

[0003] As the application requirements of SiC devices gradually increase, SiC MOSFETs are gradually shifting from planar to trench types. However, due to the difference in dielectric constant between SiC material and gate oxide material, according to Gauss's law, the electric field strength inside the oxide layer of SiC trench MOSFETs is 2.5 times the peak electric field inside SiC. Furthermore, SiC material itself has a high critical breakdown electric field. This leads to excessive electric field stress in the gate oxide layer, affecting the long-term reliability of the device and even causing device failure. Therefore, shielding the gate oxide electric field at the bottom of the trench is particularly important; however, the introduction of a gate oxide electric field shielding structure inevitably increases the on-resistance of the device. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, the present invention provides a SiC MOSFET device structure and its manufacturing method.

[0005] The SiC MOSFET device structure includes an N+ type SiC substrate and an N- type drift region formed on the N+ type SiC substrate; a P- type base region and an N+ source region formed on the upper part of the N- type drift region; a shielding structure formed in the cell; and a trench structure formed in the cell.

[0006] The shielding structure extends sequentially through the N+ source region and the P-type base region into the N-type drift region. The shielding structure includes a deep P+ region located on both sides of the cell and a shallow P+ region located between the two deep P+ regions. The junction depth of the deep P+ region is greater than the junction depth of the shallow P+ region. The lateral spacing between the deep P+ region and the adjacent shallow P+ region is less than the lateral spacing between the two adjacent deep P+ regions.

[0007] The trench structure includes multiple trenches. As the multiple trenches are arranged from the deep P+ region to the shallow P+ region, the lateral width of each trench gradually decreases, and the longitudinal depth of each trench first decreases and then increases.

[0008] In one embodiment, the lateral spacing between the deep P+ region and the shallow P+ region is W1, the lateral distance from the outer edge of the deep P+ region on one side of the cell to the nearest cell boundary line is W2, and the lateral distance from the outer edge of the deep P+ region on the other side of the cell to the nearest cell boundary line is W3, and W1 is less than the sum of W2 and W3.

[0009] In one embodiment, the plurality of trenches includes at least a first trench, a second trench, a third trench, and a fourth trench; The first trench is located between two adjacent deep P+ regions and has a trench flow path. The first trench has the smallest width and the deepest depth. The second trench is located between the deep P+ region and the shallow P+ region and has a trench flow path. The width of the second trench is between the first trench and the third trench, and the depth is the shallowest. The third trench partially overlaps with the deep P+ region, wherein one sidewall of the third trench overlaps with the deep P+ region, and the other sidewall of the third trench is not shielded by the deep P+ region to retain the flow path; the third trench has the largest width and its depth is between the first trench and the second trench. The fourth trench is located at the same position as the shallow P+ region, and the size and structure of the fourth trench are the same as those of the first trench.

[0010] In one embodiment, the plurality of trenches further includes a fifth trench, which is located between the third trench and the second trench and has a trench flow path. The width of the fifth trench is between the third trench and the second trench, and the depth is between the third trench and the second trench.

[0011] In one embodiment, the plurality of trenches further includes a sixth trench, which is located between the second trench and the fourth trench and has a trench flow path. The width of the sixth trench is between the second trench and the fourth trench, and the depth is less than that of the second trench.

[0012] In one embodiment, the shallow P+ region is arranged intermittently along the direction parallel to the length of the trench.

[0013] In one embodiment, the fourth trench forms a three-dimensional flow path through the discontinuous region of the shallow P+ zone.

[0014] In one embodiment, an additional P+ injection area is provided at the bottom of the fourth trench with the smallest width.

[0015] In one embodiment, an odd number of trenches are provided between two adjacent deep P+ regions.

[0016] In one embodiment, the N-type drift region is further combined with a semi-superjunction or superjunction structure, the semi-superjunction or superjunction structure comprising alternating P-regions and current spreading layers, wherein the stripe orientation of the P-regions and the current spreading layers is perpendicular to the stripe orientation of the shielding structure, or parallel to the stripe orientation of the shielding structure, or intersects the stripe orientation of the shielding structure at any angle.

[0017] This invention also discloses a method for manufacturing the aforementioned SiC MOSFET device structure. This method includes, but is not limited to, the following steps: A SiC epitaxial wafer is provided, and ion implantation is performed sequentially on the SiC epitaxial wafer of the P-type base region, the N+ source region, the deep P+ region, and the shallow P+ region; wherein the deep P+ region and the shallow P+ region form the shielding structure, and the epitaxial wafer includes the N+ type SiC substrate and the N- type drift region formed thereon; A thick etch mask is deposited, and the thick etch mask is patterned at the corresponding positions where the trenches need to be formed to form mask openings of different lateral sizes; then a thin etch mask is deposited, and further patterned etching is performed, wherein the lateral size of the mask openings gradually decreases from the deep P+ region to the shallow P+ region, and there is no mask only at the mask opening with the smallest lateral size, while the thin etch mask is present at the other mask openings; By utilizing the differences in the coverage state of thin etched masks at different openings and the etch load effect, the trench structures with different widths and depths can be formed simultaneously through a one-step etch process.

[0018] In one embodiment, the method further includes the following steps: The trench structure is subjected to high-temperature activation by ion implantation and trench rounding treatment. Subsequently, gate oxide layer growth, gate polysilicon filling and etch-back, interlayer dielectric deposition and source contact hole formation are completed in sequence to prepare the gate structure and source contact. The source electrode and drain electrode are formed by performing source metallization on the front side and substrate thinning and drain metallization on the back side.

[0019] The present invention has the following beneficial technical effects: Firstly, this structure employs a combination of deep P+ regions on both sides and a discontinuous shallow P+ region in the middle to reduce the gate oxide electric field at the bottom of the trench (the junction depth of the deep P+ region is greater than that of the shallow P+ region). Simultaneously, a trench with the smallest width and largest depth is designed for current flow between the two deep P+ regions; a trench with the second smallest width and smallest depth is designed for current flow between the deep and shallow P+ regions; a trench with the largest width and second deepest depth is designed in the overlapping area with the deep P+ regions, with the deep P+ regions only overlapping with one side of the trench, allowing current flow on the other side; and a trench with the same structure as the one between the two deep P+ regions is designed in the shallow P+ region, allowing current flow through discontinuous non-shallow P+ regions in three dimensions. This structural design, while reducing the gate oxide electric field, fully utilizes the available space to add trench structures with varying widths and depths, significantly improving the device's current-carrying capacity.

[0020] Secondly, under short-circuit conditions, this structural design utilizes the deep P+ region combined with the shallow P+ region to form depletion expansion, reducing the short-circuit current. The trench with the smallest width and largest depth between the two deep P+ regions (e.g., the first trench) forcibly splits the short-circuit current in the JFET region and induces current flow from the depletion expansion high-resistance region, thus reducing the short-circuit current. Simultaneously, the deep trench (e.g., the fourth trench) that overlaps with the intermittent shallow P+ region can also forcibly split the short-circuit current and induce current flow from the depletion expansion high-resistance region, further reducing the short-circuit current. This achieves an optimized trade-off between on-resistance and short-circuit capability.

[0021] Thirdly, in this structural design, by utilizing the differences in the coverage state of the thin etched mask at different openings and the etch load effect, a trench structure with different widths and depths can be formed simultaneously through a one-step etch process. Attached Figure Description

[0022] The above-described invention and the following detailed description will be better understood when read in conjunction with the accompanying drawings. It should be noted that the drawings are merely examples of the claimed invention. In the drawings, the same reference numerals represent the same or similar elements.

[0023] Figure 1 A top view of a SiC MOSFET structure according to an embodiment of the present invention is shown; Figure 2 Show Figure 1 The cross-sectional view of the SiC MOSFET structure shown is along the AA' direction; Figure 3 This illustrates the distance relationships between the P+ regions according to an embodiment of the present invention; Figure 4 The manufacturing process of a differentiated trench according to an embodiment of the present invention is illustrated; Figure 5 The manufacturing process of a differentiated trench according to an embodiment of the present invention is illustrated; Figure 6The diagram shows the cross-sectional structure after the trench etching is completed, followed by high-temperature activation, fillet treatment, gate oxide growth, gate polysilicon filling and etch-back, interlayer dielectric deposition, and source contact hole opening. Figure 7 The complete cross-sectional structure of the device after all front-side metallization and back-side processing are completed is shown. Figure 8 A top view of a SiC MOSFET structure according to a variant embodiment of the present invention is shown; Figure 9 Show Figure 8 AA' section diagram; Figure 10 A top view of a SiC MOSFET structure according to a variant embodiment of the present invention is shown; Figure 11 Show Figure 10 AA' section diagram; Figure 12 A top view of a SiC MOSFET structure according to a variant embodiment of the present invention is shown; Figure 13 Show Figure 12 AA' section diagram; Figure 14 A top view of a SiC MOSFET structure according to a variant embodiment of the present invention is shown; Figure 15 Show Figure 14 AA' section diagram; Figure 16 Show Figure 14 BB' cross-sectional view; Figure 17 A top view of a SiC MOSFET structure according to a variant embodiment of the present invention is shown; Figure 18 A top view of a SiC MOSFET structure according to a variant embodiment of the present invention is shown.

[0024] The meanings of the labels in the figures are as follows: 101 Deep P+ zone; 102 Shallow P+ area; 201 First trench; 202 Second trench; 203 Third trench; 204 Fourth trench; 210 First sidewall; 211 Second sidewall; 301 High-concentration N+ type substrate; 302 N-type drift zone; 303 P-type base region; 304 N+ source region; 401 Mask structure; 701 Wu metal; 702 Source Metal; 703 Drain metal; 704 Ni metal; 901 First P+ injection region; 1101 Fifth trench; 1102 Sixth trench; 1301 Seventh Trench; 1302 Eighth trench; 1303 Second P+ injection region; 1501 P-section; 1601 CSL2 area; 1. First structure; 2. Second structure; 3. The third structure. Detailed Implementation

[0025] The following detailed description of the features and advantages of the present invention is sufficient to enable any person skilled in the art to understand the technical content of the invention and implement it accordingly. Furthermore, based on the disclosure in this specification, those skilled in the art can easily understand the related objects and advantages of the invention. Although the description of the invention will be presented in conjunction with preferred embodiments, this does not mean that the features of the invention are limited to these embodiments. To provide a deep understanding of the invention, many specific details will be included in the following description. The invention may also be implemented without using these details. Moreover, to avoid confusion or obscuring the focus of the invention, some specific details will be omitted in the description.

[0026] As the application requirements of SiC devices gradually increase, SiC MOSFETs are gradually shifting from planar to trench types. However, due to the difference in dielectric constant between SiC material and gate oxide material, according to Gauss's law, the electric field strength inside the oxide layer of SiC trench MOSFETs is 2.5 times the peak electric field inside SiC. Furthermore, SiC material itself has a high critical breakdown electric field. This leads to excessive electric field stress in the gate oxide layer, affecting the long-term reliability of the device and even causing device failure. Therefore, shielding the gate oxide electric field at the bottom of the trench is particularly important; however, the introduction of a gate oxide electric field shielding structure inevitably increases the on-resistance of the device.

[0027] To address the aforementioned issues, this invention proposes a SiC trench gate MOSFET structure. This structure employs a deep P+ design with a junction depth ≥2.5µm on both sides combined with a shallow P+ design with a discontinuous junction depth ≥1.8µm in the middle to reduce the gate oxide electric field at the bottom of the trench. Simultaneously, multiple current-carrying paths are designed using the effective cell size, significantly improving the device's current-carrying capacity while reducing the gate oxide electric field.

[0028] Furthermore, the SiC trench gate MOSFET structure of the present invention can forcibly split the short-circuit current under short-circuit conditions by utilizing the shallow P+ and trench structure, inducing current to flow from the depletion to the high-resistivity region, thereby improving the short-circuit capability.

[0029] Figure 1 A top view of a SiC trench gate MOSFET structure according to an embodiment of the present invention is shown. The SiC MOSFET structure of the present invention includes a shielding structure and a trench structure designed in conjunction with the shielding structure. Figure 1 The top view shows the shielding structure design of the SiC trench gate MOSFET structure within one cell cycle, which is used to reduce the gate oxide electric field at the bottom of the trench.

[0030] It should be noted that the three-dimensional direction or trench length direction mentioned in this article refers to Figure 1 The Z direction is shown; the longitudinal or depth direction mentioned in this article refers to the chip depth direction, that is, the direction from the front of the chip to the back of the chip; the horizontal or lateral direction mentioned in this article refers to... Figure 1 The X direction is shown.

[0031] Those skilled in the art will understand that a cell is the smallest repeating unit in the layout of a SiC MOSFET chip. All the figures in this invention show the structure within a single cell cycle, and the left and right boundaries of the figures are the cell boundaries with respect to adjacent cells.

[0032] like Figure 1 As shown, within one cell cycle, the shielding structure of the SiC MOSFET structure includes two deep P+ regions 101 arranged along the transverse (X direction) of the cell and a shallow P+ region 102 located between the two deep P+ regions 101, wherein the shallow P+ region 102 between the two deep P+ regions 101 is discontinuously arranged along the direction parallel to the trench length (i.e., the Z direction or the three-dimensional direction).

[0033] Two deep P+ regions 101 are located on either side of the cell. The deep P+ regions 101 have the first junction depth.

[0034] The shallow P+ region 102 is located between the two deep P+ regions 101. The shallow P+ region 102 has a second junction depth, which is less than the first junction depth.

[0035] In one embodiment, the first junction depth is ≥2.5 μm.

[0036] In one embodiment, the second junction depth is ≥1.8 μm.

[0037] It should be noted that the shallow P+ region 102 does not extend continuously along the direction parallel to the trench length (i.e., the Z direction or the three-dimensional direction), but is distributed intermittently.

[0038] The shallow P+ region 102 is an island-shaped or segmented structure with discontinuous arrangement. Its discontinuous regions are retained as N-type SiC, providing a three-dimensional current path along the direction parallel to the trench length.

[0039] In addition, the distance between each P+ region can have the following relationship: In the lateral dimension design, the lateral spacing between the deep P+ region 101 and its adjacent shallow P+ region 102 is defined as W1; the lateral spacing between two adjacent deep P+ regions 101 is defined as W2+W3, where W2 is the lateral distance between the right side of the right deep P+ region in the cell and the nearest cell dividing line; W3 is the lateral distance between the left side of the left deep P+ region in the cell and the nearest cell dividing line.

[0040] It should be noted here that the lateral distance between two adjacent deep P+ regions 101 refers to the lateral distance between the right deep P+ region and the left deep P+ region of the adjacent cell on the right (not shown). Therefore, the lateral distance can be obtained as W2+W3.

[0041] In one embodiment, the lateral spacing W1 between the deep P+ region 101 and its adjacent shallow P+ region 102 is less than the lateral distance W2+W3 between two adjacent deep P+ regions 101, that is, W1 is less than W2+W3.

[0042] The specific dimensions of W1, W2, and W3 can be adjusted based on the ability to control the electric field at the bottom of the trench.

[0043] Figure 2 Show Figure 1 The diagram shows a cross-sectional view of the SiC trench gate MOSFET structure along the AA' direction (i.e., a schematic diagram in the vertical or depth direction).

[0044] The positional relationship between the shielding structure and the trench structure in the SiC MOSFET structure of the present invention is as follows: Figure 2 As shown. The trench structure includes multiple adjacent trenches, wherein a gate oxide layer (SiO2) is grown on the inner wall of each trench, and each trench is filled with a polysilicon gate. From Figure 2 As can be seen, there are multiple trenches (201, 202, 203, 204) with different widths and depths arranged between the two deep P+ zones 101, between the deep P+ zone 101 and the shallow P+ zone 102, and within the shallow P+ zone.

[0045] In one embodiment, the trench structure may include a first trench 201, a second trench 202, a third trench 203, and a fourth trench 204. The first trench 201 and the fourth trench 204 have the same depth and width.

[0046] In one embodiment, the first trench 201 is located between two adjacent deep P+ regions 101, having a trench flow path. The first trench 201 has the smallest width and the largest depth. It should be noted that, although in Figure 2 The trench 201 shown may not appear to be between two adjacent deep P+ regions, but those skilled in the art will understand that the trench 201 is actually located between the right deep P+ region and the left deep P+ region of the adjacent cell (not shown) on the right. In other words, the two adjacent deep P+ regions mentioned herein refer to two adjacent deep P+ regions that originate from two adjacent cells and cross the cell boundary line.

[0047] In one embodiment, the second trench 202 is located between the deep P+ region 101 and the shallow P+ region 102, with the second widest and the smallest depth, and has a trench flow path.

[0048] In one embodiment, the third trench 203 partially overlaps with the deep P+ region 101, having the largest width followed by the second largest depth. Furthermore, the deep P+ region 101 may overlap only with the first sidewall 210 of the third trench 203, while the lower part of the second sidewall 211 on the other side of the third trench 203 is not shielded by the deep P+ region to preserve the flow path.

[0049] In one embodiment, a fourth trench 204 is arranged in the shallow P+ region, and the structure of the fourth trench 204 is the same as that of the first trench 201 between the two deep P+ regions 101. Furthermore, the fourth trench 204 allows flow through the interval region of the shallow P+ region in the trench length direction (three-dimensional direction).

[0050] The trench structure design of this invention, while reducing the gate oxide electric field, makes full use of the effective size to add trench structures with different widths and depths, which significantly improves the current carrying capacity of the device.

[0051] Furthermore, under short-circuit conditions, this structural design utilizes the deep P+ region combined with the shallow P+ region to form depletion expansion, reducing short-circuit current. The trench with the smallest width and largest depth between the two deep P+ regions forcibly splits the short-circuit current in the JFET region and induces current flow from the depletion expansion high-resistance region, further reducing the short-circuit current. Simultaneously, the deep trench overlapping the intermittent shallow P+ region can also forcibly split the short-circuit current and induce current flow from the depletion expansion high-resistance region, reducing the short-circuit current. This achieves an optimized trade-off between on-resistance and short-circuit capability.

[0052] The present invention also provides a method for manufacturing a SiC trench gate MOSFET structure.

[0053] Figure 3 The diagram shows a SiC epitaxial wafer and the cross-sectional structure after sequential ion implantation of the P-type base, N+ source region, and P+ shielding region on the SiC epitaxial wafer, corresponding to step (1) of the manufacturing method.

[0054] Step (1): Provide a SiC epitaxial wafer, and sequentially implant P-type base region 303, N+ source region 304, deep P+ region 101 and shallow P+ region 102 on the SiC epitaxial wafer, wherein the deep P+ region 101 and shallow P+ region 102 form a shielding structure.

[0055] Combination Figure 3 As shown, the SiC epitaxial wafer includes a high-concentration N+ type substrate 301 and an N- type drift region 302 epitaxially grown on the substrate.

[0056] In one embodiment, the doping concentration of the high-concentration N+ type substrate 301 is approximately greater than 5 × 10¹. 8 cm - ³.

[0057] In one embodiment, the doping concentration of the N-type drift region 302 is approximately 1 × 10¹ 4 ~9×10¹ 6 cm - ³. The specific concentration and thickness of the drift region need to be optimized based on the chip's voltage withstand capability.

[0058] The P-type base region 303 is the P-type base region where the device channel is located. In one embodiment, its doping concentration ranges from approximately 8 × 10¹. 5 ~1×10¹ 8 cm - ³, the longitudinal junction depth is about 0.2~0.4μm; to ensure the channel length and gate control capability, the distance between the upper surface of the P-type base region 303 and the SiC surface is ≥0.4μm, that is, an N-type layer of appropriate thickness is also retained above the P-type base region.

[0059] The N+ source region 304 is formed above the P-type base region 303, and the entire region above the P-type base region 303 is the N+ source region 304.

[0060] In one embodiment, the doping concentration of the N+ source region 304 is approximately greater than 1 × 10¹ 8 cm - ³.

[0061] The deep P+ region 101 is located on both sides of the cell, extending downwards from the SiC surface through the N+ source region 304, the P-type base region 303, and into the N-type drift region 302.

[0062] In one embodiment, the vertical junction depth of the deep P+ region 101 is ≥2.5 μm, and the doping concentration is ≥5 × 10¹. 7cm - ³.

[0063] The shallow P+ region 102 is located midway between the two deep P+ regions 101, extending downwards from the SiC surface through the N+ source region 304 and the P-type base region 303 into the N-type drift region 302. Along the length of the trench, the shallow P+ region 102 can be designed with a discontinuous distribution. The longitudinal junction depth of the shallow P+ region 102 is less than that of the deep P+ region 101.

[0064] In one embodiment, the vertical junction depth of the shallow P+ region 102 is ≥1.8 μm, and the doping concentration is ≥5 × 10¹. 7 cm - ³.

[0065] In addition, the lateral spacing (W1) between the deep P+ region 101 and the shallow P+ region 102 structures must be smaller than the lateral spacing (W2+W3) between the deep P+ and deep P+ structures. The specific dimensions of W1, W2, and W3 can be adjusted in conjunction with the electric field control capability at the bottom of the trench.

[0066] refer to Figure 3 In terms of lateral dimension design, the lateral spacing between the deep P+ region 101 and its adjacent shallow P+ region 102 is defined as W1; the lateral spacing between two adjacent deep P+ regions 101 is W2+W3, where W2 is the distance between the right side of the right deep P+ region in the cell and the nearest cell dividing line; and W3 is the distance between the left side of the left deep P+ region in the cell and the nearest cell dividing line.

[0067] It should be noted here that the lateral distance between two adjacent deep P+ regions 101 refers to the lateral distance between the right deep P+ region and the left deep P+ region of the adjacent cell on the right (not shown). Therefore, this lateral distance can be obtained as W2+W3.

[0068] In one embodiment, the lateral spacing W1 between the deep P+ region 101 and its adjacent shallow P+ region 102 is less than the lateral distance W2+W3 between two adjacent deep P+ regions 101, that is, W1 is less than W2+W3.

[0069] Figure 4 and Figure 5 The process for fabricating differentiated trenches according to an embodiment of the present invention is illustrated. Figure 4 To deposit and pattern the structure after the double-layer etched mask, the corresponding manufacturing method is step (2); Figure 5 To further differentiate the trench structure formed after SiC etching, the corresponding manufacturing step (3) is performed.

[0070] Step (2): First, deposit a thick etching mask, then pattern the etching mask at the corresponding locations where trenches need to be formed to create mask openings of different lateral sizes; then deposit a thin etching mask and further pattern the etching to form openings such as... Figure 4 The mask structure 401. The lateral dimension of the mask opening gradually decreases from the deep P+ region to the shallow P+ region (i.e., the opening size: third structure 3 > second structure 2 > first structure 1), and there is no mask only at the opening with the smallest lateral dimension (i.e., the first structure 1), while the aforementioned thin etch mask exists at the other openings.

[0071] In one embodiment, the thickness of the thin etching mask can be 50nm-200nm.

[0072] Step (3): Utilizing the differences in the coverage state of thin etched masks at different openings and the etching load effect, trench structures with different widths and depths are simultaneously formed on the same SiC wafer through a one-step etching process (for example, the first trench 201 is the first structure 1, the second trench 202 is the second structure 2, the third trench 203 is the third structure 3, and the fourth trench 204 is the first structure 1). Among them, from the deep P+ region to the shallow P+ region, the lateral dimension of the trench gradually decreases (i.e., the lateral dimension of the trench: the third structure 3 > the second structure 2 > the first structure 1), and the longitudinal dimension of the trench first decreases and then increases (i.e., the longitudinal dimension of the trench: the first structure 1 > the third structure 3 > the second structure 2).

[0073] Specifically, the first trench 201 is located between two deep P+ zones, with the smallest width and the deepest depth. The second trench 202 is located between the deep P+ zone 101 and the shallow P+ zone 102, forming a trench flow path, with its width between the first trench 201 and the third trench 203, and its shallowest depth. The third trench 203 partially overlaps with the deep P+ zone 101, that is, one sidewall of the third trench 203 overlaps with the deep P+ zone 101, and the other sidewall of the third trench 203 is not shielded by the deep P+ zone 101, retaining an N-type flow path; it has the largest width, and its depth is between the first trench 201 and the second trench 202; the fourth trench 204 is completely located within the shallow P+ zone 102, and its size and structure can be the same as the first trench 201.

[0074] In one embodiment, Figure 5 The transverse dimensions of different grooves can be distributed between 0.2μm and 0.8μm, and the longitudinal dimensions can be distributed between 0.9μm and 1.8μm.

[0075] Figure 6 The cross-sectional structure is shown after the trench etching is completed, followed by high-temperature activation, fillet treatment, gate oxide growth, gate polysilicon filling and etch-back, interlayer dielectric deposition, and source contact hole opening. This corresponds to step (4) of the manufacturing method.

[0076] Step (4): The trench structure is subjected to ion implantation for high-temperature activation and trench rounding. Subsequently, gate oxide growth, gate polysilicon filling and etch-back, interlayer dielectric deposition, and source contact hole formation are completed sequentially to prepare the gate structure and source contact. Specifically, photoresist is used for trench filling and carbonization, and the trench structure is protected by a carbon film and activated at, for example, 1800°C. After completion, the carbon film is removed, and the top and bottom corners of the trench are rounded in, for example, H2 atmosphere at 1400°C. Subsequently, trench gate oxide, gate POLY filling, trench surface POLY etch-back, interlayer dielectric deposition, and source alloy hole opening processes are performed respectively.

[0077] Figure 7 The complete device cross-sectional structure after all front-side metallization and back-side processing is shown, corresponding to step (5) of the manufacturing method.

[0078] Step (5): Perform source metallization on the front side and substrate thinning and drain metallization on the back side to form the source electrode and drain electrode. Specifically, in Figure 6 Based on this, Ni source alloy sputtering and alloying, Wu metal 701 filling, and front-side source metal 702 thickening are performed. Finally, the back-side structure undergoes substrate thinning, Ni metal 704 sputtering, laser annealing to form an ohmic alloy, and drain metal 703 thickening. The final structure is as follows. Figure 7 As shown.

[0079] This invention has the following innovative features: Firstly, this structure employs a combination of deep P+ regions on both sides and a discontinuous shallow P+ region in the middle to reduce the gate oxide electric field at the bottom of the trench (the junction depth of the deep P+ region is greater than that of the shallow P+ region). Simultaneously, a trench with the smallest width and largest depth is designed for current flow between the two deep P+ regions; a trench with the second smallest width and smallest depth is designed for current flow between the deep and shallow P+ regions; a trench with the largest width and second deepest depth is designed in the overlapping area with the deep P+ regions, with the deep P+ regions only overlapping with one side of the trench, allowing current flow on the other side; and a trench with the same structure as the one between the two deep P+ regions is designed in the shallow P+ region, allowing current flow through discontinuous non-shallow P+ regions in three dimensions. This structural design, while reducing the gate oxide electric field, fully utilizes the available space to add trench structures with varying widths and depths, significantly improving the device's current-carrying capacity.

[0080] Secondly, under short-circuit conditions, this structural design utilizes the deep P+ region combined with the shallow P+ region to form depletion expansion, reducing the short-circuit current. The trench with the smallest width and largest depth between the two deep P+ regions (e.g., the first trench) forcibly splits the short-circuit current in the JFET region and induces current flow from the depletion expansion high-resistance region, thus reducing the short-circuit current. Simultaneously, the deep trench (e.g., the fourth trench) that overlaps with the intermittent shallow P+ region can also forcibly split the short-circuit current and induce current flow from the depletion expansion high-resistance region, further reducing the short-circuit current. This achieves an optimized trade-off between on-resistance and short-circuit capability.

[0081] Thirdly, in this structural design, by utilizing the differences in the coverage state of thin etched masks at different openings and the etch load effect, trench structures with different widths and depths are formed simultaneously through a one-step etch process.

[0082] It should be noted that the numerical range of the parameters described in this invention allows for process fluctuations of ±20%.

[0083] Furthermore, the SiC trench gate MOSFET of the present invention is not limited to the structure described above. Without departing from the essential spirit of the invention, the trench gate MOSFET of the present invention can have various modified structures, and several exemplary, but not limiting, embodiments are described below.

[0084] Figure 8 and Figure 9 A variant embodiment of the present invention is shown, wherein, Figure 8 This is a top view. Figure 9 for Figure 8 The AA' cross-sectional view. This variant embodiment is similar to... Figure 1 and Figure 2 The main structures of the embodiments shown are basically the same, and the identical parts will not be described again. The difference between the two is that this variant embodiment additionally provides a first P+ injection region 901 at the bottom of the trench with the smallest lateral dimension to further increase the flow path. In addition, in this variant embodiment, the shallow P+ region is continuous along the direction parallel to the length of the trench.

[0085] Figure 10 and Figure 11 A variant embodiment of the present invention is shown, wherein, Figure 10 This is a top view. Figure 11 for Figure 10 The AA' cross-sectional view. This variant embodiment is similar to... Figure 1 and Figure 2 The main structure of the embodiments shown is basically the same, and the same parts will not be described again. The difference between the two is that the modified embodiment designs more grooves between the deep P+ region and the shallow P+ region, including the fifth groove 1101 and the sixth groove 1102, to increase the flow path.

[0086] The fifth trench 1101 is located between the third trench 203 and the second trench 202, and has a trench flow path. Its width and depth are between those of the third trench 203 and the second trench 202. The sixth trench 1102 is located between the second trench 202 and the fourth trench 204, and has a trench flow path. Its width and depth are between those of the second trench 202 and the fourth trench 204, and its depth is less than that of the second trench 202. It should be noted that the fifth trench 1101 and the sixth trench 1102 can coexist, or only one of them can exist, to adapt to different flow requirements.

[0087] Figure 12 and Figure 13 A variant embodiment of the present invention is shown, wherein, Figure 12 This is a top view. Figure 13 for Figure 12 The AA' cross-sectional view. This variant embodiment is similar to... Figure 1 and Figure 2 The main structures of the embodiments shown are basically the same, and the same parts will not be described again. The difference between the two is that the modified embodiment designs more trenches between the deep P+ region and the shallow P+ region, including the seventh trench 1301 and the eighth trench 1302. The seventh trench 1301 has the same structure as the fifth trench 1101, and the eighth trench 1302 has the same structure as the sixth trench 1102. In addition, a second P+ injection region 1303 is additionally provided at the bottom of the trench with the smallest lateral dimension to further increase the flow path.

[0088] Figure 14 , Figure 15 , Figure 16 The main structure of the present invention is shown ( Figure 1 and Figure 2 Based on this, further evolution schemes combining semi-superjunction or superjunction structures are proposed. Among them, Figure 14 This is a top view. Figure 15 for Figure 14 AA' section diagram, Figure 16 for Figure 14 The BB' cross-sectional diagram shows that, in the N-type drift region, in addition to the aforementioned deep P+ region, shallow P+ region, and differentiated trench structure, alternating P-regions 1501 and CSL2 (Current Spread Layer 2) regions 1601 are introduced to form a semi-superjunction or superjunction structure. The doping concentration of P-region 1501 ranges from approximately 1 × 10¹. 5 ~1×10¹ 8 cm - ³, the doping concentration range of CSL2 region 1601 is 1×10¹ 5 ~1×10¹ 8 cm -³. The stripes of P-zone 1501 and CSL2 zone 1601 can be designed to be perpendicular to the P+ strip structure (P+ strip structure refers to the deep P+ zone / shallow P+ zone strip structure).

[0089] In addition, the strip design of the P-area and CSL2 area can also be parallel to the P+ strip structure, such as... Figure 17 As shown; or designed to intersect the P+ strip structure at any angle, such as... Figure 18 As shown. The width of the strip structures in the P-region and CSL2 region can be adjusted according to the corresponding concentration.

[0090] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0091] Furthermore, the terms "upper," "lower," "left," "right," "top," "bottom," "horizontal," and "vertical" used in the following description should be understood as the orientations shown in the relevant paragraphs and accompanying drawings. These relative terms are for illustrative purposes only and do not imply that the described apparatus must be manufactured or operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0092] It is understood that while terms such as "first," "second," and "third" may be used herein to describe various components, channels, assemblies, regions, layers, and / or parts, these components, channels, assemblies, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different components, channels, assemblies, regions, layers, and / or parts. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0093] As indicated in this application, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0094] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used to describe embodiments are sometimes modified by the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used are approximate values, which may be changed depending on the characteristics required by the individual embodiment. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit preservation. Although the numerical ranges and parameters used to confirm their breadth of range in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

[0095] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic related to at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0096] The terms and expressions used above are for descriptive purposes only, and the present invention should not be limited to these terms and expressions.

[0097] Similarly, it should be noted that, in order to simplify the description of the present application and thus help in understanding one or more embodiments of the invention, the foregoing description of the embodiments of the present application may sometimes combine multiple features into one embodiment, drawing or description thereof.

[0098] Similarly, it should be noted that although the present invention has been described with reference to specific embodiments, those skilled in the art should recognize that the above embodiments are only used to illustrate the present invention, and various equivalent changes or substitutions can be made without departing from the spirit of the present invention.

Claims

1. A SiC MOSFET device structure, characterized in that, include: N+ type SiC substrate and N- type drift region formed on the N+ type SiC substrate; The P-type base region and N+ source region are formed on the upper part of the N-type drift region; A shielding structure formed within a cell, the shielding structure extending sequentially through the N+ source region and the P-type base region into the N-type drift region, the shielding structure including deep P+ regions located on both sides of the cell and shallow P+ regions located between the two deep P+ regions; the junction depth of the deep P+ regions is greater than the junction depth of the shallow P+ regions; the lateral spacing between the deep P+ regions and the adjacent shallow P+ regions is less than the lateral spacing between the two adjacent deep P+ regions; The groove structure formed within the cell includes multiple grooves. As the multiple grooves are arranged from the deep P+ region to the shallow P+ region, the lateral width of each groove gradually decreases, and the longitudinal depth of each groove first decreases and then increases.

2. The SiC MOSFET device structure as described in claim 1, characterized in that, The lateral distance between the deep P+ region and the shallow P+ region is W1. The lateral distance from the outer edge of the deep P+ region on one side of the cell to the nearest cell boundary line is W2. The lateral distance from the outer edge of the deep P+ region on the other side of the cell to the nearest cell boundary line is W3. And W1 is less than the sum of W2 and W3.

3. The SiC MOSFET device structure as described in claim 1, characterized in that, The plurality of trenches includes at least a first trench, a second trench, a third trench, and a fourth trench; The first trench is located between two adjacent deep P+ regions and has a trench flow path. The first trench has the smallest width and the deepest depth. The two adjacent deep P+ regions refer to two adjacent deep P+ regions that come from adjacent cells and cross the cell boundary line. The second trench is located between the deep P+ region and the shallow P+ region and has a trench flow path. The width of the second trench is between the first trench and the third trench, and the depth is the shallowest. The third trench partially overlaps with the deep P+ region, wherein one sidewall of the third trench overlaps with the deep P+ region, and the other sidewall of the third trench is not shielded by the deep P+ region to retain the flow path; the third trench has the largest width and its depth is between the first trench and the second trench. The fourth trench is located at the same position as the shallow P+ region, and the size and structure of the fourth trench are the same as those of the first trench.

4. The SiC MOSFET device structure as described in claim 3, characterized in that, The plurality of trenches also includes a fifth trench, which is located between the third trench and the second trench and has a trench flow path. The width of the fifth trench is between the third trench and the second trench, and the depth is between the third trench and the second trench.

5. The SiC MOSFET device structure as described in claim 3, characterized in that, The plurality of trenches also includes a sixth trench, which is located between the second trench and the fourth trench and has a trench flow path. The width of the sixth trench is between the second trench and the fourth trench, and the depth is less than that of the second trench.

6. The SiC MOSFET device structure as described in claim 3, characterized in that, The shallow P+ zones are intermittently arranged along the length of the trench.

7. The SiC MOSFET device structure as described in claim 6, characterized in that, The fourth trench forms a three-dimensional flow path through the discontinuous region of the shallow P+ zone.

8. The SiC MOSFET device structure as described in claim 3, characterized in that, An additional P+ injection zone is provided at the bottom of the fourth trench, which has the smallest width.

9. The SiC MOSFET device structure as described in claim 1, characterized in that, An odd number of grooves are provided between two adjacent deep P+ regions.

10. The SiC MOSFET device structure as described in claim 1, characterized in that, The N-type drift region is also combined with a semi-superjunction or superjunction structure, which includes alternating P-regions and current spreading layers, wherein the stripe orientation of the P-regions and the current spreading layers is perpendicular to the stripe orientation of the shielding structure, or parallel to the stripe orientation of the shielding structure, or intersects the stripe orientation of the shielding structure at any angle.

11. A method for manufacturing a SiC MOSFET device structure as described in any one of claims 1 to 10, characterized in that, Includes the following steps: A SiC epitaxial wafer is provided, and ion implantation of the P-type base region, the N+ source region, the deep P+ region and the shallow P+ region are performed sequentially on the SiC epitaxial wafer; The deep P+ region and the shallow P+ region form the shielding structure, and the epitaxial wafer includes the N+ type SiC substrate and the N- type drift region formed thereon; A thick etch mask is deposited, and the thick etch mask is patterned at the corresponding positions where the trenches need to be formed to form mask openings of different lateral sizes; Then, a thin etching mask is deposited for further patterned etching. The lateral size of the mask opening gradually decreases from the deep P+ region to the shallow P+ region. There is no mask only at the mask opening with the smallest lateral size, while the thin etching mask is present at the other mask openings. By utilizing the differences in the coverage state of thin etched masks at different openings and the etch load effect, the trench structures with different widths and depths can be formed simultaneously through a one-step etch process.

12. The method as described in claim 11, characterized in that, Also includes: The trench structure is subjected to high-temperature activation by ion implantation and trench rounding treatment. Subsequently, gate oxide layer growth, gate polysilicon filling and etch-back, interlayer dielectric deposition and source contact hole formation are completed in sequence to prepare the gate structure and source contact. The source electrode and drain electrode are formed by performing source metallization on the front side and substrate thinning and drain metallization on the back side.

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