Semiconductor device, semiconductor wafer, inspection method, and method for manufacturing semiconductor device

Abstract

Embodiments of the present application generally relate to a semiconductor device, a semiconductor wafer, an inspection method, and a manufacturing method of a semiconductor device. A semiconductor device of an embodiment includes a first semiconductor region, first and second insulating regions, first to fourth high concentration layers, and a first and second contact pair. The first semiconductor region has an impurity concentration that decreases from a lower surface to an upper surface. The first and second insulating regions are disposed from the upper surface to the lower surface, and lower ends are located at a height where the impurity concentration of the first semiconductor region is a first concentration and a second concentration lower than the first concentration, respectively. The first contact pair has first and second contact portions electrically connected to the first and second high concentration layers, respectively, sandwiching the first insulating region in a third direction. The second contact pair has third and fourth contact portions electrically connected to the third and fourth high concentration layers, respectively, sandwiching the second insulating region in the third direction.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2025-045772 (filed on March 19, 2025). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] Embodiments of the present invention generally relate to semiconductor devices, semiconductor wafers, inspection methods, and methods for manufacturing semiconductor devices. Background Technology

[0004] Semiconductor devices are known to have semiconductor regions with multiple stacked epitaxial growth layers. In such semiconductor devices, it is sometimes difficult to inspect the quality of the epitaxial growth layers. Summary of the Invention

[0005] The semiconductor device of the embodiment includes a first semiconductor region, a first insulating region, a second insulating region, first and second high-concentration layers, third and fourth high-concentration layers, a first contact pair, and a second contact pair. In the first semiconductor region, along a first direction which is the thickness direction, the impurity concentration of a first or second conductivity type decreases from the lower surface to the upper surface. The first insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, with its lower end located at a height where the impurity concentration of the first semiconductor region is a first concentration, and the first insulating region extends in a second direction orthogonal to the first direction. The second insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, with its lower end located at a height where the impurity concentration of the first semiconductor region is a second concentration lower than the first concentration, and the second insulating region extends in the second direction. The first and second high-concentration layers are disposed on the upper surface of the first semiconductor region, sandwiching the first insulating region in a third direction orthogonal to the first and second directions. The third and fourth high-concentration layers are disposed on the upper surface of the first semiconductor region, sandwiching the second insulating region in the third direction. The first contact pair has a first contact portion electrically connected to the first high-concentration layer and a second contact portion electrically connected to the second high-concentration layer. The second contact pair has a third contact portion electrically connected to the third high-concentration layer and a fourth contact portion electrically connected to the fourth high-concentration layer.

[0006] The semiconductor wafer of the embodiment includes: a first semiconductor region, in which the impurity concentration of a first or second conductivity type decreases from a lower surface to an upper surface along a first direction that is a thickness direction; a first insulating region, which is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the first insulating region being located at a height where the impurity concentration of the first semiconductor region is a first concentration, and the first insulating region extending in a second direction orthogonal to the first direction; and a second insulating region, which is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the second insulating region being located at a height where the impurity concentration of the first semiconductor region is lower than the first concentration. The concentration of the second insulating region extends in the second direction; first and second high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the first insulating region in a third direction orthogonal to the first and second directions; third and fourth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the second insulating region in the third direction; a first contact pair has a first contact portion electrically connected to the first high-concentration layer and a second contact portion electrically connected to the second high-concentration layer; and a second contact pair has a third contact portion electrically connected to the third high-concentration layer and a fourth contact portion electrically connected to the fourth high-concentration layer.

[0007] The inspection method described in this implementation is used to determine the quality of a semiconductor region and includes the following steps:

[0008] A semiconductor device is prepared, comprising: a first semiconductor region, wherein, along a first direction which is a thickness direction, the impurity concentration of a first or second conductivity type decreases from a lower surface toward an upper surface; a first insulating region, which extends from the upper surface of the first semiconductor region toward a lower surface of the first semiconductor region, the lower end of the first insulating region being at a height where the impurity concentration of the first semiconductor region is a first concentration, and the first insulating region extending in a second direction orthogonal to the first direction; and a second insulating region, which extends from the upper surface of the first semiconductor region toward a lower surface of the first semiconductor region, the lower end of the second insulating region being at a height where the impurity concentration of the first semiconductor region is lower than the first concentration. The second high-concentration layer extends in the second direction; first and second high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the first insulating region in a third direction orthogonal to the first and second directions; third and fourth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the second insulating region in the third direction; a first contact pair has a first contact portion electrically connected to the first high-concentration layer and a second contact portion electrically connected to the second high-concentration layer; and a second contact pair has a third contact portion electrically connected to the third high-concentration layer and a fourth contact portion electrically connected to the fourth high-concentration layer; and

[0009] The first resistance value between the first and second contact parts and the second resistance value between the third and fourth contact parts are measured.

[0010] The method for manufacturing the semiconductor device according to the embodiment includes the following steps:

[0011] Prepare the substrate;

[0012] By forming a first epitaxial growth layer of a first or second conductivity type with a first impurity concentration of a first concentration on the substrate, forming a second epitaxial growth layer with a second impurity concentration of a lower than the first concentration on the first epitaxial growth layer, and forming a third epitaxial growth layer with a third impurity concentration of a lower than the second concentration on the second epitaxial growth layer, a first semiconductor region comprising the first to third epitaxial growth layers and wherein the impurity concentration decreases along a first direction which is the thickness direction is formed on the substrate.

[0013] A first trench is formed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region to a height where the impurity concentration is the first concentration, and a second trench is formed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region to a height where the impurity concentration is the second concentration;

[0014] A first insulating region is formed in the first trench, and a second insulating region is formed in the second trench;

[0015] On the upper surface of the first semiconductor region, first and second high-concentration layers are formed in a third direction orthogonal to the first and second directions, sandwiching the first insulating region, and third and fourth high-concentration layers are formed in the third direction, sandwiching the second insulating region; and

[0016] First and second contact portions electrically connected to the first and second high-concentration layers, and third and fourth contact portions electrically connected to the third and fourth high-concentration layers are formed.

[0017] The semiconductor device of the embodiment includes: a first semiconductor region, in which the impurity concentration of a first or second conductivity type decreases from a lower surface to an upper surface along a first direction that is a thickness direction; a first insulating region, which is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the first insulating region being at a height where the impurity concentration of the first semiconductor region is a first concentration, and the first insulating region extending in a second direction orthogonal to the first direction; and a second insulating region, which is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the second insulating region being at the same height as the lower end of the first insulating region, and the second insulating region extending in the second direction. The second insulating region extends and has a width different from that of the first insulating region; first and second high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the first insulating region in a third direction orthogonal to the first and second directions; third and fourth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the second insulating region in a third direction; a first contact pair has a first contact portion electrically connected to the first high-concentration layer and a second contact portion electrically connected to the second high-concentration layer; and a second contact pair has a third contact portion electrically connected to the third high-concentration layer and a fourth contact portion electrically connected to the fourth high-concentration layer.

[0018] According to embodiments of the present invention, a semiconductor device having multiple epitaxial growth layers can be provided that allows for easy inspection of the quality of the epitaxial growth layers. Attached Figure Description

[0019] Figure 1 This is a top view of the semiconductor device according to the first embodiment.

[0020] Figure 2 This is a cross-sectional view of the semiconductor device according to the first embodiment.

[0021] Figure 3 It is a graph showing the relationship between the resistance value and the electric field strength of the first semiconductor region in the semiconductor device of the first embodiment.

[0022] Figure 4 This is a schematic cross-sectional view illustrating an example of the operation of the semiconductor device according to the first embodiment.

[0023] Figure 5A This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0024] Figure 5B It continues Figure 5A A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0025] Figure 5C It continues Figure 5B A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the first embodiment.

[0026] Figure 6 This is a cross-sectional view showing an example of the operation of a semiconductor device, a variation of the first embodiment.

[0027] Figure 7 This is a cross-sectional view of the semiconductor device according to the second embodiment.

[0028] Figure 8A This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the second embodiment.

[0029] Figure 8B It continues Figure 8A A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the second embodiment.

[0030] Figure 8C It continues Figure 8B A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the second embodiment.

[0031] Figure 8D It continues Figure 8CA cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the second embodiment.

[0032] Figure 8E It continues Figure 8D A cross-sectional view illustrating an example of the manufacturing process of the semiconductor device according to the second embodiment.

[0033] Figure 9 This is a cross-sectional view of the semiconductor device according to the third embodiment. Detailed Implementation

[0034] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. These embodiments do not limit the present invention. The drawings are schematic or conceptual, and the proportions of the parts may not be identical to reality. In the specification and drawings, elements identical to those described in previously existing drawings are labeled with the same reference numerals, and detailed descriptions are appropriately omitted.

[0035] Additionally, for ease of explanation, such as Figure 1 and Figure 2 As shown, an orthogonal XYZ coordinate system is used. The Z-axis direction is the stacking direction (thickness direction) of the semiconductor device. Additionally, the source electrode side in the Z-axis direction is also referred to as "upper," and the drain electrode side as "lower." However, this expression is for convenience and is independent of the direction of gravity. The Z-axis direction is the first direction in the claims. The Y-axis direction is the second direction in the claims. The X-axis direction is the third direction in the claims.

[0036] Furthermore, in the following explanations, to indicate the relative levels of impurity concentration for each conductivity type, the terms n+, n, n- and p+, p, p- are sometimes used. That is, n+ indicates a relatively higher n-type impurity concentration compared to n, and n- indicates a relatively lower n-type impurity concentration compared to n. Additionally, p... + The terms "p" and "n" indicate a relatively high concentration of p-type impurities compared to "p," while "p-" indicates a relatively low concentration of p-type impurities compared to "p." In cases where both p-type and n-type impurities are present in each region, these expressions represent the relative levels of net impurity concentration after these impurities compensate for each other. "n-type," "n+-type," and "n-type" are examples of the first conductivity type in the claims. "p-type," "p+-type," and "p-type" are examples of the second conductivity type in the claims. Furthermore, in the following description, "n-type" and "p-type" may be reversed. That is, the first conductivity type may also be p-type.

[0037] Furthermore, the impurity concentration in the semiconductor region can be measured, for example, by secondary ion mass spectrometry (SIMS). Additionally, the relative level of the impurity concentration can also be determined, for example, by the level of the carrier concentration obtained using scanning capacitance microscopy (SCM).

[0038] In addition, dimensions such as the height and width of the insulating region can be determined, for example, by surface and / or cross-sectional analysis using methods such as transmission electron microscopy (TEM), energy dispersive X-ray spectroscopy (EDX), and scanning electron microscopy (SEM).

[0039] Furthermore, the terms used in this specification, such as “same,” “identical,” “equal,” etc., which determine their degree, as well as the values ​​of dimensions and physical properties, are not limited to a strict meaning but should be interpreted as encompassing a range of degrees to which the same function can be expected.

[0040] (First Implementation)

[0041] Reference Figure 1 and Figure 2 The semiconductor device 1 of the first embodiment will be described. Figure 1 This is a top view of the semiconductor device 1 according to the first embodiment. Figure 2 This is a cross-sectional view of the semiconductor device 1 according to the first embodiment, along... Figure 1 A cross-sectional view along line AA.

[0042] like Figure 1 and Figure 2 As shown, the semiconductor device 1 of this embodiment includes a semiconductor layer 2 and contact portions 31 to 37.

[0043] like Figure 2 As shown, the semiconductor layer 2 has an upper surface 2a and a lower surface 2b on the side opposite to the upper surface 2a. The semiconductor layer 2 includes, for example, a field plate electrode (FP electrode) 13, an epitaxial growth layer 21, an epitaxial growth layer 22, an epitaxial growth layer 23, a high-concentration layer 24, a substrate 25, and insulating regions 41, 42, 43, 44, 45, and 46.

[0044] Semiconductor layer 2 includes a substrate 25 serving as a semiconductor substrate and epitaxial growth layers 21-23 disposed thereon. In this embodiment, semiconductor layer 2 is silicon (Si). In this case, arsenic (As), phosphorus (P), or antimony (Sb) is used as an n-type impurity, and boron (B) is used as a p-type impurity. In this embodiment, epitaxial growth layers 21-23, high-concentration layer 24, and substrate 25 are n-type semiconductor regions. Alternatively, phosphorus is used as an n-type impurity for epitaxial growth layers 21-23, and arsenic is used as an n-type impurity for substrate 25. Furthermore, epitaxial growth layers 21-23, high-concentration layer 24, and substrate 25 may also be p-type semiconductor regions. Additionally, semiconductor layer 2 may also be composed of compound semiconductors such as silicon carbide (SiC) or gallium nitride (GaN).

[0045] FP electrodes 13 are respectively disposed inside insulating regions 41-46. By providing FP electrodes 13, when the semiconductor device 1 is in the off state, for example by applying a reverse voltage between the drain electrode and the source electrode (not shown), the depletion layer extends from the insulating regions 41-46 where the FP electrodes 13 are disposed to the surrounding semiconductor regions. By connecting this depletion layer to the depletion layer extending from the insulating regions 41-46 where adjacent FP electrodes 13 are disposed, the withstand voltage of the semiconductor device 1 can be improved.

[0046] In addition, Figure 1 and Figure 2 In the example, the width (length in the X-axis direction) of the FP electrode 13 disposed in the insulating regions 42, 44, and 46 is longer than the width of the FP electrode 13 disposed in the insulating regions 41, 43, and 45. However, this is not a limitation; the width of the FP electrode 13 disposed in the insulating regions 42, 44, and 46 may also be the same as the width of the FP electrode 13 disposed in the insulating regions 41, 43, and 45. Alternatively, the insulating regions 41 to 46 may not contain any FP electrodes 13.

[0047] An epitaxial growth layer 21 is disposed on the substrate 25 and contains n-type or p-type impurities. In this embodiment, the impurity concentration of the epitaxial growth layer 21 is a first concentration. Furthermore, the resistivity (resistivity coefficient) of the epitaxial growth layer 21 is a first resistivity. The first resistivity is, for example, 0.03 Ω·cm. The epitaxial growth layer 21 is an example of the first epitaxial growth layer described in the claims.

[0048] An epitaxial growth layer 22 is disposed on top of an epitaxial growth layer 21 and contains impurities of the same conductivity type as the epitaxial growth layer 21. In this embodiment, the impurity concentration of the epitaxial growth layer 22 is a second concentration. This second concentration is lower than the impurity concentration of the epitaxial growth layer 21, i.e., a first concentration. Therefore, the resistivity of the epitaxial growth layer 22 is a second resistivity that is greater than the resistivity of the epitaxial growth layer 21, i.e., the first resistivity. The second resistivity is, for example, 0.17 Ω·cm. The epitaxial growth layer 22 is an example of a second epitaxial growth layer as described in the claims.

[0049] An epitaxial growth layer 23 is disposed on top of an epitaxial growth layer 22 and contains impurities of the same conductivity type as epitaxial growth layers 21 and 22. In this embodiment, the impurity concentration of the epitaxial growth layer 23 is a third concentration. This third concentration is lower than the impurity concentration of the epitaxial growth layer 22, i.e., the second concentration. Therefore, the resistivity of the epitaxial growth layer 23 is a third resistivity, which is greater than the resistivity of the epitaxial growth layer 22, i.e., the second resistivity. The third resistivity is, for example, 0.6 Ω·cm. The epitaxial growth layer 23 is an example of the third epitaxial growth layer in the claims.

[0050] A high-concentration layer 24 is disposed on top of the epitaxial growth layer 23. The high-concentration layer 24 contains impurities of the same conductivity type as the epitaxial growth layers 21-23. That is, the epitaxial growth layers 21-23, the high-concentration layer 24, and the substrate 25 have the same conductivity type. In other words, in… Figure 2 No regions with different conductivity types are provided around the insulating regions 41-46 shown. In this embodiment, the high-concentration layer 24 is an n+ type semiconductor region, and the impurity concentration of the high-concentration layer 24 is higher than the impurity concentration of the epitaxial growth layer 23. The impurity concentration of the high-concentration layer 24 is, for example, 1 × 10⁻⁶. 18 cm- 3 Above and 1×10 22 cm- 3 Therefore, ohmic contact between the high-concentration layer 24 and the contact portions 31-37 (described later) can be ensured.

[0051] like Figure 1 and Figure 2 As shown, the high-concentration layer 24 includes high-concentration layers 241, 242, 243, 244, 245, 246, and 247. High-concentration layers 241 to 247 are electrically connected to contact portions 31 to 37, which will be described later.

[0052] High-concentration layers 241 and 242 are arranged such that an insulating region 41 is sandwiched in the X-axis direction, which is orthogonal to the Z-axis and Y-axis directions. High-concentration layers 241 and 242 are examples of the ninth and tenth high-concentration layers in the claims.

[0053] The high-concentration layer 242 and the high-concentration layer 243 are arranged such that the insulating region 42 is sandwiched in the X-axis direction.

[0054] High-concentration layers 243 and 244 are disposed such that they sandwich the insulating region 43 in the X-axis direction. High-concentration layers 243 and 244 are examples of the first and second high-concentration layers in the claims.

[0055] High-concentration layers 244 and 245 are disposed such that they sandwich the insulating region 44 in the X-axis direction. High-concentration layers 244 and 245 are examples of the fifth and sixth high-concentration layers in claims.

[0056] High-concentration layers 245 and 246 are disposed such that they sandwich the insulating region 45 in the X-axis direction. High-concentration layers 245 and 246 are examples of the third and fourth high-concentration layers in the claims.

[0057] High-concentration layers 246 and 247 are disposed such that they sandwich the insulating region 46 in the X-axis direction. High-concentration layers 246 and 247 are examples of the seventh and eighth high-concentration layers in the claims.

[0058] like Figure 1 As shown, high-concentration layers 241-247 extend in the Y-axis direction, which is orthogonal to the Z-axis direction. Alternatively, high-concentration layers 241-247 may also extend to a predetermined length in the Y-axis direction. In this case, for example, high-concentration layer 242 may also extend in... Figure 1 The upper part of the middle connects the insulating region 41 and the insulating region 42.

[0059] Furthermore, in the following description, without distinguishing between high-concentration layers 241 to 247, they are collectively referred to as high-concentration layer 24.

[0060] like Figure 2 As shown, substrate 25 is located below epitaxial growth layer 21. Substrate 25 contains impurities of the same conductivity type as epitaxial growth layers 21-23. In this embodiment, the impurity concentration of substrate 25 is higher than the impurity concentration, i.e., the first concentration, of epitaxial growth layer 21. Therefore, the resistivity of substrate 25 is lower than the resistivity, i.e., the first resistivity, of epitaxial growth layer 21. The resistivity of substrate 25 is, for example, 1 mΩ·cm.

[0061] Epitaxial growth layers 21, 22, and 23, along with substrate 25, constitute the first semiconductor region as described in the claims. Specifically, in epitaxial growth layers 21, 22, and 23, and substrate 25, which constitute the first semiconductor region, along the Z-axis direction (the thickness direction of semiconductor layer 2), the concentration of n-type impurities decreases from the lower surface of the first semiconductor region towards the upper surface. Furthermore, in... Figure 2 In this example, the lower surface of the first semiconductor region (the lower surface of the substrate 25) is located on the lower surface 2b of the semiconductor layer 2. On the other hand, the upper surface of the first semiconductor region (the upper surface of the epitaxial growth layer 23) is in contact with the lower surface of the high-concentration layer 24. The upper surface of the high-concentration layer 24 is located on the upper surface 2a of the semiconductor layer 2.

[0062] Furthermore, in this embodiment, the first semiconductor region has three epitaxial growth layers 21 to 23. However, it is not limited to this; the first semiconductor region may also have two or more epitaxial growth layers. When the first semiconductor region has multiple epitaxial growth layers, each epitaxial growth layer may also have a certain impurity concentration, with the impurity concentration decreasing stepwise from the lower surface to the upper surface of the first semiconductor region. Alternatively, the impurity concentration in the first semiconductor region may decrease continuously from the lower surface to the upper surface. In the case of a continuously decreasing impurity concentration, the first semiconductor region may have one epitaxial growth layer where the impurity concentration decreases continuously from the lower surface to the upper surface.

[0063] In addition, Figure 2 The diagram shows the boundaries between the substrate 25 and the epitaxial growth layer 21, the boundaries between the epitaxial growth layer 21 and the epitaxial growth layer 22, and the boundaries between the epitaxial growth layer 22 and the epitaxial growth layer 23. However, in actual semiconductor devices 1, the impurity concentrations of the substrate 25 and the epitaxial growth layers 21-23 may vary continuously due to heat treatment. Therefore, their boundaries may not be clearly defined.

[0064] The insulating regions 41 to 46 are all disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region. The insulating regions 41 to 46 may contain, for example, silicon oxide or silicon nitride.

[0065] The lower end of the insulating region 41 is located at a height (position in the Z-axis direction) where the impurity concentration in the first semiconductor region is higher than the first concentration. In this embodiment, the lower end of the insulating region 41 is located at the same height as the boundary between the substrate 25 and the epitaxial growth layer 21. The insulating region 41 is an example of the fifth insulating region in the claims.

[0066] The lower end of the insulating region 42 is at the same height as the lower end of the insulating region 41. That is, the lower end of the insulating region 42 is at a height where the impurity concentration in the first semiconductor region is higher than the first concentration. In this embodiment, the lower end of the insulating region 42 is at the same height as the boundary between the substrate 25 and the epitaxial growth layer 21. In addition, the width of the insulating region 42 is different from the width of the insulating region 41.

[0067] The lower end of the insulating region 43 is located at a height where the impurity concentration of the first semiconductor region is a first concentration. In this embodiment, the lower end of the insulating region 43 is located at the same height as the boundary between the epitaxial growth layer 21 and the epitaxial growth layer 22. The insulating region 43 is an example of the first insulating region in the claims.

[0068] The lower end of insulating region 44 is at the same height as the lower end of insulating region 43. That is, the lower end of insulating region 44 is located at a height where the impurity concentration of the first semiconductor region is a first concentration. In this embodiment, the lower end of insulating region 44 is at the same height as the boundary between epitaxial growth layer 21 and epitaxial growth layer 22. Furthermore, the width of insulating region 44 is different from the width of insulating region 43. Insulating region 43 is an example of the third insulating region in the claims.

[0069] The lower end of the insulating region 45 is located at a height where the impurity concentration of the first semiconductor region is the second concentration. In this embodiment, the lower end of the insulating region 45 is located at the same height as the boundary between the epitaxial growth layer 22 and the epitaxial growth layer 23. The insulating region 45 is an example of the second insulating region in the claims.

[0070] The lower end of insulating region 46 is at the same height as the lower end of insulating region 45. That is, the lower end of insulating region 46 is located at a height where the impurity concentration of the first semiconductor region is the second concentration. In this embodiment, the lower end of insulating region 46 is at the same height as the boundary between epitaxial growth layer 22 and epitaxial growth layer 23. Furthermore, the width of insulating region 46 is different from the width of insulating region 45. Insulating region 46 is an example of the fourth insulating region in the claims.

[0071] In addition, such as Figure 1 As shown, insulating regions 41-46 extend in the Y-axis direction. In this embodiment, insulating regions 41-46 extend in the Y-axis direction by at least a length d. The length d is, for example, 10 μm. Furthermore, the length d can be longer or shorter than 10 μm, as long as the current path can pass through the bottom of the insulating regions 41-46 in the Z-axis direction when measuring the resistance of the first semiconductor region. Therefore, the resistivity of the epitaxial growth layers 21-23 can be appropriately measured.

[0072] In addition, in this embodiment, such as Figure 1 As shown, the insulating region 41 is also arranged such that it sandwiches both ends of the insulating regions 41-46 in the Y-axis direction. That is, the portion of the insulating region 41 extending in the Y-axis direction and one end of the insulating regions 42-46 in the Y-axis direction ( Figure 1The upper end of the insulating region 41 (extending along the X-axis) is connected to the insulating region 41. Similarly, the portion of the insulating region 41 extending along the Y-axis and the other end of the insulating regions 42-46 in the Y-axis direction ( Figure 1 The lower end of the insulating region 41 (which is located at the bottom of the first semiconductor region) is connected to the insulating region 41 extending along the X-axis. This allows for a more reliable current path through the bottom of the insulating regions 41-46 in the Z-axis direction when measuring the resistance of the first semiconductor region. Alternatively, instead of the insulating region 41, an insulating region with a lower end height different from that of the insulating region 41 can be provided, sandwiching both ends of the insulating regions 41-46 in the Y-axis direction. For example, instead of the insulating region 41, any one of the insulating regions 43-46 can be provided, sandwiching both ends of the insulating regions 41-46 in the Y-axis direction.

[0073] like Figure 1 and Figure 2 As shown, contact portions 31 to 37 are disposed on the upper surface 2a of the semiconductor layer 2, and are electrically connected to the high-concentration layers 241 to 247, respectively. More specifically, contact portion 31 is electrically connected to the high-concentration layer 241, contact portion 32 is electrically connected to the high-concentration layer 242, contact portion 33 is electrically connected to the high-concentration layer 243, contact portion 34 is electrically connected to the high-concentration layer 244, contact portion 35 is electrically connected to the high-concentration layer 245, contact portion 36 is electrically connected to the high-concentration layer 246, and contact portion 37 is electrically connected to the high-concentration layer 247. Furthermore, contact portions 31 to 37 may also be electrically connected to monitoring pads or the like disposed on the scribe lines of the semiconductor device 1.

[0074] Furthermore, contact portion 31 and contact portion 32 constitute a contact pair for measuring the resistance of a first semiconductor region spanning the insulating region 41 between contact portion 31 and contact portion 32. Contact portion 31 is an example of the ninth contact portion in the claims. Contact portion 32 is an example of the tenth contact portion in the claims. The contact pair constituted by contact portion 31 and contact portion 32 is an example of the fifth contact pair in the claims.

[0075] The contact portion 32 and the contact portion 33 constitute a contact pair for measuring the resistance of a first semiconductor region spanning the insulating region 42 between the contact portion 32 and the contact portion 33.

[0076] Contact portion 33 and contact portion 34 constitute a contact pair for measuring the resistance of a first semiconductor region spanning the insulating region 43 between contact portion 33 and contact portion 34. Contact portion 33 is an example of a first contact portion in the claims. Contact portion 34 is an example of a second contact portion in the claims. The contact pair constituted by contact portion 33 and contact portion 34 is an example of a first contact pair in the claims.

[0077] Contact portion 34 and contact portion 35 constitute a contact pair for measuring the resistance of a first semiconductor region spanning the insulating region 44 between contact portion 34 and contact portion 35. Contact portion 33 is an example of the fifth contact portion in the claims. Contact portion 34 is an example of the sixth contact portion in the claims. The contact pair constituted by contact portion 34 and contact portion 35 is an example of the third contact pair in the claims.

[0078] Contact portion 35 and contact portion 36 constitute a contact pair for measuring the resistance of a first semiconductor region spanning an insulating region 45 between contact portion 35 and contact portion 36. Contact portion 35 is an example of a third contact portion in the claims. Contact portion 36 is an example of a fourth contact portion in the claims. The contact pair constituted by contact portion 35 and contact portion 36 is an example of a second contact pair in the claims.

[0079] Contact portion 36 and contact portion 37 constitute a contact pair for measuring the resistance of a first semiconductor region spanning the insulating region 46 between contact portion 36 and contact portion 37. Contact portion 36 is an example of the seventh contact portion in the claims. Contact portion 37 is an example of the eighth contact portion in the claims. The contact pair constituted by contact portion 36 and contact portion 37 is an example of the fourth contact pair in the claims.

[0080] In addition, Figure 2 In the example, each high-concentration layer is electrically connected to a contact portion. However, this is not a limitation. For high-concentration layers 242 to 246, two contact portions can also be electrically connected to each high-concentration layer, forming distinct contact pairs. For instance, high-concentration layer 244 can be electrically connected to two contact portions 34, where one contact portion 34 and contact portion 33 form one contact pair (first contact pair), and the other contact portion 34 and contact portion 35 form another contact pair (third contact pair).

[0081] Figure 3 This is a graph representing the electric field intensity of the first semiconductor region in the semiconductor device of the first embodiment and the comparative example. More specifically, Figure 3The distribution of the electric field intensity in the first semiconductor region when a reverse voltage (reverse bias) is applied between the drain electrode and the source electrode (not shown) is illustrated. As described above, in the semiconductor device 1 of this embodiment, the resistivity of the epitaxial growth layers 21-23 increases in the order of epitaxial growth layers 21, 22, and 23. On the other hand, Figure 3 The comparative example shown corresponds to, for example, cases where the resistivity of epitaxial layers 21-23 is the same, but the FP electrode 13 and insulating regions 41-46 are not provided. Furthermore, Figure 3 The electric field strength of the first embodiment shown is relative to Figure 2 The values ​​were obtained by applying 0V to the FP electrodes 13 in the insulating regions 41 to 46 and measuring them.

[0082] like Figure 3 As shown, in the semiconductor device 1 of this embodiment, since the resistivity increases in the order of epitaxial growth layers 21, 22, and 23, the electric field strength becomes uniform during reverse bias. That is, in this embodiment, the withstand voltage can be ensured throughout the entire first semiconductor region during reverse bias. On the other hand, in the semiconductor device of the comparative example, the electric field strength is not uniform during reverse bias, and the electric field strength has a peak value P. Therefore, the withstand voltage of the semiconductor device of the comparative example is determined by the electric field strength at the peak value P, and the overall withstand voltage is reduced. Therefore, in this embodiment, by increasing the resistivity in the order of epitaxial growth layers 21, 22, and 23, the electric field concentration in the first semiconductor region can be mitigated, and the withstand voltage of the semiconductor device 1 can be improved. Furthermore, for this reason, by measuring the resistivity of epitaxial growth layers 21 to 23, quality control (QC) of the semiconductor device 1 can be performed.

[0083] Next, refer to Figure 4 An example of the operation of the semiconductor device 1 used to measure the resistivity of epitaxial growth layers 21 to 23 will be described. Figure 4 This is a schematic cross-sectional view illustrating an example of the operation of the semiconductor device 1 according to the first embodiment.

[0084] like Figure 4 As shown, measuring units 51 to 56 are electrically connected to the contact portions 31 to 37 of the semiconductor device 1. The measuring units 51 to 56 are devices for measuring the resistance values ​​in paths R1 to R6 as the resistance values ​​between the contact portions of each contact pair.

[0085] More specifically, the measuring unit 51 is electrically connected to the contact parts 31 and 32 to measure the resistance value (DC resistance value) between the contact parts 31 and 32. This resistance value is, for example,... Figure 4The resistance value in path R1. Path R1 is a current path through epitaxial growth layers 21-23 based on their respective thicknesses (length in the Z-axis direction) and through the substrate 25 based on the width of the insulating region 41. Furthermore, in the resistance value of path R1, the resistance value of the high-concentration layer 24 is omitted because it is sufficiently small compared to the resistance values ​​of the epitaxial growth layers 21-23 and the substrate 25. The resistance values ​​of subsequent paths R2-R6 are the same.

[0086] The measuring unit 52 is electrically connected to the contact parts 32 and 33 to measure the resistance value between the contact parts 32 and 33. This resistance value is, for example,... Figure 4 The resistance value in path R2. Path R2 is a current path through epitaxial growth layers 21-23 based on their respective thicknesses, and through substrate 25 based on the width of insulating region 42.

[0087] The measuring unit 53 is electrically connected to the contact parts 33 and 34 to measure the resistance value between the contact parts 33 and 34. This resistance value is, for example,... Figure 4 The resistance value in path R3. Path R3 is the current path through epitaxial growth layers 22 and 23 based on their respective thicknesses, and through epitaxial growth layer 21 based on the width of insulating region 43. Specifically, the resistance value of path R3 is expressed as r1 + 2r2 + 2r3, using the resistance value r1 through the portion of epitaxial growth layer 21, the resistance value r2 through the portion of epitaxial growth layer 22, and the resistance value r3 through the portion of epitaxial growth layer 23. The resistance value in path R3 is an example of the first resistance value.

[0088] The measuring unit 54 is electrically connected to the contact parts 34 and 35 to measure the resistance value between the contact parts 34 and 35. This resistance value is, for example,... Figure 4 The resistance value in path R4. Path R4 is the current path through epitaxial growth layers 22 and 23 based on their respective thicknesses, and through epitaxial growth layer 21 based on the width of insulating region 44.

[0089] The measuring unit 55 is electrically connected to the contact parts 35 and 36 to measure the resistance value between the contact parts 35 and 36. This resistance value is, for example,... Figure 4 The resistance value in path R5. Path R5 is a current path through epitaxial growth layer 23 based on the thickness of epitaxial growth layer 23 and through epitaxial growth layer 22 based on the width of insulating region 45. Specifically, the resistance value of path R5 is expressed as r2′+2·r3 using the resistance value r2′ of the portion through epitaxial growth layer 22 and the resistance value r3 of the portion through epitaxial growth layer 23. The resistance value in path R5 is an example of a second resistance value.

[0090] The measuring unit 56 is electrically connected to the contact parts 36 and 37 to measure the resistance value between the contact parts 36 and 37. This resistance value is, for example,... Figure 4 The resistance value in path R6. Path R6 is the current path through epitaxial growth layer 23 based on the thickness of epitaxial growth layer 23 and through epitaxial growth layer 22 based on the width of insulating region 46.

[0091] As explained above, the semiconductor device 1 of this embodiment includes a first semiconductor region, an insulating region 43, an insulating region 45, high-concentration layers 243, 244, 245, 246, a first contact pair, and a second contact pair. In the first semiconductor region, along the Z-axis direction, which is the thickness direction, the concentration of n-type or p-type impurities decreases from the lower surface to the upper surface. The insulating region 43 is provided from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, and the lower end of the insulating region 43 is located at a height where the impurity concentration of the first semiconductor region is a first concentration. The insulating region 43 extends in the Y-axis direction, which is orthogonal to the Z-axis direction. The insulating region 45 is provided from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, and the lower end of the insulating region 45 is located at a height where the impurity concentration of the first semiconductor region is a second concentration lower than the first concentration. The insulating region 45 extends in the Y-axis direction. The high-concentration layers 243 and 244 are provided on the upper surface of the first semiconductor region and are arranged such that they sandwich the insulating region 43 in the X-axis direction, which is orthogonal to both the Z-axis and Y-axis directions. High-concentration layers 245 and 246 are disposed on the upper surface of the first semiconductor region and are arranged such that an insulating region 45 is sandwiched in the X-axis direction. The first contact pair has a contact portion 33 electrically connected to the high-concentration layer 243 and a contact portion 34 electrically connected to the high-concentration layer 244. The second contact pair has a contact portion 35 electrically connected to the high-concentration layer 245 and a contact portion 36 electrically connected to the high-concentration layer 246.

[0092] According to the semiconductor device 1 of this embodiment, the resistivity of the epitaxial growth layers 21 to 23 can be calculated based on the resistance values ​​of paths R1 to R6 measured by the measuring units 51 to 56, and the quality of the epitaxial growth layers 21 to 23 can be easily checked.

[0093] Specifically, for example, based on the resistance value r1+2·r2+2·r3 of path R3 measured by measurement unit 53 and the resistance value r2′+2·r3 of path R5 measured by measurement unit 55, the difference r1-r2′+2·r2 between the resistance values ​​of path R3 and path R5 is calculated. Based on this difference and the width (length in the X-axis direction) and height (length in the Z-axis direction) of insulating regions 43 and 45, a value related to the resistivity of epitaxial growth layers 21 and 22 is calculated. Moreover, when the difference between r1 and r2′ is negligible compared to 2·r2, the aforementioned difference is 2·r2. In this case, by dividing the aforementioned difference by 2 to obtain the value r2, and dividing it by the difference in height of insulating regions 43 and 45, the resistivity of epitaxial growth layer 22 can be calculated. For example, if the difference between r1 and r2′ is negligible compared to 2·r2, the width of the insulating regions 43 and 45 can be sufficiently small relative to the difference in their heights. In this case, the quality of the epitaxial growth layer 22 can be easily and more appropriately inspected.

[0094] Furthermore, the semiconductor device 1 of this embodiment includes an insulating region 44 with the same height at its lower end as the insulating region 43, but a different width. Therefore, for example, based on the resistance values ​​of paths R3 and R4 and the widths of the insulating regions 43 and 44, the contribution of the epitaxial growth layer 21 to the resistance values ​​of paths R3 and R4 can be excluded. Similarly, based on the resistance values ​​of paths R5 and R6 and the widths of the insulating regions 45 and 46, the contribution of the epitaxial growth layer 22 to the resistance values ​​of paths R5 and R6 can be excluded. Moreover, based on the resistance values ​​of paths R3 to R6 after excluding the contributions of the epitaxial growth layers 21 and 22, and the heights of the insulating regions 43 to 46, the resistivity of the epitaxial growth layers 22 and 23 can be calculated respectively. Thus, the quality of the epitaxial growth layers 22 and 23 can be easily and more appropriately inspected.

[0095] Furthermore, the semiconductor device 1 of this embodiment includes insulating regions 41 and 42, whose lower ends are located in the first semiconductor region and have different heights and widths, with impurity concentrations higher than the first concentration. Therefore, for example, based on the resistance values ​​of paths R1 and R2 and the widths of the insulating regions 41 and 42, the contribution of the substrate 25 to the resistance values ​​of paths R1 and R2 can be excluded. Moreover, for example, the resistivity of the substrate 25 can be calculated based on the resistance values ​​of paths R1 to R3 after excluding the contribution of the substrate 25 and the heights of the insulating regions 41 to 43. Thus, for example, the relationship between the resistivity of the epitaxial growth layers 21 to 23 and the resistivity of the substrate 25 can be examined, and the quality of the epitaxial growth layers 21 to 23 can be checked more easily and appropriately.

[0096] Furthermore, in this embodiment, the resistivity of the substrate 25 can also be calculated based on the resistance values ​​of paths R1 and R2 and the widths of the insulating regions 41 and 42. Similarly, the resistivity of the epitaxial growth layer 21 can be calculated based on the resistance values ​​of paths R3 and R4 and the widths of the insulating regions 43 and 44. Likewise, the resistivity of the epitaxial growth layer 22 can be calculated based on the resistance values ​​of paths R5 and R6 and the widths of the insulating regions 45 and 46. That is, since the semiconductor device 1 includes at least insulating regions 43 and 44, the resistivity of the epitaxial growth layer 21 can be calculated by dividing the value obtained by subtracting the resistance value of path R3 from the resistance value of path R4 by the value obtained by subtracting the width of insulating region 43 from the width of insulating region 44. Therefore, the quality of the epitaxial growth layer 21 can be easily inspected. Similarly, since the semiconductor device 1 includes at least insulating regions 45 and 46, the resistivity of the epitaxial layer 22 can be calculated by dividing the value obtained by subtracting the resistance value of path R5 from the resistance value of path R6 by the value obtained by subtracting the width of insulating region 45 from the width of insulating region 46. Therefore, the quality of the epitaxial layer 22 can be easily inspected.

[0097] Therefore, according to the semiconductor device 1 of this embodiment, the resistivity of the substrate 25 and the epitaxial growth layers 21 to 22 can be calculated based on the resistance values ​​measured by the measuring units 51 to 56 and the width and height of the insulating regions 41 to 46.

[0098] Furthermore, for example, in the resistance value r1+2·r2+2·r3 of path R3, if the contribution r1 of epitaxial growth layer 21 is negligible compared to the contributions r2 and r3 of epitaxial growth layers 22 and 23, the insulating region 44 can be omitted. Similarly, in the resistance value of path R5, if the contribution r2′ of epitaxial growth layer 22 is negligible compared to the contribution r3 of epitaxial growth layer 23, the insulating region 45 can be omitted.

[0099] Furthermore, the semiconductor wafer can have the above-described structure. That is, by using a semiconductor wafer having the epitaxial growth layers 21-23, the high-concentration layer 24, the substrate 25, and the insulating regions 41-46 described above, the quality of the epitaxial growth layers 21-23 in the semiconductor wafer can be easily inspected. Additionally, in this case, the epitaxial growth layers 21-23, the high-concentration layer 24, the substrate 25, and the insulating regions 41-46 can also be arranged along the scribe line of the semiconductor wafer.

[0100] <Manufacturing Method of Semiconductor Device 1>

[0101] Next, refer to Figures 5A-5C An example of the manufacturing method of the semiconductor device 1 of this embodiment will be described. Figures 5A-5C This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor device 1 according to the first embodiment.

[0102] First, such as Figure 5A As shown, a semiconductor wafer 200 is prepared. The semiconductor wafer 200 includes an epitaxial growth layer 21, an epitaxial growth layer 22, an epitaxial growth layer 23, and a substrate 25. Additionally, the semiconductor wafer 200 includes trenches T1 to T6 formed from the upper surface 2a toward the lower surface. These trenches T1 to T6 are trenches in which FP electrodes 13 and insulating regions 41 to 46 are formed internally in subsequent processes.

[0103] Furthermore, the semiconductor wafer 200 is formed, for example, as follows: First, a substrate 25 is prepared. Then, an epitaxial growth layer 21 having a first concentration of n-type impurities is epitaxially grown on the upper surface of the substrate 25. Then, an epitaxial growth layer 22 having a second concentration of n-type impurities is epitaxially grown on the upper surface of the epitaxial growth layer 21. Then, an epitaxial growth layer 23 having a third concentration of n-type impurities is epitaxially grown on the upper surface of the epitaxial growth layer 23.

[0104] Then, trenches T1 to T6 are formed. For example, a resist film is first formed on the upper surface 2a of the semiconductor wafer 200, excluding the areas where trenches T1 and T2 are to be formed. Then, trenches T1 and T2 are formed by reactive ion etching (RIE) or the like, using the resist film as a mask. Then, the resist film is removed.

[0105] Next, a photoresist film is formed on the upper surface 2a of the semiconductor wafer 200, excluding the areas where trenches T3 and T4 are to be formed. Then, trenches T3 and T4 are formed using a re-electrode (RIE) or similar device that uses the photoresist film as a mask. The conditions for the RIE in this process are changed compared to those used when forming trenches T1 and T2. This allows trenches T3 and T4 to be formed with depths different from those of trenches T1 and T2. Afterward, the photoresist film is removed.

[0106] Next, a photoresist film is formed on the upper surface 2a of the semiconductor wafer 200, excluding the areas where trenches T5 and T6 are to be formed. Then, trenches T5 and T6 are formed using a re-electrode (RIE) or similar device that uses the photoresist film as a mask. The conditions for the RIE in this process are changed compared to those used when forming trenches T1 to T4. Therefore, it is possible to form trenches T5 and T6 with depths different from those of trenches T1 to T4.

[0107] Through the above processes, a semiconductor wafer 200 is formed. Furthermore, the order in which trenches T1 to T6 are formed is not limited to the examples described above and can be arbitrary.

[0108] Next, as Figure 5BAs shown, insulating regions 400 are formed on the inner walls of trenches T1 to T6 and on the upper surface 2a of semiconductor wafer 200 by thermal oxidation or the like. Then, conductive materials such as polycrystalline silicon are deposited within the insulating regions 400 in trenches T1 to T6 by chemical vapor deposition (CVD). Next, the conductive materials are etched back using chemical mechanical polishing (CMP) and chemical dry etching (CDE). This forms the FP electrode 13.

[0109] Next, as Figure 5C As shown, the portion of the insulating region located above the upper surface 2a of the semiconductor wafer 200 is then removed using methods such as RIE. As a result, insulating regions 41 to 46 remain in trenches T1 to T6, respectively.

[0110] Next, by ion implanting impurities of the same conductivity type as the epitaxial growth layers 21-23 onto the upper surface 2a of the semiconductor wafer 200, a high-concentration layer 24 (high-concentration layers 241-247) is formed, which is not shown in the figure. Then, contact portions 31-37, which are electrically connected to the high-concentration layers 241-247, are formed. Next, the semiconductor wafer 200 is diced to monolithize it into multiple semiconductor devices 1. Through the above processes, the semiconductor device 1 is manufactured.

[0111] (A variation of the first embodiment)

[0112] In the first embodiment described above, insulating regions 42, 44, and 46 are formed, each with a lower end height the same as insulating regions 41, 43, and 45, but a width different from that of insulating regions 41, 43, and 45. However, it is not limited to this; insulating regions with lower end heights and widths the same as insulating regions 41, 43, and 45 may also be formed. Hereinafter, this case will be described as a variation of the first embodiment, focusing on the differences from the first embodiment described above.

[0113] Figure 6 This is a cross-sectional view showing an operational example of the semiconductor device 1A, a modified example of the first embodiment. For example... Figure 6 As shown, the semiconductor device 1A of this modified example has insulating regions 42A, 44A, and 46A respectively to replace the insulating regions 42, 44, and 46 of the semiconductor device 1 of the first embodiment.

[0114] The lower end of insulating region 42A is at the same height as the lower end of insulating region 41. Furthermore, the width of insulating region 42A is the same as the width of insulating region 41. Additionally, insulating region 42A is adjacent to insulating region 41 in the X-axis direction. That is, in the X-axis direction, between insulating region 41 and insulating region 42A, there are no other insulating regions (such as insulating region 43) whose lower end height differs from that of insulating regions 41 and 42A.

[0115] The lower end of insulating region 44A is at the same height as the lower end of insulating region 43. Furthermore, the width of insulating region 44A is the same as the width of insulating region 43. Additionally, insulating region 44A is adjacent to insulating region 43 in the X-axis direction.

[0116] The lower end of insulating region 46A is at the same height as the lower end of insulating region 45. Furthermore, the width of insulating region 46A is the same as the width of insulating region 45. Additionally, insulating region 46A is adjacent to insulating region 45 in the X-axis direction.

[0117] In addition, in this modified example, measuring units 52A, 54A, and 56A are connected instead of measuring units 52, 54, and 56, and the resistance values ​​of paths R2A, R4A, and R6A are measured instead of the resistance values ​​of paths R2, R4, and R6 in the first embodiment.

[0118] More specifically, the measuring unit 52A is electrically connected to the contact parts 31 and 33, and measures the resistance value between the contact parts 31 and 33. This resistance value is, for example,... Figure 6 The resistance value in path R2A. Path R2A is a current path through epitaxial growth layers 21-23 based on their respective thicknesses, and through substrate 25 based on the widths of insulating regions 41 and 42A and the width of the first semiconductor region between insulating regions 41 and 42A.

[0119] The measuring unit 54A is electrically connected to the contact parts 33 and 35 to measure the resistance value between the contact parts 33 and 35. This resistance value is, for example,... Figure 6 The resistance value in path R4A. Path R4A is the current path through epitaxial growth layers 22 and 23 based on the respective thicknesses of epitaxial growth layers 22 and 23, and through epitaxial growth layer 21 based on the widths of insulating regions 43 and 44A and the width of the first semiconductor region between insulating regions 43 and 44A.

[0120] The measuring unit 56A is electrically connected to contact parts 35 and 37 to measure the resistance value between contact parts 35 and 37. This resistance value is, for example,... Figure 6The resistance value in path R6A. Path R6A is a current path through epitaxial growth layer 23 based on the thickness of epitaxial growth layer 23, and through epitaxial growth layer 22 based on the width of insulating region 45 and insulating region 46A and the width of the first semiconductor region between insulating region 45 and insulating region 46A.

[0121] In this modified example, the distances between paths R1 and R2A in the epitaxial growth layers 21-23 are equal, while their distances in the substrate 25 are different. Therefore, based on the resistance values ​​of paths R1 and R2A and the widths of the insulating regions 41 and 42A, the contribution of the substrate 25 to the resistance values ​​of paths R1 and R2A can be eliminated.

[0122] Similarly, paths R3 and R4A are equidistant in epitaxial growth layers 22 and 23, but different in epitaxial growth layer 21. Therefore, based on the resistance values ​​of paths R3 and R4A and the widths of insulating regions 43 and 44A, the contribution of epitaxial growth layer 21 to the resistance values ​​of paths R3 and R4A can be eliminated.

[0123] Similarly, paths R5 and R6A are equidistant in epitaxial growth layer 23, but different in epitaxial growth layer 22. Therefore, based on the resistance values ​​of paths R5 and R6A and the widths of insulating regions 45 and 46A, the contribution of epitaxial growth layer 22 to the resistance values ​​of paths R5 and R6A can be eliminated.

[0124] Therefore, according to the semiconductor device 1A of this modified example, the resistivity of the substrate 25 and the epitaxial growth layers 21 and 22, and the resistivity of the epitaxial growth layer 23 can be calculated based on the resistance values ​​measured by the measuring units 51, 52A, 53, 54A, 55, and 56A, and the width and height of the insulating regions 41, 42A, 43, 44A, 45, and 46A, respectively. Thus, similar to the first embodiment, the quality of the epitaxial growth layers 21 to 23 can be easily inspected.

[0125] (Second Implementation)

[0126] Next, the second embodiment, in which a barrier film is provided below the insulating regions 41 to 46, will be described, focusing on the differences from the first embodiment described above. Figure 7 This is a cross-sectional view of the semiconductor device according to the second embodiment.

[0127] like Figure 7As shown, the semiconductor device 1B of this embodiment, in addition to the components of the semiconductor device 1 of the first embodiment, also includes insulating regions 61-66 disposed between the bottom of insulating regions 41-46 and the first semiconductor region. Insulating regions 61-66, for example, comprise silicon oxide or silicon nitride. Insulating regions 61-66 are formed, for example, by thermally oxidizing the insulating regions 610-660 (described later) which serve as barrier films.

[0128] The bottom of insulating region 41 sandwiches insulating region 61 with the first semiconductor region. Insulating region 61 has, for example, the same width as insulating region 41. In this embodiment, the lower end of insulating region 61 is located below the boundary between substrate 25 and epitaxial growth layer 21.

[0129] The bottom of insulating region 42 sandwiches insulating region 62 with the first semiconductor region. Insulating region 62 has, for example, the same width as insulating region 42. In this embodiment, the lower end of insulating region 62 is located below the boundary between substrate 25 and epitaxial growth layer 21.

[0130] The bottom of insulating region 43 sandwiches insulating region 63 with the first semiconductor region. Insulating region 63 has, for example, the same width as insulating region 43. In this embodiment, the lower end of insulating region 63 is located below the boundary between epitaxial growth layer 21 and epitaxial growth layer 22. Insulating region 63 is an example of the sixth insulating region in the claims.

[0131] The bottom of insulating region 44 sandwiches insulating region 64 with the first semiconductor region. Insulating region 64 has, for example, the same width as insulating region 44. In this embodiment, the lower end of insulating region 64 is located below the boundary between epitaxial growth layer 21 and epitaxial growth layer 22.

[0132] The bottom of insulating region 45 sandwiches insulating region 65 with the first semiconductor region. Insulating region 65 has, for example, the same width as insulating region 45. In this embodiment, the lower end of insulating region 65 is located below the boundary between epitaxial growth layer 22 and epitaxial growth layer 23. Insulating region 65 is an example of the seventh insulating region in the claims.

[0133] The bottom of insulating region 46 sandwiches insulating region 66 with the first semiconductor region. Insulating region 66 has, for example, the same width as insulating region 46. In this embodiment, the lower end of insulating region 66 is located below the boundary between epitaxial growth layer 22 and epitaxial growth layer 23.

[0134] In this embodiment, for each of the insulating regions 41 to 46, the distance between the insulating region and the semiconductor layer 2 in the Z-axis direction is longer than the distance between the insulating region and the semiconductor layer 2 in the X-axis direction.

[0135] According to this embodiment, the manufacturing process of the semiconductor device 1B described below can be simplified.

[0136] <Manufacturing Method of Semiconductor Device 1B>

[0137] Next, refer to Figures 8A to 8E An example of a method for manufacturing the semiconductor device 1B according to this embodiment will be described. Figures 8A to 8E This is a cross-sectional view illustrating an example of the manufacturing process of the semiconductor device 1B according to the second embodiment.

[0138] First, prepare Figure 8A The semiconductor wafer component shown has an epitaxial growth layer 21, a substrate 25, an insulating region 610, and an insulating region 620.

[0139] also, Figure 8A The semiconductor wafer component shown is formed, for example, as follows: First, a substrate 25 is prepared. Then, an insulating material is deposited on a portion of the upper surface of the substrate 25 by CVD and wet etching to form insulating regions 610 and 620. Both insulating regions 610 and 620 are examples of a first barrier film. Next, an epitaxial growth layer 21 having a first concentration of n-type impurities is epitaxially grown on the upper surface of the substrate 25. The epitaxial growth layer 21 fills the insulating regions 610 and 620. Furthermore, the lower ends of the insulating regions 610 and 620 are located at the boundary between the substrate 25 and the epitaxial growth layer 21.

[0140] Next, as Figure 8B As shown, insulating material is deposited on a portion of the upper surface of the epitaxial growth layer 21 by CVD and wet etching to form insulating regions 630 and 640. Both insulating regions 630 and 640 are examples of a second barrier film. Subsequently, an epitaxial growth layer 22 with a second concentration of n-type impurities is epitaxially grown on the upper surface of the epitaxial growth layer 21. The epitaxial growth layer 22 fills the insulating regions 630 and 640. Furthermore, the lower ends of the insulating regions 630 and 640 are located at the boundary between the epitaxial growth layer 21 and the epitaxial growth layer 22.

[0141] Next, as Figure 8CAs shown, insulating material is deposited on a portion of the upper surface of the epitaxial growth layer 22 using CVD and wet etching to form insulating regions 650 and 660. Both insulating regions 650 and 660 are examples of a third barrier film. Subsequently, an epitaxial growth layer 23 with a third concentration of n-type impurities is epitaxially grown on the upper surface of the epitaxial growth layer 22. The epitaxial growth layer 23 fills the insulating regions 650 and 660. Furthermore, the lower ends of the insulating regions 650 and 660 are located at the boundary between the epitaxial growth layer 22 and the epitaxial growth layer 23. The result of this process is the formation of a semiconductor wafer 200A.

[0142] Next, as Figure 8D As shown, trenches T1 to T6 are formed. More specifically, firstly, a photoresist film is formed on the upper surface 2a of the semiconductor wafer 200A, excluding the areas where trenches T1 to T6 are to be formed. Then, trenches T1 to T6 are formed by using the photoresist film as a mask and the RIE (Residual Insulator) with insulating regions 610 to 660 as a barrier film.

[0143] Next, as Figure 8E As shown, insulating regions 400 are formed on the inner walls of trenches T1 to T6 and on the upper surface 2a of semiconductor wafer 200A by thermal oxidation or the like. In this embodiment, insulating regions 610 to 660 are respectively called insulating regions 61 to 66.

[0144] Furthermore, in this embodiment, in Figure 8E In the illustrated process, since the insulating regions also extend into the first semiconductor region located below insulating regions 610 to 660, the lower ends of insulating regions 61 to 66 are located lower than the lower ends of insulating regions 610 to 660. More specifically, the lower ends of insulating regions 610 and 620 are located lower than the boundary between substrate 25 and epitaxial growth layer 21. Furthermore, the lower ends of insulating regions 63 and 64 are located lower than the boundary between epitaxial growth layer 21 and epitaxial growth layer 22. Additionally, the lower ends of insulating regions 65 and 66 are located lower than the boundary between epitaxial growth layer 22 and epitaxial growth layer 23.

[0145] The subsequent processes are the same as in the first embodiment. Thus, the semiconductor device 1B of this embodiment is manufactured.

[0146] According to the manufacturing method of the semiconductor device 1B of this embodiment, trenches T1 to T6 can be formed simultaneously. Therefore, the manufacturing process of the semiconductor device 1B can be simplified.

[0147] (Third Implementation)

[0148] Next, a third embodiment that integrates the semiconductor device 1 of the first embodiment into a MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) will be described. Figure 9 This is a cross-sectional view of the semiconductor device 1C according to the third embodiment. Hereinafter, the semiconductor device 1C of this embodiment will be described focusing on the differences from the first embodiment. Furthermore, in the following description, the case where the semiconductor device 1C is a vertically oriented MOSFET will be described. In addition, the semiconductor device 1C may also be a transistor or diode, such as an IGBT (Insulated Gate Bipolar Transistor). Alternatively, the semiconductor device 1C may also be a horizontally oriented device.

[0149] like Figure 9 As shown, the semiconductor device 1C of this embodiment, in addition to the components of the semiconductor device 1 of the first embodiment, also includes a drain electrode 11, a source electrode 12, a gate electrode 14, a substrate region 26, and an insulating region 47.

[0150] In the following description, the region in semiconductor device 1C that functions as a MOSFET is referred to as the cell region, and the region located at the end of the MOSFET is referred to as the end region. The cell region is the region where current flows between the drain electrode 11 and the source electrode 12. The end region, for example, is a region provided in a plane orthogonal to the Z-axis direction that surrounds the cell region. In this embodiment, the source electrode 12, the gate electrode 14, the substrate region 26, and the insulating region 47 are provided in the cell region. The insulating regions 41-46 and the contact portions 31-37 are provided in the end region. Alternatively, the insulating regions 41-46 and the contact portions 31-37 may also be provided in the cell region.

[0151] The drain electrode 11 functions as the drain electrode of the MOSFET. The drain electrode 11 is disposed on the lower surface 2b of the semiconductor layer 2. The drain electrode 11 is electrically connected to the substrate 25 in the cell region. The drain electrode 11 may contain at least one of copper (Cu), titanium (Ti), tungsten (W), and aluminum (Al). The drain electrode 11 is an example of a first electrode.

[0152] The source electrode 12 functions as the source electrode of the MOSFET. The source electrode 12 is disposed on the upper surface 2a of the cell region of the semiconductor layer 2. The source electrode 12 is electrically connected to the FP electrode 13 and the high-density layer 24 in the cell region. Furthermore, the source electrode 12 is contained within... Figure 9A contact portion 12a protrudes downward from the center. The contact portion 12a penetrates the high-concentration layer 24 and reaches the substrate region 26. The source electrode 12 is electrically connected to the substrate region 26 via the contact portion 12a. Furthermore, although not shown, the source electrode 12 may also be electrically connected to the FP electrode 13 within the insulating regions 41-46. The source electrode 12 may contain at least one of copper (Cu), titanium (Ti), tungsten (W), and aluminum (Al). The source electrode 12 is an example of a second electrode.

[0153] The gate electrode 14 functions as the gate electrode of the MOSFET. The gate electrode 14 is disposed within the insulating region 47 and is positioned opposite the substrate region 26 in the X-axis direction, separated by the insulating region 47. The gate electrode 14 is electrically insulated from the semiconductor layer 2 by the insulating region 47. The gate electrode 14 is made, for example, of polysilicon containing p-type or n-type impurities. When a voltage is applied to the gate electrode 14, a channel is formed in the substrate region 26 opposite to the gate electrode 14, allowing charge carriers (electrons or holes) to flow between the epitaxial growth layer 23 and the high-concentration layer 24. This turns the MOSFET on.

[0154] Substrate region 26 functions as the substrate region of the MOSFET. In this embodiment, substrate region 26 is disposed within the cell region and located above epitaxial growth layer 23. Substrate region 26 contains impurities of a different conductivity type than epitaxial growth layers 21-23 and substrate 25 (first semiconductor region). In this embodiment, substrate region 26 is a p-type semiconductor region. Substrate region 26 constitutes a second semiconductor region. The p-type impurity concentration of substrate region 26 is, for example, 1 × 10⁻⁶. 16 cm- 3 Above and 1×10 20 cm- 3 the following.

[0155] An insulating region 47 is disposed in the cell region from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region. The insulating region 47 may contain, for example, silicon oxide or silicon nitride. In this embodiment, the lower end of the insulating region 47 is at the same height as the lower ends of the insulating regions 43 and 44. Thus, insulating regions 43, 44 and 47 can be formed together. Furthermore, the height of the lower end of the insulating region 47 is arbitrary. For example, the lower end of the insulating region 47 may be at the same height as the lower ends of the insulating regions 41 and 42, or at the same height as the lower ends of the insulating regions 45 and 46, or at other heights.

[0156] In addition, Figure 9In this example, the epitaxial growth layers 21-23 and the upper part of the substrate 25 in the cell region function as the drift region of the MOSFET. Additionally, the high-density layer 24 in the cell region functions as the source region of the MOSFET. Furthermore, the lower part of the substrate 25 in the cell region functions as the drain region of the MOSFET.

[0157] Alternatively, a drain region can be provided on the lower surface 2b of the semiconductor layer 2 in the cell region to ensure ohmic contact with the drain electrode 11. The drain region contains impurities of the same conductivity type as the epitaxial growth layers 21-23 and the substrate 25 (first semiconductor region). Furthermore, the impurity concentration in the drain region is, for example, 1 × 10⁻⁶. 18 cm- 3 Above and 1×10 21 cm- 3 The drain region is formed, for example, by ion implantation of impurities of the same conductivity type as the substrate 25 onto the lower surface of the substrate 25.

[0158] Furthermore, the structure of MOSFETs is not limited to Figure 9 The examples shown are arbitrary. For example, in Figure 9 In this configuration, the gate electrode 14 and the FP electrode 13 are disposed within the same insulating region 47. However, the gate electrode 14 and the FP electrode 13 may also be disposed within different insulating regions. Alternatively, the semiconductor device 1C may have a planar gate structure in which the gate electrode 14 and the insulating region are disposed on the upper surface 2a of the semiconductor layer 2. Alternatively, the gate electrode 14 may be disposed within the insulating regions 41-46 in the end region.

[0159] According to this embodiment, the contact portions 31-37 and the insulating regions 41-46 can be integrated into a MOSFET or the like. Therefore, the quality of the epitaxial growth layers 21-23 can be easily inspected in the MOSFET or the like. That is, physical product quality control (physical QC) can be easily performed. Furthermore, in this embodiment, the structure of integrating the semiconductor device 1 of the first embodiment into a MOSFET has been described. However, it is not limited to this; the semiconductor device 1B of the second embodiment can also be integrated into a MOSFET.

[0160] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0161] (Postscript 1)

[0162] A semiconductor device comprising:

[0163] In a first semiconductor region, along a first direction which is the thickness direction, the impurity concentration of a first or second conductivity type decreases from the lower surface toward the upper surface.

[0164] A first insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the first insulating region is located at the height of the first semiconductor region where the impurity concentration is a first concentration, and the first insulating region extends in a second direction orthogonal to the first direction;

[0165] A second insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the second insulating region is located at the height of the first semiconductor region where the impurity concentration is a second concentration lower than the first concentration, and the second insulating region extends in the second direction;

[0166] First and second high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the first insulating region in a third direction orthogonal to the first and second directions;

[0167] The third and fourth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the second insulating region in the third direction.

[0168] A first contact pair, the first contact pair having a first contact portion electrically connected to the first high-concentration layer and a second contact portion electrically connected to the second high-concentration layer; and

[0169] The second contact pair has a third contact portion electrically connected to the third high-concentration layer and a fourth contact portion electrically connected to the fourth high-concentration layer.

[0170] (Postscript 2)

[0171] According to the semiconductor device described in Appendix 1, the first semiconductor region is an epitaxial growth layer disposed on a substrate.

[0172] (Note 3)

[0173] According to the semiconductor device described in Appendix 2, wherein,

[0174] The first semiconductor region includes:

[0175] The impurity concentration is the first concentration of the first epitaxial growth layer;

[0176] The impurity concentration is the second concentration and the second epitaxial growth layer is located above the first epitaxial growth layer; and

[0177] The impurity concentration is a third concentration that is lower than the second concentration and is located on top of the second epitaxial growth layer.

[0178] (Note 4)

[0179] The semiconductor device according to any one of Appendices 1 to 3 further comprises:

[0180] A third insulating region is provided from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region. The lower end of the third insulating region is at the same height as the lower end of the first insulating region. The third insulating region extends in the second direction and the width of the third insulating region is different from the width of the first insulating region.

[0181] A fourth insulating region is provided from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region. The lower end of the fourth insulating region is at the same height as the lower end of the second insulating region. The fourth insulating region extends in the second direction and the width of the fourth insulating region is different from the width of the second insulating region.

[0182] The fifth and sixth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the third insulating region in the third direction.

[0183] The seventh and eighth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the fourth insulating region in the third direction.

[0184] A third contact pair, the third contact pair having a fifth contact portion electrically connected to the fifth high-concentration layer and a second contact portion electrically connected to the sixth high-concentration layer; and

[0185] The fourth contact pair has a seventh contact portion electrically connected to the seventh high-concentration layer and an eighth contact portion electrically connected to the eighth high-concentration layer.

[0186] (Note 5)

[0187] The semiconductor device according to any one of Appendices 1 to 4 further comprises:

[0188] A fifth insulating region is provided from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the fifth insulating region is located at the height of the first semiconductor region where the impurity concentration is higher than the first concentration, and the fifth insulating region extends in the second direction;

[0189] Ninth and tenth high-concentration layers, which are disposed on the upper surface of the first semiconductor region and sandwich the fifth insulating region in the third direction; and

[0190] The fifth contact pair has a ninth contact portion electrically connected to the ninth high-concentration layer and a second contact portion electrically connected to the tenth high-concentration layer.

[0191] (Note 6)

[0192] The semiconductor device according to any one of Appendices 1 to 5 further comprises:

[0193] A sixth insulating region sandwiched between the bottom of the first insulating region and the first semiconductor region; and

[0194] The seventh insulating region is sandwiched between the bottom of the second insulating region and the first semiconductor region.

[0195] (Note 7)

[0196] The semiconductor device according to any one of Appendices 1 to 6 further comprises:

[0197] An eighth insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, is adjacent to the first insulating region in the third direction, the lower end of the eighth insulating region is at the same height as the lower end of the first insulating region, the eighth insulating region extends in the second direction, and the width of the eighth insulating region is the same as the width of the first insulating region.

[0198] A ninth insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, and is adjacent to the second insulating region in the third direction. The lower end of the ninth insulating region is at the same height as the lower end of the second insulating region. The ninth insulating region extends in the second direction, and the width of the ninth insulating region is the same as the width of the second insulating region.

[0199] Eleventh and twelfth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the eighth insulating region in the third direction.

[0200] The thirteenth and fourteenth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the ninth insulating region in the third direction.

[0201] A sixth contact pair, the sixth contact pair having an eleventh contact portion electrically connected to the eleventh high-concentration layer and a twelfth contact portion electrically connected to the twelfth high-concentration layer; and

[0202] The seventh contact pair has a thirteenth contact portion electrically connected to the thirteenth high-concentration layer and a fourteenth contact portion electrically connected to the fourteenth high-concentration layer.

[0203] (Note 8)

[0204] A semiconductor wafer, wherein:

[0205] In a first semiconductor region, along a first direction which is the thickness direction, the impurity concentration of a first or second conductivity type decreases from the lower surface toward the upper surface.

[0206] A first insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the first insulating region is located at the height of the first semiconductor region where the impurity concentration is a first concentration, and the first insulating region extends in a second direction orthogonal to the first direction;

[0207] A second insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the second insulating region is located at the height of the first semiconductor region where the impurity concentration is a second concentration lower than the first concentration, and the second insulating region extends in the second direction;

[0208] First and second high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the first insulating region in a third direction orthogonal to the first and second directions;

[0209] The third and fourth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the second insulating region in the third direction.

[0210] A first contact pair, the first contact pair having a first contact portion electrically connected to the first high-concentration layer and a second contact portion electrically connected to the second high-concentration layer; and

[0211] The second contact pair has a third contact portion electrically connected to the third high-concentration layer and a fourth contact portion electrically connected to the fourth high-concentration layer.

[0212] (Note 9)

[0213] An inspection method for determining the quality of a semiconductor region, comprising the following steps:

[0214] A semiconductor device is prepared, comprising: a first semiconductor region, wherein, along a first direction which is a thickness direction, the impurity concentration of a first or second conductivity type decreases from a lower surface toward an upper surface; a first insulating region, which extends from the upper surface of the first semiconductor region toward a lower surface of the first semiconductor region, the lower end of the first insulating region being at a height where the impurity concentration of the first semiconductor region is a first concentration, and the first insulating region extending in a second direction orthogonal to the first direction; and a second insulating region, which extends from the upper surface of the first semiconductor region toward a lower surface of the first semiconductor region, the lower end of the second insulating region being at a height where the impurity concentration of the first semiconductor region is lower than the first concentration. The second high-concentration layer extends in the second direction; first and second high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the first insulating region in a third direction orthogonal to the first and second directions; third and fourth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the second insulating region in the third direction; a first contact pair has a first contact portion electrically connected to the first high-concentration layer and a second contact portion electrically connected to the second high-concentration layer; and a second contact pair has a third contact portion electrically connected to the third high-concentration layer and a fourth contact portion electrically connected to the fourth high-concentration layer; and

[0215] The first resistance value between the first and second contact parts and the second resistance value between the third and fourth contact parts are measured.

[0216] (Postscript 10)

[0217] A method for manufacturing a semiconductor device, wherein the following steps are performed:

[0218] Prepare the substrate.

[0219] By forming a first epitaxial growth layer of a first or second conductivity type with a first impurity concentration of a first concentration on the substrate, forming a second epitaxial growth layer with a second impurity concentration lower than the first concentration on the first epitaxial growth layer, and forming a third epitaxial growth layer with a third impurity concentration lower than the second concentration on the second epitaxial growth layer, a first semiconductor region comprising the first to third epitaxial growth layers and wherein the impurity concentration decreases along a first direction that is the thickness direction is formed on the substrate.

[0220] A first trench is formed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region to a height where the impurity concentration is the first concentration, and a second trench is formed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region to a height where the impurity concentration is the second concentration.

[0221] A first insulating region is formed in the first trench, and a second insulating region is formed in the second trench.

[0222] On the upper surface of the first semiconductor region, a first and a second high-concentration layer sandwiching the first insulating region in a third direction orthogonal to the first and second directions, and a third and a fourth high-concentration layer sandwiching the second insulating region in the third direction, are formed.

[0223] First and second contact portions electrically connected to the first and second high-concentration layers, and third and fourth contact portions electrically connected to the third and fourth high-concentration layers are formed.

[0224] (Postscript 11)

[0225] According to the method for manufacturing a semiconductor device as described in Appendix 10, wherein,

[0226] The process of forming the first semiconductor region further includes:

[0227] A first barrier film is formed on the substrate prior to the formation of the first epitaxial growth layer;

[0228] After the formation of the first epitaxial growth layer and before the formation of the second epitaxial growth layer, a second barrier film is formed on the first epitaxial growth layer; and

[0229] After the formation of the second epitaxial growth layer and before the formation of the third epitaxial growth layer, a third barrier film is formed on the second epitaxial growth layer;

[0230] The first trench is formed by removing a portion of the first semiconductor region above the second barrier film.

[0231] The second trench is formed by removing a portion of the first semiconductor region above the third barrier film.

[0232] (Postscript 12)

[0233] A semiconductor device comprising:

[0234] In a first semiconductor region, along a first direction which is the thickness direction, the impurity concentration of a first or second conductivity type decreases from the lower surface toward the upper surface.

[0235] A first insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the first insulating region is located at the height of the first semiconductor region where the impurity concentration is a first concentration, and the first insulating region extends in a second direction orthogonal to the first direction;

[0236] A second insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the second insulating region is at the same height as the lower end of the first insulating region, the second insulating region extends in the second direction, and the width of the second insulating region is different from the width of the first insulating region;

[0237] First and second high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the first insulating region in a third direction orthogonal to the first and second directions;

[0238] The third and fourth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the second insulating region in the third direction.

[0239] A first contact pair, the first contact pair having a first contact portion electrically connected to the first high-concentration layer and a second contact portion electrically connected to the second high-concentration layer; and

[0240] The second contact pair has a third contact portion electrically connected to the third high-concentration layer and a fourth contact portion electrically connected to the fourth high-concentration layer.

Claims

1. A semiconductor device, characterized in that, have: In a first semiconductor region, along a first direction which is the thickness direction, the impurity concentration of a first or second conductivity type decreases from the lower surface toward the upper surface. A first insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the first insulating region is located at the height of the first semiconductor region where the impurity concentration is a first concentration, and the first insulating region extends in a second direction orthogonal to the first direction; A second insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the second insulating region is located at the height of the first semiconductor region where the impurity concentration is a second concentration lower than the first concentration, and the second insulating region extends in the second direction; First and second high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the first insulating region in a third direction orthogonal to the first and second directions; The third and fourth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the second insulating region in the third direction. A first contact pair, the first contact pair having a first contact portion electrically connected to the first high-concentration layer and a second contact portion electrically connected to the second high-concentration layer; as well as The second contact pair has a third contact portion electrically connected to the third high-concentration layer and a fourth contact portion electrically connected to the fourth high-concentration layer.

2. The semiconductor device according to claim 1, characterized in that, The first semiconductor region includes an epitaxial growth layer.

3. The semiconductor device according to claim 2, characterized in that, It also has: A sixth insulating region sandwiched between the bottom of the first insulating region and the first semiconductor region; and The seventh insulating region is sandwiched between the bottom of the second insulating region and the first semiconductor region.

4. The semiconductor device according to claim 2, characterized in that, It also has: An eighth insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, is adjacent to the first insulating region in the third direction, the lower end of the eighth insulating region is at the same height as the lower end of the first insulating region, the eighth insulating region extends in the second direction, and the width of the eighth insulating region is the same as the width of the first insulating region. A ninth insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, and is adjacent to the second insulating region in the third direction. The lower end of the ninth insulating region is at the same height as the lower end of the second insulating region. The ninth insulating region extends in the second direction, and the width of the ninth insulating region is the same as the width of the second insulating region. Eleventh and twelfth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the eighth insulating region in the third direction. The thirteenth and fourteenth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the ninth insulating region in the third direction. The sixth contact pair has an eleventh contact portion electrically connected to the eleventh high-concentration layer and a twelfth contact portion electrically connected to the twelfth high-concentration layer; as well as The seventh contact pair has a thirteenth contact portion electrically connected to the thirteenth high-concentration layer and a fourteenth contact portion electrically connected to the fourteenth high-concentration layer.

5. The semiconductor device according to claim 2, characterized in that, The first semiconductor region includes: The impurity concentration is the first epitaxial growth layer with the first concentration; The second epitaxial growth layer has the second impurity concentration and is located above the first epitaxial growth layer; and The impurity concentration is a third concentration that is lower than the second concentration and is located on the third epitaxial growth layer above the second epitaxial growth layer.

6. The semiconductor device according to claim 4, characterized in that, It also has: A sixth insulating region sandwiched between the bottom of the first insulating region and the first semiconductor region; and The seventh insulating region is sandwiched between the bottom of the second insulating region and the first semiconductor region.

7. The semiconductor device according to claim 1, characterized in that, It also has: A third insulating region is provided from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region. The lower end of the third insulating region is at the same height as the lower end of the first insulating region. The third insulating region extends in the second direction and the width of the third insulating region is different from the width of the first insulating region. A fourth insulating region is provided from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region. The lower end of the fourth insulating region is at the same height as the lower end of the second insulating region. The fourth insulating region extends in the second direction and the width of the fourth insulating region is different from the width of the second insulating region. The fifth and sixth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the third insulating region in the third direction. The seventh and eighth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the fourth insulating region in the third direction. The third contact pair has a fifth contact portion electrically connected to the fifth high-concentration layer and a sixth contact portion electrically connected to the sixth high-concentration layer; as well as The fourth contact pair has a seventh contact portion electrically connected to the seventh high-concentration layer and an eighth contact portion electrically connected to the eighth high-concentration layer.

8. The semiconductor device according to claim 7, characterized in that, It also has: A sixth insulating region sandwiched between the bottom of the first insulating region and the first semiconductor region; and The seventh insulating region is sandwiched between the bottom of the second insulating region and the first semiconductor region.

9. The semiconductor device according to claim 7, characterized in that, It also has: An eighth insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, is adjacent to the first insulating region in the third direction, the lower end of the eighth insulating region is at the same height as the lower end of the first insulating region, the eighth insulating region extends in the second direction, and the width of the eighth insulating region is the same as the width of the first insulating region. A ninth insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, and is adjacent to the second insulating region in the third direction. The lower end of the ninth insulating region is at the same height as the lower end of the second insulating region. The ninth insulating region extends in the second direction, and the width of the ninth insulating region is the same as the width of the second insulating region. Eleventh and twelfth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the eighth insulating region in the third direction. The thirteenth and fourteenth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the ninth insulating region in the third direction. The sixth contact pair has an eleventh contact portion electrically connected to the eleventh high-concentration layer and a twelfth contact portion electrically connected to the twelfth high-concentration layer; as well as The seventh contact pair has a thirteenth contact portion electrically connected to the thirteenth high-concentration layer and a fourteenth contact portion electrically connected to the fourteenth high-concentration layer.

10. The semiconductor device according to claim 1, characterized in that, It also has: A fifth insulating region is provided from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the fifth insulating region is located at the height of the first semiconductor region where the impurity concentration is higher than the first concentration, and the fifth insulating region extends in the second direction; The ninth and tenth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the fifth insulating region in the third direction. as well as The fifth contact pair has a ninth contact portion electrically connected to the ninth high-concentration layer and a tenth contact portion electrically connected to the tenth high-concentration layer.

11. The semiconductor device according to claim 10, characterized in that, It also has: A sixth insulating region sandwiched between the bottom of the first insulating region and the first semiconductor region; and The seventh insulating region is sandwiched between the bottom of the second insulating region and the first semiconductor region.

12. The semiconductor device according to claim 10, characterized in that, It also has: An eighth insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, is adjacent to the first insulating region in the third direction, the lower end of the eighth insulating region is at the same height as the lower end of the first insulating region, the eighth insulating region extends in the second direction, and the width of the eighth insulating region is the same as the width of the first insulating region. A ninth insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, and is adjacent to the second insulating region in the third direction. The lower end of the ninth insulating region is at the same height as the lower end of the second insulating region. The ninth insulating region extends in the second direction, and the width of the ninth insulating region is the same as the width of the second insulating region. Eleventh and twelfth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the eighth insulating region in the third direction. The thirteenth and fourteenth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the ninth insulating region in the third direction. The sixth contact pair has an eleventh contact portion electrically connected to the eleventh high-concentration layer and a twelfth contact portion electrically connected to the twelfth high-concentration layer; as well as The seventh contact pair has a thirteenth contact portion electrically connected to the thirteenth high-concentration layer and a fourteenth contact portion electrically connected to the fourteenth high-concentration layer.

13. The semiconductor device according to claim 1, characterized in that, It also has: A sixth insulating region sandwiched between the bottom of the first insulating region and the first semiconductor region; and The seventh insulating region is sandwiched between the bottom of the second insulating region and the first semiconductor region.

14. The semiconductor device according to claim 13, characterized in that, It also has: An eighth insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, is adjacent to the first insulating region in the third direction, the lower end of the eighth insulating region is at the same height as the lower end of the first insulating region, the eighth insulating region extends in the second direction, and the width of the eighth insulating region is the same as the width of the first insulating region. A ninth insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, and is adjacent to the second insulating region in the third direction. The lower end of the ninth insulating region is at the same height as the lower end of the second insulating region. The ninth insulating region extends in the second direction, and the width of the ninth insulating region is the same as the width of the second insulating region. Eleventh and twelfth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the eighth insulating region in the third direction. The thirteenth and fourteenth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the ninth insulating region in the third direction. The sixth contact pair has an eleventh contact portion electrically connected to the eleventh high-concentration layer and a twelfth contact portion electrically connected to the twelfth high-concentration layer; as well as The seventh contact pair has a thirteenth contact portion electrically connected to the thirteenth high-concentration layer and a fourteenth contact portion electrically connected to the fourteenth high-concentration layer.

15. The semiconductor device according to claim 1, characterized in that, It also has: An eighth insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, is adjacent to the first insulating region in the third direction, the lower end of the eighth insulating region is at the same height as the lower end of the first insulating region, the eighth insulating region extends in the second direction, and the width of the eighth insulating region is the same as the width of the first insulating region. A ninth insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, and is adjacent to the second insulating region in the third direction. The lower end of the ninth insulating region is at the same height as the lower end of the second insulating region. The ninth insulating region extends in the second direction, and the width of the ninth insulating region is the same as the width of the second insulating region. Eleventh and twelfth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the eighth insulating region in the third direction. The thirteenth and fourteenth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the ninth insulating region in the third direction. The sixth contact pair has an eleventh contact portion electrically connected to the eleventh high-concentration layer and a twelfth contact portion electrically connected to the twelfth high-concentration layer; as well as The seventh contact pair has a thirteenth contact portion electrically connected to the thirteenth high-concentration layer and a fourteenth contact portion electrically connected to the fourteenth high-concentration layer.

16. A semiconductor wafer, characterized in that, have: In a first semiconductor region, along a first direction which is the thickness direction, the impurity concentration of a first or second conductivity type decreases from the lower surface toward the upper surface. A first insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the first insulating region is located at the height of the first semiconductor region where the impurity concentration is a first concentration, and the first insulating region extends in a second direction orthogonal to the first direction; A second insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the second insulating region is located at the height of the first semiconductor region where the impurity concentration is a second concentration lower than the first concentration, and the second insulating region extends in the second direction; First and second high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the first insulating region in a third direction orthogonal to the first and second directions; The third and fourth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the second insulating region in the third direction. A first contact pair, the first contact pair having a first contact portion electrically connected to the first high-concentration layer and a second contact portion electrically connected to the second high-concentration layer; as well as The second contact pair has a third contact portion electrically connected to the third high-concentration layer and a fourth contact portion electrically connected to the fourth high-concentration layer.

17. An inspection method for determining the quality of a semiconductor region, characterized in that, It includes the following steps: A semiconductor device is prepared, comprising: a first semiconductor region, wherein the impurity concentration of a first or second conductivity type decreases from a lower surface toward an upper surface along a first direction which is a thickness direction; a first insulating region, which is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the first insulating region being at a height where the impurity concentration of the first semiconductor region is a first concentration, and the first insulating region extending in a second direction orthogonal to the first direction; a second insulating region, which is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the second insulating region being at a height where the impurity concentration of the first semiconductor region is a second concentration lower than the first concentration, and the second insulating region extending in the second direction; and first and second high-concentration layers, which are disposed on the upper surface of the first semiconductor region and sandwich the first insulating region in a third direction orthogonal to the first and second directions. Third and fourth high-concentration layers, the third and fourth high-concentration layers being disposed on the upper surface of the first semiconductor region and sandwiching the second insulating region in the third direction; a first contact pair, the first contact pair having a first contact portion electrically connected to the first high-concentration layer and a second contact portion electrically connected to the second high-concentration layer; and a second contact pair, the second contact pair having a third contact portion electrically connected to the third high-concentration layer and a fourth contact portion electrically connected to the fourth high-concentration layer; as well as The first resistance value between the first and second contact parts and the second resistance value between the third and fourth contact parts are measured.

18. A method for manufacturing a semiconductor device, characterized in that, The following procedures will be performed: Prepare the substrate; By forming a first epitaxial growth layer of a first or second conductivity type with a first impurity concentration of a first concentration on the substrate, forming a second epitaxial growth layer with a second impurity concentration of a lower than the first concentration on the first epitaxial growth layer, and forming a third epitaxial growth layer with a third impurity concentration of a lower than the second concentration on the second epitaxial growth layer, a first semiconductor region comprising the first to third epitaxial growth layers and wherein the impurity concentration decreases along a first direction which is the thickness direction is formed on the substrate. A first trench is formed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region to a height where the impurity concentration is the first concentration, and a second trench is formed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region to a height where the impurity concentration is the second concentration; A first insulating region is formed in the first trench, and a second insulating region is formed in the second trench; On the upper surface of the first semiconductor region, first and second high-concentration layers are formed in a third direction orthogonal to the first and second directions, sandwiching the first insulating region, and third and fourth high-concentration layers are formed in the third direction, sandwiching the second insulating region; and First and second contact portions electrically connected to the first and second high-concentration layers, and third and fourth contact portions electrically connected to the third and fourth high-concentration layers are formed.

19. The method for manufacturing a semiconductor device according to claim 18, characterized in that, The process of forming the first semiconductor region further includes: A first barrier film is formed on the substrate prior to the formation of the first epitaxial growth layer; After the formation of the first epitaxial growth layer and before the formation of the second epitaxial growth layer, a second barrier film is formed on the first epitaxial growth layer; as well as After the formation of the second epitaxial growth layer and before the formation of the third epitaxial growth layer, a third barrier film is formed on the second epitaxial growth layer; The first trench is formed by removing a portion of the first semiconductor region above the second barrier film. The second trench is formed by removing a portion of the first semiconductor region above the third barrier film.

20. A semiconductor device, characterized in that, have: In a first semiconductor region, along a first direction which is the thickness direction, the impurity concentration of a first or second conductivity type decreases from the lower surface toward the upper surface. A first insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the first insulating region is located at the height of the first semiconductor region where the impurity concentration is a first concentration, and the first insulating region extends in a second direction orthogonal to the first direction; A second insulating region is disposed from the upper surface of the first semiconductor region toward the lower surface of the first semiconductor region, the lower end of the second insulating region is at the same height as the lower end of the first insulating region, the second insulating region extends in the second direction, and the width of the second insulating region is different from the width of the first insulating region; First and second high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the first insulating region in a third direction orthogonal to the first and second directions; The third and fourth high-concentration layers are disposed on the upper surface of the first semiconductor region and sandwich the second insulating region in the third direction. A first contact pair, the first contact pair having a first contact portion electrically connected to the first high-concentration layer and a second contact portion electrically connected to the second high-concentration layer; as well as The second contact pair has a third contact portion electrically connected to the third high-concentration layer and a fourth contact portion electrically connected to the fourth high-concentration layer.

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