A gallium oxide power diode with a spatial modulation junction termination and a method of manufacturing the same

Abstract

This invention discloses a gallium oxide space modulation junction terminated extended power diode and its fabrication method. This structure effectively distributes the electric field through periodically arranged NiO rings, alleviating the problem of anode electric field concentration. The structural parameters were simulated and optimized using TCAD software. Results show that the highest breakdown voltage of the double-layer structure (…) V BR The voltage withstand capability was increased to 6.05 kV, and at 5 kV, the relative doping window (RDW) broadened to ±80%, which is superior to previously reported similar β-Ga2O3 devices (3 kV ±50%). Furthermore, the device maintained a voltage withstand capability of 3.55 mΩ·cm while achieving high breakdown voltage performance. 2 The ratio of on-resistance (R) on,sp ) and 10.31 GW / cm 2 The power figure of merit (PFOM) is obtained. This provides a feasible device design scheme for achieving β-Ga2O3 power devices that balance high voltage withstand capability and a wide process window, offering valuable reference for improving device reliability and manufacturing feasibility.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and more particularly to gallium oxide space modulation junction terminated extended power diodes and their fabrication methods. Background Technology

[0002] In recent years, with the increasing demand for high efficiency, high power density, and miniaturization in power electronic systems, the research on wide bandgap semiconductor materials has gradually become a global focus. Gallium oxide (with β-Ga2O3 as the most typical example) has become a widely studied object due to its excellent material properties. This material has an ultra-wide bandgap of 4.4-4.9 eV, can withstand a critical breakdown electric field of about 8 MV / cm, and has a high electron mobility of about 300 cm² / V·s. Its Baliga figure of merit (BFOM) can reach 3444, far exceeding that of carbon silicide (SiC) and gallium nitride (GaN). In addition, Ga2O3 can also be used to obtain large-size, high-quality single-crystal substrates through low-cost melt methods. In terms of growth technology, methods such as halide vapor phase epitaxy (HVPE), metal-organic chemical vapor deposition (MOCVD), and molecular beam epitaxy (MBE) can achieve n-type doping concentrations from 1×10⁻⁶. 15 cm -3 Up to 1×10 19 cm -3 The fabrication of high-quality Ga2O3 epitaxial layers within a specific range. Therefore, gallium oxide is considered a next-generation semiconductor material with great potential in the field of power electronics.

[0003] Due to the lack of an effective p-type doping mechanism in Ga2O3, Ga2O3 Schottky barrier diodes (SBDs) were a key research focus in the early stages, with optimization of the termination structure being of great significance. Typical structures include field plates (FP), field confinement rings (FLR), magnesium ion implantation terminations (Mg-ET), tilted mesa, and groove structures. Although these designs improve the breakdown characteristics of SBDs to some extent, fully realizing the breakdown advantages of Ga2O3 itself remains a significant challenge. In contrast, PN heterojunction diodes are more valuable in demonstrating the high breakdown potential of Ga2O3. In recent years, p-type NiO has been considered an ideal candidate material for constructing Ga2O3-based PN heterojunction diodes. NiO is a naturally controllably doped p-type semiconductor with a critical breakdown field of approximately 4–6 MV / cm and a relative permittivity of approximately 15. This allows it to achieve an extremely high overall critical breakdown electric field when combined with Ga2O3, thereby obtaining a higher reverse breakdown voltage and fully leveraging the material advantages of Ga2O3. Existing research has shown that introducing a termination structure into a PN heterojunction diode can achieve a breakdown voltage of over 10 kV and a power factor of over 10 GW. Among them, junction termination extension (JTE) has attracted widespread attention because it is relatively simple to design and fabricate, and can effectively suppress electric field concentration in the electrode region and improve the breakdown voltage.

[0004] However, most current research focuses on further improving the breakdown voltage, neglecting the fact that the optimal doping dose window required for high breakdown voltage in JTE structures is often too narrow, and the hole concentration degradation caused by the thermal stability of NiO, which is particularly critical under non-ideal process conditions and practical operating scenarios. The electric field uniformity in the JTE region is highly dependent on the doping concentration. Due to process errors during manufacturing, it is difficult to precisely control the doping concentration, or the charge concentration may fluctuate due to temperature changes in practical applications. This may cause the JTE region to fail, leading to premature device breakdown and thus failing to fully utilize the advantages of Ga2O3 materials. Summary of the Invention

[0005] This invention proposes a gallium oxide space modulation junction terminated extended power diode with high voltage withstand capability, low loss and wide process tolerance, as well as its fabrication method.

[0006] 1. A first aspect of the present invention provides a single-layer gallium oxide space modulation junction terminated extended power diode, comprising, from bottom to top, a cathode, an n-type Ga2O3 substrate, an n-type Ga2O3 drift layer, a space modulation junction terminated extended SM-JTE region formed by p-type NiO, an anode contact region formed by p-type NiO, an anode, and an HfO2 passivation layer, wherein the diameters of the anode and the anode contact region are smaller than those of the n-type Ga2O3 drift layer; the space modulation junction terminated extended SM-JTE region includes an inner ring JET region and an outer ring SM region, wherein the JTE region is a NiO JTE body and is partially located below the anode contact region and partially extends beyond the anode contact region; the SM region has N sub-regions radially arranged from the edge of the NiO JTE body, which are sequentially arranged from the inside to the outside as regions. i =1,2…, N Each sub-region is provided with a NiO ring structure, wherein the NiO ring structure consists of one or more NiO rings within the sub-region, and the remaining portion is covered by an HfO2 passivation layer. The radial width of each sub-region is fixed. ,in W s is the base width, the first... i The number of NiO rings in each subregion is And when At that time, the spacing between adjacent NiO rings within the sub-region is fixed as W S ,when At that time, the width of the NiO ring within the sub-region is fixed as W s, the spacing between adjacent NiO rings is The HfO2 passivation layer covers the n-type Ga2O3 drift layer and the spatial modulation junction terminal extension SM-JTE region, and contacts the anode contact area and the anode edge.

[0007] The SM-JTE region has a thickness of 150~250 nm, and the JET region extends beyond the anode contact region in width. L E The thickness is 10–30 μm, and the N value of the sub-region is 6–12. The thickness of the n-type Ga₂O₃ substrate is 500–650 μm, and the donor concentration is higher than 1 × 10⁻⁶. 19 cm -3 The thickness of the n-type Ga2O3 drift layer is 7~13 μm, and the donor concentration is 1.0×10⁻⁶. 16 cm -3 ~2.0×10 16 cm -3 The thickness of the anode contact region formed by p-type NiO is 75~150 nm, and the acceptor concentration is higher than 1.0 × 10⁻⁶. 19 cm -3 .

[0008] 2. A second aspect of the present invention provides a double-layer gallium oxide space modulation junction terminated extended power diode, comprising, from bottom to top, a cathode, an n-type Ga2O3 substrate, an n-type Ga2O3 drift layer, a space modulation junction terminated extended SM-JTE region formed by p-type NiO, an anode contact region formed by p-type NiO, an anode, and an HfO2 passivation layer. The diameters of the anode and the anode contact region are smaller than those of the n-type Ga2O3 drift layer. The space modulation junction terminated extended SM-JTE region includes an upper SM-JTE region and a lower SM-JTE region. The upper SM-JTE region includes an upper JET region and an upper SM region. The upper JET region is a NiOJTE1 body and is partially located below the anode contact region and partially extends beyond the anode contact region. The upper SM region has N1 sub-regions radially arranged from the edge of the NiOJTE1 body, which are arranged sequentially from the inside to the outside. i =1,2…, N 1. Each sub-region is provided with a NiO ring structure, wherein the NiO ring structure consists of one or more NiO rings within the sub-region, and the remaining portion is covered by an HfO2 passivation layer. The radial width of each sub-region is fixed. ,in W S1 As the base width, the first i The number of NiO rings in each subregion is And when At that time, the spacing between adjacent NiO rings within the sub-region is fixed as W S1 ,when At that time, the width of the NiO ring within the sub-region is fixed as W S1 The spacing between adjacent NiO rings is The lower SM-JTE region includes a lower JET region and a lower SM region. The lower JET region is a NiO JTE2 body and is partially located below the upper SM-JTE region and partially extends beyond the upper SM-JTE region. The lower SM region has N2 sub-regions radially arranged from the edge of the NiO JTE2 body, which are arranged sequentially from the inside to the outside. i =1,2…, N 2. Each sub-region is provided with a NiO ring structure, wherein the NiO ring structure consists of one or more NiO rings within the sub-region, and the remaining portion is covered by an HfO2 passivation layer. The radial width of each sub-region is fixed. , No. i The number of NiO rings in each subregion is And when At that time, the spacing between adjacent NiO rings within the sub-region is fixed as WS2 ,when At that time, the width of the NiO ring within the sub-region is fixed as W S2 The spacing between adjacent NiO rings is The HfO2 passivation layer covers the n-type Ga2O3 drift layer and the spatial modulation junction terminal extension SM-JTE region, and contacts the anode contact area and the anode edge.

[0009] The upper and lower SM-JTE regions are both 150~250 nm in size, and the width of the upper JET region extending beyond the anode contact area is... L E1 The width is 10~30 μm, and the portion of the lower JET region that extends beyond the upper SM-JTE region is [missing information]. L E2 For and L E1 = L E2 The number of sub-regions N 1 = N 2 = 6~12, the aforementioned W S1 =W S2 = 0.5~2 μm, Ratio= D JTE2 / D JTE1 =1.0~0.1, where D JTE2 For the charge density of the upper SM-JTE region, D JTE1 This represents the charge density of the lower SM-JTE region. The thickness of the n-type Ga2O3 substrate is 500~650 μm, and the donor concentration is higher than 1 × 10⁻⁶. 19 cm -3 The thickness of the n-type Ga2O3 drift layer is 7~13 μm, and the donor concentration is 1.0×10⁻⁶. 16 cm -3 ~2.0×10 16 cm -3 The thickness of the anode contact region formed by p-type NiO is 75~150 nm, and the acceptor concentration is higher than 1.0 × 10⁻⁶. 19 cm -3 .

[0010] 3. A third aspect of the present invention provides a method for fabricating the above-mentioned monolayer gallium oxide space modulation junction terminated extended power diode, comprising the following steps: Step 1: Use N+ Type β-Ga2O3 substrate, in the N + N-type β-Ga2O3 substrates were epitaxially grown on the front side using halide vapor phase epitaxy. - Type β-Ga2O3 drift layer; Step 2: For the N - The β-Ga2O3 drift layer was cleaned by sequentially cleaning with acetone, isopropanol and deionized water to remove surface impurities and organic residues, or by oxidizing with piranha solution. After cleaning, it was dried with high-purity nitrogen. Step 3: In the N + A cathode electrode was formed by electron beam evaporation deposition of a Ti / Au metal stack on the back side of a β-Ga2O3 substrate; subsequently, it was rapidly thermally annealed at 470°C for 1 min in a nitrogen atmosphere to form a cathode ohmic contact. Step 4: In the N - A double-layer release photoresist is spin-coated onto the surface of a β-Ga2O3 drift layer. An opening pattern is formed in the photoresist layer by exposure and development to expose the P-type substrate to be deposited. - The region of the NiO thin film; the opening pattern corresponds to the spatial modulation junction terminal extension SM-JTE region to be formed; Step 5: Deposit P on the surface of the sample obtained in Step 4 using radio frequency magnetron sputtering. - The NiO thin film was sputtered under the following conditions: RF power 300 W, cavity pressure 4 mTorr, and an Ar / O2 mixture atmosphere. The P value was controlled by adjusting the O2 / (O2+Ar) flow ratio. - Doping concentration of NiO thin film; Step 6: Perform a stripping process on the sample obtained in Step 5 to remove the double-layer stripping photoresist and the P deposited on the photoresist layer. - The NiO film retains only the P deposited in the area exposed by the opening pattern. - NiO thin film, thereby forming a patterned NiO terminal layer; the patterned NiO terminal layer is a spatial modulation junction terminal extension SM-JTE region; Step 7: A patterned photoresist layer is re-formed in the center of the patterned NiO terminal layer described in Step 6. An anode contact layer opening pattern is formed in the photoresist layer through exposure and development to expose the P to be deposited. + The region of NiO thin film; subsequently, P was deposited using radio frequency magnetron sputtering. + NiO thin film is used as the anode ohmic contact layer; Step 8: Perform a stripping process on the sample obtained in Step 7 to remove the patterned photoresist layer and the P deposited on the photoresist layer. + NiO thin film, retaining only P in the anode contact area +NiO film; then annealed at 300°C for 5 min in a nitrogen atmosphere to improve the crystal quality and contact properties of the NiO film; Step 9: The P mentioned in step 8 + The anode metal region is defined on top of the NiO thin film by photolithography, and a Ni / Au metal stack is deposited by electron beam evaporation, followed by a lift-off process to form the anode electrode; Step 10: Anneal the sample from Step 9 in a nitrogen atmosphere at 300°C for 5 min to improve the Ni / Au anode metal and P + Ohmic contact between NiO; Step 11: Deposit an HfO2 passivation layer on the front side of the device from step 10, so that the HfO2 passivation layer covers N. - Type β-Ga2O3 drift layer and patterned NiO terminal layer.

[0011] 4. A fourth aspect of the present invention provides a method for fabricating the above-mentioned double-layer gallium oxide space modulation junction terminated extended power diode, comprising the following steps: Step 1: Use N + Type β-Ga2O3 substrate, in the N + N-type β-Ga2O3 substrates were epitaxially grown on the front side using halide vapor phase epitaxy. - Type β-Ga2O3 drift layer; Step 2: For the N - The β-Ga2O3 drift layer was cleaned by sequentially cleaning with acetone, isopropanol and deionized water to remove surface impurities and organic residues, or by oxidizing with piranha solution. After cleaning, it was dried with high-purity nitrogen. Step 3: In the N + A cathode electrode was formed by electron beam evaporation deposition of a Ti / Au metal stack on the back side of a β-Ga2O3 substrate; subsequently, it was rapidly thermally annealed at 470°C for 1 min in a nitrogen atmosphere to form a cathode ohmic contact. Step 4: In the N - A double-layer release photoresist is spin-coated onto the surface of a β-Ga2O3 drift layer. A first opening pattern is formed in the photoresist layer through exposure and development to expose the first P-type deposit to be deposited. - The region of the NiO thin film; the first opening pattern corresponds to the lower SM-JTE region to be formed; Step 5: Deposit the first P on the surface of the sample obtained in Step 4 using radio frequency magnetron sputtering. - The NiO thin film, the process conditions for radio frequency magnetron sputtering are RF power 300 W, cavity pressure 4 mTorr, and atmosphere of Ar / O2 mixture, and the first P is controlled by adjusting the O2 / (O2+Ar) flow ratio.- Doping concentration of NiO thin film; Step 6: Perform a stripping process on the sample obtained in Step 5 to remove the double-layer stripping photoresist and the first P layer deposited on the photoresist layer. - The NiO film retains only the first P deposited in the area exposed by the first opening pattern. - A NiO thin film is formed to create a first patterned NiO terminal layer; the first patterned NiO terminal layer is the lower SM-JTE region. Step 7: Spin-coat a double-layer stripping photoresist again on the sample surface where the first patterned NiO terminal layer has been formed. Form a second opening pattern in the photoresist layer by alignment, exposure and development to expose the area where the second P NiO film is to be deposited; the second opening pattern corresponds to the upper SM-JTE area to be formed. Step 8: Deposit a second P NiO thin film on the surface of the sample obtained in step 7 using radio frequency magnetron sputtering, wherein the process conditions for radio frequency magnetron sputtering are the same as those in step 5; Step 9: Perform a stripping process on the sample obtained in Step 8 to remove the double-layer stripping photoresist and the second P NiO film deposited on the photoresist layer, retaining only the second P NiO film deposited in the area exposed by the second opening pattern, thereby forming a second patterned NiO terminal layer; the second patterned NiO terminal layer is the upper SM-JTE region, and the lower SM-JTE region and the upper SM-JTE region together form the spatial modulation junction terminal extension SM-JTE region; Step 10: In step 9, a patterned photoresist layer is re-formed in the middle of the second patterned NiO terminal layer. An anode contact layer opening pattern is formed in the photoresist layer by exposure and development to expose the P to be deposited. + The region of NiO thin film; subsequently, P was deposited using radio frequency magnetron sputtering. + NiO thin film is used as the anode ohmic contact layer; Step 11: Perform a stripping process on the sample obtained in Step 10 to remove the patterned photoresist layer and the P deposited on the photoresist layer. + NiO thin film, retaining only P in the anode contact area + NiO film; then annealed at 300°C for 5 min in a nitrogen atmosphere to improve the crystal quality and contact properties of the NiO film; Step 12: The P mentioned in step 11 + The anode metal region is defined on top of the NiO thin film by photolithography, and a Ni / Au metal stack is deposited by electron beam evaporation, followed by a lift-off process to form the anode electrode; Step 13: Anneal the sample from Step 12 in a nitrogen atmosphere at 300°C for 5 min to improve the Ni / Au anode metal and P + Ohmic contact between NiO; Step 14: Deposit an HfO2 passivation layer on the front side of the device from step 13, so that the HfO2 passivation layer covers N. - Type β-Ga2O3 drift layer, lower SM-JTE region and upper SM-JTE region.

[0012] Beneficial effects: 1. The monolayer gallium oxide space modulation junction terminated extended power diode of the present invention, the monolayer SM-JTE structure optimized as described above, can achieve a maximum voltage of 6kV. V BR This effectively reduces the peak electric field at the device terminal edge, but under 5kV withstand voltage conditions... D JTE The window range remains only 0.33-0.5×10 14 cm -2 (Figure 8(c)) corresponds to RDW=±20%, and the process tolerance is still limited.

[0013] 2. The bilayer gallium oxide space-modulated junction terminated extended power diode of this invention suppresses electric field concentration at the anode edge in the upper SM-JTE region, while promoting lateral expansion and uniform distribution of the termination electric field in the lower SM-JTE region. This achieves synergistic control of the electric field at the heterojunction interface, thereby significantly widening the doping process window. Based on TCAD simulation verification, the highest breakdown voltage (V) of the bilayer structure is [value missing]. BR The voltage was increased to 6.05 kV, exceeding the ideal parallel-plane junction voltage. BR The relative doping window (RDW) is increased to ±80% at 5 kV, which is superior to previously reported β-Ga₂O₃ devices (3 kV ±50%). Furthermore, the device maintains a voltage rating of 3.55 mΩ·cm while achieving high breakdown voltage performance. 2 The specific on-resistance (Ron,sp) is 10.31 GW / cm. 2 Power figure of merit (PFOM) with leakage current as low as 10 -7 A / cm 2 This study provides a feasible device design scheme for achieving β-Ga2O3 power devices that balance high voltage withstand capability and a wide process window, offering valuable insights for improving device reliability and manufacturing feasibility. Attached Figure Description

[0014] Figure 1(a) is a schematic diagram of a single-layer SM-JTE structure; Figure 1(b) is a schematic diagram of the double-layer SM-JTE structure; Figure 2(a) is a schematic diagram of the NiO ring distribution when n is an odd number; Figure 2(b) is a schematic diagram of the distribution of NiO rings when n is even; Figure 2(c) is a schematic diagram of the effective charge density of NiO and the distribution of NiO rings in the terminal region when n is an even number. Figure 3 A schematic diagram of the fabrication process for double-layer SM-JTE HJD; Figure 4(a) is a schematic diagram of the equipotential line distribution in the β-Ga2O3 HJD junction region without JET structure under reverse bias of 5 kV; Figure 4(b) is a schematic diagram of the equipotential line distribution in the β-Ga2O3 HJD junction region of the traditional JTE structure under a reverse bias of 5 kV; Figure 4(c) is a schematic diagram of the equipotential line distribution in the β-Ga2O3 HJD junction region of a single-layer SM-JTE structure under a reverse bias of 5 kV; Figure 4(d) is a schematic diagram of the equipotential line distribution in the β-Ga2O3 HJD junction region of the double-layer SM-JTE structure under a reverse bias of 5 kV; Figure 5(a) shows four structures: no JET, conventional JTE, single-layer SM-JTE, and double-layer SM-JTE. V BR and D JTE A line graph showing the relationship between changes; Figure 5(b) shows the electric field distribution at the heterojunction interface of four structures: JET, conventional JTE, single-layer SM-JTE, and double-layer SM-JTE, under reverse bias of 5 kV. Figure 5(c) shows the schematic diagram and calculation formula of the one-dimensional electric field distribution of β-Ga2O3 HJD; Figure 6(a) shows the structure without JET under a 5kV reverse bias. JTE =5.0×10 13 cm -2 A schematic diagram of the two-dimensional electric field distribution; Figure 6(b) shows the single-layer SM-JTE structure under a 5kV reverse bias. JTE =2.0×10 13 cm -2 A schematic diagram of the two-dimensional electric field distribution; Figure 6(c) Single-layer SM-JTE structure under 5kV reverse bias D JTE =4.2×10 13 cm -2 A schematic diagram of the two-dimensional electric field distribution; Figure 6(d) shows the single-layer SM-JTE structure under a 5kV reverse bias. JTE =8.0×10 13 cm-2 A schematic diagram of the two-dimensional electric field distribution; Figure 7 Along Figure 6(a), Figure 6(b), Figure 6(c) , 6(c) The cross-sectional electric field distribution curves of the four devices were extracted by the horizontal cutting line AA' on the surface of the β-Ga2O3 drift layer. Figure 8(a) shows the different traditional JTE structures L E of V BR Follow D JTE A line graph showing the relationship between changes; Figure 8(b) shows the single-layer SM-JTE structure. L E = 20 μm W S = 0.5 μm different N of V BR Follow D JTE A line graph showing the relationship between changes; Figure 8(c) shows a single-layer SM-JTE structure. L E = 20 μm N = 9 different W s V BR Follow D JTE A line graph showing the relationship between changes; Figure 9(a) shows the dual-layer SM-JTE device. N 1 = N 2 = 9 W S1 = W S2 = 0.5 μm different L E2 In this case V BR Follow D JTE A line graph showing the relationship between changes; Figure 9(b) shows the dual-layer SM-JTE device. L E1 = L E2 = 20 μm W S1 = W S2 = 0.5 μm different N 2 cases VBR Follow D JTE A line graph showing the relationship between changes; Figure 9(c) shows the dual-layer SM-JTE device. L E1 = L E2 = 20 μm N 1 = N 2 = 9 is different W S2 In this case V BR Follow D JTE A line graph showing the relationship between changes; Figure 10 For the optimal structural parameters of the double-layer SM-JTE under different ratios V BR Follow D JTE Change relationship Figure 11(a) is a line graph showing the distribution of the surface electric field of the β-Ga2O3 drift layer of the optimal double-layer SM-JTE structure under Ratio=1.6 with a reverse bias of 5kV. Figure 11(b) is a line graph showing the surface electric field distribution of the β-Ga2O3 drift layer of the optimal double-layer SM-JTE structure under Ratio=1.0 with a reverse bias of 5kV. Figure 11(c) is a line graph showing the distribution of the surface electric field of the β-Ga2O3 drift layer of the optimal double-layer SM-JTE structure under Ratio=0.2 with a reverse bias of 5kV. Figure 12(a) shows the Ron,sp and current density as a function of anode radius for four structures: no JET, conventional JTE, single-layer SM-JTE, and double-layer SM-JTE. R adius Line graph showing the relationship between changes. Figure 12(b) shows four structures: no JET, traditional JTE, single-layer SM-JTE, and double-layer SM-JTE. R adius Linear J-V characteristic curve at 300 μm; Figure 12(c) shows four structures: no JET, traditional JTE, single-layer SM-JTE, and double-layer SM-JTE. R adius Semi-log J-V characteristic plot at 300 μm; Figure 12(d) shows four structures: no JET, conventional JTE, single-layer SM-JTE, and double-layer SM-JTE. R adiusAt 300 μm, Ron, sp, and PFOM vary with D JTE A line graph showing the relationship between changes; Detailed Implementation

[0015] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. However, the present invention is not limited to these embodiments. Any improvements or substitutions based on the basic spirit of these embodiments shall still fall within the scope of protection claimed by the present invention.

[0016] Example 1: As Figure 1(a) , 2(a) As shown in 2(b) and 2(c), this embodiment provides a single-layer gallium oxide space modulation junction terminal extension power diode, the structure of which from bottom to top includes a cathode, an n-type Ga2O3 substrate, an n-type Ga2O3 drift layer, a space modulation junction terminal extension SM-JTE region formed by p-type NiO, an anode contact region formed by p-type NiO, an anode, and an HfO2 passivation layer.

[0017] The diameter of the anode and the anode contact region is smaller than that of the n-type Ga2O3 drift layer. The spatial modulation junction termination extension SM-JTE region includes an inner JET region and an outer SM region. The JTE region is a NiO JTE body, partly located below the anode contact region and partly extending beyond the anode contact region. The SM region has N sub-regions radially arranged from the edge of the NiO JTE body, arranged sequentially from the inside to the outside. i =1,2…, N Each sub-region is provided with a NiO ring structure, wherein the NiO ring structure is provided with one or more NiO rings in the sub-region and the rest is covered by an HfO2 passivation layer.

[0018] The radial width of each sub-region is fixed as follows: ,in W s is the base width. i The number of NiO rings in each subregion is And when At that time, the spacing between adjacent NiO rings within the sub-region is fixed as W S ;when At that time, the width of the NiO ring within the sub-region is fixed as W s, the spacing between adjacent NiO rings is The HfO2 passivation layer covers the n-type Ga2O3 drift layer and the spatial modulation junction terminal extension SM-JTE region, and contacts the anode contact area and the anode edge.

[0019] The SM-JTE region has a thickness of 150~250 nm, and the JET region extends beyond the anode contact region in width. L E The size is 10~30 μm, and the sub-region N is 6~12. W S = The thickness of the n-type Ga2O3 substrate is 0.5~2 μm, and the donor concentration is higher than 1 × 10⁻⁶ μm. 19 cm -3 The thickness of the n-type Ga2O3 drift layer is 7~13 μm, and the donor concentration is 1.0×10⁻⁶. 16 cm -3 ~2.0×10 16 cm -3 The thickness of the anode contact region formed by p-type NiO is 75~150 nm, and the acceptor concentration is higher than 1.0 × 10⁻⁶. 19 cm -3 .

[0020] The thickness of the SM-JTE region can be selected, but is not limited to, 150, 210, or 250 nm, and the width of the JET region extending beyond the anode contact region... L E The sub-region N can be selected, but is not limited to, 10, 17, 23, or 30 μm, and can be selected, but is not limited to, 6, 8, or 12. W S The thickness can be selected, but is not limited to, 0.5, 0.8, 1.5, or 2 μm. The thickness of the n-type Ga2O3 substrate can be selected, but is not limited to, 500, 600, or 650 μm, and the donor concentration is higher than 1 × 10⁻⁶. 19 cm -3 The thickness of the n-type Ga2O3 drift layer can be selected, but is not limited to, 7, 10, or 13 μm, and the donor concentration is 1.0 × 10⁻⁶. 16 cm -3 ~2.0×10 16 cm -3 The thickness of the anode contact region formed by p-type NiO can be selected, but is not limited to, 75, 100, or 150 nm, and the acceptor concentration is higher than 1.0 × 10⁻⁶. 19 cm -3 .

[0021] Example 2: Figure 1(b) , 2(a)As shown in 2(b) and 2(c), this embodiment provides a double-layer gallium oxide space modulation junction terminal extension power diode, the structure of which from bottom to top includes a cathode, an n-type Ga2O3 substrate, an n-type Ga2O3 drift layer, a space modulation junction terminal extension SM-JTE region formed by p-type NiO, an anode contact region formed by p-type NiO, an anode, and an HfO2 passivation layer.

[0022] The diameter of the anode and the anode contact region is smaller than that of the n-type Ga2O3 drift layer. The spatial modulation junction termination extension SM-JTE region includes an upper SM-JTE region and a lower SM-JTE region. The upper SM-JTE region includes an upper JET region and an upper SM region. The upper JET region is a NiO JTE1 body and is partially located below the anode contact region and partially extends beyond the anode contact region. The upper SM region has N1 sub-regions radially arranged from the edge of the NiO JTE1 body, which are arranged sequentially from the inside to the outside. i =1,2…, N 1. Each sub-region is provided with a NiO ring structure, wherein the NiO ring structure consists of one or more NiO rings within the sub-region, and the remaining portion is covered by an HfO2 passivation layer. The radial width of each sub-region is fixed. ,in W S1 The base width. i The number of NiO rings in each subregion is And when At that time, the spacing between adjacent NiO rings within the sub-region is fixed as W S1 ;when At that time, the width of the NiO ring within the sub-region is fixed as W S1 The spacing between adjacent NiO rings is .

[0023] The lower SM-JTE region includes a lower JET region and a lower SM region. The lower JET region is a NiOJTE2 body and is partially located below the upper SM-JTE region and partially extends beyond the upper SM-JTE region. The lower SM region has N2 sub-regions radially arranged from the edge of the NiOJTE2 body, which are arranged sequentially from the inside to the outside. i =1,2…, N 2. Each sub-region is provided with a NiO ring structure, wherein the NiO ring structure consists of one or more NiO rings within the sub-region, and the remaining portion is covered by an HfO2 passivation layer. The radial width of each sub-region is fixed. , No. i The number of NiO rings in each subregion is ,in WS2 The base width. And when At that time, the spacing between adjacent NiO rings within the sub-region is fixed as W S2 ,when At that time, the width of the NiO ring within the sub-region is fixed as W S2 The spacing between adjacent NiO rings is The HfO2 passivation layer covers the n-type Ga2O3 drift layer and the spatial modulation junction terminal extension SM-JTE region, and contacts the anode contact area and the anode edge.

[0024] The upper and lower SM-JTE regions are both 150~250 nm in size, and the width of the upper JET region extending beyond the anode contact area is... L E1 The width of the portion of the lower JET region that extends beyond the upper SM-JTE region is [missing information]. L E2 and L E1 = L E2 =10~30 μm, the number of sub-regions N 1 = N 2 = 6~12, the aforementioned W S1 =W S2 = 0.5~2 μm, Ratio= D JTE2 / D JTE1 =1.0~0.2, where D JTE1 For the charge density of the upper SM-JTE region, D JTE2 This represents the charge density of the lower SM-JTE region. The thickness of the n-type Ga2O3 substrate is 500~650 μm, and the donor concentration is higher than 1 × 10⁻⁶. 19 cm -3 The thickness of the n-type Ga2O3 drift layer is 7~13 μm, and the donor concentration is 1.0×10⁻⁶. 16 cm -3 ~2.0×10 16 cm -3 The thickness of the anode contact region formed by p-type NiO is 75~150 nm, and the acceptor concentration is higher than 1.0 × 10⁻⁶. 19 cm -3 .

[0025] The upper SM-JTE region and the lower SM-JTE region can be selected, but are not limited to, 150, 170, 190, 210, 230, or 250 nm. L E1 and L E2 The number of sub-regions can be selected, but is not limited to, 10, 15, 20, 25, or 30 μm. N 1 and N 2 can be selected, but is not limited to, 6, 8, 10, or 12, the... W S1 and W S2 Available options include, but are not limited to, 0.5, 0.9, 1.5, or 2 μm, Ratio= D JTE2 / D JTE1 =0.2, 0.4, 0.6, 0.8 or 1.0, the thickness of the n-type Ga2O3 substrate can be selected, but is not limited to, 500, 600 or 650 μm, and the donor concentration is higher than 1 × 10⁻⁶. 19 cm -3 The thickness of the n-type Ga2O3 drift layer can be selected, but is not limited to, 7, 9, or 13 μm, and the donor concentration is 1.0 × 10⁻⁶. 16 cm -3 ~2.0×10 16 cm -3 The thickness of the anode contact region formed by p-type NiO can be selected, but is not limited to, 75, 90, 120, or 150 nm, and the acceptor concentration is higher than 1.0 × 10⁻⁶ nm. 19 cm -3 .

[0026] Example 3: This example provides a method for fabricating the monolayer gallium oxide space modulation junction terminated extended power diode of Example 1, including the following steps: Step 1: Provide an N + Type β-Ga2O3 substrate, the N + The doping concentration of the β-Ga₂O₃ substrate is higher than 1×10⁻⁶. 19 cm -3 ; in the N + N-type β-Ga2O3 substrates were epitaxially grown on the front side using halide vapor phase epitaxy (HVPE). - The N⁻ type β-Ga₂O₃ drift layer has a thickness of 7~13 μm and a doping concentration of 1.0×10⁻⁶. 16 cm -3 ~2.0×10 16 cm -3 .

[0027] Step 2: Clean the β-Ga2O3 epitaxial wafer by sequentially cleaning it with acetone, isopropanol and deionized water to remove surface impurities and organic residues; if necessary, use piranha solution for oxidation cleaning, and dry it with high-purity nitrogen gas after cleaning.

[0028] Step 3: In the N + On the back side of the β-Ga2O3 substrate, Ti / Au metal stacks with thicknesses of 30~70 nm and 100~200 nm were deposited by electron beam evaporation to form the cathode electrode; then, the cathode electrode was rapidly thermally annealed at 470°C for 1 min in a nitrogen atmosphere to form the cathode ohmic contact.

[0029] Step 4: In the N - A double-layer release photoresist is spin-coated onto the surface of a β-Ga2O3 drift layer. The double-layer release photoresist comprises a lower layer LOR10A and an upper layer AZ3312. An opening pattern is formed in the photoresist layer by exposure and development to expose the P to be deposited. - The region of the NiO thin film; the first opening pattern corresponds to the spatial modulation junction terminal extension SM-JTE region to be formed, including the inner JET region and the outer SM region.

[0030] Step 5: Deposit P on the surface of the sample obtained in Step 4 using radio frequency magnetron sputtering. - NiO thin film, the P - The NiO thin film thickness is 150~250 nm; the process conditions for the radio frequency magnetron sputtering are: radio frequency power 300 W, cavity pressure 4 mTorr, and atmosphere of Ar / O2 mixture, and the first P is controlled by adjusting the O2 / (O2+Ar) flow ratio. - Doping concentration of NiO thin films.

[0031] Step 6: Perform a stripping process on the sample obtained in Step 5 to remove the double-layer stripping photoresist and the P deposited on the photoresist layer. - The NiO film retains only the P deposited in the area exposed by the opening pattern. - A NiO thin film is formed to create a patterned NiO terminal layer; the patterned NiO terminal layer includes a continuous JTE region and a discrete NiO ring array region.

[0032] Step 7: Re-form a patterned photoresist layer in the middle of the patterned NiO terminal layer, and form an anode contact layer opening pattern in the photoresist layer by exposure and development to expose the P to be deposited. + The region of NiO thin film; subsequently, P was deposited using radio frequency magnetron sputtering. + NiO thin film, the P +The NiO thin film thickness is 75~150 nm, and the doping concentration is higher than 1.0×10⁻⁶. 19 cm -3 It is used as the ohmic contact layer for the anode.

[0033] Step 8: Perform a stripping process on the sample obtained in Step 7 to remove the patterned photoresist layer and the P deposited on the photoresist layer. + NiO thin film, retaining only P in the anode contact area + NiO film; then annealed at 300°C for 5 min in a nitrogen atmosphere to improve the crystallinity and contact properties of the NiO film.

[0034] Step 9: Define the anode metal region above the anode contact layer by photolithography, and deposit Ni / Au metal stacks with thicknesses of 50~80 nm and 100~150 nm by electron beam evaporation; then perform a lift-off process to form the anode electrode.

[0035] Step 10: Anneal the sample from Step 9 in a nitrogen atmosphere at 300°C for 5 minutes to improve the Ni / Au anode metal and P... + Ohmic contact between NiO.

[0036] Step 14: Deposit an HfO2 passivation layer on the front side of the device, so that the HfO2 passivation layer covers N. - Type β-Ga2O3 drift layer, JTE region and discrete NiO ring array region.

[0037] Example 4: Figure 3 As shown, this embodiment provides a method for fabricating the double-layer gallium oxide space modulation junction terminated extended power diode in Embodiment 2, including the following steps: Step 1: Provide an N + Type β-Ga2O3 substrate, the N + The doping concentration of the β-Ga₂O₃ substrate is higher than 1×10⁻⁶. 19 cm -3 ; in the N + N-type β-Ga2O3 substrates were epitaxially grown on the front side using halide vapor phase epitaxy (HVPE). - The N⁻ type β-Ga₂O₃ drift layer has a thickness of 7~13 μm and a doping concentration of 1.0×10⁻⁶. 16 cm -3 ~2.0×10 16 cm -3 .

[0038] Step 2: Clean the β-Ga2O3 epitaxial wafer by sequentially cleaning it with acetone, isopropanol and deionized water to remove surface impurities and organic residues; if necessary, use piranha solution for oxidation cleaning, and dry it with high-purity nitrogen gas after cleaning.

[0039] Step 3: In the N + On the back side of the β-Ga2O3 substrate, Ti / Au metal stacks with thicknesses of 30~70 nm and 100~200 nm were deposited by electron beam evaporation to form the cathode electrode; then, the cathode electrode was rapidly thermally annealed at 470°C for 1 min in a nitrogen atmosphere to form the cathode ohmic contact.

[0040] Step 4: In the N - A double-layer release photoresist is spin-coated onto the surface of a β-Ga2O3 drift layer. The double-layer release photoresist comprises a lower layer LOR10A and an upper layer AZ3312. A first opening pattern is formed in the photoresist layer by exposure and development to expose the first P to be deposited. - The region of the NiO thin film; the first opening pattern corresponds to the lower SM-JTE region to be formed, including the JTE2 region and the SM2 discrete NiO ring array region.

[0041] Step 5: Deposit the first P on the surface of the sample obtained in Step 4 using radio frequency magnetron sputtering. - NiO thin film, the first P - The NiO thin film thickness is 150~250 nm; the process conditions for the radio frequency magnetron sputtering are: radio frequency power 300 W, cavity pressure 4 mTorr, and atmosphere of Ar / O2 mixture, and the first P is controlled by adjusting the O2 / (O2+Ar) flow ratio. - Doping concentration of NiO thin films.

[0042] Step 6: Perform a stripping process on the sample obtained in Step 5 to remove the double-layer stripping photoresist and the first P deposited on the photoresist layer. - The NiO film retains only the first P deposited in the area exposed by the first opening pattern. - A NiO thin film is formed to create a first patterned NiO terminal layer; the first patterned NiO terminal layer includes a continuous JTE2 region and an SM2 discrete NiO ring array region.

[0043] Step 7: Spin-coat a double-layer release photoresist again on the sample surface where the first patterned NiO terminal layer has been formed. The double-layer release photoresist includes a lower layer LOR10A and an upper layer AZ3312. Form a second opening pattern in the photoresist layer by alignment, exposure, and development to expose the second P to be deposited. -The region of the NiO thin film; the second opening pattern corresponds to the lower SM-JTE region to be formed, including the continuous JTE1 region and the SM1 discrete NiO ring array region.

[0044] Step 8: Deposit a second P NiO film using radio frequency magnetron sputtering. The thickness of the second P NiO film is 150~250 nm. The doping concentration of the second P NiO film is different from that of the first P NiO film to form the upper SM-JTE region, including the JTE1 region and the SM1 discrete NiO ring array region.

[0045] Step 9: Perform a stripping process on the sample obtained in Step 8 to remove the double-layer stripping photoresist and the second P NiO film deposited on the photoresist layer, retaining only the second P NiO film deposited in the area exposed by the second opening pattern, thereby forming a second patterned NiO terminal layer; the second patterned NiO terminal layer includes a continuous JTE1 region and an SM1 discrete NiO ring array region.

[0046] Step 10: Re-form a patterned photoresist layer in the middle of the second patterned NiO terminal layer, and form an anode contact layer opening pattern in the photoresist layer by exposure and development to expose the P to be deposited. + The region of NiO thin film; subsequently, P was deposited using radio frequency magnetron sputtering. + NiO thin film, the P + The NiO thin film thickness is 75~150 nm, and the doping concentration is higher than 1.0×10⁻⁶. 19 cm -3 It is used as the ohmic contact layer for the anode.

[0047] Step 11: Perform a stripping process on the sample obtained in Step 10 to remove the patterned photoresist layer and the P deposited on the photoresist layer. + NiO thin film, retaining only P in the anode contact area + NiO film; then annealed at 300°C for 5 min in a nitrogen atmosphere to improve the crystallinity and contact properties of the NiO film.

[0048] Step 12: In the P + The anode metal region is defined above the NiO anode contact layer by photolithography, and Ni / Au metal stacks with thicknesses of 50~80 nm and 100~150 nm are deposited by electron beam evaporation. Subsequently, a lift-off process is performed to form the anode electrode.

[0049] Step 13: Anneal the sample in a nitrogen atmosphere at 300°C for 5 minutes to improve the Ni / Au anode metal and P + Ohmic contact between NiO.

[0050] Step 14: Deposit an HfO2 passivation layer on the front side of the device, so that the HfO2 passivation layer covers N. - Type β-Ga2O3 drift layer, JTE region and discrete NiO ring array region.

[0051] Example 5: As shown in Figures 4-12, this example illustrates the TCAD simulation process based on the single-layer gallium oxide space modulation junction terminated extended power diode of Example 1 and the double-layer gallium oxide space modulation junction terminated extended power diode of Example 2. The optimal parameters of the device are obtained through TCAD simulation. The physical models used in this simulation mainly include bandgap narrowing, thermionic emission, Fermi-Dirac statistics, high-field mobility saturation, and SRH recombination models. Due to the steady-state electrical characteristics under reverse bias, isothermal simulation conditions are used. Furthermore, accurate experimental data on the collisional ionization of the β-Ga2O3 / NiO system is lacking; therefore, the effects of self-heating, incomplete ionization, and collisional ionization models are not considered in the design simulation. The main material parameters of the device are shown in Table 1, and other parameters use the software default settings. The defect parameters of the β-Ga2O3 / NiO interface are based on the literature (Design of a 10 kV and 16.5 GW cm). −2 The NiO / β-Ga2O3 Heterojunction Diode on a Complete Wafer with a Positive Beveled-Mesa was used, with acceptor and donor defect levels located at the bottom of the conduction band and the top of the valence band, respectively, with a peak concentration of 1 × 10⁻⁶. 18 cm -2 The breakdown voltage of the device is exponentially distributed, relative to the critical breakdown electric field strength of each material. E C Using this as the criterion, when the internal electric field strength of the material reaches its critical breakdown electric field value, the device is considered to have broken down. This applies to β-Ga₂O₃, NiO, and HfO₂. E C The values ​​were set to 8 MV / cm, 5 MV / cm, and 5.3 MV / cm, respectively. To verify the effectiveness of the model, the simulation model was calibrated using the positive IV characteristic curve of the SA-MZJTE structure at 25 °C from the literature (3.9 kV Vertical β-Ga2O3 Hetero-Junction Diode With High-Temperature Operational Capability). The experimentally extracted turn-on voltage (V) on ) and R on,sp The values ​​are 1.73 V and 3.5 mΩ·cm, respectively. 2The corresponding simulation results are 2.67 V and 3.5 mΩ·cm. 2 Among them, V on The higher value is related to the simplified settings of the heterojunction interface band shift and interface defect parameters in the simulation. R... on,sp The results are highly consistent with the experimental results, verifying the accuracy of the simulation model and parameter settings presented in this paper.

[0052]

[0053] 1. Verification of withstand voltage performance of single-layer SM-JTE structure devices and double-layer SM-JTE structure devices.

[0054] Figure 4 compares the results without JTE ( Figure 4a ), traditional JTE ( Figure 4b ), single-layer SM-JTE ( Figure 4c ) and double-layer SM-JTE ( Figure 4d The equipotential line distribution at the heterojunction interface of four β-Ga₂O₃ HJD structures under a reverse bias of 5 kV is shown. The electrode, substrate, and drift region parameters of these four structures are all set to the same values.

[0055] When the four structures operate under reverse bias, the equipotential lines exhibit different degrees of curvature and concentration locations. In the non-JTE structure, the equipotential lines are significantly curved and highly concentrated at the anode edge, indicating a drastic potential change and the highest local electric field peak in this region, as shown in Figure 4(a). In the traditional JTE structure, single-layer, and double-layer SM-JTE structures, there is charge compensation between the negative charge in the terminal region and the space charge in the drift region. The equipotential lines of the device are redistributed along the terminal direction, and their curvature and density are significantly reduced, as shown in Figures 4(b)-(d). Although all three terminal structures can improve the density of the equipotential lines, the SM-JTE structure enables the terminal charge to gradually decrease from the anode edge to the outer edge of the terminal, thereby achieving a smoother potential distribution in the terminal region, reducing the local peak electric field, and increasing Vo. BR .

[0056] Figure 5(a) shows the four β-Ga2O3 HJD structures: no JTE, conventional JTE, single-layer SM-JTE, and double-layer SM-JTE. V BR Follow D JTE The relationship between the changes. The optimal parameters obtained from subsequent optimizations were used for each structure. The highest value of the structure without JTE. V BR Only 0.4 kV, corresponding D JTE =0.5 × 10 14 cm -2 Traditional JTE architecture can achieve the highest...V BR The voltage was increased to 3.7 kV, but this value only appeared in [the following context]. D JTE =0.26 × 10 14 cm -2 Nearby, indicating the device V BR right D JTE Fluctuations are quite sensitive. The highest values ​​for single-layer and double-layer SM-JTE structures... V BR Reaching 6 kV and 6.05 kV respectively, corresponding to D JTE They are 0.4 × 10 14 cm -2 and 2.2 × 10 14 cm -2 Under 5 kV withstand voltage conditions, single-layer SM-JTE D JTE The range is 0.33-0.5 × 10 14 cm -2 The corresponding RDW = ±20%. Dual-layer SM-JTE D JTE The range has been expanded to 0.33–2.95 × 10⁻⁶. 14 cm -2 The corresponding RDW = ±80%. The results show that the dual-layer SM-JTE maintains high... V BR At the same time, it significantly improved the device's ability to... D JTE Tolerance for fluctuations.

[0057] Figure 5(b) compares the maximum performance of each device under a 5 kV reverse bias condition for the four structures. V BR The electric field distribution at the heterojunction interface is shown. The peak electric fields of the structures without JTE, conventional JTE, single-layer SM-JTE, and double-layer SM-JTE are 13, 9.3, 6.8, and 6.5 MV / cm, respectively. When the terminal structure is changed from conventional JTE to single-layer SM-JTE and double-layer SM-JTE, the peak electric field at the heterojunction interface continuously decreases, indicating that the SM-JTE structure can effectively suppress electric field concentration, which is consistent with its higher peak electric field. V BR Consistent with larger RDW performance.

[0058] Figure 5(c) shows the one-dimensional ideal electric field distribution under reverse bias of β-Ga₂O₃ HJD obtained based on the Poisson equation. Ideal breakdown voltage. V BR,idThe voltage is approximately 6.6 kV according to the formula in the diagram. Using terminal efficiency (η= V BR,act / V BR,id The terminal performance was evaluated (×100%), and the calculated efficiency was only 6% for the JTE-less type, while the highest efficiency for the JTE type was 56%. The highest efficiencies for the single-layer and double-layer SM-JTE types reached 90.9% and 91.7%, respectively. Compared with the JTE-less and traditional JTE structures, the SM-JTE structure can more fully utilize the breakdown voltage potential of β-Ga2O3, enabling the device to achieve higher efficiency. V BR Approaching the one-dimensional theoretical breakdown limit.

[0059] 2. Pressure resistance principle analysis and structural optimization of single-layer SM-JTE HJD.

[0060] Figure 6 shows the differences between devices without JTE and single-layer SM-JTE devices under a 5kV reverse bias at different voltage levels. D JTE The two-dimensional electric field distribution of the optimal structural parameters under the given conditions. For the non-JTE structure, due to the curvature effect, the peak electric field at the anode edge of the device reaches as high as 13 MV / cm (Fig. 6(a)), which is much higher than that of the device with the SM-JTE structure. For the single-layer SM-JTE structure, the magnitude and location of the peak electric field are similar to those of the other structures. D JTE Value-related. When D JTE = 2.0 × 10 13 cm -2 At this time (Figure 6(b)), the terminal charge density is low, and the electric field concentration at the anode edge is still quite obvious, with a peak value of 10.8 MV / cm. D JTE = 8.0×10 13 cm -2 At time (Fig. 6(d)), although the electric field at the anode edge decreases somewhat, the terminal region is not fully depleted due to the excessively high terminal charge density, and the peak electric field shifts to the SM-JTE region, with a peak value of approximately 8.3 MV / cm. D JTE = 4.2×10 13 cm -2 At time (Fig. 6(c)), the electric field distribution between the anode edge and the terminal region is most uniform, and the peak electric field at the interface decreases to 6.8 MV / cm, thus producing the highest V BR Therefore, only with an appropriate terminal charge density can a single-layer SM-JTE structure achieve a better electric field distribution and higher efficiency. V BR .

[0061] Figure 7 The electric field distribution curve extracted along the tangent AA' on the surface of the β-Ga2O3 drift layer in Figure 6 is for the corresponding device. Figure 8 shows the traditional and single-layer SM-JTE structures. V BR Follow D JTE The changing relationship, A single-layer SM-JTE consists of a traditional JTE body and a NiO ring in the SM region, which together maximize the single-layer SM-JTE structure. D JTE Window, for JTE body length L E Number of SM sub-regions N and W s was optimized, and the optimization results are shown in Figure 8. With L E and N The increase (Figure 8(a)-(b)) in the device V BR The effect of the NiO ring on the edge electric field of the heterojunction gradually increases and then saturates because the effect gradually weakens as the terminal region moves away from the anode edge of the heterojunction. To optimize the utilization of the terminal space while ensuring breakdown performance, [the following is a continuation of the previous sentence, but the context is unclear]. L E and N The ranges were determined to be 10–30 μm and 6–12 μm, respectively. Furthermore, reducing… W s can improve V BR (Figure 8(c)), the reason being the smaller W S This allows for a more continuous equivalent charge distribution in the NiO ring at the terminal region, thus facilitating the uniform expansion of the edge electric field. Considering the approximately 400 nm resolution of the i-line lithography machine, to ensure sufficient process margin for the NiO ring during lithography, the following parameters were determined: W S The range is 0.5~2 μm.

[0062] It is evident that the single-layer SM-JTE structure, after the aforementioned optimizations, can achieve a maximum voltage of 6 kV. V BR This effectively reduces the peak electric field at the device's terminal edge, but under a 5 kV withstand voltage condition... D JTE The window range remains only 0.33-0.5 × 10 14 cm -2 (Figure 8(c)) corresponds to RDW=±20%, and the process tolerance is still limited.

[0063] 3. Structural optimization and RDW research of double-layer SM-JTE HJD.

[0064] To further broaden the process window, an additional SM-JTE region is added below the single-layer SM-JTE region, forming a double-layer SM-JTE structure. The upper SM-JTE reduces the peak electric field at the anode edge of the device, while the lower SM-JTE further diffuses the electric field distribution, thereby significantly improving the process tolerance of the NiO layer doping. The charge-to-dose ratio of the upper and lower SM-JTE layers is... The optimization of the bilayer SM-JTE structure includes two parts: optimization of the geometric parameters of the lower SM-JTE and optimization of the terminal charge dose ratio between the upper and lower layers. During the optimization process, the upper SM-JTE structural parameters were adopted using the optimal parameters of the single-layer structure, and the ratio was fixed at 1. Only the structural parameters of the lower SM-JTE were optimized. The optimization results are shown in Figures 9(a)–(c). L E1 = L E2 = 10~30 μm N 1 = N 2 = 6~12 W S1 = W S2 When the thickness is 0.5~2 μm, the bilayer SM-JTE has the widest width. D JTE The window, therefore, determines this set of parameters as the optimal device structure parameters for the dual-layer SM-JTE.

[0065] Based on the optimal parameters of the two-layer structure, the effect of Ratio on... D JTE The effects of windows, such as Figure 10 As shown, as the Ratio decreases from 1.6 to 0.2, the corresponding... D JTE The window range is from 0.33 to 0.76 × 10 14 cm -2 Widened to 0.33-2.95 ×10 14 cm -2 The corresponding RDW increased from ±39% to ±80%. When the ratio further decreased to 0.1, D JTE It is 0.81-2.10 × 10 14 cm -2 The corresponding range V BR Below 5 kV, it is not conducive to maintaining a stable high voltage. V BRTherefore, Ratio = 0.2 is determined to be the optimal value.

[0066] Figure 11 compares the surface electric field of the β-Ga2O3 drift layer at the heterojunction interface of the bilayer SM-JTE structure under different ratios at a reverse bias of 5 kV. D JTE The distribution of changes. When Ratio = 1.6 (Figure 11(a)), the charge dose of the lower SM-JTE is higher than that of the upper layer ( D JTE2 = 1.6 D JTE1 At this point, the lower SM-JTE dominates the regulation of the terminal electric field. Complete depletion of the lower SM-JTE increases the peak electric field in the underlying β-Ga2O3 drift region, even exceeding 8 MV / cm, leading to an uneven overall electric field distribution and increasing the risk of premature breakdown. As the ratio decreases to 1.0 (Figure 11(b)), the charge doses of the upper and lower SM-JTE layers are the same. D JTE2 = D JTE1 Compared to Ratio=1.6, the peak electric field in the drift region corresponding to the lower SM-JTE decreased by only 0.004 MV / cm, and the electric field distribution in the drift region corresponding to the upper SM-JTE remained almost unchanged, indicating that the synergistic control of the electric field between the upper and lower SM-JTEs is still limited. Further reducing the Ratio to 0.2 (Figure 11(c)), the charge dose of the upper SM-JTE is higher than that of the lower SM-JTE. D JTE2 = 0.2 D JTE1 At this point, the upper SM-JTE layer enhances its control over the electric field at the anode edge, suppressing the peak electric field at the anode edge. Simultaneously, the lower SM-JTE layer effectively disperses the new local electric field peaks caused by the increased charge dose from the upper SM-JTE layer. This synergistic control of the electric field by the upper and lower SM-JTE layers results in a more uniform electric field distribution across the entire terminal, with the peak electric field decreasing accordingly. D JTE The fluctuations are smaller, thus improving the device's performance. V BR right D JTE The tolerance for fluctuations has been broadened. D JTE Process window.

[0067] 4. Comparison of positive characteristics and power figure of merit between single-layer SM-JTE structure and double-layer SM-JTE structure.

[0068] Figure 12 compares the forward conduction characteristics of four structures: no JTE, traditional JTE, single-layer SM-JTE, and double-layer SM-JTE. R on,sp Extracted from the slope of the positive linear JV curve, the maximum current density (J) max The current density is taken when the anode voltage is 7 V. Figure 12(a) compares the current density of each structure at the maximum. V BR Corresponding D JTE Under the condition, R on,sp With J max Relationship with anode radius. As the anode radius increases, the conductivity of each structure gradually stabilizes. At an anode radius of 500 μm, the Rconductivity of no JTE, conventional JTE, single-layer and double-layer SM-JTE is significantly improved. on,sp The corresponding J values ​​are 3.70, 4.07, 3.73, and 3.26 mΩ·cm², respectively. max The values ​​are 1082, 984, 1072, and 1164 A / cm², respectively. The dual-layer SM-JTE structure simultaneously achieves the lowest R... on,sp And the highest J max It exhibits excellent conductivity.

[0069] Figure 12(b) shows the positive JV characteristic curves at an anode radius of 300 μm, and the V values ​​for the four structures. on Both are approximately 2.7 V. Regarding conduction performance, the R of the dual-layer SM-JTE... on,sp The lowest value is 3.55 mΩ·cm², with Ri being the lowest for both JTE and single-layer SM-JTE. on,sp They are close, at 4.17 mΩ·cm² and 4.15 mΩ·cm² respectively, compared to the traditional JTE R... on,sp The highest is 4.55 mΩ·cm², which is different from different D JTE The difference in conductivity in the terminal region is related to the conditions. Figure 12(c) shows the JV characteristic curves in a semi-logarithmic coordinate system. The reverse leakage current of the four structures is approximately 10. -7 A / cm 2 The corresponding on / off ratio is close to 10. 10 It exhibits excellent rectification characteristics.

[0070] Figure 12(d) compares the four structures of R on,sp and PFOM D JTE The relationship between the changes. Regarding conduction performance, because the termination region provides an additional conductive path, the R with the termination structure... on,sp All are lower than R without JTE structure on,sp (3.65 mΩ·cm²). With DJTE Enlarged, conventional JTE, single-layer and double-layer SM-JTE R on,sp The conductivity rapidly decreased and stabilized at 3.51, 3.46, and 3.49 mΩ·cm², respectively. This rapid stabilization is attributed to the relatively weak hole conductivity of the NiO terminals. Furthermore, the bilayer SM-JTE structure, due to the charge distribution across the upper and lower layers, has a slightly lower local doping concentration than the monolayer structure, resulting in its ability to withstand high... D JTE R below on,sp Slightly higher. Regarding the power figure of merit, the inset of Figure 12(d) shows a peak PFOM of up to 10.31 GW / cm² for the dual-layer SM-JTE structure. 2 This far exceeds the 0.05, 2.94, and 8.43 GW / cm² of structures without JTE, traditional JTE, and single-layer SM-JTE, respectively. 2 The double-layer structure throughout D JTE It maintained a higher and more stable PFOM within the range, demonstrating its significant comprehensive advantages in terms of withstand voltage and conduction loss.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that various changes in form and detail can be made to it without departing from the scope defined by the claims of the present invention.

Claims

1. A single-layer gallium oxide space modulation junction terminated extended power diode, characterized in that: From bottom to top, it includes a cathode, an n-type Ga2O3 substrate, an n-type Ga2O3 drift layer, a space modulation junction terminal extension (SM-JTE) region formed by p-type NiO, an anode contact region formed by p-type NiO, an anode, and an HfO2 passivation layer. The diameter of the anode and the anode contact region is smaller than that of the n-type Ga2O3 drift layer. The spatial modulation junction termination extended SM-JTE region includes an inner JET region and an outer SM region. The JTE region is a NiO JTE body, partly located below the anode contact area and partly extending beyond the anode contact area. The SM region has N sub-regions radially arranged from the edge of the NiO JTE body, which are arranged sequentially from the inside to the outside. i =1,2…, N Each sub-region is provided with a NiO ring structure, wherein the NiO ring structure consists of one or more NiO rings within the sub-region, and the remaining portion is covered by an HfO2 passivation layer. The radial width of each sub-region is fixed. ,in W s is the base width, the first... i The number of NiO rings in each subregion is And when At that time, the spacing between adjacent NiO rings within the sub-region is fixed as W S ,when At that time, the width of the NiO ring within the sub-region is fixed as W s, the spacing between adjacent NiO rings is ; The HfO2 passivation layer covers the n-type Ga2O3 drift layer and the spatial modulation junction terminal extension SM-JTE region, and contacts the anode contact area and the anode edge.

2. The gallium oxide space modulation junction terminated extended power diode as described in claim 1, characterized in that: The thickness of the SM-JTE region is 150~250nm, and the width of the JET region extending beyond the anode contact area is... L E The size is 10~30 μm, and the sub-region N is 6~12.

3. A double-layer gallium oxide space modulation junction terminated extended power diode, characterized in that: From bottom to top, it includes a cathode, an n-type Ga2O3 substrate, an n-type Ga2O3 drift layer, a space modulation junction terminal extension (SM-JTE) region formed by p-type NiO, an anode contact region formed by p-type NiO, an anode, and an HfO2 passivation layer. The diameter of the anode and the anode contact region is smaller than that of the n-type Ga2O3 drift layer. The space modulation junction terminal extension (SM-JTE) region includes an upper SM-JTE region and a lower SM-JTE region. The upper SM-JTE region includes an upper JET region and an upper SM region. The upper JET region is a NiO JTE1 body, partly located below the anode contact area and partly extending beyond the anode contact area. The upper SM region has N1 sub-regions radially arranged from the edge of the NiO JTE1 body, which are arranged sequentially from the inside to the outside. i =1,2…, N 1 Each sub-region is provided with a NiO ring structure, wherein the NiO ring structure consists of one or more NiO rings within the sub-region, and the remaining portion is covered by an HfO2 passivation layer. The radial width of each sub-region is fixed. ,in W S1 As the base width, the first i The number of NiO rings in each subregion is And when At that time, the spacing between adjacent NiO rings within the sub-region is fixed as W S1 ,when At that time, the width of the NiO ring within the sub-region is fixed as W S1 The spacing between adjacent NiO rings is ; The lower SM-JTE region includes a lower JET region and a lower SM region. The lower JET region is a NiO JTE2 body and is partially located below and partially extends beyond the upper SM-JTE region. The lower SM region has N2 sub-regions radially arranged from the edge of the NiO JTE2 body, which are arranged sequentially from the inside to the outside. i =1,2…, N 2 Each sub-region is provided with a NiO ring structure, wherein the NiO ring structure consists of one or more NiO rings within the sub-region, and the remaining portion is covered by an HfO2 passivation layer. The radial width of each sub-region is fixed. , No. i The number of NiO rings in each subregion is And when At that time, the spacing between adjacent NiO rings within the sub-region is fixed as W S2 ,when At that time, the width of the NiO ring within the sub-region is fixed as W S2 The spacing between adjacent NiO rings is ; The HfO2 passivation layer covers the n-type Ga2O3 drift layer and the spatial modulation junction terminal extension SM-JTE region, and contacts the anode contact area and the anode edge.

4. The double-layer gallium oxide space modulation junction terminated extended power diode as described in claim 3, characterized in that: Both the upper and lower SM-JTE regions are 150~250 nm in size, and the width of the upper JTE region extending beyond the anode contact region is... L E1 The width is 10~30 μm, and the portion of the lower JET region that extends beyond the upper SM-JTE region is [missing information]. L E2 It is 10~30 μm, and L E1 = L E2 The number of sub-regions N 1 = N 2 = 6~12, the aforementioned W S1 =W S2 = 0.5~2 μm, Ratio= D JTE2 / D JTE1 =1.0~0.1, where D JTE1 For the charge density of the upper SM-JTE region, D JTE2 This represents the charge density of the lower SM-JTE region.

5. The monolayer gallium oxide space modulation junction terminated extended power diode as described in claim 2, characterized in that: The n-type Ga2O3 substrate has a thickness of 500~650 μm and a donor concentration higher than 1 × 10⁻⁶. 19 cm -3 The thickness of the n-type Ga2O3 drift layer is 7~13 μm, and the donor concentration is 1.0×10⁻⁶. 16 cm -3 ~2.0×10 16 cm -3 The thickness of the anode contact region formed by p-type NiO is 75~150 nm, and the acceptor concentration is higher than 1.0 × 10⁻⁶. 19 cm -3 .

6. The double-layer gallium oxide space modulation junction terminated extended power diode as described in claim 4, characterized in that: The n-type Ga2O3 substrate has a thickness of 500~650 μm and a donor concentration higher than 1 × 10⁻⁶. 19 cm -3 The thickness of the n-type Ga2O3 drift layer is 7~13 μm, and the donor concentration is 1.0×10⁻⁶. 16 cm -3 ~2.0×10 16 cm -3 The thickness of the anode contact region formed by p-type NiO is 75~150 nm, and the acceptor concentration is higher than 1.0 × 10⁻⁶. 19 cm -3 .

7. The method for fabricating a monolayer gallium oxide space modulation junction terminated extended power diode as described in claim 5, characterized in that, Includes the following steps: Step 1: Use one N + Type β-Ga2O3 substrate, in the N + N-type β-Ga2O3 substrates were epitaxially grown on the front side using halide vapor phase epitaxy. - Type β-Ga2O3 drift layer; Step 2: For the N - The β-Ga2O3 drift layer was cleaned by sequentially cleaning with acetone, isopropanol and deionized water to remove surface impurities and organic residues, or by oxidizing with piranha solution. After cleaning, it was dried with high-purity nitrogen. Step 3: In the N + The cathode electrode is formed by electron beam evaporation deposition of a Ti / Au metal stack on the back side of the β-Ga2O3 substrate; Subsequently, it was rapidly thermally annealed at 470°C for 1 min in a nitrogen atmosphere to form a cathode ohmic contact; Step 4: In the N - A double-layer release photoresist is spin-coated onto the surface of a β-Ga2O3 drift layer. An opening pattern is formed in the photoresist layer by exposure and development to expose the P-type substrate to be deposited. - The region of the NiO thin film; the opening pattern corresponds to the spatial modulation junction terminal extension SM-JTE region to be formed; Step 5: Deposit P on the surface of the sample obtained in Step 4 using radio frequency magnetron sputtering. - The NiO thin film was sputtered under the following conditions: RF power 300 W, cavity pressure 4 mTorr, and an Ar / O2 mixture atmosphere. The P value was controlled by adjusting the O2 / (O2+Ar) flow ratio. - Doping concentration of NiO thin film; Step 6: Perform a stripping process on the sample obtained in Step 5 to remove the double-layer stripping photoresist and the P deposited on the photoresist layer. - The NiO film retains only the P deposited in the area exposed by the opening pattern. - NiO thin film, thereby forming a patterned NiO terminal layer; the patterned NiO terminal layer is a spatial modulation junction terminal extension SM-JTE region; Step 7: A patterned photoresist layer is re-formed in the center of the patterned NiO terminal layer described in Step 6. An anode contact layer opening pattern is formed in the photoresist layer through exposure and development to expose the P to be deposited. + Regions of the NiO thin film; P was subsequently deposited using radio frequency magnetron sputtering. + NiO thin film is used as the anode ohmic contact layer; Step 8: Perform a stripping process on the sample obtained in Step 7 to remove the patterned photoresist layer and the P deposited on the photoresist layer. + NiO thin film, retaining only P in the anode contact area + NiO film; then annealed at 300°C for 5 min in a nitrogen atmosphere to improve the crystal quality and contact properties of the NiO film; Step 9: The P mentioned in step 8 + The anode metal region is defined on top of the NiO thin film by photolithography, and a Ni / Au metal stack is deposited by electron beam evaporation, followed by a lift-off process to form the anode electrode; Step 10: Anneal the sample from Step 9 in a nitrogen atmosphere at 300°C for 5 min to improve the Ni / Au anode metal and P + Ohmic contact between NiO; Step 11: Deposit an HfO2 passivation layer on the front side of the device from step 10, so that the HfO2 passivation layer covers N. - Type β-Ga2O3 drift layer and patterned NiO terminal layer.

8. The method for fabricating a double-layer gallium oxide space modulation junction terminated extended power diode as described in claim 6, characterized in that, Includes the following steps: Step 1: Use one N + Type β-Ga2O3 substrate, in the N + N-type β-Ga2O3 substrates were epitaxially grown on the front side using halide vapor phase epitaxy. - Type β-Ga2O3 drift layer; Step 2: For the N - The β-Ga2O3 drift layer was cleaned by sequentially cleaning with acetone, isopropanol and deionized water to remove surface impurities and organic residues, or by oxidizing with piranha solution. After cleaning, it was dried with high-purity nitrogen. Step 3: In the N + The cathode electrode is formed by electron beam evaporation deposition of a Ti / Au metal stack on the back side of the β-Ga2O3 substrate; Subsequently, it was rapidly thermally annealed at 470°C for 1 min in a nitrogen atmosphere to form a cathode ohmic contact; Step 4: In the N - A double-layer release photoresist is spin-coated onto the surface of a β-Ga2O3 drift layer. A first opening pattern is formed in the photoresist layer through exposure and development to expose the first P-type deposit to be deposited. - The region of the NiO thin film; the first opening pattern corresponds to the lower SM-JTE region to be formed; Step 5: Deposit the first P on the surface of the sample obtained in Step 4 using radio frequency magnetron sputtering. - The NiO thin film, the process conditions for radio frequency magnetron sputtering are RF power 300 W, cavity pressure 4 mTorr, and atmosphere of Ar / O2 mixture, and the first P is controlled by adjusting the O2 / (O2+Ar) flow ratio. - Doping concentration of NiO thin film; Step 6: Perform a stripping process on the sample obtained in Step 5 to remove the double-layer stripping photoresist and the first P layer deposited on the photoresist layer. - The NiO film retains only the first P deposited in the area exposed by the first opening pattern. - A NiO thin film is formed to create a first patterned NiO terminal layer; the first patterned NiO terminal layer is the lower SM-JTE region. Step 7: Spin-coat a double-layer stripping photoresist again on the sample surface where the first patterned NiO terminal layer has been formed. Form a second opening pattern in the photoresist layer by alignment, exposure and development to expose the area where the second P NiO film is to be deposited; the second opening pattern corresponds to the upper SM-JTE area to be formed. Step 8: Deposit a second P NiO thin film on the surface of the sample obtained in step 7 using radio frequency magnetron sputtering, wherein the process conditions for radio frequency magnetron sputtering are the same as those in step 5; Step 9: Perform a stripping process on the sample obtained in Step 8 to remove the double-layer stripping photoresist and the second P NiO film deposited on the photoresist layer, retaining only the second P NiO film deposited in the area exposed by the second opening pattern, thereby forming a second patterned NiO terminal layer; the second patterned NiO terminal layer is the upper SM-JTE region, and the lower SM-JTE region and the upper SM-JTE region together form the spatial modulation junction terminal extension SM-JTE region; Step 10: In step 9, a patterned photoresist layer is re-formed in the middle of the second patterned NiO terminal layer. An anode contact layer opening pattern is formed in the photoresist layer by exposure and development to expose the P to be deposited. + Regions of the NiO thin film; P was subsequently deposited using radio frequency magnetron sputtering. + NiO thin film is used as the anode ohmic contact layer; Step 11: Perform a stripping process on the sample obtained in Step 10 to remove the patterned photoresist layer and the P deposited on the photoresist layer. + NiO thin film, retaining only P in the anode contact area + NiO film; then annealed at 300°C for 5 min in a nitrogen atmosphere to improve the crystal quality and contact properties of the NiO film; Step 12: The P mentioned in step 11 + The anode metal region is defined on top of the NiO thin film by photolithography, and a Ni / Au metal stack is deposited by electron beam evaporation, followed by a lift-off process to form the anode electrode; Step 13: Anneal the sample from Step 12 in a nitrogen atmosphere at 300°C for 5 min to improve the Ni / Au anode metal and P + Ohmic contact between NiO; Step 14: Deposit an HfO2 passivation layer on the front side of the device from step 13, so that the HfO2 passivation layer covers N. - Type β-Ga2O3 drift layer, lower SM-JTE region and upper SM-JTE region.

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