A total dose hardened ldmos device structure and method of fabrication

Abstract

The application relates to a total dose hardened LDMOS device structure and a preparation method. The method comprises the following steps: performing photoetching and multi-step implantation on P columns and N columns on an N well; performing P-Body photoetching and implantation on the N well, and performing high-temperature annealing on the P-Body, the P columns and the N columns; performing photoetching and etching of a field region oxide medium layer on surfaces of the P columns and the N columns; growing a gate oxide medium layer, and performing deposition and etching of a gate polycrystal control region; performing N+ and P+ photoetching and implantation, and performing annealing and activation to form source electrodes, drain electrodes and body contact regions; performing overall covering through chemical deposition of an isolation medium layer, performing photoetching and dry etching of contact holes, leading out a gate polycrystal control end, a source body contact end and a drain end respectively, and conducting through metal layer contact; and performing chemical deposition, photoetching and etching of a passivation medium layer. The application eliminates a direct leakage path of source and drain electrodes after a total dose test, and realizes a total dose hardening function of shielding an LDMOS device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and specifically relates to a total dose hardened LDMOS device structure and its fabrication method. Background Technology

[0002] Laterally diffused metal-oxide-semiconductor (LDMOS) is fabricated on an epitaxial layer of silicon. With the rapid development of power integrated circuits, the research and development of LDMOS devices in power semiconductor processes is becoming increasingly important. LDMOS is a type of lateral high-voltage device called DMOS, possessing advantages such as high voltage withstand capability, high gain, and low distortion. It is also more easily compatible with CMOS processes, thus finding wide application in microwave, radio frequency, and power drive integrated circuits.

[0003] With the continuous development of satellites and deep space exploration, the demand for microwave, radio frequency, and power drive circuits is increasing. LDMOS devices are precisely the core components facing the challenge of radiation hardening. However, LDMOS devices developed using non-hardened processes cannot meet the requirements of aerospace radiation-hardened microwave, radio frequency, and power drive chip applications, severely restricting my country's development of core radiation-hardened devices in this field. It is necessary to solve the technical problem caused by the total dose radiation effect of LDMOS devices. In radiation-hardened LDMOS devices, there is a thick field oxide layer under gate polycrystalline control, which is highly sensitive to the total dose effect. Under radiation conditions, the field oxide is ionized into electron-hole pairs. Electrons are instantly removed under the influence of the electric field, leaving hole traps at the Si / SiO2 interface. As the radiation dose increases, the traps continuously capture holes, accumulating positive charges, causing a rapid increase in the leakage current between the source and drain, resulting in the LDMOS device being permanently turned on and failing.

[0004] Therefore, there is an urgent need for this invention to propose a total dose-strengthened LDMOS device structure and fabrication method to solve the above-mentioned technical problems. Summary of the Invention

[0006] The purpose of this invention is to provide a total dose hardened LDMOS device structure and fabrication method. This invention prevents the silicon Si surface inversion under total dose by using a P-pillar design to prevent the SiO2 dielectric field plate in the thick field region of the drift region from inverting. This eliminates the direct leakage path between the source and drain after the total dose test, thereby achieving the total dose hardening function of the shielded LDMOS device.

[0007] To address the aforementioned technical problems, this invention provides a method for fabricating a total dose-hardened LDMOS device structure, comprising: Provide an epitaxial layer on a silicon substrate; by sequentially forming an N+ buried layer and an N-well on the epitaxial layer, and performing photolithography and multi-step implantation on the P-pillars and N-pillars in the N-well, a drift region with breakdown voltage isolation between the source and drain is formed; P-Body photolithography and implantation are performed on the N-well, and the P-Body, P-pillar and N-pillar are subjected to high-temperature annealing to deepen the P-Body to form a bulk region, and to form P-pillar and N-pillar that are connected vertically. Photolithography and etching of field region oxide dielectric layers on the surfaces of P-pillars and N-pillars; By growing a gate oxide dielectric layer and depositing and etching the gate polycrystalline control region; The source, drain, and body contact regions are formed by performing N+ and P+ photolithography and implantation in the P-body, N+ photolithography and implantation in the N-well, and annealing activation. The isolation dielectric layer is fully covered by chemical deposition, and the contact holes are photolithographically and dryly etched to bring out the gate polysilicon control terminal, source contact terminal and drain terminal respectively, so as to enable the metal layer to make contact and conduct. The device is protected by performing metal layer deposition, photolithography, and etching, and then performing chemical deposition, photolithography, and etching of the passivation dielectric layer.

[0008] Preferably, N-pillar lithography and multi-step implantation are performed in the drift region. The N-impurity implanted in the N-pillar is an N-type impurity As or P, the implantation energy is 50keV~1000keV, and the implantation dose is 5E11~1E12. After high-temperature annealing, the depth of the N-pillar is 3μm~5μm and the width is 2μm~5μm.

[0009] Preferably, within the drift region, P-pillar lithography and multi-step implantation are performed. The P-impurity implanted into the P-pillar is a P-type impurity B, BF2, or BF3, with an implantation energy of 30keV to 500keV and an implantation dose of 5E12 to 1E13. After high-temperature annealing, the depth of the P-pillar is 3μm to 5μm, and the width is 1μm to 3μm. By controlling the injection energy within the P-pillars and the N-pillars and adjusting the annealing temperature, a columnar concentration-doped morphology with vertically connected columns can be achieved.

[0010] Preferably, the impurity injected into the P-Body is a P-type impurity B, BF2 or BF3, the injection energy is 50keV~100keV, and the injection dose is 1E13~1E14. The P-Body, P-pillar, and N-pillar are subjected to high-temperature annealing at a temperature of 1000℃~1200℃ for a time of 80min~150min.

[0011] Preferably, the thickness of the field oxide dielectric layer is 350 nm to 1500 nm; the thickness of the gate oxide dielectric layer is 15 nm to 80 nm; the thickness of the gate polycrystalline control region is 0.5 μm to 1.0 μm; the thickness of the isolation dielectric layer is 0.6 μm to 0.8 μm; and the thickness of the passivation dielectric layer is 0.5 μm to 1.0 μm. The field oxide dielectric layer, the gate oxide dielectric layer, and the isolation dielectric layer are all made of SiO2 dielectric layer; the passivation dielectric layer is made of SiO2 or a mixture of SiO2 and Si3N4.

[0012] Preferably, the N+ and P+ photolithography and implantation are performed in the P-body, and the N+ photolithography and implantation are performed in the N-well, wherein the N-type impurity implanted by N+ is As or P, the implantation energy is 40 keV~80 keV, and the implantation dose is 1E15-1E16; wherein the P-type impurity implanted by P+ is B, BF2 or BF3, the implantation energy is 20 keV~60 keV, and the implantation dose is 1E15-5E15.

[0013] Preferably, the aperture size of the contact hole is 150nm~300nm, and a tungsten plug is formed in the contact hole by chemical vapor deposition to bring out the gate, drain, source and body contact areas of the LDMOS device from the contact hole, thereby realizing the connection function with the metal layer.

[0014] This invention also provides a total dose hardened LDMOS device structure, fabricated using the method described above for fabricating a total dose hardened LDMOS device structure, comprising: N+ buried layer and N well, wherein the N+ buried layer and N well are sequentially disposed on the surface of the P- epitaxial layer of the P+ substrate; The P-Body, as the body region, is arranged on one side inside the N-well and exposed flush with the surface of the N-well. The P+ body contact region and the N+ source injection region are respectively arranged adjacently inside the P-Body and exposed flush with the surface of the P-Body; The N+ drain injection region is located inside the N-well on the side away from the P-Body and is exposed flush with the surface of the N-well. P-pillars and N-pillars, multiple P-pillars and N-pillars are arranged alternately and adjacently inside the drift region, the drift region is formed in the N-well between the N+ source injection region and the N+ drain injection region; The field oxide dielectric layer and the gate oxide dielectric layer are provided. The field oxide dielectric layer covers the plurality of P pillars and N pillars. The gate oxide dielectric layer spans and covers the drift region. One end of the gate oxide dielectric layer terminates at the edge of the N+ source injection region, and the other end contacts the edge of the field oxide dielectric layer. A gate polycrystalline control region covers the surface of the field region oxide dielectric layer and the gate oxide dielectric layer; An isolation dielectric layer covers the P-Body, the gate polysilicon control region, the N+ drain injection region, and the N-well surface; Contact holes, a plurality of the contact holes are arranged inside the isolation dielectric layer, for leading out the N+ source injection region, the P+ body contact region, the N+ drain injection region and the gate polysilicon control region to the metal layer respectively; A passivation dielectric layer covers the surface of the isolation dielectric layer, and the metal layers are respectively disposed inside the passivation dielectric layer.

[0015] Preferably, there are two P-pillars and three N-pillars, with one P-pillar contacting each pair of adjacent N-pillars to form an alternating distribution structure.

[0016] Preferably, the edge of the N+ drain injection region is in contact with the edge of the outermost N pillar, and the N+ source injection region and the P+ body contact region are led out to the metal layer through a shared contact hole.

[0017] Compared with the prior art, the present invention has the following beneficial effects: This invention introduces novel N-Pillar and P-Pillar source-drain breakdown voltage structures in the drift region of LDMOS devices for the first time. This solves the problems of source-drain leakage and breakdown voltage drop caused by total dose radiation accumulation in LDMOS devices, ensuring the conventional device characteristics of LDMOS devices. The P-Pillar design prevents silicon-Si surface inversion under total dose conditions in the thick field region oxide layer of the drift region's SiO2 dielectric field plate, eliminating the direct leakage path between the source and drain after total dose testing, thus achieving total dose hardening of the shielded LDMOS device. Furthermore, the fabrication method of the LDMOS device structure in this invention uses conventional processes and procedures in semiconductor device manufacturing, exhibiting strong adaptability and simplicity, making it highly operable. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the fabrication process of a total dose-strengthened LDMOS device structure provided by the present invention.

[0019] Figure 2 This is a schematic diagram of N-Pillar photolithography injection for fabricating LDMOS devices on an N-well NWELL.

[0020] Figure 3 This is a schematic diagram of P-Pillar photolithography injection.

[0021] Figure 4 This is a schematic diagram of P-Body photolithography injection.

[0022] Figure 5 This is a schematic diagram of the high-temperature annealing process for N-Pillar, P-Pillar, and P-Body.

[0023] Figure 6 This is a schematic diagram of photolithographic etching of a SiO2 dielectric field plate used to create the field oxide layer.

[0024] Figure 7 This is a schematic diagram of the deposition and etching of the gate oxide SiO2 dielectric and the gate polycrystalline control region.

[0025] Figure 8 This is a schematic diagram of N+ and P+ photolithography and implantation.

[0026] Figure 9 This is a schematic diagram of the fabrication of the contact hole and the completion of the tungsten plug.

[0027] Figure 10 This is a schematic diagram of the fabrication of the metal layer AlSiCu and the passivation layer SiO2 dielectric. Detailed Implementation

[0028] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0029] like Figure 1 As shown in the figure, this invention specifically provides a method for fabricating a total dose-hardened LDMOS device structure, the process of which includes the following steps: Step S11: Fabrication of the drift region N-Pillar (N-pillar) and P-Pillar (P-pillar) using photolithography and implantation; Through photolithography and multi-step implantation of the N-Pillar and P-Pillar, a drift region with voltage isolation between the source and drain is formed; Total dose hardening is performed in the drift region, which is the high-voltage withstand region of the LDMOS device, containing a thick field oxygen region and also the region most affected by the total dose. Photolithography and multi-step implantation of the N-Pillar and P-Pillar eliminate thick field oxygen inversion, thereby achieving leakage isolation between the source and drain. Simultaneously, the charge balance principle is used to improve the silicon withstand voltage, increase the doping concentration of the drift region, reduce the drift region area, and lower the parasitic resistance of this region, achieving high drive capability of the LDMOS device; Step S12: Photolithographic implantation of P-Body (i.e., as the body region); high-temperature annealing of P-Body and N-Pillar and Pillar to form P-Body and Pillar with vertical connection, which is used to realize the breakdown voltage between source and drain and the characteristics of LDMOS device; Step S13: High-temperature annealing of N-Pillar, P-Pillar, and P-Body; Step S14: Fabricate the SiO2 dielectric field plate of the field region oxide layer; complete the modulation electric field of the polycrystalline field plate of the LDMOS device to improve the breakdown voltage of the LDMOS device; Step S15: Fabricate gate oxide and gate polysilicon; these serve as the gate control terminal of the LDMOS device, controlling the switching of the device. Step S16: Fabricate N+, P+ and contact holes; form source, drain and body contact areas respectively, and form contact holes using tungsten plugs, and bring out the gate polycrystalline control terminal, source body contact terminal and drain terminal respectively for metal layer to contact; Step S17: Create the metal layer and passivation layer.

[0030] The specific steps and processes are as follows: First, an N+ buried layer (NBL) 1 and an N-well (NWELL) 2 are sequentially formed on the epitaxial layer of a Si substrate. Source and drain drift regions are fabricated on the N-well 2. A mask 3 is provided, and N-pillar lithography and multi-step implantation are performed. N-type impurities such as As or P are implanted into the N-pillar 4, with an implantation energy of 50keV~1000keV and an implantation dose of 5E11~1E12. After high-temperature annealing of the P-body 6, the depth is 3μm~5μm and the width is 2μm~5μm (depending on the LDMOS device operating voltage). The implantation energy is controlled and the annealing temperature is adjusted to achieve a columnar doped morphology with interconnected layers. Figure 2 The diagram shown is a cross-sectional view after this step is completed.

[0031] In the source and drain drift regions, P-Pillar 5 photolithography and multi-step implantation are performed first. The P-Pillar 5 implants P-type impurities such as B / BF2 / BF3 at an implantation energy of 30keV~500keV and an implantation dose of 5E12~1E13. After high-temperature annealing of the P-Body 6, the depth is 3μm~5μm and the width is 1μm~3μm (depending on the LDMOS device operating voltage). By controlling the implantation energy and adjusting the annealing temperature, a columnar doped morphology with interconnected top and bottom is achieved. Figure 3 The diagram shown is a cross-sectional view after this step is completed.

[0032] The P-Body 6 of the LDMOS device is fabricated. The implanted impurities in the P-Body 6 are P-type impurities such as B / BF2 / BF3. The implantation energy of the P-Body 6 is 50keV~100keV, and the implantation dose is 1E13~1E14, forming a breakdown voltage and device characteristic control region, such as... Figure 4 The diagram shown is a cross-sectional view after this step is completed.

[0033] The N-Pillar 4, P-Pillar 5, and P-Body 6 of the LDMOS device are subjected to high-temperature annealing at 1000℃~1200℃ for 80~150 minutes to form the device control region and the voltage-delay drift region that is interconnected on both sides. Figure 5 The diagram shown is a cross-sectional view after this step is completed.

[0034] Polycrystalline field plate fabrication involves field oxide deposition, photolithography, and etching to form the desired morphology. The thickness of the SiO2 dielectric 7 in the field region is 350nm~1500nm. Thick dielectric layers are prone to generating numerous hole traps at the interface under total dose radiation, causing inversion loss of device characteristics on the silicon-Si surface. The successful design and fabrication of P-Pillar 5 eliminates the inversion problem of the SiO2 dielectric 7 in the field region on the silicon-Si surface. Simultaneously, it works in conjunction with N-Pillar 4, utilizing the charge balance principle to improve the silicon-Si ultimate breakdown voltage and reduce the drift region area. Figure 6 The diagram shown is a cross-sectional view after this step is completed.

[0035] The gate oxide SiO2 dielectric 8 has a thickness of 15nm~80nm, and a gate polycrystalline control region 9 with a thickness of 0.5μm~1.0μm is deposited and etched to form the device gate polycrystalline control terminal, such as... Figure 7 The diagram shown is a cross-sectional view after this step is completed.

[0036] Photolithography and implantation are performed on the N+ drain implantation region 101, N+ source implantation region 102, and P+ body contact region 11 of the high- and low-voltage transistors. The N+ impurities implanted in the N+ drain implantation region 101 and N+ source implantation region 102 are mostly As or P, with an implantation energy of 40 keV~80 keV and an implantation dose of 1E15-1E16. For the P+ body contact region 11, P-type impurities are B, BF2, or BF3, with an implantation energy of 20 keV~60 keV and an implantation dose of 1E15-5E15. Figure 8 The diagram shown is a cross-sectional view after this step is completed.

[0037] A SiO2 dielectric layer 12, with a thickness of 0.6 μm to 0.8 μm, is grown by chemical deposition to provide full coverage as an isolation layer. Contact holes 13 are then formed using photolithography and dry etching. The contact holes 13 are designed with a size of 150 nm to 300 nm. Tungsten plugs are formed within the contact holes 13 using chemical vapor deposition. The gate, drain, source, and body contact regions of the LDMOS device are then led out from the contact holes to achieve interconnection. Figure 9 The diagram shown is a cross-sectional view after this step is completed.

[0038] A metal layer 14 with a thickness of 0.7 μm to 1.5 μm is deposited and connected to contact holes 13 for chip functional connection and subsequent bonding. Simultaneously, a passivation dielectric 15 is deposited, consisting of SiO2 or SiO2+Si3N4, with a thickness of 0.5 μm to 1.0 μm, to complete device isolation and protection. Figure 10 The diagram shown is a cross-sectional view after this step is completed.

[0039] like Figure 10 As shown, this embodiment of the invention specifically provides a total dose-hardened LDMOS device structure, including: N+ buried layer and N well, wherein the N+ buried layer (NBL) 1 and N well (NWELL) 2 are sequentially disposed on the surface of the P- epitaxial layer of the P+ substrate; P-Body 6, as the body region, is arranged inside one side of the N-well 2 and exposed flush with the surface of the N-well 2; The P+ body contact region 11 and the N+ source injection region 102 are respectively arranged adjacently inside the P-Body 6 and exposed flush with the surface of the P-Body 6. The N+ drain injection region 101 is disposed inside the N-well 2 on the side away from the P-Body 6 and exposed flush with the surface of the N-well 2. P-pillars 5 and N-pillars 4, a plurality of P-pillars 5 and N-pillars 4 are arranged alternately and adjacently inside the drift region, the drift region being formed in the N-well 2 between the N+ source injection region 102 and the N+ drain injection region 101; The field oxide dielectric layer 7 and the gate oxide dielectric layer 8 are provided. The field oxide dielectric layer 7 covers the plurality of P pillars 5 and N pillars 4. The gate oxide dielectric layer 8 spans and covers the drift region. One end of the gate oxide dielectric layer 8 terminates at the edge of the N+ source injection region 102, and the other end contacts the edge of the field oxide dielectric layer 7. The gate polycrystalline control region 9 covers the surface of the field region oxide dielectric layer 7 and the gate oxide dielectric layer 8; An isolation dielectric layer 12 covers the surface of the P-Body 6, the gate polysilicon control region 9, the N+ drain injection region 101, and the N-well 2. Contact holes 13, a plurality of contact holes 13 are arranged inside the isolation dielectric layer 12, for leading out the N+ source injection region 102, the P+ body contact region 11, the N+ drain injection region 101 and the gate polysilicon control region 9 to the metal layer 14 respectively; A passivation dielectric layer 15 covers the surface of the isolation dielectric layer 12, and the metal layers 14 are respectively disposed inside the passivation dielectric layer 15.

[0040] Two P-pillars 5 are arranged, and three N-pillars 4 are arranged. There is one P-pillar 5 between every two adjacent N-pillars 4 to form an alternating distribution structure.

[0041] The edge of the N+ drain injection region 101 is in contact with the edge of the outermost N pillar 4, and the N+ source injection region 102 and the P+ body contact region 11 are led out to the metal layer 14 through a shared contact hole 13.

[0042] The above main design methods have led to the development of a total dose hardened LDMOS device structure and fabrication method. This invention innovatively proposes a total dose hardened LDMOS device structure and fabrication method, employing the charge balance principle and introducing N-Pillar and P-Pillar designs. This improves the utilization rate of the silicon Si ultimate breakdown voltage and reduces the drift region area. Furthermore, the presence of P-Pillar eliminates the inversion of the SiO2 dielectric in the field region on the silicon Si surface, enhancing the total dose resistance of the LDMOS device. This invention achieves total dose hardening capability without adding any new process steps.

[0043] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for fabricating a total dose-hardened LDMOS device structure, characterized in that, include: Provides an epitaxial layer on a silicon substrate; By sequentially forming an N+ buried layer and an N-well on the epitaxial layer, and performing photolithography and multi-step implantation on the P-pillar and N-pillar within the N-well, a drift region with withstand voltage isolation between the source and drain is formed. P-Body photolithography and implantation are performed on the N-well, and the P-Body, P-pillar and N-pillar are subjected to high-temperature annealing to deepen the P-Body to form a bulk region, and to form P-pillar and N-pillar that are connected vertically. Photolithography and etching of field region oxide dielectric layers on the surfaces of P-pillars and N-pillars; By growing a gate oxide dielectric layer and depositing and etching the gate polycrystalline control region; The source, drain, and body contact regions are formed by performing N+ and P+ photolithography and implantation in the P-body, N+ photolithography and implantation in the N-well, and annealing activation. The isolation dielectric layer is fully covered by chemical deposition, and the contact holes are photolithographically and dryly etched to bring out the gate polysilicon control terminal, source contact terminal and drain terminal respectively, so as to enable the metal layer to make contact and conduct. The device is protected by performing metal layer deposition, photolithography, and etching, and then performing chemical deposition, photolithography, and etching of the passivation dielectric layer.

2. The method for fabricating a total dose-enhanced LDMOS device structure as described in claim 1, characterized in that, Within the drift region, N-pillar lithography and multi-step implantation are performed. The N-impurity implanted into the N-pillar is an N-type impurity As or P, with an implantation energy of 50keV~1000keV and an implantation dose of 5E11~1E12. After high-temperature annealing, the depth of the N-pillar is 3μm~5μm and the width is 2μm~5μm.

3. The method for fabricating a total dose-enhanced LDMOS device structure as described in claim 2, characterized in that, Within the drift region, P-pillar lithography and multi-step implantation are performed. The P-impurities implanted into the P-pillars are P-type impurities B, BF2, or BF3, with an implantation energy of 30keV to 500keV and an implantation dose of 5E12 to 1E13. After high-temperature annealing, the depth of the P-pillars is 3μm to 5μm, and the width is 1μm to 3μm. By controlling the injection energy within the P-pillars and the N-pillars and adjusting the annealing temperature, a columnar concentration-doped morphology with vertically connected columns can be achieved.

4. The method for fabricating a total dose-enhanced LDMOS device structure as described in claim 1, characterized in that, The impurity injected into the P-Body is a P-type impurity B, BF2 or BF3, with an injection energy of 50keV~100keV and an injection dose of 1E13~1E14. The P-Body, P-pillar, and N-pillar are subjected to high-temperature annealing at a temperature of 1000℃~1200℃ for a time of 80min~150min.

5. The method for fabricating a total dose-enhanced LDMOS device structure as described in claim 1, characterized in that, The thickness of the field oxide dielectric layer is 350 nm to 1500 nm; the thickness of the gate oxide dielectric layer is 15 nm to 80 nm; the thickness of the gate polycrystalline control region is 0.5 μm to 1.0 μm; the thickness of the isolation dielectric layer is 0.6 μm to 0.8 μm; and the thickness of the passivation dielectric layer is 0.5 μm to 1.0 μm. The field oxide dielectric layer, the gate oxide dielectric layer, and the isolation dielectric layer are all made of SiO2 dielectric layer; the passivation dielectric layer is made of SiO2 or a mixture of SiO2 and Si3N4.

6. The method for fabricating a total dose-enhanced LDMOS device structure as described in claim 1, characterized in that, The process involves N+ and P+ lithography and implantation within the P-body, and N+ lithography and implantation within the N-well. The N-type impurity implanted in the N+ lithography is As or P, with an implantation energy of 40 keV to 80 keV and an implantation dose of 1E15-1E16. The P-type impurity implanted in the P+ lithography is B, BF2, or BF3, with an implantation energy of 20 keV to 60 keV and an implantation dose of 1E15-5E15.

7. The method for fabricating a total dose-enhanced LDMOS device structure as described in claim 1, characterized in that, The aperture size of the contact hole is 150nm~300nm, and a tungsten plug is formed in the contact hole by chemical vapor deposition to bring out the gate, drain, source and body contact areas of the LDMOS device from the contact hole, thereby realizing the connection function with the metal layer.

8. A total dose-hardened LDMOS device structure, fabricated using the method for fabricating a total dose-hardened LDMOS device structure as described in any one of claims 1 to 7, characterized in that, include: N+ buried layer and N well, wherein the N+ buried layer and N well are sequentially disposed on the surface of the P- epitaxial layer of the P+ substrate; The P-Body, as the body region, is arranged on one side inside the N-well and exposed flush with the surface of the N-well. The P+ body contact region and the N+ source injection region are respectively arranged adjacently inside the P-Body and exposed flush with the surface of the P-Body; The N+ drain injection region is located inside the N-well on the side away from the P-Body and is exposed flush with the surface of the N-well. P-pillars and N-pillars, multiple P-pillars and N-pillars are arranged alternately and adjacently inside the drift region, the drift region is formed in the N-well between the N+ source injection region and the N+ drain injection region; The field oxide dielectric layer and the gate oxide dielectric layer are provided. The field oxide dielectric layer covers the plurality of P pillars and N pillars. The gate oxide dielectric layer spans and covers the drift region. One end of the gate oxide dielectric layer terminates at the edge of the N+ source injection region, and the other end contacts the edge of the field oxide dielectric layer. A gate polycrystalline control region covers the surface of the field region oxide dielectric layer and the gate oxide dielectric layer; An isolation dielectric layer covers the P-Body, the gate polysilicon control region, the N+ drain injection region, and the N-well surface; Contact holes, a plurality of the contact holes are arranged inside the isolation dielectric layer, for leading out the N+ source injection region, the P+ body contact region, the N+ drain injection region and the gate polysilicon control region to the metal layer respectively; A passivation dielectric layer covers the surface of the isolation dielectric layer, and the metal layers are respectively disposed inside the passivation dielectric layer.

9. The total dose-enhanced LDMOS device structure as described in claim 8, characterized in that, Two P-pillars are arranged, and three N-pillars are arranged. There is one P-pillar between every two adjacent N-pillars to form an alternating distribution structure.

10. The total dose-enhanced LDMOS device structure as described in claim 9, characterized in that, The edge of the N+ drain injection region is in contact with the edge of the outermost N pillar, and the N+ source injection region and the P+ body contact region are led out to the metal layer through a shared contact hole.

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