A tilt angle controllable gate structure and a preparation method thereof

Abstract

The application discloses a preparation method of a gate structure with adjustable inclination, and comprises the following steps: obtaining a structure to be etched, wherein the structure to be etched comprises, from bottom to top, a barrier layer, a passivation layer and a photoresist layer; performing photoetching on the upper surface of the photoresist layer to obtain a first photoresist groove; performing pre-etching in the region of the first photoresist groove to obtain a passivation layer groove; performing lateral etching on the photoresist layer in the region of the first photoresist groove to obtain a second photoresist groove; performing main etching in the region of the second photoresist groove, so that the distance between the bottom of the current passivation layer groove and the surface of the adjacent barrier layer is a second distance, and the sidewall forms a passivation layer step; performing auxiliary etching in the region of the current passivation layer groove to form a gate groove, and modifying the appearance of the gate groove to smooth the sidewall thereof; and performing gate photoetching and gate metal evaporation in the obtained gate groove to obtain a gate structure with an inclined side. The application can improve the electrical performance of the gate structure.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor fabrication, specifically relating to a tilt-adjustable gate structure and its fabrication method. Background Technology

[0002] Due to the highly competitive power performance of gallium nitride-based high electron mobility transistors (GaN HEMTs) at high frequencies, the application frequency range of GaN-based electrical devices has continued to rise in recent years. As a key control unit for controlling channel current, the physical dimensions and morphology of the gate structure have become crucial for improving the frequency characteristics of GaN HEMT devices and reducing electron transit delay.

[0003] Currently, traditional gate structure fabrication methods first utilize photoresist thermal reflow technology or dry etching technology to isotropically broaden the passivation layer, creating trenches with a certain sidewall angle within the passivation layer. Then, metal is deposited within the trenches through metal evaporation and lift-off processes, thereby constructing a solid gate structure within the passivation layer.

[0004] However, the photoresist hot reflow technology has limited control over the morphology of the groove, making it difficult to control the precision of the etching of the gate structure groove. The plasma bombardment of the dry etching technology is prone to damage to the surface of the barrier layer. If the bombardment energy is reduced to avoid damage to the surface of the barrier layer, the sidewalls of the gate structure groove will become steep, resulting in insufficient subsequent metal filling and thus affecting the electrical performance of the gate structure. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a tilt-adjustable gate structure and its fabrication method. The technical problem to be solved by this invention is achieved through the following technical solution: In a first aspect, the present invention provides a method for fabricating a gate structure with adjustable tilt angle, comprising the following steps: S1. Obtain the structure to be etched, wherein the structure to be etched includes a barrier layer, a passivation layer and a photoresist layer stacked sequentially from bottom to top; S2. Photolithography is performed on the upper surface of the photoresist layer to obtain the first photoresist trench; S3. Pre-etching is performed in the area of ​​the first photoresist trench to remove part of the passivation layer and obtain a passivation layer trench; wherein, the distance between the bottom of the passivation layer trench and the surface of the adjacent barrier layer is a first distance; S4. Laterally shape the photoresist layer within the region of the first photoresist trench. Etching exposes the passivation layer plane to be etched on the side of the current passivation layer trench, thus obtaining a second photoresist trench. S5. Perform main etching in the area of ​​the second photoresist trench to remove part of the passivation layer, so that the distance between the bottom of the current passivation layer trench and the surface of the adjacent barrier layer is the second distance, and passivation layer steps are formed on the sidewall, wherein the second distance is less than the first distance. S6. Perform auxiliary etching in the area of ​​the current passivation layer trench to remove the bottom passivation layer, flatten the passivation layer steps into a slope to form a gate trench, and modify the shape of the gate trench to smooth its sidewalls. S7. Perform gate photolithography and gate metal evaporation in the obtained gate trench to obtain a gate structure with inclined edges.

[0006] In one embodiment of the present invention, performing steps S4-S5 includes: Combine S4 and S5 into a loop unit and execute it a preset number of times; During each execution of the loop unit, the lateral width of the passivation layer plane to be etched in S4 remains the same, which is used to define equal-width steps on the sidewall of the passivation layer. In each execution of the loop unit, the amount of reduction of the second distance in S5 remains the same, which is used to etch out steps of equal depth within the passivation layer. After the loop unit completes the preset number of operations, the second distance is less than 10 nm.

[0007] In one embodiment of the present invention, the preset number of times is monotonically related to the tilt angle of the inclined side of the gate structure.

[0008] In one embodiment of the present invention, after obtaining the first photoresist trench, the method further includes: A mask is prepared and stacked on the photoresist layer, such that the mask is located on one side of the first photoresist trench to cover it, thereby obtaining a gate structure with one side tilted in step S7.

[0009] In one embodiment of the present invention, the process conditions corresponding to step S3 include: The concentration is 80 sccm. The concentration was 20 sccm, the ICP power was 1000W, and the RF power was 150W.

[0010] In one embodiment of the present invention, the process conditions corresponding to step S4 include: The concentration was 40 sccm, the ICP power was 200W, and the RF power was 25W.

[0011] In one embodiment of the present invention, the process conditions corresponding to step S5 include: The concentration is 80 sccm. The concentration was 20 sccm, the ICP power was 1000W, and the RF power was 150W.

[0012] In one embodiment of the present invention, the process conditions corresponding to step S6 include: The concentration was 40 sccm, the ICP power was 200W, and the RF power was 5W.

[0013] Secondly, the present invention provides a tilt-adjustable gate structure, which is prepared using the tilt-adjustable gate structure preparation method described in any one of the first aspects.

[0014] In one embodiment of the present invention, when the barrier layer is not less than 10 nm, the corresponding process conditions for step S6 include: The concentration is 40 sccm. The concentration was 10 sccm, the ICP power was 200W, and the RF power was 5W.

[0015] Compared with the prior art, the beneficial effects of the present invention are: First, this invention removes a portion of the passivation layer in advance through pre-etching in step S3, maintaining a first distance between its bottom and the barrier layer surface. This action pre-cuts the passivation layer volume by about half vertically, effectively reducing the vertical excavation burden of the subsequent main etching in S5 and avoiding selective deterioration of the sidewalls caused by a single long-term dry etching process. Subsequently, this invention performs a highly integrated joint cycle of photoresist lateral etching in step S4 and passivation layer main etching in step S5. In each cycle, step S4 gradually exposes the plane of the passivation layer to be etched through lateral expansion, while step S5 performs vertical etching, adding a step to the sidewall while deepening the trench. Since the total height of the passivation layer trench is rigidly constrained spatially by the original thickness of the passivation layer, this invention increases the number of passivation layer steps formed on the sidewall in a stepwise manner by increasing the number of joint cycle executions of steps S4 and S5. When the number of executions is small, the sidewall morphology tends to be steep; when the number of executions increases, the overall envelope surface tends to be gentler due to the increased density of the step group. This process, which uses the "number of cycles" and "lateral exposed area" to collaboratively define the density of the step group, achieves high-precision, linear, and quantitative control of the final tilt angle of the grid slot.

[0016] Secondly, addressing the fundamental problem in traditional techniques where reduced etching energy to protect the substrate results in steep trench sidewalls, leading to insufficient subsequent metal filling and interfacial voids, this invention successfully constructs a multi-level step group composed of discrete right-angle corners on the passivation layer sidewalls through multiple cycles of S4 and S5. During the auxiliary etching stage in step S6, the plasma exhibits isotropic chemical abrasion characteristics, causing the sharp right-angle corners of the step group, which are spatially prominent, to be preferentially subjected to surface stripping and planarization by the plasma. As the number of cycles increases, the step group becomes increasingly compact, and the auxiliary etching's effect on removing sharp edges becomes more significant. This transforms the originally rigid multi-level step-like cliff morphology in situ into a seamless, continuously sliding, smooth slope without step corners, thereby completing the smoothing of the entire gate trench sidewall morphology. This continuous, smooth funnel-shaped trench sidewall eliminates the microscopic shadowing effect caused by traditional steep sidewalls or stepped cliffs during the solid gate metal deposition filling in step S7. It ensures that metal atoms can spread and fill the entire gate trench sidewall, eliminates void traces at the metal-passivation layer interface, significantly reduces gate parasitic resistance, and improves device withstand voltage reliability.

[0017] Finally, this invention perfectly decouples the fundamental contradiction in traditional processes—the "fineness of the trench bottom width" and "zero-damage protection of the barrier layer"—in its process flow. On one hand, during the rapid excavation process of the multi-round main etching in step S5, the core area at the very bottom is always rigidly shielded and protected by the photoresist film above. Its vertical deepening process is not accompanied by the outward lateral expansion of the bottom, thus ensuring that the extremely fine core width (fine gate length) at the bottom of the trench does not expand outward uncontrollably with the increase of etching depth. On the other hand, the main etching stops after advancing to the second distance closest to the surface of the barrier layer, and the crucial action of finally exposing the substrate is independently undertaken by the auxiliary etching in step S6. The auxiliary etching advances the spacing from the second distance to 0nm in one go to achieve complete penetration. Since this step removes the inert gas with strong physical bombardment effect, it eliminates the physical damage and lattice destruction traces of high-energy heavy ions to the semiconductor substrate, maintains the integrity of the original lattice structure on the surface of the barrier layer to the greatest extent, and suppresses the interface leakage current and electron trapping effect caused by damage defects. Finally, while ensuring stable control of the extremely fine gate length and maintaining zero damage on the surface of the barrier layer, a smooth and compliant sidewall is obtained.

[0018] Therefore, this invention can improve the electrical performance of the gate structure while avoiding the influence of the fabrication process on the gate structure. The invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0019] Figure 1 This is a schematic flowchart of the method for preparing the tilt-adjustable gate structure provided in the embodiments of the present invention; Figure 2 This is a schematic diagram of the structure to be etched provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the epitaxial substrate in the structure to be etched provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of an epitaxial substrate having a source electrode and a drain electrode in the structure to be etched provided in the embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of an epitaxial substrate with a passivation layer in the structure to be etched, provided in an embodiment of the present invention; Figure 6 A schematic diagram showing the execution results of the steps in the method for preparing a tilt-adjustable gate structure according to an embodiment of the present invention; Figure 7 This is a schematic diagram showing the execution result of the loop unit being executed twice according to an embodiment of the present invention; Figure 8 This is a schematic diagram illustrating the angle control principle of the tilt-adjustable grid structure provided in this embodiment of the invention. Figure 9 This is a schematic diagram of the product structure during the photolithography of gate trenches in the manufacturing process of the GaN HEMT device with an adjustable tilt gate structure provided in this embodiment of the invention. Figure 10 This is a schematic diagram of a tilt-adjustable grid structure provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the product structure during the gate structure fabrication process in the manufacturing process of the GaN HEMT device with adjustable tilt gate structure provided in this embodiment of the invention. Figure 12 A schematic diagram of the product structure after the gate structure is fabricated in the manufacturing process of the GaN HEMT device with adjustable tilt gate structure provided in this embodiment of the invention. Figure 13 This is a schematic diagram of another tilt-adjustable grid structure provided in an embodiment of the present invention; Figure 14 This is a roughness comparison diagram of a conventional gate structure device and a tilt-adjustable gate structure device provided in the embodiments of the present invention; Figure 15 This is a schematic diagram comparing the electric field distribution of a conventional gate structure and a tilt-adjustable gate structure provided in an embodiment of the present invention; Figure 16 This is a schematic diagram of FIB test results for a conventional gate structure and a tilt-adjustable gate structure provided in an embodiment of the present invention; Figure 17 This is a roughness comparison diagram of a conventional gate structure and an adjustable tilt angle ultrafine gate structure provided in an embodiment of the present invention; Figure 18 This is a schematic diagram comparing the mobility of a conventional gate structure device and a tilt-adjustable gate structure device provided in an embodiment of the present invention. Figure 19 These are the CDSEM test results of the gate trench after photolithography and after etching provided in the embodiments of the present invention. Detailed Implementation

[0020] Gallium nitride-based high electron mobility transistors (GaN HEMTs) exhibit highly competitive power performance at high frequencies, meeting the requirements of millimeter-wave communication and thus becoming ideal devices for RF power amplifiers. In recent years, as the application frequency bands of GaN HEMT devices have continued to rise, reducing the gate length has become a key path to improve the frequency characteristics of GaN HEMT devices, thereby increasing the cutoff frequency (fT) and maximum oscillation frequency (fMAX) by reducing electron transit delay. This poses significant challenges to the morphology, rate, and damage of the passivation layer etching in the gate region.

[0021] In device fabrication, lateral expansion of the passivation layer during etching is an unavoidable defect in traditional etching processes, primarily due to two reasons: First, etching processes cannot achieve absolute anisotropy, inevitably leading to lateral etching. Second, conventional etching gases react with the photoresist, causing the pattern formed by photolithography to expand continuously, resulting in an increased final pattern size. Simultaneously, damage to the barrier layer during etching reduces the device's saturation current, increases leakage current, and impairs power characteristics. This is especially true for thin-barrier devices, where the two-dimensional electron gas is closer to the top of the barrier layer, making them more sensitive to etching damage. Furthermore, shortening the gate length increases the aspect ratio, worsens the filling properties during gate metal evaporation, increases fabrication complexity, and also affects the gate's control over the channel.

[0022] Based on the above, there is a need for a method to fabricate a gate structure that can shorten the gate length while also achieving low etching damage and good metal filling.

[0023] In a gate structure fabrication method, a two-step etching process combining dry and wet etching is used to fabricate the gate structure, thus enabling its application in integrated circuit manufacturing. In this method, anisotropic dry etching is first used to remove part of the passivation layer, forming a trench of a certain depth. Then, isotropic wet etching is used to remove the remaining passivation layer while simultaneously etching the gate sidewalls on both sides, resulting in a tilt angle that is related to the ratio of the depths of the dry and wet etching processes. This achieves a gate etching technique with controllable tilt angle.

[0024] In another method for fabricating a gate structure, a gate fabrication process using photoresist thermal reflow and dry etching is employed. First, the thermal reflow process is used to reduce the sidewall angle of the photoresist and shrink the trench size. Then, dry etching is used to remove the passivation layer in the gate region, which can achieve a gate length of less than 100nm while maintaining a sidewall tilt angle of 70°.

[0025] In another method for fabricating a gate structure, a gate fabrication process combining thermal reflow with main etching and over-etching is used. First, the photoresist is tilted at a certain angle through thermal reflow. Then, the passivation layer is removed by main etching. Finally, an over-etching process is used, which has zero bias power and a significantly increased chamber pressure. The etching gas has a short free path and low acceleration energy, which can greatly reduce etching damage and remove residual passivation layer at the same time. The gate length fabricated is 0.5 micrometers.

[0026] In summary, recent advancements in gate fabrication have encompassed various processes, including thermal reflow, F-based dry etching, and wet etching, with each method pursuing different desired effects. Some gate fabrication methods achieve a specific tilt angle on the gate sidewalls or aim to shorten the gate length; others focus on reducing etching damage. However, currently, no single gate fabrication method simultaneously possesses the characteristics of low damage, short gate length, and tilted sidewalls.

[0027] Specifically, while the two-step etching method combining dry and wet etching for gate structure fabrication utilizes the isotropic nature of wet etching to achieve tilted sidewalls, it also results in a large etching margin, making it impossible to achieve extremely fine gate lengths below 100 nm. Furthermore, this method involves high temperatures and safety risks; hot phosphoric acid requires high-temperature operation, is highly corrosive, and easily generates harmful gases. Finally, the fabrication accuracy is relatively low. As the reaction proceeds, the solution concentration changes due to water vapor evaporation and reactant reduction, leading to unstable etching rates and consequently decreased accuracy.

[0028] While the gate fabrication process using photoresist thermal reflow and dry etching can achieve extremely fine gates with tilted sidewalls, it still has significant limitations: First, the photoresist formed by thermal reflow is not completely unreactive with the etching gas, especially when the etching gas contains... During etching, the photoresist reacts with the etching gas and is laterally etched. The actual gate size fabricated is inevitably smaller than the size of the photolithographic trench after reflow, making it difficult to achieve extremely fine gates using thermal reflow combined with etching. Secondly, poor dimensional consistency and uneven spacing between wafers and within the wafer affect photoresist flow, leading to decreased uniformity. Thirdly, while single-step dry etching reduces the outward spread, it also causes some etching damage, which can damage the barrier layer and degrade device performance.

[0029] Although the gate fabrication process using hot reflow combined with main etching and over-etching reduces etching damage by adding an over-etching step, the instability and poor uniformity of hot reflow are still unavoidable. Furthermore, the poor anisotropy of the over-etching method, in order to reduce etching damage, leads to a further increase in gate size.

[0030] For RF power amplifiers, thinning the barrier and shortening the gate length are key to improving their frequency performance. However, barrier thinning makes the device more sensitive to etching damage, requiring strict control over etching damage; shortening the gate length also increases the difficulty of metal filling, necessitating multi-step processes to fabricate tilted sidewalls. Therefore, existing technologies are insufficient to meet the needs of future RF power amplifiers, necessitating the development of novel gate structure fabrication methods to create ultra-fine sidewall tilted gates, thus promoting the application of RF power amplifiers at higher frequency bands.

[0031] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0032] Firstly, embodiments of the present invention provide a method for fabricating a gate structure with adjustable tilt angle. Before describing the method, it should be noted that the embodiments of the present invention use an ICP-RIE etching machine as the implementation hardware, which provides stable etching rate and low etching damage.

[0033] Please see Figure 1 , Figure 1 This is a schematic flowchart of a method for fabricating a tilt-adjustable gate structure according to an embodiment of the present invention.

[0034] The method includes the following steps S1-S7: S1. Obtain the structure to be etched, which includes a barrier layer, a passivation layer and a photoresist layer stacked sequentially from bottom to top.

[0035] Specifically, in one embodiment of the present invention, the structure to be etched includes a barrier layer, a passivation layer, and a photoresist layer stacked sequentially from bottom to top; wherein the barrier layer includes an AlGaN barrier layer, the passivation layer includes a SiN passivation layer, and the photoresist layer includes EPI621 photoresist. Figure 2 As shown.

[0036] In another embodiment of the present invention, the structure to be etched includes a processed epitaxial substrate and a photoresist layer.

[0037] The epitaxial substrate before processing was grown using an MOCVD system, with triethylgallium (TEGa) as the Ga source, trimethylaluminum (TMAl) as the Al source, ammonia (NH3) as the N source, and high-purity hydrogen as the carrier gas. The substrate, from top to bottom, includes a SiC substrate, a GaN buffer layer, a GaN channel layer, and an AlGaN barrier layer, as shown below. Figure 3 As shown, the epitaxial substrate before processing undergoes process steps to obtain the processed epitaxial substrate.

[0038] Specifically, the epitaxial substrate processing steps are as follows: Step 1: Fabricate source and drain electrodes on the epitaxial substrate, such as... Figure 4 As shown.

[0039] 1) Photolithography of the source and drain electrode regions on the AlGaN barrier layer: (a) Preheat the epitaxial substrate on a hot plate at 200°C for 5 minutes; (b) Spreading adhesive (PMGI SF6) was applied to the AlGaN barrier layer at a spin coater speed of 2000 rad / min for 40 seconds, resulting in a spin coat thickness of 0.35 μm. The sample was then baked on a hot plate at 200°C for 5 minutes. (c) Photoresist (EPI621) was applied to the release adhesive. The spin coater was rotated at 5000 rad / min and the spin coat time was 30 seconds. The thickness of the spin coat was 0.77 μm. Then the sample was placed on a hot plate at 90°C and baked for 1 minute. (d) Place the sample that has been coated and spin-coated into the photolithography machine to expose the coated surface for 230ms, and then bake the exposed sample on a hot plate at 110°C for 1 minute. (e) Immerse in developer (EPD1000) to remove photoresist and stripper, develop for 45 seconds, then rinse with ultrapure water and dry with nitrogen to obtain the defined source electrode region and drain electrode region. 2) Evaporate the source and drain electrodes on the AlGaN barrier layer within the source and drain electrode regions, and on the photoresist outside the source and drain electrode regions: (a) The sample with the photolithographic pattern of the active electrode and the drain electrode is placed in a plasma resist remover for underfilm treatment at a power of 200W. The concentration was 100 sccm, and the treatment time was 5 minutes. (b) Place the sample into the electron beam evaporation stage and wait for the vacuum level in the reaction chamber of the electron beam evaporation stage to reach the specified value. Following the torsion process, ohmic metals are evaporated onto the AlGaN barrier layers in the source and drain regions, and onto the photoresist outside the source and drain regions, to form the source and drain electrodes. The ohmic metals, from bottom to top, are Ti = 200 Å; Al = 1600 Å; Ni = 550 Å; Au = 450 Å. (c) The sample after ohmic metal evaporation is stripped to remove the ohmic metal, photoresist and release adhesive outside the source electrode and drain electrode, and then the sample is rinsed with ultrapure water and dried with nitrogen.

[0040] 3) The samples after ohmic metal evaporation and stripping are placed in a rapid thermal annealing furnace for annealing treatment. This allows the ohmic metal on the AlGaN barrier layer in the source and drain electrodes to sink to the GaN buffer layer, thereby forming an ohmic contact between the ohmic metal and the heterojunction channel. The annealing process conditions are as follows: annealing atmosphere... The annealing temperature was 840°C and the annealing time was 60 seconds.

[0041] Step 2: A SiN passivation layer is grown on the AlGaN barrier layer of the source electrode, drain electrode, and active region using a PECVD process, such as... Figure 5 As shown. Includes the following steps: 1) Perform surface cleaning on the samples after the source and drain electrodes have been fabricated: (a) The sample was placed in acetone solution and ultrasonically cleaned for 5 minutes at an ultrasonic intensity of 2.2. (b) Place the sample in a stripping solution at 60°C and heat in a water bath for 15 minutes; (c) The sample was placed in acetone solution and isopropanol solution in sequence and ultrasonically cleaned for 3 minutes with an ultrasonic intensity of 2.2. (d) Rinse the sample with ultrapure water and dry it with nitrogen gas; 2) A 120 nm thick AlGaN barrier layer was grown on the source electrode, drain electrode, and active region using PECVD. The passivation layer is grown under the following process conditions: (2%) / ) = 200 sccm, =2sccm, =0sccm, =200sccm, pressure=600mT, temperature=350℃, power=22W, deposition time=25 minutes.

[0042] S2. Photolithography is performed on the upper surface of the photoresist layer to obtain the first photoresist trench.

[0043] The photolithography methods include electron beam lithography, nanoimprint lithography (NIL), extreme ultraviolet lithography (EUV), or stepper projection lithography with phase shift mask, etc.

[0044] The function of the first photoresist trench is to provide conditions for direct etching of the passivation layer in S3, avoid pre-etching gas etching of the photoresist, and improve etching time and efficiency.

[0045] Specifically, such as Figure 6 As shown in Figure (a), in one embodiment of the present invention, the layout size is designed to be 30-50 nm wide. Since the exposure and development of the photoresist will result in a certain pattern expansion, the width of the first photoresist trench generated by the exposure is 50-70 nm, and the height is equal to the thickness of the photoresist layer.

[0046] S3. Pre-etching is performed in the area of ​​the first photoresist trench to remove part of the passivation layer and obtain a passivation layer trench; wherein, the distance between the bottom of the passivation layer trench and the surface of the adjacent barrier layer is a first distance.

[0047] The passivation trench is a groove located inside the passivation layer, with its top opening at the junction of the photoresist layer and the passivation layer, and its bottom located above the barrier layer.

[0048] In one possible implementation, the process conditions corresponding to step S3 include: The concentration is 80 sccm. The concentration was 20 sccm, the ICP power was 1000W, and the RF power was 150W.

[0049] Specifically, such as Figure 6 As shown in Figure (b), in one embodiment of the present invention, the etching gas used for pre-etching is... (80sccm) combination (20 sccm), ICP power 1000W, RF power 150W. The distance between the bottom of the passivation trench and the adjacent barrier layer surface is the overall... 50% to 60% of the passivation layer.

[0050] This step involves sufficient etching gas, and with a sufficiently high ICP power, the gas molecules will fully dissociate into... Atoms and Atoms. RF power determines the downward velocity of particles; 150W of RF power can ensure... Atoms and Atoms rapidly moving towards Surface motion gives the pre-etching process good anisotropy. During actual verification, the pre-etching exhibited a shrinkage in trench size. Because the etching gas flows better in the middle of the trench, facilitating the removal of etching products, the etching speed is faster. The etching speed is slower at the edges of the trench near the photoresist sidewalls, resulting in a 5-10 nm shrinkage in trench size on each side after etching. Since the passivation layer thickness is typically 120 nm, the sidewall tilt angle remains above 85° after the trench shrinkage, and can still be approximated as vertical sidewalls. Due to the shrinkage in trench size, the final trench width obtained after etching is 40-60 nm.

[0051] S4. Laterally apply the photoresist layer within the area of ​​the first photoresist trench. Etching exposes the plane of the passivation layer to be etched on the side of the current passivation trench, thus obtaining the second photoresist trench.

[0052] In this process, the passivation layer plane to be etched is located below the photoresist layer, on both sides of the passivation layer trench, exposing the upper surface of the passivation layer. The function of the passivation layer plane to be etched is to control the lateral distance of the passivation layer etched in step S5. It can be understood that when the sidewalls of the passivation layer trench need to have a stepped shape, the lateral width of each step is equal to the lateral width of the passivation layer plane to be etched generated in each step S4.

[0053] The function of the second photoresist trench is to provide the etching range for the main etching in S5, guide the main etching to etch the passivation layer inside the second photoresist trench, and at the same time provide protection for the passivation layer outside the second photoresist trench.

[0054] In one possible implementation, the process conditions corresponding to step S4 include: The concentration was 40 sccm, the ICP power was 200W, and the RF power was 25W.

[0055] Specifically, such as Figure 6 As shown in Figure (c) of this invention, in one embodiment, Etching employs plasma reaction technology, using The plasma reacts with the photoresist, causing a change in the morphology of the photoresist. The concentration was 40 sccm, ICP power was 200 W, and RF power was 25 W. Compared to pre-etching, this step involved reactants... The reduced flow rate means that a high ICP concentration is not required for complete dissociation. The reduced RF power also makes... Plasma etching is isotropic, which is beneficial for lateral etching of photoresist. After fixing the etching gas flow rate and power, the degree of lateral etching of photoresist is related to the reaction time. The lateral etching amount of photoresist needs to be controlled by setting the time according to the preset tilt angle of the fabricated gate.

[0056] It should be noted that a typical etching time of 40 seconds corresponds to a final sidewall angle of 70°. If the etching time is too short, the resulting slope will be too steep, and the improvement effect on metal filling and gate electric field will be insignificant. If the etching time is too long, the amount of photoresist lateral etching will be too much, which will make it difficult to flatten the steps formed by the main etching into a slope, and the final sidewall will appear stepped.

[0057] S5. Perform main etching on the passivation layer in the area of ​​the second photoresist trench to remove part of the passivation layer, so that the distance between the bottom of the current passivation layer trench and the surface of the adjacent barrier layer is the second distance, and passivation layer steps are formed on the sidewall, wherein the second distance is less than the first distance.

[0058] In one possible implementation, steps S4-S5 are performed, including: Combine S4 and S5 into a loop unit and execute it a preset number of times.

[0059] During each execution of the loop unit, the lateral width of the passivation layer plane to be etched in S4 remains the same, which is used to define equal-width steps on the sidewalls of the passivation layer.

[0060] During each execution of the loop unit, the reduction in the second distance in S5 remains the same, which is used to etch equal-depth steps within the passivation layer.

[0061] After the loop unit completes its execution count, the second distance is less than 10nm.

[0062] The loop unit refers to executing S4 and S5 sequentially. Within the loop unit, step S4 can be executed once or more before each execution of S5. There is no special limit to the number of times S4 can be executed.

[0063] Equal width and equal depth stepped steps lay the foundation for smoothing the sidewalls of the passivation layer trench in S6.

[0064] Specifically, in one embodiment provided by the present invention, the loop unit executes twice, including first executing S4 once, then executing S5 once; subsequently executing S4 once more, and then executing S5 once more. The execution steps are as follows: Figure 7 As shown.

[0065] In one possible implementation, the preset number of times is monotonically related to the tilt angle of the inclined side of the gate structure.

[0066] like Figure 8As shown, the number of times the loop unit is executed is monotonically correlated with the target tilt angle of the gate trench sidewall. This means that since the passivation layer trench is shaped like an inverted triangle, a target tilt angle exists on the gate trench sidewall; the height of the passivation layer trench is equal to the passivation layer thickness, and according to the Pythagorean theorem, changing the width of the passivation layer trench can change the target tilt angle; changing the number of times the loop unit is executed can change the width of the passivation layer trench. Therefore, the more times the loop unit is executed, the wider the passivation layer trench becomes, and the smaller the target tilt angle becomes.

[0067] Specifically, in one embodiment of the present invention, the purpose of the main etching is to form steps on the SiN sidewalls, preparing for the subsequent fabrication of inclined sidewalls.

[0068] When the fabricated device requires a small tilt angle, if only a single step is used... Etching laterally to the target width of the photoresist results in larger steps in the fabrication process, which is detrimental to the planarization of subsequent auxiliary etching. Therefore, multiple steps are required. The etching process, combined with the main etching step, breaks down the lateral expansion into multiple etching steps, with each single etching step only responsible for a portion of the expansion. This results in a multi-step structure, where each step is relatively narrow, making flattening easier and facilitating the formation of slopes with small inclination angles.

[0069] In one possible implementation, the process conditions corresponding to step S5 include: The concentration is 80 sccm. The concentration was 20 sccm; the ICP power was 1000W, and the RF power was 150W.

[0070] Specifically, such as Figure 6 As shown in Figure (d), in one embodiment of the present invention, the etching formula used in the main etching is the same as that used in the pre-etching, with a fast etching rate and good anisotropy, in order to reduce trench expansion and retain the size of the ultra-fine gate. This not only deepens the originally formed ultra-fine trench, essentially removing the remaining passivation layer at the bottom, but also creates a second passivation layer with a distance of less than 10 nm to protect the barrier layer. Simultaneously, steps are formed on both sides of the original trench, with the width of the steps being... The etched photoresist has a consistent lateral etching depth.

[0071] Because the main etching process has a fast etching rate and good anisotropy, especially The large atomic mass results in a strong bombardment of the barrier layer surface, which can cause some damage. Therefore, this step requires retaining a passivation layer of less than 10 nm to protect the barrier layer. This thin passivation layer is removed simultaneously during the subsequent auxiliary etching to form the tilt angle, but too much of it cannot be retained, as this would prolong the subsequent auxiliary etching time, increase trench expansion, and result in an excessively large final gate size. After the main etching is completed, the trench size will shrink to 30-50 nm.

[0072] S6. Perform auxiliary etching in the area of ​​the current passivation layer trench to remove part of the passivation layer, thereby flattening the passivation layer step into a slope, so that the distance between the bottom of the current passivation layer trench and the surface of the adjacent barrier layer is 0nm, forming a gate trench, and modifying the morphology of the gate trench to smooth its sidewalls.

[0073] In one possible implementation, the process conditions corresponding to step S6 include: The concentration was 40 sccm, the ICP power was 200W, and the RF power was 5W.

[0074] Specifically, such as Figure 6 As shown in Figure (e), in one embodiment of the present invention, auxiliary etching is a key step in forming the inclined sidewalls, and the etching gas used is only... (40 sccm), abandoning the one with a strong bombardment effect Gas. ICP power 200W, RF power 5W. Compared with pre-etching and main etching, the gas flow rate of auxiliary etching is halved, and the power is also significantly reduced, which slows down the etching rate of auxiliary etching and enhances isotropy. During the removal of the remaining passivation layer, auxiliary etching polishes the SiN steps, making them planar and forming inclined sidewalls. The etching time of this step is set according to the thickness of the remaining passivation layer, and a certain amount of overetching is required to ensure that the remaining passivation layer is completely removed. Due to the slow speed and poor anisotropy of auxiliary etching, it removes... Etching gases with high atomic mass, such as electron gases, cause minimal etching damage. Therefore, after completely removing the remaining passivation layer, the damage to the barrier layer is extremely low, ensuring that the two-dimensional electron gas concentration remains unaffected, making it suitable for thin barrier devices. It should be noted that auxiliary etching will have some etching outward expansion. However, since the remaining passivation layer is usually small, the vertical etching depth of auxiliary etching is only about 10 nm, the etching time is short, and its lateral etching amount is minimal, only serving to flatten the step into a slope. Therefore, its lateral outward expansion is minimal, and the final trench size is around 50 nm.

[0075] In one possible implementation, when the barrier layer is not less than 10 nm, the process conditions corresponding to step S6 include: The concentration was 40 sccm, the ICP power was 200W, and the RF power was 5W.

[0076] Specifically, in one embodiment of the present invention, during the auxiliary etching step, the etching gas is not entirely used. Instead, a small amount is added. This method can enhance the anisotropy and etching rate of the third etching step, preventing excessive gate length expansion and ensuring a small gate length. However, it increases etching damage, reduces interface roughness, and worsens mobility. This method is suitable for GaN HEMT devices with a barrier layer thickness exceeding 10 nm. When the barrier layer thickness is reduced to below 10 nm, the etching damage cannot be ignored.

[0077] Specifically, in one embodiment of the present invention, performing steps S1-S6 includes: A gate trench region is photolithographically patterned on the SiN passivation layer, and the SiN passivation layer within the gate trench region is etched using an ICP process, such as... Figure 9 As shown.

[0078] 1) Using EBL photolithography to lithographically depict the gate trench region on the SiN passivation layer: (a) Preheat the sample on a hot plate at 200°C for 5 minutes; (b) Electron beam photoresist coating and spin-coating were performed at a spin speed of 3500 rad / min, a spin time of 40 seconds, a photoresist layer thickness of 450 nm, and the sample was baked on a hot plate at 150°C for 1 minute. (c) The sample is placed in an electron beam lithography machine to expose the photoresist in the gate trench area; (d) After exposure, the sample is placed in the developer to remove the photoresist in the grid trench area and then dried with nitrogen. 2) Remove the SiN passivation layer in the gate trench area using a four-step etching process: (a) The conditions for the first step of pre-etching are: =80sccm, =20sccm, pressure =5Pa, upper electrode power =1000W, lower electrode power =150W. The etching depth is equal to 40%~50% of the SiN layer thickness.

[0079] (b) Step Two The etching conditions are: =50sccm, pressure=5Pa, upper electrode power=200W, lower electrode power=25W. Etching time is set according to the required tilt angle.

[0080] (c) The conditions for the third main etching step are: =50sccm, pressure=5Pa, upper electrode power=200W, lower electrode power=25W. The SiN passivation layer was etched to less than 10nm.

[0081] (d) The conditions for the fourth auxiliary etching step are: =50sccm, pressure=5Pa, upper electrode power=200W, lower electrode power=5W. Etching removes the remaining passivation layer and improves the sidewall tilt angle.

[0082] Finally, the appearance of the passivation layer trenches obtained through the four-step etching method is as follows: Figure 10 As shown S7. Perform gate photolithography and gate metal evaporation in the obtained gate trench to obtain a gate structure with inclined edges.

[0083] Among them, such as Figure 6 As shown in Figure (f), the edge-tilted gate structure includes a T-gate with a gate field plate. The T-gate with the gate field plate can reduce the gate resistance, modulate the peak electric field below the gate, improve the breakdown voltage, and extend the application scenarios of the device under high voltage.

[0084] In one embodiment of the present invention, the gate lithography and gate metal evaporation process includes the following steps: Step 1: Photolithographically etch the gate electrode region and fabricate the gate electrode using electron beam evaporation, such as... Figure 11 As shown.

[0085] 1) Photolithographic gate electrode region on AlGaN barrier layer: (a) Preheat the sample on a hot plate at 200°C for 5 minutes; (b) Apply release adhesive (PMGI SF6) to the SiN passivation layer. The spin coater speed is 2000 rad / min, the spin coat time is 40 seconds, and the spin coat thickness is 0.35 μm. Then, place the sample on a hot plate at 200°C and bake for 5 minutes. (c) Photoresist (EPI621) was applied to the release adhesive. The spin coater was rotated at 5000 rad / min and the spin coat time was 30 seconds. The thickness of the spin coat was 0.77 μm. Then the sample was placed on a hot plate at 90°C and baked for 1 minute. (d) Place the sample that has been coated and spin-coated into the photolithography machine to expose the coated surface for 280ms, and then bake the exposed sample on a hot plate at 110°C for 1 minute. (e) Immerse in developer (EPD1000) to remove photoresist and stripper, develop for 60 seconds, then rinse with ultrapure water and dry with nitrogen.

[0086] 2) Evaporating the gate electrode on the AlGaN barrier layer within the gate electrode region and on the photoresist outside the gate electrode region: (a) The sample with the photolithographic pattern of the gate electrode is placed in a plasma resist remover for underfilm treatment, with a power of 200W. =100sccm, processing time 5 minutes; (b) The sample is placed in an electron beam evaporation stage. After the vacuum degree of the reaction chamber of the electron beam evaporation stage reaches 2×10-6 Torr, the gate metal is evaporated on the AlGaN barrier layer in the gate electrode region and the photoresist outside the gate electrode region. The gate metal is in the order of Ni / Au=450 / 2700 Å from bottom to top. (c) The sample after the gate metal evaporation is completed is stripped to remove the gate metal, photoresist and stripping adhesive outside the gate electrode area. The sample is rinsed with ultrapure water and dried with nitrogen to form the gate electrode.

[0087] Step 2: Photolithographically pattern the metal interconnect opening regions on the SiN passivation layer, and then sequentially etch away the SiN passivation layer in the interconnect opening regions using an ICP process. Photolithographically pattern the metal interconnect opening regions on the SiN passivation layer: (a) Preheat the sample on a hot plate at 200°C for 5 minutes; (b) Apply photoresist (EPI621) to the sample, spin the sample at a speed of 3000 rad / min for 30 seconds, and then bake the sample on a hot plate at 90°C for 1 minute. (c) Place the sample that has been coated and spin-coated into the photolithography machine to expose the coated surface for 280ms, and then bake the exposed sample on a hot plate at 110°C for 1 minute. (d) After exposure, the sample is placed in the developer (EPD1000) to remove the photoresist in the interconnect opening area. The development time is 75 seconds, and the sample is rinsed with ultrapure water and dried with nitrogen. (e) Before etching the metal interconnect opening area, perform hard film preparation and bake the sample on a hot plate at 100°C for 1 minute; 3) Using ICP etching process, the reaction gas is and , =60sccm, =2sccm, pressure=1Pa, upper electrode power=100W, lower electrode power=25W, remove the 120nm thick SiN passivation layer in the interconnect opening area.

[0088] Step 3: Photolithographically pattern the metal interconnect layer regions on the source and drain electrodes in the metal interconnect opening area and on the SiN passivation layer without opening etching, and fabricate the metal interconnect layer using electron beam evaporation: 1) Photolithography of the metal interconnect layers on the source and drain electrodes in the metal interconnect opening region and on the SiN passivation layer without opening etching: (a) Place the sample with the completed metal interconnect opening etching on a hot plate at 200°C for 5 minutes for preheating; (b) Spreading adhesive (PMGI SF6) was applied to the AlGaN barrier layer at a spin coater speed of 2000 rad / min for 40 seconds, resulting in a spin coat thickness of 0.35 μm. The sample was then baked on a hot plate at 200°C for 5 minutes. (c) Photoresist (EPI621) was applied to the release adhesive. The spin coater was rotated at 5000 rad / min and the spin coat time was 30 seconds. The thickness of the spin coat was 0.77 μm. Then the sample was placed on a hot plate at 90°C and baked for 1 minute. (d) Place the sample that has been coated and spin-coated into the photolithography machine to expose the coated surface for 270ms, and then bake the exposed sample on a hot plate at 110°C for 1 minute. (e) Immerse in developer (EPD1000) to remove photoresist and stripper in the metal interconnect area for 60 seconds, then rinse with ultrapure water and dry with nitrogen. 2) Evaporate the metal interconnect layer on the electrodes and SiN passivation layer within the metal interconnect region and on the photoresist outside the metal interconnect region: (a) The sample with metal interconnect regions was placed in a plasma stripper for undercoat treatment at a power of 200W. =100sccm, processing time 5 minutes; (b) The sample is placed in an electron beam evaporation stage. After the vacuum degree of the reaction chamber of the electron beam evaporation stage reaches 2×10-6 Torr, the interconnect metal is evaporated on the electrodes and SiN passivation layer in the metal interconnect region and on the photoresist outside the metal interconnect region to form a metal interconnect layer. The metal interconnect layer is formed from bottom to top with Ti / Au=450 / 2700 Å to lead out the electrodes. (c) The sample after interconnect metal evaporation is stripped to remove metal, photoresist, and release adhesive outside the metal interconnect layer. The sample is then rinsed with ultrapure water and dried with nitrogen to complete device fabrication. Figure 12 As shown.

[0089] This invention provides a method for fabricating a tilt-adjustable gate structure. After obtaining the first photoresist trench, the method further includes: A mask is prepared and stacked on a photoresist layer, such that the mask is located on one side of the first photoresist trench and plays a covering role, thereby obtaining a gate structure with one side tilted in step S6.

[0090] Specifically, in one embodiment of the present invention, a mask is prepared between the source and the gate to achieve a masking effect, thereby enabling... Etching can only process the photoresist between the drain and the gate, forming a structure like... Figure 13The single-sided stepped structure shown can be further etched to form a single-sided tilted gate structure. In actual testing, only the drain is typically biased, while the source is usually grounded. Therefore, the electric field concentration effect between the gate and source is relatively weak, and the peak electric field is much lower than that between the gate and drain. The fundamental reason why the breakdown voltage of the device cannot be improved is that the peak electric field between the gate and drain is too large. Therefore, the gate sidewall between the gate and source can maintain a vertical structure. The advantage of this measure is that it can reduce the parasitic effects between the gate and source. Therefore, during fabrication, only the gate sidewall on the drain side can be tilted to reduce the peak electric field between the gate and drain, effectively improving the device breakdown voltage. Using a vertical sidewall structure between the gate and source reduces parasitic effects and is beneficial for improving the frequency characteristics of the device, allowing it to adapt to higher operating frequencies.

[0091] Secondly, embodiments of the present invention also provide a gate structure with an adjustable tilt angle, such as... Figure 14 As shown in the right figure, it was prepared using the first aspect of the method for preparing a tilt-adjustable gate structure.

[0092] It should be noted that conventional gate structures have excessively large sidewall tilt angles, resulting in poor metal filling and noticeable gaps. In contrast, gate structures with adjustable tilt angles have sidewall tilt angles of 60-70°, providing good metal filling and improving the quality of the gate metal stack.

[0093] To illustrate the performance of the tilt-adjustable grid structure provided by this invention, experimental data will be used as a reference.

[0094] like Figure 15 As shown, an adjustable-angle gate structure helps to improve the electric field accumulation effect below the gate, reduces the peak electric field on the bias drain side below the gate, and thus improves the breakdown voltage of the device. Figure 16 As shown, the breakdown voltage of GaN HEMT devices with adjustable gate tilt is significantly improved.

[0095] In a conventional rectangular vertical gate, the gate metal sidewall is perpendicular to the surface of the AlGaN barrier layer. The gate, source, and drain form a sharp right-angle boundary. According to the electrostatic field edge effect, the electric field will be highly concentrated at the sharp corner with minimal curvature, forming a peak electric field on the gate-drain side. The right-angle boundary cannot disperse the electric field stress, and the local electric field is much higher than the average electric field of the device.

[0096] A tilted gate refers to a sidewall with a gentle slope that transitions smoothly from the gate to the drain side, without any sharp right angles. The curvature of the right-angled gate corners approaches zero, resulting in a very high electric field concentration factor. The geometric curvature of the tilted slope is significantly increased, eliminating sharp vertices. The electric field strength is positively correlated with the boundary curvature. After the sharp corners disappear, the electric field that was originally concentrated at the gate-drain corner is spread out uniformly along the slope, directly weakening the local peak electric field.

[0097] When the gate is in the off state, it is connected to a negative voltage and the drain is connected to a high voltage. The vertical gate has a drastic change in potential at the gate-drain boundary. The inclined gate slope extends the lateral distance between the gate metal and the drain channel. The potential drops gently from the gate edge to the drain end. The electric field that was originally concentrated at the gate-drain corner is laterally distributed along the inclined sidewall and the barrier layer under the gate below, making the overall electric field distribution more uniform.

[0098] In addition, the tilt-adjustable gate structure in this invention exhibits low etching damage, making it suitable for thin-barrier GaNHEMT devices. For example... Figure 17 As shown, its surface roughness is significantly reduced and its flatness is high, which helps to reduce leakage current and improve the device's breakdown voltage. Secondly, as Figure 18 As shown, the mobility of this new device is improved compared to conventional gate structure devices, indicating that it has lower etching damage, significantly improved yield, and high device reliability.

[0099] Finally, the etching process of this invention causes the size of the tilt-adjustable gate structure to shrink inward, overturning the phenomenon that traditional etching processes cause the trench size to expand outward, such as... Figure 19 As shown, after the four-step etching method, the size of the gate trench is reduced from 50.8nm to 42.1nm, which is beneficial for further reducing the gate length of the RF GaN HEMT device and further improving its frequency characteristics.

[0100] In summary, the tilt-adjustable gate structure and its fabrication method proposed in this invention can overcome the limitations of photoresist thermal reflow technology in controlling the morphology of the groove and the difficulty in controlling the etching precision of the gate structure's groove. Simultaneously, it avoids the damage to the barrier layer surface caused by plasma bombardment in dry etching technology, while also taking into account the characteristics of avoiding damage to the barrier layer surface and ensuring sufficient subsequent metal filling by tilting the sidewalls, thereby improving the electrical performance of the gate structure.

[0101] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0102] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0103] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for fabricating a gate structure with adjustable tilt angle, characterized in that, Includes the following steps: S1. Obtain the structure to be etched, wherein the structure to be etched includes a barrier layer, a passivation layer and a photoresist layer stacked sequentially from bottom to top; S2. Photolithography is performed on the upper surface of the photoresist layer to obtain the first photoresist trench; S3. Pre-etching is performed in the area of ​​the first photoresist trench to remove part of the passivation layer and obtain a passivation layer trench; wherein, the distance between the bottom of the passivation layer trench and the surface of the adjacent barrier layer is a first distance; S4. Laterally shape the photoresist layer within the region of the first photoresist trench. Etching exposes the passivation layer plane to be etched on the side of the current passivation layer trench, thus obtaining a second photoresist trench. S5. Perform main etching in the area of ​​the second photoresist trench to remove part of the passivation layer, so that the distance between the bottom of the current passivation layer trench and the surface of the adjacent barrier layer is the second distance, and passivation layer steps are formed on the sidewall, wherein the second distance is less than the first distance. S6. Perform auxiliary etching in the area of ​​the current passivation layer trench to remove the bottom passivation layer, flatten the passivation layer step into a slope to form a gate trench, and modify the shape of the gate trench to smooth its sidewalls. S7. Perform gate photolithography and gate metal evaporation in the obtained gate trench to obtain a gate structure with inclined edges.

2. The method for fabricating a tilt-adjustable gate structure according to claim 1, characterized in that, Performing steps S4-S5 includes: Combine S4 and S5 into a loop unit and execute it a preset number of times; During each execution of the loop unit, the lateral width of the passivation layer plane to be etched in S4 remains the same, which is used to define equal-width steps on the sidewall of the passivation layer. In each execution of the loop unit, the amount of reduction of the second distance in S5 remains the same, which is used to etch out steps of equal depth within the passivation layer. After the loop unit completes the preset number of operations, the second distance is less than 10 nm.

3. The method for fabricating a tilt-adjustable gate structure according to claim 2, characterized in that, The preset number of times is monotonically related to the tilt angle of the inclined side of the gate structure.

4. The method for fabricating a tilt-adjustable gate structure according to claim 1, characterized in that, After obtaining the first photoresist trench, the process further includes: A mask is prepared and stacked on the photoresist layer, such that the mask is located on one side of the first photoresist trench to cover it, thereby obtaining a gate structure with one side tilted in step S7.

5. The method for fabricating a tilt-adjustable gate structure according to claim 1, characterized in that, The process conditions corresponding to step S3 include: The concentration is 80 sccm. The concentration was 20 sccm, the ICP power was 1000W, and the RF power was 150W.

6. The method for fabricating a tilt-adjustable gate structure according to claim 1, characterized in that, The process conditions corresponding to step S4 include: The concentration was 40 sccm, the ICP power was 200W, and the RF power was 25W.

7. The method for fabricating a tilt-adjustable gate structure according to claim 1, characterized in that, The process conditions corresponding to step S5 include: The concentration is 80 sccm. The concentration was 20 sccm, the ICP power was 1000W, and the RF power was 150W.

8. The method for fabricating a tilt-adjustable gate structure according to claim 3, characterized in that, The process conditions corresponding to step S6 include: The concentration was 40 sccm, the ICP power was 200W, and the RF power was 5W.

9. The method for fabricating a tilt-adjustable gate structure according to claim 1, characterized in that, When the barrier layer is not less than 10 nm, the corresponding process conditions for step S6 include: The concentration is 40 sccm. The concentration was 10 sccm, the ICP power was 200W, and the RF power was 5W.

10. A grid structure with adjustable tilt angle, characterized in that, It was prepared using the method for preparing the tilt-adjustable gate structure according to any one of claims 1-9.

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