A power module

Abstract

The application provides a power module, and belongs to the technical field of power module packaging. The power module comprises a first substrate, a second substrate, at least two semiconductor chips, and a connecting circuit board. The first surface of the second substrate is arranged opposite to the first surface of the first substrate. The at least two semiconductor chips comprise at least one first semiconductor chip arranged on the first surface of the first substrate and at least one second semiconductor chip arranged on the first surface of the second substrate. The connecting circuit board is located between the first substrate and the second substrate. The connecting circuit board comprises a third substrate and a wiring layer in the third substrate. The wiring layer comprises at least two conductive layers stacked in a first direction and insulated from each other. The connecting circuit board comprises a plurality of connectors. One end of each connector is connected to the wiring layer, and the other end of each connector is connected to at least one of the semiconductor chips, the first substrate and the second substrate. The technical scheme of the application can realize a double-sided interconnected power module and significantly reduce the parasitic inductance of the power module.

Description

Technical Field

[0001] This application relates to the field of power module packaging technology, and more particularly to a power module. Background Technology

[0002] With the development and application of third-generation semiconductor materials, silicon carbide power modules are continuously evolving towards higher voltage and higher frequency. However, during high-speed switching of these devices, the presence of parasitic inductance can cause significant voltage overshoot and increased oscillations, leading to performance degradation issues such as dynamic and static imbalances and uneven loss distribution. Therefore, effectively evaluating and optimizing parasitic inductance during the silicon carbide module design phase has become a crucial aspect of silicon carbide power module development.

[0003] In the field of double-sided interconnect power modules, current mainstream processes use bonding wires to achieve electrical interconnection on one side of the AMB (Active Metal Brazed Substrate) substrate, and then use metal blocks to achieve electrical interconnection with the AMB substrates on both sides. This approach not only results in higher parasitic inductance but also complicates the packaging process and significantly increases manufacturing difficulty. Therefore, there is an urgent need to provide an electrical interconnection packaging structure suitable for double-sided interconnect power modules to address the technical shortcomings of existing technologies in terms of both low parasitic inductance design and the complexity of double-sided interconnection processes. Summary of the Invention

[0004] This application provides a power module that enables bi-sided interconnection and significantly reduces the parasitic inductance of the power module.

[0005] To achieve the above objectives, the technical solution adopted in the embodiments of this application is as follows: A power module, comprising: First substrate; The second substrate has its first surface disposed opposite to the first surface of the first substrate; At least two semiconductor chips, including: at least one first semiconductor chip disposed on a first surface of a first substrate, and at least one second semiconductor chip disposed on a first surface of a second substrate; A connecting circuit board is located between a first substrate and a second substrate. The connecting circuit board includes a third substrate and a wiring layer located in the third substrate. The wiring layer includes at least two conductive layers stacked along a first direction, and adjacent conductive layers are insulated from each other. Multiple connectors, one end of which is connected to a wiring layer, and the other end of which is connected to at least one of a semiconductor chip, a first substrate, and a second substrate.

[0006] In some embodiments, the power module further includes: The first terminal and the second terminal are both connected to the wiring layer.

[0007] In some embodiments, a conductive channel is provided on the third substrate along the first direction, and the conductive channel realizes the electrical connection between the wiring layer and the connector.

[0008] In some embodiments, the connection position between the connector and the connecting circuit board is provided with a pad, and the pad is electrically connected to the conductive layer through a conductive channel.

[0009] In some embodiments, the conductive layer includes: a first conductive layer and a second conductive layer; The first conductive layer is connected to the first terminal, and the second conductive layer is connected to the second terminal.

[0010] In some embodiments, the cross-sectional area of ​​the connector connected to the first conductive layer is larger than the cross-sectional area of ​​the connector connected to the second conductive layer.

[0011] In some embodiments, the total cross-sectional area of ​​the connectors connected to the first conductive layer is greater than the total cross-sectional area of ​​the connectors connected to the second conductive layer; or, The connector is a solder ball, and the number of solder balls connected to the first conductive layer is greater than the number of solder balls connected to the second conductive layer.

[0012] In some embodiments, the first conductive layer includes at least: a first sub-conductive layer, a second sub-conductive layer, and a third sub-conductive layer; The second conductive layer includes at least: a first control conductive layer and a second control conductive layer; The first terminal includes: a DC negative terminal, a DC positive terminal, and an AC terminal. The DC negative terminal and the DC positive terminal are located at one end of the connecting circuit board, and the AC terminal is located at the other end of the connecting circuit board. The second terminal includes: a first control terminal and a second control terminal; The DC negative terminal is electrically connected to the first sub-conductive layer; The DC positive terminal is electrically connected to the conductive layer of the second substrate; The AC terminal is electrically connected to the third sub-conductive layer; The first control terminal is electrically connected to the first control conductive layer; The second control terminal is electrically connected to the second control conductive layer.

[0013] In some embodiments, the connector includes: First connector, second connector, third connector, fourth connector, fifth connector, sixth connector, seventh connector, eighth connector, ninth connector and tenth connector; The first connector electrically connects the first control conductive layer to the gate of the first semiconductor chip. The second connector electrically connects the first sub-conductive layer to the source of the first semiconductor chip; The third connector electrically connects the third sub-conductive layer to the first substrate. The fourth connector electrically connects the second control conductive layer to the gate of the second semiconductor chip; The fifth connector electrically connects the third sub-conductive layer to the source of the second semiconductor chip; The sixth connector electrically connects the second sub-conductive layer to the second substrate; The seventh connector electrically connects the DC negative terminal to the first sub-conductive layer; The eighth connector electrically connects the DC positive terminal to the second sub-conductive layer; The ninth connector electrically connects the AC terminal to the third sub-conductive layer; The tenth connector electrically connects the first control terminal to the first control conductive layer and the second control terminal to the second control conductive layer.

[0014] In some embodiments, the thickness of the first conductive layer is greater than the thickness of the second conductive layer; Alternatively, the product of the thickness and width of the first conductive layer is greater than the product of the thickness and width of the second conductive layer; Alternatively, the product of the thickness and width of the first sub-conductive layer, the product of the thickness and width of the second sub-conductive layer, and the product of the thickness and width of the third sub-conductive layer are equal and greater than the product of the thickness and width of the first control conductive layer and the product of the thickness and width of the second control conductive layer.

[0015] In some embodiments, the thickness of the first conductive layer is at least 2 oz.

[0016] The beneficial effects of this application are: In this embodiment, bidirectional electrical interconnection of semiconductor chips is achieved through the relative arrangement of the first and second substrates and the coordinated configuration of the connecting circuit board and connectors. This fundamentally optimizes the internal current topology of the power module. By connecting the semiconductor chip directly to the conductive layer through the connectors, a short-path connection is achieved. While avoiding the limitations of traditional bonding wires or clip arc height and cross-sectional area, the symmetrical arrangement of the double-sided current paths achieves mutual inductance cancellation, thereby effectively shortening the current loop length, reducing package parasitic inductance, reducing switching voltage overshoot and oscillation, and improving the dynamic and static reliability of the module. Attached Figure Description

[0017] Figure 1 One of the schematic diagrams illustrating a power module according to an embodiment of this application; Figure 2A second schematic diagram illustrating a power module according to an embodiment of this application; Figure 3 Schematic diagram three illustrating the power module according to an embodiment of this application; Figure 4 Fourth schematic diagram illustrating the power module according to an embodiment of this application; Figure 5 This is a schematic flowchart illustrating one of the methods for fabricating the power module in an embodiment of this application; Figure 6a This is the second schematic flowchart illustrating the method for fabricating the power module in an embodiment of this application. Figure 6b This is the third flowchart illustrating the method for fabricating the power module in this application. Figure 7 Fourth schematic flowchart illustrating the preparation method of the power module in the embodiments of this application; Figure 8 Fifth schematic diagram illustrating the process of fabricating the power module in this application embodiment; Figure 9 This is the sixth flowchart illustrating the fabrication method of the power module in this application embodiment; Figure 10 This is the seventh flowchart illustrating the fabrication method of the power module in this embodiment of the application; Figure 11 This is one of the schematic diagrams illustrating the ball-planting process in the fabrication method of the power module in the embodiments of this application; Figure 12 This is the eighth flowchart illustrating the method for fabricating the power module in this application. Figure 13 This is the second schematic diagram illustrating the ball-planting process in the power module fabrication method of this application embodiment; Figure 14 This is the ninth flowchart illustrating the fabrication method of the power module in this application embodiment; Figure 15 This is a schematic diagram illustrating one of the dispensing and filling operations in the preparation method of the power module in this application embodiment; Figure 16 This is the second schematic diagram illustrating the dispensing and filling operation in the preparation method of the power module in this application embodiment; Figure 17 This is the tenth flowchart illustrating the method for fabricating the power module in this application. Figure 18 This is 11, a schematic flowchart illustrating the fabrication method of the power module in an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the described embodiments of this application are within the scope of protection of this application.

[0019] To address the aforementioned technical problems, embodiments of this application provide a power module capable of achieving bi-sided interconnection and significantly reducing the parasitic inductance of the power module.

[0020] like Figures 1 to 4 As shown, this application embodiment provides a power module, including: a first substrate 1, a second substrate 2, at least two semiconductor chips, a connecting circuit board 5, and multiple connectors 6. The first substrate 1, the second substrate 2, the at least two semiconductor chips, the connecting circuit board 5, and the multiple connectors 6 constitute the power module.

[0021] For example, the first substrate 1 and the second substrate 2 include AMB substrate, DBC substrate (Direct Bonding Copper), DBA substrate (Direct Bonding Aluminum), IMS substrate (Insulated Metal Substrate), LTCC substrate (Low Temperature Co-fired Ceramic Substrate), composite material substrate (such as AlSiC substrate, glass ceramic substrate), etc.

[0022] Semiconductor chips can be power semiconductor chips, such as power Si or SiC power MOSFET (metal-oxide-semiconductor field-effect transistor) chips, HEMT (high electron mobility transistor) chips, IGBT (insulated gate bipolar transistor) chips, JFET (junction field-effect transistor) chips, thyristors (such as GTO thyristors), and auxiliary function chips (such as sensor chips), etc. The type of chip selected varies depending on the application scenario of the packaging structure.

[0023] like Figures 1 to 4 As shown, the thickness direction (Y direction) of the connecting circuit board 5 is defined as the first direction, the length direction (X direction) of the connecting circuit board 5 is defined as the second direction, and the width direction (Z direction) of the connecting circuit board 5 is defined as the third direction.

[0024] like Figure 1 and Figure 2As shown, in some embodiments, the first surface 201 of the second substrate 2 is disposed opposite to the first surface 101 of the first substrate 1.

[0025] In some specific examples, the second substrate 2 and the first substrate 1 are arranged symmetrically along a first direction. Here, it is used as... Figure 1 For example, the first direction can be the thickness direction of the connecting circuit board 5, that is, the direction perpendicular to the plane formed by the length and width directions of the connecting circuit board 5.

[0026] For example, the first substrate 1 and the second substrate 2 include a first metal layer, a first insulating layer and a second metal layer stacked together. The first metal layer is located on a first surface of the first insulating layer, and the first metal layer is printed to form a circuit structure. The first semiconductor chip 3 is located on the first metal layer of the first substrate 1. The second metal layer is located on a second surface of the first insulating layer, and the second semiconductor chip 4 is located on the first metal layer of the second substrate 1.

[0027] Each of the first and second metal layers may include one of the following materials: copper, copper alloy, aluminum, aluminum alloy, or other metals or alloys. The first insulating layer may be a ceramic layer, which may include one of the following materials: alumina, aluminum nitride, zirconium oxide, silicon nitride, boron nitride, or any other dielectric ceramic.

[0028] The at least two semiconductor chips include: at least one first semiconductor chip 3 disposed on the first surface 101 of the first substrate 1, and at least one second semiconductor chip 4 disposed on the first surface 201 of the second substrate 2.

[0029] In this process, at least one first semiconductor chip 3 can be a single chip or multiple chips connected in parallel; similarly, at least one second semiconductor chip 4 can be a single chip or multiple chips connected in parallel.

[0030] It is understood that in some embodiments, since a connecting circuit board 5 needs to realize electrical interconnection between multiple semiconductor chips, the size of the connecting circuit board 5 is large, and the projection of the electrodes of all semiconductor chips on the first surface of the connecting circuit board 5 falls inside the first surface of the connecting circuit board 5.

[0031] See Figure 1 and Figure 2 An adhesive layer 11 is provided on the first surface 101 of the first substrate 1, which connects the first substrate 1 and the first semiconductor chip 3; an adhesive layer 11 is also provided on the first surface 201 of the second substrate 2, which connects the second substrate 2 and the second semiconductor chip 4. For example, the adhesive layer 11 can be a welding material (e.g., solder paste) or a sintering material (e.g., silver sintering), or other conductive layers that can achieve adhesion.

[0032] The connecting circuit board 5 is located between the first substrate 1 and the second substrate 2. The connecting circuit board 5 includes a third substrate 501 and a wiring layer located in the third substrate 501. The wiring layer includes at least two conductive layers stacked along a first direction, and adjacent conductive layers are insulated from each other.

[0033] Specifically, the connecting circuit board 5 can be an interposer. For example, the connecting circuit board 5 includes a multilayer PCB substrate (copper-clad laminate), a TSV substrate (through silicon via substrate), or a TGV substrate (through glass via substrate). In other words, the material of the connecting circuit board 5 can be selected from PCB substrate, TSV substrate, or TGV substrate to flexibly adapt to different operating conditions, allowing users to choose the optimal solution based on environmental requirements.

[0034] One end of a plurality of connectors 6 is connected to a wiring layer, and the other end is connected to at least one of a semiconductor chip, a first substrate 1, and a second substrate 2.

[0035] In this context, among the multiple conductive layers in the wiring layer, the same conductive layer is connected to an electrode (the electrode of the semiconductor chip) that has the same function. For example, two electrodes with the same function mean that both electrodes are gate electrodes or both are source electrodes.

[0036] In some examples, such as Figure 1 and Figure 3 As shown, connector 6 is spherical, meaning connector 6 is a solder ball; in other examples, such as Figure 2 and Figure 4 As shown, connector 6 is block-shaped, meaning it is either a pad or a weld block. This is understandable. Figures 1 to 4 The shape of the connecting member 6 is merely an illustrative example, and the embodiments of this application are not limited thereto.

[0037] In this embodiment, the symmetrical arrangement of the first substrate 1 and the second substrate 2, along with the coordinated configuration of the connecting circuit board 5 and the connector 6, enables bidirectional electrical interconnection of the semiconductor chip, fundamentally optimizing the internal current topology of the power module. The connector 6 directly connects the semiconductor chip to the conductive layer via a short path, avoiding the limitations of traditional bonding wires or clip arc height and cross-sectional area. The symmetrical arrangement of the double-sided current path achieves mutual inductance cancellation, thereby effectively shortening the current loop length, reducing package parasitic inductance, reducing switching voltage overshoot and oscillation, and improving the dynamic and static reliability of the module.

[0038] In some embodiments, the power module further includes a first terminal 7 and a second terminal 8, both of which are connected to the wiring layer.

[0039] For example, the first terminal 7 is a power terminal and the second terminal 8 is a control terminal (or drive terminal).

[0040] like Figure 1 As shown, the area of ​​the connecting circuit board 5 is relatively large. The first substrate 1 and the second substrate 2 only occupy a part of the area of ​​the connecting circuit board 5. The extended part of the connecting circuit board 5 can be used to connect the first terminal 7 and the second terminal 8.

[0041] exist Figure 1 and Figure 2 In the example shown, the first terminal 7 and the second terminal 8 are located on opposite sides of the connecting circuit board 5. It is understandable that... Figure 1 and Figure 2 The positional relationship between the first terminal 7, the second terminal 8, and the connecting circuit board 5 is merely one example of the embodiments of this application, and the embodiments of this application are not limited thereto. In other examples, the first terminal 7 and the second terminal 8 may also be located on the same side of the connecting circuit board 5. For example, both may be located on the side of the connecting circuit board 5 facing the first substrate 1, or both may be located on the side of the connecting circuit board 5 facing the second substrate 2.

[0042] The connector 6 in this embodiment can also be used to connect the wiring layer of the connecting circuit board 5 to the first terminal 7 and the second terminal 8.

[0043] In this embodiment, the connection between the first terminal 7, the second terminal 8 and the wiring layer of the connecting circuit board 5 simplifies the terminal connection process, shortens the power module assembly cycle, and facilitates the later maintenance and replacement of the terminals, thereby effectively extending the overall service life of the power module.

[0044] like Figures 1 to 4 As shown, in some embodiments, the third substrate 501 is provided with a conductive channel 502 along the first direction, and the conductive channel 502 realizes the electrical connection between the wiring layer and the connector 6.

[0045] It should be noted that in the power module of this application embodiment, the semiconductor chip is interconnected with the first substrate 1 and the second substrate 2 through a connecting circuit board 5. Along the first direction, the connecting circuit board 5 includes multiple layers of conductive layers and multiple layers of insulating layers stacked alternately, as well as multiple conductive channels. The connections between different conductive layers and the semiconductor chip, the first substrate 1, and the second substrate are different. For example, one conductive layer is completely electrically connected to the semiconductor chip, and another conductive layer is completely electrically connected to the first substrate 1. Different conductive channels realize the electrical connection between the conductive layer and different connectors 6, thereby achieving vertical electrical isolation and low-inductive interconnection between the semiconductor chip side and the first substrate 1 side and the second substrate 2 side within the same physical cross section.

[0046] In some embodiments, an insulating layer is provided between adjacent conductive layers inside the connecting circuit board 5. At least one through-hole is formed in the insulating layer, and the through-hole is filled with a conductive medium to form a conductive channel 502. The conductive channel 502 can connect different conductive layers. For example, the conductive medium can specifically be copper paste. Thus, by using copper paste as the conductive medium to fill the through-hole and form the conductive channel 502, the copper paste can completely fill the through-hole and connect with different conductive layers of the connecting circuit board 5, thereby achieving connection between different conductive layers.

[0047] It should be noted that the number and area of ​​vias (also known as through-holes) on the insulating layer can be set according to actual needs. In some examples, the larger the cross-sectional area of ​​the via, the higher the conductivity reliability; however, a larger cross-sectional area of ​​the via will occupy space on the connecting circuit board. To balance conductivity reliability and space utilization, the diameter of the via can range from 0.1 mm to 0.2 mm. In addition, for high-current operating conditions, the vertical conduction cross-sectional area can be increased by increasing the number of vias to distribute the current load and match the electrical parameters of high-current operating conditions. For example, the vias on the same layer are arranged in at least one of linear or matrix arrangements, with a via spacing ≥ 0.2 mm.

[0048] In this embodiment, the electrodes of the semiconductor chip can be connected to the conductive layer inside the connecting circuit board 5 through the connector 6 and the conductive channel 502, and the different conductive layers inside the connecting circuit board 5 are connected through the conductive channel 502. In this way, electrical interconnection between the semiconductor chips on both sides (i.e., the first semiconductor chip 3 and the second semiconductor chip 4) can be realized.

[0049] It should be noted that the electrodes and terminals (including the first terminal 7 and the second terminal 8) of the semiconductor chip in this embodiment are all connected to the connecting circuit board 5, and the connection between the electrodes and terminals is achieved through the conductive layer (such as copper traces) inside the connecting circuit board 5.

[0050] The connection method of the connecting circuit board in the above embodiments can optimize the wiring in the power module and realize the reverse distribution of the current in the commutation circuit to achieve mutual inductance cancellation, thereby effectively reducing parasitic inductance.

[0051] like Figure 3 and Figure 4 As shown, in some embodiments, the connection position between the connector 6 and the connecting circuit board 5 is provided with a pad 9, and the pad 9 is electrically connected to the conductive layer through a conductive channel 502.

[0052] It should be noted that multiple pads 9 can be formed on the surface of the connecting circuit board 5 by a deposition process. Each pad 9 is connected to at least one conductive channel 502 in the connecting circuit board 5, and each pad 9 is electrically connected to only one corresponding conductive layer via the conductive channel 502.

[0053] For example, the material of connector 6 can be tin. For instance, connector 6 can specifically be a solder ball or a solder block.

[0054] See Figure 1 and Figure 2 In some embodiments, the conductive layer includes a first conductive layer 503 and a second conductive layer 504; wherein the first conductive layer 503 is connected to the first terminal 7, and the second conductive layer 504 is connected to the second terminal 8.

[0055] It should be noted that the connecting circuit board 5 in this embodiment has a multi-layer structure. The first conductive layer 503 and the second conductive layer 504 in this embodiment are only one example. In actual production, two or more conductive layers can be set according to requirements.

[0056] In some specific examples, such as Figure 1 and Figure 2 As shown, in the thickness direction of the connecting circuit board 5, the first conductive layer 503 and the second conductive layer 504 can be located in different layers, and the different layers are insulated from each other. This allows the width of the first conductive layer 503 and the second conductive layer 504 to be increased in the width direction of the connecting circuit board 5, thereby increasing the current carrying capacity of the first conductive layer 503 and the second conductive layer 504.

[0057] It is understandable that in other examples, the first conductive layer 503 and the second conductive layer 504 may also be located on the same layer in the thickness direction of the connecting circuit board 5 and be insulated from each other in the width direction of the connecting circuit board 5, thereby effectively reducing the thickness of the connecting circuit board 5 and thus reducing the overall thickness of the power module.

[0058] In this embodiment, the layered design of the first conductive layer 503 and the second conductive layer 504 corresponds to the electrode connections of the first semiconductor chip 3 and the second semiconductor chip 4, respectively. This can improve the flexibility of the internal wiring of the connection circuit board 5, optimize the interconnection path length for different semiconductor chip layouts, thereby further optimizing the parasitic inductance distribution, facilitating the expansion of multiple modules, and improving the versatility and scalability of the packaging structure.

[0059] In some embodiments, the cross-sectional area of ​​the connector 6 connected to the first conductive layer 503 is larger than the cross-sectional area of ​​the connector 6 connected to the second conductive layer 504.

[0060] It should also be noted that in some embodiments, the size of the connector 6 is configured according to the size of the object being connected. For example, the diameter of the connector is proportional to the size of the object being connected.

[0061] It should be noted that, within the same package volume, by optimizing the size distribution of the connector 6 (that is, by setting different sizes of connector 6 according to the position distribution of different connected objects, the electrical interconnection of electrodes with different functions such as gate, drain, and source can be realized simultaneously, thereby optimizing the packaging process and reducing production costs.

[0062] Furthermore, in this embodiment, the connector 6 connected to the semiconductor chip and the connector 6 connected to the terminal have different sizes. This differentiated size design of the connector 6 allows for better adaptation to different application scenarios. For example, connectors 6 of different sizes can also be set according to the different distances between the connected object and the connecting circuit board 5.

[0063] In some embodiments, the total cross-sectional area of ​​the connectors connected to the first conductive layer is greater than the total cross-sectional area of ​​the connectors connected to the second conductive layer.

[0064] Or, such as Figure 3 As shown, in some other embodiments, the connector 6 can be a solder ball, in which the number of solder balls connected to the first conductive layer 503 is greater than the number of solder balls connected to the second conductive layer 504.

[0065] Here, the solder balls connected to the second conductive layer 504 do not need to carry a large current. Therefore, the number of solder balls connected to the second conductive layer 504 does not need to be too many. That is, the number of solder balls connected to the second conductive layer 504 is less than the number of solder balls connected to the first conductive layer 503.

[0066] It should be noted that the connection stability of the larger-sized connector 6 is better than that of the smaller-sized connector 6. Therefore, within the limits of implementation conditions, the size of the connector 6 should be increased as much as possible to increase the contact area and thus achieve a better connection effect.

[0067] Here, the multiple connectors 6 can be ball grid array (BGA) solder balls, which can be used to realize the soldering interconnection of the source, drain and gate of the semiconductor chip.

[0068] It should be noted that the position and number of connectors 6 can be set according to the area and layout of the source, drain, and gate of each semiconductor chip. This is understandable. Figures 1 to 4 The number and distribution of the connecting parts 6 are merely examples, and the embodiments of this application are not limited thereto.

[0069] It should also be noted that the connectors 6 connected to different conductive layers do not make contact with each other. For example, short circuits between the connectors 6 connected to different conductive layers can also be prevented by filling the spaces between them with insulating material.

[0070] See Figures 1 to 4 Conductive channels are used to achieve electrical connections between different conductive structures. The diameter of the conductive channel should be as large as possible, provided that the diameter of the conductive channel does not exceed the diameter of the corresponding solder ball it is connected to, in order to increase the conductor cross-sectional area of ​​the interconnection path and improve the current carrying capacity of the conductive channel. In addition, the conductor cross-sectional area of ​​the interconnection path can also be increased by increasing the number of conductive channels.

[0071] like Figure 1 and Figure 2 In the illustrated embodiment, the first semiconductor chip 3 and the second semiconductor chip 4 can belong to the upper arm of the power module, the first terminal 7 can be an AC terminal (i.e., alternating current terminal), and the drains of the first semiconductor chip 3 and the second semiconductor chip 4 are connected to the DC+ terminal (i.e., the positive DC terminal) through the first substrate 1 and the second substrate 2. Alternatively, the first semiconductor chip 3 and the second semiconductor chip 4 can belong to the lower arm of the power module, the first terminal 7 can be a DC- terminal (i.e., the negative DC terminal), and the drains of the first semiconductor chip 3 and the second semiconductor chip 4 are connected to the AC terminal through the first substrate 1 and the second substrate 2. Upper and lower arms with similar layouts can be combined to form a complete half-bridge or three-phase power module.

[0072] like Figure 3 and Figure 4 As shown, in some embodiments, the first conductive layer 503 includes at least: a first sub-conductive layer 5031, a second sub-conductive layer 5032 and a third sub-conductive layer 5033; the second conductive layer 504 includes at least: a first control conductive layer 5041 and a second control conductive layer 5042.

[0073] The first terminal 7 includes: a DC negative terminal 701, a DC positive terminal 702, and an AC terminal 703. The DC negative terminal 701 and the DC positive terminal 702 are disposed at one end of the connecting circuit board 5, and the AC terminal 703 is disposed at the other end of the connecting circuit board 5. The second terminal 8 includes: a first control terminal and a second control terminal.

[0074] Among them, the DC negative terminal 701 is electrically connected to the first sub-conductive layer 5031; The DC positive terminal 702 is electrically connected to the conductive layer of the second substrate 2; AC terminal 703 is electrically connected to the third sub-conductive layer 5033; The first control terminal is electrically connected to the first control conductive layer 5041; The second control terminal is electrically connected to the second control conductive layer 5042.

[0075] It should be noted that, Figure 3 and Figure 4 In this embodiment, the positions of the first terminals 7 and the second terminals 8 are merely illustrative examples, and the embodiments of this application are not limited thereto. For example, in other embodiments, the DC negative terminal 701 and the DC positive terminal 702 may also be located on the same side of the connecting circuit board 5, and they may also be disposed on the end of the connecting circuit board 5 where the AC terminal 703 is provided. These will not be described in detail here.

[0076] In some specific examples, such as Figure 3 and Figure 4 As shown, in the thickness direction of the connecting circuit board 5, the first sub-conductive layer 5031, the second sub-conductive layer 5032, and the third sub-conductive layer 5033 can be located in different layers, thereby increasing the width of the first sub-conductive layer 5031, the second sub-conductive layer 5032, and the third sub-conductive layer 5033 in the width direction of the connecting circuit board 5, and increasing the current carrying capacity of the first sub-conductive layer 5031, the second sub-conductive layer 5032, and the third sub-conductive layer 5033.

[0077] It is understandable that in other examples, the first sub-conductive layer 5031, the second sub-conductive layer 5032, and the third sub-conductive layer 5033 may also be located on the same layer in the thickness direction of the connecting circuit board 5 and be insulated from each other in the width direction of the connecting circuit board 5, thereby effectively reducing the thickness of the connecting circuit board 5 and thus reducing the overall thickness of the power module.

[0078] In some specific examples, such as Figure 3 and Figure 4As shown, in the thickness direction of the connecting circuit board 5, the first control conductive layer 5041 and the second control conductive layer 5042 can be located in different layers. In the thickness direction of the connecting circuit board 5, the first control conductive layer 5041 and the second control conductive layer 5042 are mutually insulated from each other, and are also mutually insulated from the first sub-conductive layer 5031, the second sub-conductive layer 5032 and the third sub-conductive layer 5033. The independent first control conductive layer 5041 and the second control conductive layer 5042 can improve the wiring flexibility of the control conductive layer and improve the flexibility of design and manufacturing.

[0079] It is understandable that in other examples, the first control conductive layer 5041 and the second control conductive layer 5042 may also be located on the same layer in the thickness direction of the connecting circuit board 5 and be insulated from each other in the width direction of the connecting circuit board 5, and insulated from each other in the thickness direction of the connecting circuit board 5 and the first sub-conductive layer 5031, the second sub-conductive layer 5032 and the third sub-conductive layer 5033.

[0080] In some examples, the first sub-conductive layer 5031, the second sub-conductive layer 5032, the third sub-conductive layer 5033, the first control conductive layer 5041, and the second control conductive layer 5042 can also be located on the same layer in the thickness direction of the connecting circuit board 5, and are insulated from each other in the width direction of the connecting circuit board 5. Arranging the conductive layers on the same layer can reduce the number of conductive layers, reduce the complexity of the connecting circuit board 5, and reduce the manufacturing difficulty of the connecting circuit board 5.

[0081] like Figure 3 and Figure 4 As shown, in some embodiments, the connector 6 includes: a first connector 601, a second connector 602, a third connector 603, a fourth connector 604, a fifth connector 605, a sixth connector 606, a seventh connector 607, an eighth connector 608, a ninth connector 609, and a tenth connector 610.

[0082] The first connector 601 electrically connects the first control conductive layer 5041 to the gate of the first semiconductor chip 3. The second connector 602 electrically connects the first sub-conductive layer 5031 to the source of the first semiconductor chip 3; The third connector 603 electrically connects the third sub-conductive layer 5033 to the first substrate 1. The fourth connector 604 electrically connects the second control conductive layer 5042 to the gate of the second semiconductor chip 4; The fifth connector 605 electrically connects the third sub-conductive layer 5033 to the source of the second semiconductor chip 4; The sixth connector 606 electrically connects the second sub-conductive layer 5032 to the second substrate 2; The seventh connector 607 electrically connects the DC negative terminal 701 to the first sub-conductive layer 5031; The eighth connector 608 electrically connects the DC positive terminal 702 to the second sub-conductive layer 5032; The ninth connector 609 electrically connects the AC terminal 703 to the third sub-conductive layer 5033; The tenth connector 610 electrically connects the first control terminal to the first control conductive layer 5041 and the second control terminal to the second control conductive layer 5042.

[0083] Here, the number of tenth connectors 610 is at least two, wherein at least one tenth connector 610 electrically connects the first control terminal to the first control conductive layer 5041, and at least one tenth connector 610 electrically connects the second control terminal to the second control conductive layer 5042.

[0084] It should be noted that, Figure 2 and Figure 4 The diagram schematically illustrates the case where connector 6 is a spacer or weld block. It is understood that connector 6 in the form of a spacer or weld block can specifically be a combination of multiple spacers or weld blocks, for example... Figure 2 and Figure 4 The second connector 602 and the fifth connector 605 can specifically be a combination of multiple pads or welding blocks.

[0085] See Figure 3 and Figure 4 Specifically, the DC negative terminal 701 is electrically connected to the source of the first semiconductor chip 3 via the seventh connector 607, conductive channel 502, first sub-conductive layer 5031, and second connector 602; the DC positive terminal 702 is electrically connected to the drain of the second semiconductor chip 4 via the eighth connector 608, conductive channel 502, second sub-conductive layer 5032, sixth connector 606, and second substrate 2; the AC terminal 703 is electrically connected to the source of the second semiconductor chip 4 via the ninth connector 609, conductive channel 502, third sub-conductive layer 5033, and fifth connector 605; The current terminal 703 is electrically connected to the drain of the first semiconductor chip 3 via the ninth connector 609, conductive channel 502, third sub-conductive layer 5033, third connector 603, and first substrate 1; the first control terminal in the second terminal 8 is electrically connected to the gate of the first semiconductor chip 3 via the tenth connector 610, first control conductive layer 5041, conductive channel 502, and first connector 601; the second control terminal in the second terminal 8 is electrically connected to the gate of the second semiconductor chip 4 via the tenth connector 610, conductive channel 502, second control conductive layer 5042, and fourth connector 604.

[0086] In some embodiments, the thickness of the first conductive layer 503 is greater than the thickness of the second conductive layer 504; or, the product of the thickness and width of the first conductive layer 503 is greater than the product of the thickness and width of the second conductive layer 504; or, the product of the thickness and width of the first sub-conductive layer 5031, the product of the thickness and width of the second sub-conductive layer 5032, and the product of the thickness and width of the third sub-conductive layer 5033 are equal and greater than the product of the thickness and width of the first control conductive layer and the product of the thickness and width of the second control conductive layer.

[0087] In this embodiment, the first conductive layer 503 is electrically connected to the source and drain of the semiconductor chip, and the second conductive layer 504 is electrically connected to the gate of the semiconductor chip 140. Since the current carried by the source and drain of the semiconductor chip 140 is greater than that of the gate, higher current carrying capacity and lower on-resistance are required. By increasing the thickness of the first conductive layer 503 or increasing its cross-sectional area (i.e., the product of thickness and width), the skin effect loss during high-frequency current flow can be effectively reduced, while simultaneously improving the heat dissipation efficiency of the conductive layer. When the thicknesses of the first conductive layer 503 and the second conductive layer 504 are the same, the manufacturing process of the adapter board 170 can be simplified, reducing interlayer impedance differences. When the product of their areas and thicknesses is equal, material utilization can be optimized while maintaining the same current density, avoiding localized overheating. This differentiated design satisfies the high current requirements of the main current paths (such as the drain and source) in the power module while also taking into account the refined spatial layout requirements of the control signal paths (such as the gate). Similarly, in some examples, the cross-sectional area of ​​the conductive channel 502 and the connector 6 matches the current-carrying capacity of the corresponding conductive layer in the wiring layer; in other examples, the number of conductive channels 502 and connectors 6 matches the current-carrying capacity of the corresponding conductive layer in the wiring layer. It is understandable that both the cross-sectional area and the number of conductive channels 502 and connectors 6 could match the current-carrying capacity of the corresponding conductive layer in the wiring layer.

[0088] like Figure 3 and Figure 4 In the illustrated embodiment, the first semiconductor chip 3 belongs to the upper bridge arm, and the second semiconductor chip 4 belongs to the lower bridge arm. The first semiconductor chip 3 and the second semiconductor chip 4 can form a complete half-bridge power module. Multiple first semiconductor chips 3 and second semiconductor chips 4 can be connected in parallel to increase current carrying capacity.

[0089] In some embodiments, a three-phase power module can be formed by combining three sets of half-bridges consisting of one or more parallel-connected first semiconductor chips 3 and second semiconductor chips 4.

[0090] In some embodiments, the thickness of the first conductive layer 503 is at least 2 oz.

[0091] Here, "oz" can be used to represent the thickness of copper foil, which is defined as the thickness of copper foil weighing 1 ounce when the area of ​​1 square foot is 1 ounce. 1 oz copper foil ≈ 35 micrometers (μm).

[0092] It should be noted that, in order to match the high voltage and high current operating conditions of the power port of the power module, the copper thickness of the conductive layer (or conductor layer) connected to the drain and source of the semiconductor chip should be in the range of 2 oz to 5 oz. That is to say, the copper thickness of this type of conductive layer is at least 2 oz and at most 5 oz, for example, 2 oz, 3 oz, 4 oz, 5 oz, etc.

[0093] In some specific embodiments, the conductive layer in the connecting circuit board 5 may be made of copper, or the conductive layer of the connecting circuit board 5 may be made of copper foil.

[0094] It should be noted that, within the connecting circuit board 5, while meeting insulation requirements, the conductive layer area, excluding the areas occupied by conductive channels and pads, should be filled as much as possible in the form of a continuous conductive layer to cover the remaining space. This allows for uniform distribution of high-frequency current within the layer and maximizes the effective cross-sectional area, thereby minimizing copper losses and temperature rise. Simultaneously, the mirror plane formed by the continuous conductive layer can shield the internal electric field, reducing interlayer capacitive coupling noise and suppressing common-mode electromagnetic emissions through a low-impedance return path. Specifically, the continuous conductive layer retains a predetermined width of annular isolation band near the conductive channel to avoid sharp-angle electric field concentration with the sidewall plating of the conductive channel, thus balancing insulation reliability and conductive layer fill rate. The large cross-sectional area of ​​the conductive channel increases the conductor area of ​​the interconnect path, significantly improving the current-carrying capacity of the conductive channel.

[0095] In this embodiment, by configuring the copper thickness of the conductive layer electrically connected to the semiconductor chip electrode to be at least 2 oz (approximately 70 μm), the high voltage and high current requirements of the power port of the power module can be met.

[0096] In some embodiments, electrodes with the same function in different semiconductor chips belonging to the same bridge arm are connected to the same conductive layer.

[0097] For example, in each semiconductor chip belonging to the same bridge arm, their gates are all connected to the same conductive layer of the connecting circuit board 5.

[0098] like Figure 3 As shown, one or more first semiconductor chips 3 belong to the lower bridge arm, and one or more second semiconductor chips 4 belong to the upper bridge arm. Multiple second connectors 602 can connect to the sources of different first semiconductor chips 3, and the sources of different first semiconductor chips 3 are all electrically connected to the first sub-conductive layer 5031 of the connecting circuit board 5.

[0099] In this embodiment, connecting electrodes of the same type (or function) from different semiconductor chips in the same bridge arm to the same conductive layer ensures the symmetry and balance of electrical parameters within the power circuit of the power module, avoids uneven current distribution due to path differences, and effectively reduces the risk of local overheating. Furthermore, it simplifies the wiring complexity in the power module and improves its reliability.

[0100] like Figure 1 and Figure 2 As shown, in some embodiments, the power module further includes a molding compound 10 that encapsulates the first substrate 1, the second substrate 2, the semiconductor chip, the connecting circuit board 5, and the connector 6. Exemplarily, the molding compound 10 can be formed using an underfill method. The materials of the molding compound 10 include epoxy molding compound (EMC), cyanate ester resin-based molding compound, polyimide (PI) resin-based molding compound, ceramic-filled modified resin-based molding compound, etc. These materials can provide better support for the connecting circuit board 5.

[0101] Specifically, when forming the encapsulated body 10 using the bottom filling method, the power module completed in the aforementioned steps is placed into the mold cavity, and then liquid encapsulation material is poured into the mold cavity. The encapsulation material is ensured to fully wet and cover the side surface of the first substrate 1 and the remaining exposed first surface 101, the side surface of the second substrate 2 and the remaining exposed first surface 201, the side surface of the semiconductor chip and the remaining exposed first surface, the connector 6, all side surfaces, the upper surface and the lower surface of the connecting circuit board 5, and after ensuring that there are no air bubbles in the encapsulation material, the encapsulation material is cured and demolded.

[0102] In this embodiment, in order to ensure structural strength, epoxy resin molding can be used to achieve external insulation encapsulation, encapsulating the electrical components of the power module within the molding body 10 to achieve overall protection.

[0103] In this embodiment, the bidirectional electrical interconnection of semiconductor chips is achieved through the relative arrangement of the first substrate 1 and the second substrate 2, and the coordinated configuration of the connecting circuit board 5 and the connector 6. This fundamentally optimizes the internal current topology of the power module. The semiconductor chip is directly connected to the conductive layer via the connector 6, achieving a short-path connection. While avoiding the limitations of traditional bonding wires or clip arc height and cross-sectional area, the symmetrical arrangement of the double-sided current path achieves mutual inductance cancellation, thereby effectively shortening the current loop length, reducing package parasitic inductance, reducing switching voltage overshoot and oscillation, and improving the dynamic and static reliability of the module.

[0104] like Figure 5 As shown in the embodiment of this application, a method for fabricating a power module includes: Step S51: Provide a first substrate 1 and a second substrate 2, and arrange the first surface 101 of the first substrate 1 and the first surface 201 of the second substrate 2 opposite to each other, wherein the first surface 101 of the first substrate 1 is provided with a first semiconductor chip 3, and the first surface 201 of the second substrate 2 is provided with a second semiconductor chip 4.

[0105] The fabrication method in this embodiment begins with a first substrate 1 on which a first semiconductor chip 3 is mounted and a second substrate 2 on which a second semiconductor chip 4 is mounted. Taking the first substrate 1 as an example, the step of mounting the semiconductor chip on the first substrate 1 includes: printing or coating an appropriate amount of adhesive layer 11 (such as...) on the first surface 101 of the first substrate 1. Figure 1 As shown, a semiconductor chip is placed on the first substrate 1, with the pins of the semiconductor chip aligned with a predetermined area on the first substrate 1. Then, the semiconductor chip is fixed to the first substrate 1 through curing or other processes. It is understood that the steps for mounting the semiconductor chip on the second substrate 2 are similar to those for the first substrate 1, and will not be described in detail here.

[0106] Here, the number of semiconductor chips can be determined based on actual needs.

[0107] Step S52: Provide a connecting circuit board 5 and place the connecting circuit board 5 between the first substrate 1 and the second substrate 2.

[0108] Here, the connecting circuit board 5 matches the structure described in step 11 above. Please refer to... Figure 1 and Figure 2 The connecting circuit board 5 includes a third substrate 501 and a wiring layer located in the third substrate 501. The wiring layer includes at least two conductive layers stacked along a first direction, with adjacent conductive layers being insulated from each other.

[0109] Step S53: Place multiple connectors 6 between the connecting circuit board 5 and the first substrate 1 and the second substrate 2 respectively.

[0110] In step S54, the connector 6 is soldered to the connecting circuit board 5, the first substrate 1, the second substrate 2, the first semiconductor chip 3, and the second semiconductor chip 4, so that the first semiconductor chip 3 is electrically connected to the connecting circuit board 5 and the first substrate 1, and the second semiconductor chip 4 is electrically connected to the connecting circuit board 5 and the second substrate 2.

[0111] It is understood that the execution order in this embodiment is only an optional example. In other embodiments, the connecting circuit board 5 can be placed first, and then the first substrate 1 and the second substrate 2 can be respectively placed on both sides of the connecting circuit board 5, with the first surface 101 of the first substrate 1 and the first surface 201 of the second substrate 2 facing each other. The execution order of this application embodiment is not limited to this.

[0112] like Figure 6a As shown, in some embodiments, step S54, which involves soldering the connector 6 to the connecting circuit board 5, the first substrate 1, the second substrate 2, the first semiconductor chip 3, and the second semiconductor chip 4, may involve first placing the connector 6 on the connecting circuit board 5, including the following steps: Step S61: Place the connector 6 on the connecting circuit board 5.

[0113] In this step, flux or other conductive adhesive layers are formed in corresponding areas on both sides of the connecting circuit board 5. The connector 6 is placed in corresponding positions on both sides of the connecting circuit board 5, and the connector 6 is fixedly connected to the connecting circuit board 5 through processes such as reflow soldering.

[0114] like Figure 7 As shown, in some embodiments, step S61, placing the connector 6 on the connecting circuit board 5, may include the following steps: Step S71: Place the first connector 601 in the first soldering area of ​​the connecting circuit board 5, and place the second connector 602 in the second soldering area of ​​the connecting circuit board 5. Align the first connector 601 and the second connector 602 with the soldering area of ​​the first semiconductor chip 3 for soldering the first semiconductor chip 3 to the connecting circuit board 5.

[0115] In step S72, the fourth connector 604 is placed in the fourth soldering area of ​​the connecting circuit board 5, and the fifth connector 605 is placed in the fifth soldering area of ​​the connecting circuit board 5. The fourth connector 604 and the fifth connector 605 are aligned with the soldering area of ​​the second semiconductor chip 4 for soldering the second semiconductor chip 4 to the connecting circuit board 5.

[0116] like Figure 8 As shown, in some embodiments, step S61, placing the connector 6 on the connecting circuit board 5, may further include the following steps: Step S81: Place the third connector 603 in the third soldering area of ​​the connecting circuit board 5. Align the third connector 603 with the soldering area of ​​the first substrate 1 for soldering the first substrate 1 and the connecting circuit board 5.

[0117] Step S82: Place the sixth connector 606 in the sixth soldering area of ​​the connecting circuit board 5. Align the sixth connector 606 with the soldering area of ​​the second substrate 2 for soldering the second substrate 2 and the connecting circuit board 5.

[0118] In this embodiment, such as Figure 3 and Figure 4 As shown, the electrical connection between the first substrate 1 and the connecting circuit board 5 can be achieved through the third connector 603, and the electrical connection between the second substrate 2 and the connecting circuit board 5 can be achieved through the sixth connector 606.

[0119] In step S62, flux is formed in the welding area of ​​the first semiconductor chip 3, the welding area of ​​the second semiconductor chip 4, the welding area of ​​the first substrate 1, and the welding area of ​​the second substrate 2, or flux is formed at the welding location of the connector 6.

[0120] In this step, operations such as forming flux in the welding area and forming flux at the welding part of connector 6 can be achieved by a dispensing machine.

[0121] In this process, flux or other conductive adhesive layers are formed in the welding areas of the first semiconductor chip 3 and the second semiconductor chip 4 and the welding areas of the first substrate 1 and the second substrate 2, or flux or other conductive adhesive layers are formed at the welding positions of the connector 6 on the corresponding side of the first semiconductor chip 3, the second semiconductor chip 4, the first substrate 1, and the second substrate 2.

[0122] Step S63: Pick up the connecting circuit board 5 and align the connector 6 with the welding area of ​​the first semiconductor chip 3, the welding area of ​​the second semiconductor chip 4, the welding area of ​​the first substrate 1, and the welding area of ​​the second substrate 2.

[0123] In this embodiment, the connecting circuit board 5 includes multiple welding areas (such as a first welding area, a second welding area, a fourth welding area, and a fifth welding area). Each connector 6 (such as a first connector 601, a second connector 602, a fourth connector 604, and a fifth connector 605) is placed in a suitable welding area and aligned with the corresponding welding area on the semiconductor chip (a first semiconductor chip 3 and a second semiconductor chip 4). The welding between the connecting circuit board 5 and the semiconductor chip can be achieved in subsequent steps through processes such as reflow soldering.

[0124] In this embodiment, for example, an SMT pick-and-place machine can pick up the connecting circuit board 5 and place it between the first substrate 1 and the second substrate 2. Different connectors 6 are aligned and placed with the welding areas of the corresponding first semiconductor chip 3 and second semiconductor chip 4, as well as the welding areas of the first substrate 1 and the second substrate 2.

[0125] Step S64: Weld the connector 6 to the first semiconductor chip 3, the second semiconductor chip 4, the first substrate 1, and the second substrate 2.

[0126] In this step, welding can be achieved by reflow soldering or other welding processes to electrically connect the first semiconductor chip 3 to the connecting circuit board 5 and the first substrate 1, and to electrically connect the second semiconductor chip 4 to the connecting circuit board 5 and the second substrate 2.

[0127] like Figure 6bAs shown, in some other embodiments, step S54, which involves soldering the connector 6 to the connecting circuit board 5, the first substrate 1, the second substrate 2, the first semiconductor chip 3, and the second semiconductor chip 4, may involve first placing the connector 6 on the first substrate 1, the second substrate 2, the first semiconductor chip 3, and the second semiconductor chip 4, including the following steps: In step S610, flux is formed in the welding area of ​​the first semiconductor chip 3, the welding area of ​​the second semiconductor chip 4, the welding area of ​​the first substrate 1 and the welding area of ​​the second substrate 2, or flux is formed at the welding location of the connector 6.

[0128] In this step, an appropriate amount of flux or other conductive adhesive layer is printed or applied to the welding area of ​​the first semiconductor chip 3, the welding area of ​​the second semiconductor chip 4, the welding area of ​​the first substrate 1, and the welding area of ​​the second substrate 2, or flux or other conductive adhesive layer is formed at the welding location of the connector 6.

[0129] In step S620, the connector 6 is placed in the welding area of ​​the first semiconductor chip 3, the welding area of ​​the second semiconductor chip 4, the welding area of ​​the first substrate 1, and the welding area of ​​the second substrate 2.

[0130] In this step, the connector 6 is brought into contact with the welding area of ​​the first semiconductor chip 3, the welding area of ​​the second semiconductor chip 4, the welding area of ​​the first substrate 1 and the welding area of ​​the second substrate 2 through flux, and the connector 6 is fixedly connected to the first semiconductor chip 3 and the first substrate 1 through processes such as reflow soldering, and the connector 6 is fixedly connected to the second semiconductor chip 4 and the second substrate 2.

[0131] Step S630: Pick up the connecting circuit board 5 and align the soldering area of ​​the connecting circuit board 5 with the connector 6.

[0132] In this step, the SMT pick and place the connecting circuit board 5 between the first substrate 1 and the second substrate 2, and align and place the different connectors 6 with the soldering areas on the corresponding side surfaces of the connecting circuit board 5.

[0133] Step S640: Weld connector 6 to connecting circuit board 5.

[0134] In this step, a flux or other conductive adhesive layer is formed in the soldering area on the second surface of the connecting circuit board 5, or a flux or other conductive adhesive layer is formed on the side of the connector 6 corresponding to the connecting circuit board 5. The first semiconductor chip 3 is electrically connected to the connecting circuit board 5 and the first substrate 1 through soldering processes such as reflow soldering, and the second semiconductor chip 4 is electrically connected to the connecting circuit board 5 and the second substrate 2.

[0135] Specifically, the reflow soldering fixture (such as the first mold and the second mold) provided in this application embodiment can be used to place the first substrate 1 and the first semiconductor chip 3 into the first mold, and the second substrate 2 and the second semiconductor chip 4 into the second mold. The positions of each part of the structure are adjusted (e.g., the connector 6 is placed on the connecting circuit board 5, and the welding areas of the connector 6 with the first semiconductor chip 3, the second semiconductor chip 4, the first substrate 1, and the second substrate 2 are aligned). Flux is applied to the corresponding positions, and then the assembled first mold and second mold are fastened onto the connecting circuit board 5. Finally, the reflow soldering of each part of the structure is completed. In this way, the connection between the connecting circuit board 5 and the first substrate 1, the second substrate 2, the first semiconductor chip 3, and the second semiconductor chip 4 can be achieved in one step with the help of the reflow soldering fixture, simplifying the soldering process in double-sided interconnect.

[0136] It is understood that in the above embodiments, the positions of each part of the structure can be adjusted first and then flux can be applied, or flux can be applied first and then the positions adjusted. The execution order of each step in the embodiments of this application is not limited to this.

[0137] In this embodiment, the bidirectional electrical interconnection of semiconductor chips is achieved through the relative arrangement of the first substrate 1 and the second substrate 2, and the coordinated configuration of the connecting circuit board 5 and the connector 6. This fundamentally optimizes the internal current topology of the power module. The connector 6 enables a short-path connection between the semiconductor chip and the conductive layer of the connecting circuit board 5. While avoiding the limitations of traditional bonding wires or clip arc height and cross-sectional area, the symmetrical arrangement of the double-sided current path achieves mutual inductance cancellation, thereby effectively shortening the current loop length, reducing package parasitic inductance, reducing switching voltage overshoot and oscillation, and improving the dynamic and static reliability of the module.

[0138] like Figure 9 As shown, in some embodiments, after or before the welding of the first semiconductor chip 3 and the second semiconductor chip 3 is completed, the fabrication method may further include: Step S91: Provide the first terminal 7 and the second terminal 8.

[0139] For example, the first terminal 7 is a power terminal and the second terminal 8 is a control terminal (or drive terminal).

[0140] Step S92: Place the connector 6 between the connecting circuit board 5 and the first terminal 7 and the second terminal 8.

[0141] It should be noted that, in Figure 1 and Figure 2 In the example shown, the first terminal 7 and the second terminal 8 are located on opposite sides of the connecting circuit board 5. It is understandable that... Figure 1 and Figure 2The positional relationship between the first terminal 7, the second terminal 8, and the connecting circuit board 5 is merely one example of the embodiments of this application, and the embodiments of this application are not limited thereto. In other examples, the first terminal 7 and the second terminal 8 may also be located on the same side of the connecting circuit board 5. For example, both may be located on the side of the connecting circuit board 5 facing the first substrate 1, or both may be located on the side of the connecting circuit board 5 facing the second substrate 2.

[0142] Therefore, in step S92 only... Figure 1 and Figure 2 The preparation method is illustrated using the structure shown in the diagram. It should be understood that the preparation and... Figure 1 When using other power modules with different structures, step S92 can be adjusted accordingly.

[0143] In step S93, the connector 6 is soldered to the connecting circuit board 5, the first terminal 7, and the second terminal 8, so that the first semiconductor chip 3 and the second semiconductor chip 4 are electrically connected to the first terminal 7 and the second terminal 8.

[0144] In this embodiment, the welding between the connecting circuit board 5 and the first terminal 7 and the second terminal 8 is realized through the connector 6, so that the first semiconductor chip 3 and the second semiconductor chip 4 can be electrically connected to the first terminal 7 and the second terminal 8 through the connecting circuit board 5.

[0145] In some embodiments, a ball-planting fixture can be used to provide a connector 6 on the connecting circuit board 5, thereby obtaining a connecting circuit board 5 with the connector 6. In this way, the connection between the connecting circuit board 5 and the first substrate 1, the second substrate 2, the first semiconductor chip 3, and the second semiconductor chip 4 can be realized more conveniently.

[0146] like Figure 10 As shown, in some embodiments, the method of using a ball-planting fixture to install the connector 6 on the connecting circuit board 5 may include: Step S101: Provide a first ball implantation fixture 12. The first ball implantation fixture 12 includes: a first protection zone 1201 corresponding to the first welding area and the second welding area, and a first implantation area corresponding to the ninth welding area of ​​the connecting circuit board 5.

[0147] Here, combined Figure 11 The process of ball placement on the connecting circuit board 5 is illustrated schematically. It should be understood that steps S101 to S106 are examples of some steps in this process and do not represent all embodiments. The preparation method of the embodiments of this application is not limited to this order of steps.

[0148] For example, see Figure 11The process of planting the ball can begin by picking up the connecting circuit board 5, then implanting the first connector 601 onto the connecting circuit board 5, and then implanting the second connector 602. When implanting the second connector 602, the first connector 601 can be protected by a protective zone to prevent the implantation of the second connector 602 from affecting the already planted first connector 601. Similar processes will not be described in detail.

[0149] In step S102, the first ball-implanting fixture 12 is arranged on the connecting circuit board 5, so that the first protection zone 1201 corresponds to the first welding area and the second welding area, and the first implantation area corresponds to the ninth welding area.

[0150] In step S103, the first connector 601 is placed in the first welding area through the first protection zone 1201, and the second connector 602 is placed in the second welding area. The ninth connector 609 is placed in the ninth welding area through the first implantation area.

[0151] Here, the first protection zone 1201 can protect the first connector 601 and the second connector 602, preventing the first connector 601 and the second connector 602 from being affected by subsequent processes.

[0152] Step S104: Provide a second implantation fixture 13. The second implantation fixture 13 includes: a second protection zone 1301 corresponding to the fourth welding area and the fifth welding area, and a second implantation area corresponding to the tenth welding area of ​​the connecting circuit board 5.

[0153] In step S105, the second ball implantation fixture 13 is arranged on the connecting circuit board 5, so that the second protection zone 1301 corresponds to the fourth welding area and the fifth welding area, and the second implantation area corresponds to the tenth welding area.

[0154] In step S106, the fourth connector 604 is placed in the fourth welding area through the second protection zone 1301, and the fifth connector 605 is placed in the fifth welding area. The tenth connector 610 is placed in the tenth welding area through the second implantation area.

[0155] Understandably, depending on actual needs, a first ball-planting fixture 12 may have multiple protection zones of the same or different sizes (such as a first protection zone 1201 and a second protection zone 1301). These protection zones are used to protect the connectors 6 that have been soldered onto the connecting circuit board 5. For example, the protection zone may specifically be a cavity within the first ball-planting fixture 12 that can accommodate the connectors 6.

[0156] This embodiment exemplifies the process of ball placement on the connecting circuit board 5 using the first ball placement fixture 12 and the second ball placement fixture 13, but the order of the steps is not limited to this. In addition, in actual production, the ball placement scheme on the connecting circuit board 5 (i.e., the position, number, distribution, etc. of the connectors 6) can be determined according to the design requirements of the power module.

[0157] like Figure 12 As shown, in some embodiments, the method of using a ball-planting fixture to set the connector 6 on the connecting circuit board 5 may further include: Step S1201, see Figure 13 A third implantation fixture 14 is provided, which includes a third protection zone 1401 corresponding to the first welding area and the second welding area, and a third implantation area corresponding to the third welding area.

[0158] Here, combined Figure 13 The process of ball placement on the connecting circuit board 5 is illustrated schematically. It should be understood that steps S1201 to S1212 are examples of some steps in this process and do not represent all embodiments. The preparation method of the embodiments of this application is not limited to this order of steps.

[0159] It is understood that multiple protection zones of the same or different sizes may be provided within the third ball-planting fixture 14. These protection zones are used to protect the connectors 6 that have been soldered onto the connecting circuit board 5. For example, the third protection zone 1401 may specifically be a cavity within the third ball-planting fixture 14 that can accommodate the connectors 6.

[0160] In step S1202, the third ball implantation fixture 14 is arranged on the connecting circuit board 5, so that the third protection zone 1401 corresponds to the first welding area and the second welding area, and the third implantation area corresponds to the third welding area.

[0161] In step S1203, the first connector 601 is placed in the first welding area through the third protection zone 1401, the second connector 602 is placed in the second welding area, and the third connector 603 is placed in the third welding area through the third implantation area.

[0162] Step S1204: Provide a fourth implantation fixture 15. The fourth implantation fixture 15 includes: a fourth protection zone 1501 corresponding to the first welding area and the second welding area, a fifth protection zone 1502 corresponding to the third welding area, and a fourth implantation area corresponding to the ninth welding area of ​​the connecting circuit board 5.

[0163] In step S1205, the fourth ball implantation fixture 15 is arranged on the connecting circuit board 5, so that the fourth protection zone 1501 corresponds to the first welding area and the second welding area, the fifth protection zone 1502 corresponds to the third welding area, and the fourth implantation area corresponds to the ninth welding area.

[0164] In step S1206, the first connector 601 is placed in the first welding area through the fourth protection zone 1501, the second connector 602 is placed in the second welding area, the third connector 603 is placed in the third welding area through the fifth protection zone 1502, and the ninth connector 609 is placed in the ninth welding area through the fourth implantation area.

[0165] Step S1207: Provide a fifth implantation fixture 16. The fifth implantation fixture 16 includes: a sixth protection zone 1601 corresponding to the fourth welding area and the fifth welding area, and a fifth implantation area corresponding to the sixth welding area of ​​the circuit board 5.

[0166] In step S1208, the fifth ball implantation fixture 16 is arranged on the connecting circuit board 5, so that the sixth protection zone 1601 corresponds to the fourth welding area and the fifth welding area, and the fifth implantation area corresponds to the sixth welding area.

[0167] In step S1209, the third connector 603 is placed in the third welding area through the sixth protection zone 1601, the fourth connector 604 is placed in the fourth welding area, and the sixth connector 606 is placed in the sixth welding area through the fifth implantation area.

[0168] Step S1210: Provide a sixth ball implantation fixture 17. The sixth ball implantation fixture 17 includes: a seventh protection zone 1701 corresponding to the fourth welding area and the fifth welding area, an eighth protection zone 1702 corresponding to the sixth welding area, and a sixth implantation area corresponding to the tenth welding area of ​​the connecting circuit board 5.

[0169] Step S1211: Arrange the sixth ball implantation fixture 17 on the connecting circuit board 5, so that the seventh protection zone 1701 corresponds to the fourth welding area and the fifth welding area, the eighth protection zone 1702 corresponds to the sixth welding area, and the sixth implantation area corresponds to the tenth welding area.

[0170] In step S1212, the fourth connector 604 is placed in the fourth welding area through the seventh protection zone 1701, the fifth connector 605 is placed in the fifth welding area, the sixth connector 606 is placed in the sixth welding area, and the tenth connector 610 is placed in the tenth welding area through the sixth implantation area.

[0171] like Figure 1 and Figure 2As shown, in some embodiments, after completing the aforementioned steps, the preparation method may further include a filling step of encapsulating adhesive, wherein the encapsulation body 10 may be formed by bottom filling method, and the encapsulation body 10 at least covers the first substrate 1, the second substrate 2, the first semiconductor chip 3, the second semiconductor chip 4 and the connecting circuit board 5.

[0172] Specifically, when forming the encapsulated body 10 using the bottom filling method, the power module completed in the aforementioned steps is placed into the mold cavity, and then liquid encapsulation material is poured into the mold cavity. The encapsulation material is ensured to fully wet and cover the side surface of the first substrate 1 and the remaining exposed first surface 101, the side surface of the second substrate 2 and the remaining exposed first surface 201, the side surface of the semiconductor chip and the remaining exposed first surface, the connector 6, all side surfaces, the upper surface and the lower surface of the connecting circuit board 5, and after ensuring that there are no air bubbles in the encapsulation material, the encapsulation material is cured and demolded.

[0173] For example, the materials of the molding compound 10 include: epoxy molding compound (EMC), cyanate ester resin-based molding compound, polyimide (PI) resin-based molding compound, ceramic-filled modified resin-based molding compound, etc., which can provide better support for the connecting circuit board 5.

[0174] In this embodiment, in order to ensure structural strength, epoxy resin molding can be used to achieve external insulation encapsulation, encapsulating the electrical components of the power module within the molding body 10 to achieve overall protection.

[0175] like Figure 14 As shown, in some embodiments, the encapsulating adhesive filling step may include: Step S1401: Provide frame mold 18.

[0176] Step S1402, see Figure 15 and Figure 16 The frame mold 18 is placed between the first substrate 1 and the second substrate 2, such that the frame mold 18, the first surface 101 of the first substrate 1 and the first surface 201 of the second substrate 2 cooperate to form a cavity with one end open, and the first semiconductor chip 3 and the second semiconductor chip 4 are located in the cavity.

[0177] It should be noted that for double-sided interconnect structures, the lack of an external plastic encapsulation shell makes it difficult to use silicone gel encapsulation. Furthermore, the low stiffness of silicone gel makes it insufficient to provide adequate rigidity support for the connecting circuit board 5, leading to warping and deformation during reliability testing, resulting in electrical interconnect failure. If epoxy resin encapsulation is used, the large overall size of the power module and the high injection force result in significant impact stress on the connecting circuit board 5. Given the large size, thinness, and dense solder ball array of the connecting circuit board itself, traditional encapsulation processes are prone to peeling and cracking failures.

[0178] Therefore, in this embodiment of the application, an underfill process is selected for the connecting circuit board 5 to achieve insulating encapsulation. Specifically, as... Figure 15 and Figure 16 As shown, a frame mold 18 (i.e., a dam frame) is designed and manufactured. The frame mold 18 is directly inserted into the first substrate 1 and the second substrate 2. Underfill adhesive is applied to the cavity formed between the frame mold 18 and the first substrate 1 and the second substrate 2.

[0179] Step S1403: Apply adhesive to fill the cavity from the opening.

[0180] See Figure 15 and Figure 16 The direction indicated by the arrow is the direction for dispensing and filling the adhesive.

[0181] It should be noted that before dispensing and filling, one can... Figure 15 and Figure 16 The overall structure shown is placed vertically, so that Figure 15 Taking the state shown as an example, the entire structure is rotated counterclockwise so that the opening of the cavity faces upward, and then the glue filling operation is performed until the glue covers the opening of the cavity.

[0182] Step S1404: Perform vacuum curing operation inside the cavity.

[0183] In this step, pressure curing can be applied to remove air bubbles in the adhesive and to fix the power module in an insulating package.

[0184] like Figure 17 As shown, in some embodiments, after the connector 6 is soldered to the connecting circuit board 5, the first substrate 1, the second substrate 2, the first semiconductor chip 3, and the second semiconductor chip 4, the following steps can be performed to remove residual flux: Step S1701: Perform a water washing operation on the power module to remove residual flux; Step S1702: After the water washing operation, the power module is dried; wherein the power module includes at least: a first substrate 1, a second substrate 2, a first semiconductor chip 3, and a second semiconductor chip 4.

[0185] In this embodiment, residual flux can be removed by water washing. In order to ensure the long-term reliability of the power module, the overall structure of the power module needs to be baked at high temperature after water washing to remove moisture from the substrate.

[0186] like Figure 18 As shown, in some embodiments, a method for forming the connecting circuit board 5 is also included, the method comprising: Step 1801, provide an insulating third substrate 501.

[0187] In this step, the third substrate 501 includes opposing first and second surfaces, and the third substrate 501 is pre-treated. The pre-treatment includes grinding, polishing, cleaning, and drying of the surface of the third substrate 501 to improve the interfacial bonding performance, structural stability, and environmental resistance of the third substrate 501.

[0188] Step 1802: A conductive channel 502 is formed in the third substrate 501, and a conductive material is filled in the conductive channel.

[0189] In this step, through-holes are formed in the third substrate 501 by etching processes such as wet etching and dry etching. Then, conductive material is filled into the through-holes to form conductive channels 502, which connect the first surface and the second surface of the third substrate 501.

[0190] Step 1803: A conductive layer is formed on the first surface of the third substrate 501.

[0191] In this step, a patterned conductive material is deposited on the first surface of the third substrate 501 to form a conductive layer by deposition processes such as physical vapor deposition (PVD) and chemical vapor deposition (CVD).

[0192] Methods for forming a conductive layer include additive or subtractive processes. An additive process involves first forming a patterned mask layer on the first surface of the third substrate 501, then depositing a conductive material, and finally removing the mask layer. A subtractive process involves first depositing a conductive material on the first surface of the third substrate 501, then forming a patterned mask layer on the conductive material, and finally etching the conductive material through the mask layer to form the patterned conductive layer.

[0193] The conductive layer is electrically connected to the second surface of the third substrate 501 via the conductive channel 502 formed in the aforementioned steps.

[0194] Step 1804: Deposit insulating material on the conductive layer.

[0195] In this step, an insulating material can be deposited on the conductive layer using deposition processes such as physical vapor deposition or chemical vapor deposition. The material of this insulating material can be the same as the material of the third substrate 501.

[0196] Step 1805: Form a conductive channel 502 in the insulating material and fill the conductive channel with conductive material.

[0197] In this step, through-holes penetrating the insulating material can be formed in the insulating material through etching processes such as wet etching and dry etching, and then conductive material can be formed in the through-holes to form conductive channels 502.

[0198] Step 1806: Repeat the steps of forming the conductive layer, depositing the insulating material, and forming the conductive channel until the connecting circuit board 5 is formed.

[0199] In some embodiments, after forming the connecting circuit board 5, the fabrication method further includes forming a plurality of pads 9 on the connecting circuit board 5.

[0200] Specifically, multiple pads 9 can be formed on the surface of the connecting circuit board 5 through a deposition process. Each pad 9 is connected to at least one conductive channel 502 in the connecting circuit board 5, and each pad 9 is electrically connected to only one corresponding conductive layer via the conductive channel 502.

[0201] In this step, depending on the number of conductive layers within the connecting circuit board 5, the aforementioned steps of forming conductive layers, insulating material, and forming conductive channels in the insulating material are performed at least once. For connecting circuit boards 5 that require the formation of multiple conductive layers and multiple conductive channels 502 within the connecting circuit board 5, after completing the substrate including a single conductive layer, the steps of forming conductive layers, forming insulating material, and forming conductive channels penetrating the insulating material are performed again. The number of conductive layers required determines the number of repeated steps, thereby forming a connecting circuit board 5 with a wiring layer having a predetermined number of conductive layers.

[0202] In this embodiment, the bidirectional electrical interconnection of semiconductor chips is achieved through the relative arrangement of the first substrate 1 and the second substrate 2, and the coordinated configuration of the connecting circuit board 5 and the connector 6. This fundamentally optimizes the internal current topology of the power module. The connector 6 enables a short-path connection between the semiconductor chip and the conductive layer of the connecting circuit board 5. While avoiding the limitations of traditional bonding wires or clip arc height and cross-sectional area, the symmetrical arrangement of the double-sided current path achieves mutual inductance cancellation, thereby effectively shortening the current loop length, reducing package parasitic inductance, reducing switching voltage overshoot and oscillation, and improving the dynamic and static reliability of the module.

[0203] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, since the embodiments are basically similar to the product embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the product embodiments.

[0204] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0205] It is understandable that when a component such as a layer, film, region, or substrate is referred to as being "above" or "below" another component, the component may be "directly" located "above" or "below" the other component, or there may be intermediate components present.

[0206] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0207] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A power module, characterized in that, include: First substrate; The second substrate has a first surface disposed opposite to the first surface of the first substrate; At least two semiconductor chips, including: at least one first semiconductor chip disposed on a first surface of the first substrate, and at least one second semiconductor chip disposed on a first surface of the second substrate; A connecting circuit board is located between the first substrate and the second substrate. The connecting circuit board includes a third substrate and a wiring layer located in the third substrate. The wiring layer includes at least two conductive layers stacked along a first direction, and adjacent conductive layers are insulated from each other. A plurality of connectors, one end of which is connected to the wiring layer and the other end of which is connected to at least one of the semiconductor chip, the first substrate, and the second substrate.

2. The power module according to claim 1, characterized in that, Also includes: The first terminal and the second terminal are both connected to the wiring layer.

3. The power module according to claim 1, characterized in that, The third substrate is provided with a conductive channel along the first direction, and the conductive channel realizes the electrical connection between the wiring layer and the connector.

4. The power module according to claim 3, characterized in that, The connector is provided with a pad at the connection position with the connecting circuit board, and the pad is electrically connected to the conductive layer through the conductive channel.

5. The power module according to claim 2, characterized in that, The conductive layer includes: a first conductive layer and a second conductive layer; The first conductive layer is connected to the first terminal, and the second conductive layer is connected to the second terminal.

6. The power module according to claim 5, characterized in that, The cross-sectional area of ​​the connector connected to the first conductive layer is greater than the cross-sectional area of ​​the connector connected to the second conductive layer.

7. The power module according to claim 6, characterized in that, The total cross-sectional area of ​​the connectors connected to the first conductive layer is greater than the total cross-sectional area of ​​the connectors connected to the second conductive layer; or... The connector is a solder ball, and the number of solder balls connected to the first conductive layer is greater than the number of solder balls connected to the second conductive layer.

8. The power module according to any one of claims 5 to 7, characterized in that, The first conductive layer includes at least: a first sub-conductive layer, a second sub-conductive layer, and a third sub-conductive layer; The second conductive layer includes at least: a first control conductive layer and a second control conductive layer; The first terminal includes: a DC negative terminal, a DC positive terminal, and an AC terminal. The DC negative terminal and the DC positive terminal are disposed at one end of the connecting circuit board, and the AC terminal is disposed at the other end of the connecting circuit board. The second terminal includes: a first control terminal and a second control terminal; The DC negative terminal is electrically connected to the first sub-conductive layer; The DC positive terminal is electrically connected to the conductive layer of the second substrate; The AC terminal is electrically connected to the third sub-conductive layer; The first control terminal is electrically connected to the first control conductive layer; The second control terminal is electrically connected to the second control conductive layer.

9. The power module according to claim 8, characterized in that, The connector includes: First connector, second connector, third connector, fourth connector, fifth connector, sixth connector, seventh connector, eighth connector, ninth connector and tenth connector; The first connector electrically connects the first control conductive layer to the gate of the first semiconductor chip. The second connector electrically connects the first sub-conductive layer to the source of the first semiconductor chip; The third connector electrically connects the third sub-conductive layer to the first substrate. The fourth connector electrically connects the second control conductive layer to the gate of the second semiconductor chip. The fifth connector electrically connects the third sub-conductive layer to the source of the second semiconductor chip; The sixth connector electrically connects the second sub-conductive layer to the second substrate. The seventh connector electrically connects the DC negative terminal to the first sub-conductive layer; The eighth connector electrically connects the DC positive terminal to the second sub-conductive layer; The ninth connector electrically connects the AC terminal to the third sub-conductive layer; The tenth connector electrically connects the first control terminal to the first control conductive layer and the second control terminal to the second control conductive layer.

10. The power module according to claim 8, characterized in that, The thickness of the first conductive layer is greater than the thickness of the second conductive layer; Alternatively, the product of the thickness and width of the first conductive layer is greater than the product of the thickness and width of the second conductive layer; Alternatively, the product of the thickness and width of the first sub-conductive layer, the product of the thickness and width of the second sub-conductive layer, and the product of the thickness and width of the third sub-conductive layer are equal and greater than the product of the thickness and width of the first control conductive layer and the product of the thickness and width of the second control conductive layer.

11. The power module according to claim 10, characterized in that, The thickness of the first conductive layer is at least 2 oz.

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