Semiconductor structure and method of forming the same

Abstract

Semiconductor structures and methods of forming the same are provided. In embodiments, an exemplary method includes receiving a precursor structure including: a nanostmcture located over a substrate; a gate structure located over the nanostmcture, the gate structure including a gate dielectric layer located over the plurality of nanostmctures and a gate electrode located over the gate dielectric layer; a source / drain component coupled to the nanostmcture and an interlayer dielectric (ILD) layer located over the substrate. The method further includes selectively removing portions of the ILD layer to form a trench having a bottom surface lower than a top surface of the source / drain component, forming a dielectric cap in the trench and on the ILD layer, the dielectric cap and the ILD layer including different compositions, and forming a source / drain contact extending through the dielectric cap to couple to the source / drain component, the source / drain contact having a greater electrical conductivity than the source / drain component.

Description

Technical Field

[0001] Embodiments of this disclosure provide semiconductor structures and methods for forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnect devices per chip area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. This scaling down process generally provides benefits through increased production efficiency and reduced associated costs.

[0003] This scaling down also increases the complexity of handling and manufacturing ICs, and similar advancements in IC handling and manufacturing are needed to achieve these progresses. For example, as integrated circuit (IC) technology has moved towards smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCE). Multi-gate devices generally refer to devices having a gate structure or portion thereof disposed above more than one side of the channel region. FinFETs and gate-all-around (GAA) transistors (also known as non-planar transistors) are examples of multi-gate devices, and they have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have raised channels wrapped by gates on more than one side (e.g., the gates wrap the top and sidewalls of a “fin” of semiconductor material extending from the substrate). Compared to planar transistors, this configuration provides better channel control and significantly reduces SCE (particularly by reducing subthreshold leakage, i.e., the coupling between the source and drain of a FinFET in the “off” state). GAA transistors have a gate structure that can extend partially or completely around the channel region to provide access to the channel region on one or more sides. The channel region of a GAA transistor can be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures. These shapes of the channel region also give GAA transistors different names. For example, a GAA transistor with a nanosheet channel region can be called a nanosheet transistor. While existing structures are generally sufficient for their intended purpose, they are not entirely satisfactory in every respect. Summary of the Invention

[0004] Embodiments of this disclosure provide a method for forming a semiconductor structure, comprising: receiving a precursor structure including: a plurality of nanostructures located above a substrate; a gate structure located above the plurality of nanostructures, the gate structure including a gate dielectric layer located above the plurality of nanostructures and a gate electrode located above the gate dielectric layer; a source / drain component coupled to the plurality of nanostructures; and an interlayer dielectric (ILD) layer located above the substrate; selectively removing a portion of the interlayer dielectric layer above the source / drain component to form a trench, wherein the bottom surface of the trench is lower than the top surface of the source / drain component; forming a dielectric cap in the trench and on the interlayer dielectric layer, wherein the dielectric cap and the interlayer dielectric layer comprise different compositions; and forming a source / drain contact extending through the dielectric cap to couple to the source / drain component, wherein the conductivity of the source / drain contact is greater than the conductivity of the source / drain component.

[0005] Another embodiment of this disclosure provides a method for forming a semiconductor structure, comprising: forming an active region extending along a first direction, the active region including a channel region and a source / drain component adjacent to the channel region; forming an isolation component connected to an end portion of the active region along the first direction; depositing an etch stop layer over the source / drain component and the isolation component; forming a dielectric layer on the etch stop layer; selectively removing a top portion of the dielectric layer to expose a top surface of the etch stop layer; after the selective removal, forming a dielectric cap over the etch stop layer, wherein the dielectric cap and the dielectric layer comprise different compositions; and forming a conductive component extending through the dielectric cap and located over the isolation component, wherein the conductivity of the conductive component is greater than the conductivity of the source / drain component.

[0006] Another embodiment of this disclosure provides a semiconductor structure including: an active region extending longitudinally along a first direction, the active region including a channel region and a source / drain component adjacent to the channel region; a gate structure located above the channel region and extending along a second direction different from the first direction; a source / drain contact located above the source / drain component and electrically coupled to the source / drain component; an isolation component in contact with an end portion of the active region; a dielectric layer extending above the isolation component; a dielectric cap located on the dielectric layer, wherein the dielectric cap and the dielectric layer comprise different components; and a conductive component extending through the dielectric cap. Attached Figure Description

[0007] This disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industry practice, the various parts are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various parts may be arbitrarily increased or decreased for clarity of discussion.

[0008] Figure 1 A flowchart of a method for forming a semiconductor structure according to one or more aspects of this disclosure is shown.

[0009] Figure 2 Experiences based on various aspects of this disclosure are shown. Figure 1 A partial top view of the exemplary precursor structure for each operational stage in the method.

[0010] Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A This illustrates one or more aspects of the present disclosure. Figure 1 Along such as during each manufacturing stage in the method Figure 2 The diagram shows a partial cross-sectional view of the precursor structure taken by line A-A'.

[0011] Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B This illustrates one or more aspects of the present disclosure. Figure 1 Along such as during each manufacturing stage in the method Figure 2 The diagram shows a partial cross-sectional view of the precursor structure taken by line B-B'.

[0012] Figure 9 A graph showing the ratio of etch selectivity between two dielectric layers to the flow rate of etchant gas according to various embodiments of the present disclosure is presented.

[0013] Figure 17 The various aspects of this disclosure are shown. Figures 18A to 18B A partial top view of the precursor structure shown. Detailed Implementation

[0014] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0015] For ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used herein to describe the relationship of one element or component to another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device in use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0016] Additionally, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, the term is intended to encompass values ​​within a reasonable range, taking into account the inherent variations that occur during manufacturing as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing a part having characteristics associated with the value, the value or range encompasses a reasonable range including the described value, such as within + / - 10% of the described value. For instance, a material layer with a thickness of "about 5 nm" could encompass dimensions ranging from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%.

[0017] Semiconductor structures include device regions for forming devices (e.g., FinFETs or GAA transistors) and non-device regions (e.g., edge regions) adjacent to the device regions. Source / drain contacts and gate structures can be formed in both the device and non-device regions. In some prior art, forming source / drain contacts includes forming an etch stop layer and an interlayer dielectric (ILD) layer over a substrate, and etching through the ILD layer and the etch stop layer to form source / drain contact openings exposing source / drain components in the device region and source / drain contact openings in the non-device region. However, the thickness of a portion of the ILD layer in the non-device region is much greater than the thickness of a portion of the ILD layer over the source / drain components. In embodiments where the ILD layer comprises oxide and the etching process is configured to simultaneously form source / drain contact openings in both the device and non-device regions, the etching process can etch a large amount of oxide-based ILD layer in the non-device region, and the resulting source / drain contact openings in the non-device region may be too deep, resulting in deep source / drain contacts in the non-device region and thus causing high parasitic capacitance.

[0018] This disclosure relates to a semiconductor structure with reduced parasitic capacitance. In an embodiment, after forming the etch stop layer and the ILD layer, the top portion of the ILD layer directly above the source / drain components is replaced by a dielectric cap. The dielectric cap is more etch-resistant than the ILD layer during the formation of the source / drain contact openings. Therefore, the amount of oxide-based ILD layer to be removed in the non-device regions during the formation of the source / drain contact openings is reduced. As a result, the source / drain contacts formed in the non-device regions will have a reduced thickness (or depth). Parasitic capacitance can be advantageously reduced, and the performance of the semiconductor structure can be improved.

[0019] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This is a flowchart illustrating a method 100 for forming a semiconductor structure according to an embodiment of the present disclosure. The following is in conjunction with... Figures 2 to 21B Method 100 is described. Method 100 is merely an example and is not intended to limit this disclosure to what is expressly shown therein. Additional steps may be provided before, during, and after method 100, and some of the described steps may be replaced, eliminated, or rearranged for additional embodiments of the method. For simplicity, not all steps are described in detail herein. Because the precursor structure 200 will be fabricated into a semiconductor structure after the manufacturing process, the precursor structure 200 may be referred to as semiconductor structure 200 as needed by the context. To avoid ambiguity, Figures 2 to 8B and Figures 10A to 21B The X, Y, and Z directions are perpendicular to each other and are used consistently throughout this disclosure. Unless otherwise specified, the same reference numerals denote the same parts throughout this disclosure.

[0020] refer to Figure 1 , Figure 2 and Figures 3A to 3B Method 100 includes block 102, wherein a precursor structure 200 is received. Figure 2 The experience described in this disclosure is as follows: Figure 1 A partial top view of the precursor structure 200 for each operational stage in the method. Figure 3A It shows along such Figure 2 The diagram shows a partial cross-sectional view of the precursor structure 200 taken by line AA, and... Figure 3B It shows along such Figure 2 The diagram shows a partial cross-sectional view of the precursor structure 200 taken by line BB. The precursor structure 200 includes a first region 200A for forming a device (e.g., a FinFET or GAA transistor) and a second region 200B adjacent to the first region 200A.

[0021] like Figures 3A to 3B As shown, the precursor structure 200 includes a substrate 202. The substrate 202 can be an elemental (single-element) semiconductor, such as crystalline silicon (Si) or germanium (Ge); a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium arsenide phosphide (GaInAsP); a non-semiconductor material, such as soda-lime glass, fused silica, fused silica, and / or calcium fluoride (CaF2); and / or combinations thereof. In one embodiment, the substrate 202 is a silicon (Si) substrate. The composition of the substrate 202 can be homogeneous, or it can include various layers, some of which can be selectively etched to form active regions (e.g., active region 204). These layers may have similar or different compositions, and in various embodiments, some substrate layers have non-uniform compositions to induce device strain and thus modulate device performance. Examples of layered substrates include silicon-on-insulator (SOI) substrate 202. In some such examples, the layers of substrate 202 may include insulators such as semiconductor oxides, semiconductor nitrides, semiconductor oxide nitrides, semiconductor carbides, and / or other suitable insulating materials. Doped regions (such as wells) may be formed in substrate 202.

[0022] Still referencing Figure 2 and Figures 3A to 3B The precursor structure 200 includes an active region 204 located above the substrate 202 and in the first region 200A. Figure 2 and Figures 3A to 3B The number of active regions 204 depicted is merely an example; the precursor structure 200 may include any suitable number of active regions. Each active region 204 may be formed by the top portion 202t of the substrate 202 (e.g., Figures 3A to 3B A vertical stack 207, consisting of alternating semiconductor layers disposed on a substrate 202, is formed. In an embodiment, the vertical stack 207 includes a plurality of channel layers 208 interleaved with a plurality of sacrificial layers 206. Each channel layer 208 may include a semiconductor material such as silicon, germanium, silicon carbide, silicon germanium, GeSn, SiGeSn, SiGeCSn, other suitable semiconductor materials, or combinations thereof, while the composition of each sacrificial layer 206 differs from the composition of the channel layers 108. In an embodiment, each channel layer 208 includes silicon (Si), and each sacrificial layer 206 includes silicon germanium (SiGe). Although the illustrated example of the vertical stack 207 includes three channel layers and three sacrificial layers, it should be understood that the vertical stack 207 may include any suitable number (e.g., 2 to 10) of channel layers and any suitable number of sacrificial layers. The top portion 202t of the vertical stack 207 and the substrate 202 is then patterned to form an active region 204. In some embodiments, the patterned top portion 202t of the substrate 202 may be referred to as a mesa structure or a base fin. Each active region 204 extends longitudinally along the X direction and is divided into a channel region 204C that overlaps with the dummy gate stack 210 (described below) and a source / drain region 204SD that does not overlap with the dummy gate stack 210. Depending on the context, the source / drain region 204SD may refer individually or collectively to the source region or the drain region. Each channel region 204C is disposed between the two source / drain regions 204SD along the X direction.

[0023] The precursor structure 200 also includes a first isolation member 203a located in a first region 200A and a second isolation member 203b located in a second region 200B. The first isolation member 203a is formed around the active region 204 to isolate one active region 204 from adjacent active regions 204. Figure 3AIn the illustrated embodiment, the upper portion of the active region 204 rises above the first isolation member 203a and the second isolation member 203b, while the lower portion of the active region 204 remains covered or buried in the first isolation member 203a and adjacent to the second isolation member 203b. The second isolation member 203b is formed next to the end portion of the active region 204. The first isolation member 203a and the second isolation member 203b may include shallow trench isolation (STI) members. In this embodiment, the first isolation member 203a extends along the X direction, and the second isolation member 203b extends from the first isolation member 203a and along the Y direction. That is, there is no physical interface between the first isolation member 203a and the second isolation member 203b. In the example process, dielectric material is deposited over the precursor structure 200 to fill the trenches between the active regions 204 in the first region 200A and the spaces in the second region 200B, thinned and planarized (e.g., by chemical mechanical polishing (CMP)) until the top surfaces of the active regions 204 are exposed, and further recessed or etched back by dry etching, wet etching, and / or combinations thereof to form the lower portion 205a of the first isolation member 203a and the second isolation member 203b. The lower portion 205a may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials, and may be deposited by CVD, flowable CVD (FCVD), spin coating, and / or other suitable processes. Another dielectric material is then deposited and etched back to form the upper portion 205b of the first isolation member 203a and the second isolation member 203b. The lower portion 205a and the upper portion 205b may have different compositions. In an embodiment, the lower portion 205a comprises an oxide-based material (e.g., silicon oxide) having a dielectric constant of about 3 to about 5. The upper portion 205b may comprise silicon nitride.

[0024] Still refer to Figure 1 , Figure 2 , Figures 3A to 3B Method 100 includes block 104, wherein a dummy gate stack 210 is formed in a first region 200A and a second region 200B. An active region 204 extends longitudinally along a first direction (e.g., the X direction), and the dummy gate stack 210 extends longitudinally along a second direction (e.g., the Y direction) different from the first direction. The channel region 204C and the dummy gate stack 210 also define a source / drain (S / D) region 204SD that does not vertically overlap with the dummy gate stack 210. In this embodiment, a gate replacement process (or post-gate process) is employed, wherein the dummy gate stack 210 serves as a placeholder for the gate structure 240 (e.g., ...). Figure 11A(As shown). Other processes and configurations are possible. Although not individually labeled, each dummy gate stack 210 includes a dummy gate dielectric layer, a dummy gate electrode layer above the dummy gate dielectric layer, and a gate top hard mask layer above the dummy gate electrode layer. The dummy gate dielectric layer may include silicon oxide. The dummy gate electrode layer may include polysilicon. The gate top hard mask layer may include a silicon oxide layer, silicon nitride, and / or other suitable materials. Suitable deposition, photolithography, and etching processes may be used to form the dummy gate stack 210. Figure 2 Five dummy gate stacks 210 are shown, but the precursor structure 200 may include any suitable number of dummy gate stacks 210 located in the first region 200A and any suitable number of dummy gate stacks 210 located in the second region 200B. The dummy gate stacks 210 in the first region 200A extend over the active region 204 and the first isolation member 203a, and the dummy gate stacks 210 in the second region 200B extend over the second isolation member 203b. In the illustrated embodiment, one of the dummy gate stacks 210 extends across the boundary between the first region 200A and the second region 200B, and includes a portion on the active region 204 and a portion on the second isolation member 203b. In some embodiments, the dummy gate stacks 210 in the first region 200A and the dummy gate stacks 210 in the second region 200B have the same gate pitch.

[0025] refer to Figure 1 and Figures 4A to 4B Method 100 includes block 106, wherein a gate spacer 214a is formed along the sidewall of the dummy gate stack 210. In an embodiment, a spacer layer is conformally deposited over the precursor structure 200 and then etched back to form a gate spacer 214a extending along the sidewall surface of the dummy gate stack 210 and a fin sidewall spacer 214b adjacent to the active region 204. The spacer layer may be a single-layer or multi-layer structure and may be conformally deposited over the precursor structure 200 by atomic layer deposition (ALD), chemical vapor deposition (CVD), or any other suitable deposition process. For ease of description of a layer having a substantially uniform thickness over the various regions of the precursor structure 200, the term “conformally” may be used herein. The spacer layer may include silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, metal nitride, or other suitable dielectric materials. In an embodiment, the etch-back of the spacer layer may also recess the first isolation member 203a and the second isolation member 203b.

[0026] Still referencing Figure 1 and Figures 4A to 4BMethod 100 includes block 108, wherein the source / drain region 204SD of the active region 204 is recessed to form an S / D opening 216. After forming the gate spacer 214a, the source / drain region 204SD of the active region 204 is recessed to form the source / drain opening 216. In embodiments, the source / drain region 204SD of the active region 204 is anisotropically etched using plasma etching with suitable etchants, such as oxygen-containing etchants, hydrogen-containing etchants, fluorine-containing etchants (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing etchants (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing etchants (e.g., HBr and / or CHBr3), iodine-containing etchants, other suitable etchants, and / or combinations thereof. In an embodiment, the etching process used to form the S / D opening 216 can also cause the first isolation member 203a and the second isolation member 203b to be recessed. For example, as Figure 4B As shown, after the S / D opening 216 is formed, the first isolation member 203a has a non-flat top surface. Similarly, as Figure 4A As shown, the second isolation member 203b has a non-flat top surface. In some embodiments, the non-flat top surface of the first isolation member 203a may be a concave top surface. In various embodiments, the etch-back of the spacer layer and the etch process for forming the S / D opening 216 may include performing the same etch process.

[0027] refer to Figure 1 and Figures 5A to 5B Method 100 includes a frame 110 in which an internal spacer component 218 is formed. After forming the source / drain opening 216, a sacrificial layer 206 exposed in the source / drain opening 216 is selectively and partially recessed to form an internal spacer recess (filled by the internal spacer component 218), while the exposed channel layer 208 is substantially unetched. This selective recessing may include a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree of recess of the sacrificial layer 206 can be controlled by the duration of the etching process. After forming the internal spacer recess, an internal spacer material layer is then conformally deposited over the precursor structure 200 (including over and within the internal spacer recess) using CVD or ALD. The internal spacer material may include silicon nitride, silicon carbonitride, silicon carbonitride, silicon oxide, silicon carbonitride, silicon carbide, or silicon oxynitride. Then, as... Figure 5AAs shown, the inner spacer material layer is etched back to form the inner spacer component 218. In some embodiments, the composition of the inner spacer component 218 is different from that of the gate spacer 214a, such that the etch-back of the inner spacer material layer substantially does not etch the gate spacer 214a. It is worth noting that the formation of the inner spacer component 218 (including the corresponding manufacturing steps described above) can be optional. That is, in some embodiments, the formation of the inner spacer component 218 can be omitted, and the inner spacer component 218 may not be present in the final structure.

[0028] refer to Figure 1 and Figures 6A to 6B Method 100 includes block 112, wherein a source / drain (S / D) component 220 is formed in an S / D opening 216. Depending on the context, the source / drain component may refer individually or collectively to a source or a drain. In the illustrated example, an epitaxial layer 222 is formed in a lower portion of the source / drain opening 216 prior to forming the S / D component 220. The epitaxial layer 222 may be an undoped epitaxial layer (e.g., undoped silicon). An optional dielectric layer 224 may be formed on the epitaxial layer 222 and in the source / drain opening 216. In various embodiments, the top surface of the dielectric layer 224 may be lower than the bottom surface of the bottommost channel layer in the channel layer 208. In some embodiments, such as Figures 6A to 6B As shown, an optional dielectric layer 224 may also be formed on the recessed first isolation member 203a and the recessed second isolation member 203b. In some embodiments, such as Figures 7A to 7B As shown, the precursor structure 200 may include a dielectric layer 224 in the source / drain opening 216, but does not include the dielectric layer 224 on the first isolation member 203a and the second isolation member 203b.

[0029] The S / D component 220 may include one or more epitaxial layers. For example, the S / D component 220 may include a first layer and a second layer, the first layer being connected to the channel region 204C, and the second layer being spaced apart from the channel region 204C by the first layer. The dopant concentration in the first layer is less than the dopant concentration in the second layer. The width of the source / drain component 220 is greater than the width of the channel region 204C. Figure 6BAs shown, the S / D component 220 is suspended from the first isolation component 203a. Depending on the conductivity type of the transistor to be formed, the source / drain component 220 can be an n-type source / drain component or a p-type source / drain component. Exemplary n-type source / drain components may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials (e.g., SiC, SiCP, SiCAs), and can be in-situ doped during the epitaxial process by introducing an n-type dopant (such as phosphorus, arsenic, or antimony), or out-of-situ doped using a junction implantation process. Exemplary p-type source / drain components may include germanium, gallium-doped silicon-germanium, boron-doped silicon-germanium, or other suitable materials, and can be in-situ doped during the epitaxial process by introducing a p-type dopant (such as boron or gallium), or out-of-situ doped using a junction implantation process.

[0030] refer to Figure 1 and Figures 7A to 7B Method 100 includes block 114, wherein a contact etch stop layer 226 and a first interlayer dielectric (ILD) layer 228 are formed over a substrate 202. After forming the source / drain components 220, the contact etch stop layer (CESL) 226 and the first interlayer dielectric (ILD) layer 228 are deposited over the precursor structure 200. CESL 226 may comprise silicon nitride, silicon oxynitride, and / or other suitable materials, and can be formed by ALD, plasma-enhanced chemical vapor deposition (PECVD) processes, and / or other suitable deposition or oxidation processes. In this embodiment, to facilitate the formation of satisfactory trenches / openings in subsequent processes, the contact etch stop layer 226 is a bilayer structure comprising a first layer 226a and a second layer 226b situated on the first layer 226a. The first layer 226a and the second layer 226b have different compositions. The second layer 226b and the ILD layer 228 have etch selectivity, and the first layer 226a and caps 236a-236b (e.g., Figures 10A to 10B (As shown) has etch selectivity. In one embodiment, the first layer 226a comprises silicon oxide, and the second layer 226b comprises silicon nitride. After depositing CESL 226, a first ILD layer 228 is deposited over the precursor structure 200 by, for example, a PECVD process or other suitable deposition technique. The first ILD layer 228 may comprise materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. A planarization process (such as a chemical mechanical polishing (CMP) process) may be performed on the precursor structure 200 to remove excess material and expose the top surface of the dummy gate electrode layer of the dummy gate stack 210. After performing the planarization process, the first ILD layer 228 may have a substantially flat top surface.

[0031] The first ILD layer 228 has a non-uniform thickness above the substrate 202. For example, in Figures 7A to 7B In the cross-sectional view shown, the ILD layer 228 has a thickness T1 directly above the source / drain component 220, a thickness T2 directly above the second isolation component 203b, and a thickness T3 directly above the first isolation component 203a. Thickness T2 is greater than thickness T1. That is, the portion of the first ILD layer 228 located on the second isolation component 203b is thicker than the portion of the first ILD layer 228 directly above the source / drain component 220. In various embodiments, thickness T2 may be substantially equal to thickness T3. As described above, in some prior art for forming source / drain contacts, a portion of the ILD layer 228 located in the second region 200B and above the second isolation component 203b can be strictly removed, resulting in deep source / drain contact openings in the second region 200B, and thus high parasitic capacitance.

[0032] refer to Figure 1 and Figures 8A to 8B Method 100 includes block 116, wherein an etching process 232 is performed to selectively recess a first ILD layer 228, thereby forming a first trench 230a extending over a source / drain component 220 in a first region 200A and a second trench 230b located directly above a second isolation component 203b in a second region 200B. The etching process 232 is configured to selectively remove the top portion 228a of the first ILD layer 228, while substantially not etching the CESL 226, the gate spacer 214a, and the dummy gate electrode layer of the dummy gate stack 210. After performing the etching process 232, the remaining portion 228b of the first ILD layer 228 may be referred to as the first ILD layer 228b. The removed top portion 228a of the first ILD layer 228 has a thickness T4. The thickness T4 is not less than the thickness T1. That is, after performing the etching process 232, the first trench 230a exposes the top surface of the CESL 226 in the first region 200A. In other words, a portion of the first ILD layer 228 formed above the top surface of the source / drain component 220 is completely removed. In this illustrated embodiment, the thickness T4 is greater than T1.

[0033] When viewed from the Y direction (e.g.) Figure 8A As shown), the depth D1 of the first trench 230a is approximately equal to the thickness T1, and when viewed from the X direction (as shown in the figure), the depth D1 is approximately equal to the thickness T1, and ... when viewed from the X direction (as shown in the figure). Figure 8B As shown), the depth D2 of the first trench 230a is substantially equal to the thickness T4. In this illustrated embodiment, D2 is greater than D1. When viewed from the Y or X direction, the depth D3 of the second trench 230b is substantially equal to the thickness T4. D3 is greater than D1. In other words, as... Figure 8AAs shown, the second trench 230b is deeper than the first trench 230a. The first ILD layer 228b has a top surface 228t. The distance between the top surface 228t and the top surface 208t of the topmost channel layer in the channel layers 208 is no greater than about 4 nm. If this distance is greater than about 4 nm, the dielectric cap formed in the second trench 230b may be too thick, the duration of subsequent etching processes may be increased, and the risk of damage to other surrounding components during subsequent etching processes may increase. In various embodiments, the top surface 228t may be higher than, lower than, or coplanar with the top surface 208t.

[0034] In this disclosure, the parameters of etching process 232 (e.g., etchant flow rate, etching time, etching temperature) are configured to achieve the aforementioned depth and position relationships, while substantially not etching the CESL 226, the gate spacer 214a, and the dummy gate electrode layer of the dummy gate stack 210. In an embodiment, the first ILD layer 228 comprises oxide, and the second layer 226b of CESL 226 comprises silicon nitride. Etching process 232 is dry etching, and the etchant of etching process 232 comprises a combination of hydrogen fluoride (HF) and ammonia (NH3). The etchant gases ammonia (NH3) and hydrogen fluoride (HF) are adsorbed by oxide-based surfaces (e.g., the first ILD layer 228) and nitride-based surfaces (e.g., the second layer 226b of CESL 226 and / or the gate spacer 214a). The etchant gases ammonia (NH3) and hydrogen fluoride (HF) will form ammonium fluoride (NH4F), which facilitates the recessing of the oxide layer (e.g., the first ILD layer 228). During the etching process 232, the chemical reactions may include: HF + NH3 → NH4F, NH4F + SiO2 → (NH4)2SiF6 + H2O, (NH4)2SiF6 → SiF4 + NH3 + HF. More specifically, the reaction between HF and NH3 forms ammonium fluoride (NH4F). Ammonium fluoride (NH4F) then reacts with silicon oxide to form ammonium hexafluorosilicate ((NH4)2SiF6). That is, in this process, ammonium fluoride (NH4F) is used as an etchant to remove or etch the oxide layer (e.g., SiO2). Upon heating, ammonium hexafluorosilicate ((NH4)2SiF6) decomposes to release ammonia (NH3), hydrogen fluoride (HF), and silicon tetrafluoroide (SiF4) gases—this may appear to be a sublimation process, although it is actually a thermal decomposition.

[0035] In this disclosure, high etch selectivity is desired between the oxide layer (e.g., the first ILD layer 228) and the nitride layer (e.g., the second layer 226b of CESL 226). To achieve high etch selectivity between the oxide layer (e.g., the first ILD layer 228) and the nitride layer (e.g., the second layer 226b of CESL 226), the ratio of the flow rate of hydrogen fluoride (HF) to the flow rate of ammonia (NH3) is between about 6:1 and about 1:10. If the ratio is higher than 6:1, the hydrogen fluoride (HF) content in the etchant gas may be too high, resulting in low etch selectivity between the oxide and nitride layers, because hydrogen fluoride (hydrofluoric acid) prefers to adsorb on the nitride-based surface rather than the oxide-based surface. The high ratio may also cause undesirable damage to the nitride-based CESL 226 and the gate spacer 214a. If the ratio is less than about 1:10, the hydrogen fluoride (HF) content in the etchant gas may be too low to generate enough ammonium fluorosilicate (AFS) ((NH4)2SiF6), the oxide layer (i.e., the first ILD layer 228) may be etched at a very low rate, and the duration of the etching process 232 will increase. Figure 9 A graph showing the relationship between the flow rate ratio and the etch selectivity between oxide and silicon nitride is illustrated. In one embodiment, the flow rate ratio of hydrogen fluoride (HF) to ammonia (NH3) is between about 6:1 and about 1:5. In another embodiment, the flow rate ratio of hydrogen fluoride (HF) to ammonia (NH3) is between about 6:1 and about 1:3. To obtain satisfactory etching results, the etching temperature of etching process 232 can be between about 40°C and about 90°C. If the etching temperature is higher than about 90°C, the first ILD layer 228 may recess too quickly, making it impossible to precisely control the extent to which it is etched; if the etching temperature is lower than about 40°C, the reaction rate of the chemical reaction may decrease, and etching process 232 may proceed more slowly, leading to increased manufacturing costs. In some embodiments, etching process 232 may include performing multiple etching cycles. An etching cycle may refer to a repeating sequence of steps for removing the top portion 228a of the first ILD layer 228. The number of etching cycles in etching process 232 can be between about 9 and about 15. If the number of etching cycles is less than 9, the duration of each etching cycle may be too long, increasing the risk of damaging CESL 226 during each etching cycle; if the number of etching cycles is greater than 15, the duration of etching process 232 may be too long, leading to increased manufacturing costs.

[0036] refer to Figure 1 and Figures 10A to 10BMethod 100 includes block 118, wherein a first cap 236a is formed in a first trench 230a and a second cap 236b is formed in a second trench 230b. After forming the first trench 230a and the second trench 230b, a dielectric material layer is deposited over the substrate 202 (including in the first trench 230a and the second trench 230b). The dielectric material layer can be deposited over the precursor structure 200 by atomic layer deposition (ALD), chemical vapor deposition (CVD), or any other suitable deposition process. The dielectric material layer may include silicon nitride, silicon oxycarbide, silicon carbonitride, silicon carbonitride, metal nitride, or other suitable dielectric materials. A dielectric material layer that is more etch-resistant than the first ILD layer 228 relative to certain etchants is selected. In an embodiment, the dielectric material layer includes silicon nitride. After depositing the dielectric material layer, a planarization process is performed to remove excess portions of the dielectric material layer on the dummy gate electrode, thereby defining the final structure of the first cap 236a in the first trench 230a and the second cap 236b in the second trench 230b. The first cap 236a and the second cap 236b typically follow the shapes of the first trench 230a and the second trench 230b, respectively. For example, the thickness of the second cap 236b above the second isolation member 203b is greater than the thickness of the portion of the first cap 236a directly above the source / drain member 220. In an embodiment, the thickness of the second cap 236b directly above the second isolation member 203b is substantially equal to the thickness of the portion of the first cap 236a directly above the first isolation member 203a, which is greater than the thickness of the portion of the first cap 236a directly above the source / drain member 220. Figure 10A In the cross-sectional view shown, the second cap 236b extends over the top surface 228t of the first ILD layer 228b, and the bottom surface of the second cap 236b is lower than the bottom surface of the first cap 236a. The distance between the bottom surface of the second cap 236b and the top surface 208t of the topmost channel layer in the channel layers 208 is no greater than about 4 nm. If this distance is greater than about 4 nm, the second cap 236b may be too thick, potentially increasing the duration of subsequent etching processes and increasing the risk of damaging other surrounding components during those processes. In various embodiments, the bottom surface of the second cap 236b (e.g., the top surface 228t) may be higher than, lower than, or coplanar with the top surface 208t. In the illustrated embodiment, a portion of the first ILD layer 228 disposed directly above the source / drain component 220 is essentially removed, and the first cap 236a is disposed on the CESL 226. However, it should be understood that in various embodiments, the removal of this portion of the first ILD layer 228 is incomplete, and there may be residue of the first ILD layer 228 disposed between CESL 226 and the first cap 236a.

[0037] refer to Figure 1 and Figures 11A to 11B Method 100 includes block 120, wherein the dummy gate stack 210 and sacrificial layer 206 are replaced with gate structure 240. After forming a first cap 236a in a first trench 230a and a second cap 236b in a second trench 230b, a first etching process can be performed to selectively remove the dummy gate electrode layer and dummy gate dielectric layer of the dummy gate stack 210, while substantially not removing the gate spacer 214a to form the gate trench (now filled by gate structure 240). After removing the dummy gate stack 210, a second etching process can be performed to selectively remove the sacrificial layer 206 in the channel region 204C to release the channel layer 208 as channel member 208. The selective removal of the sacrificial layer 206 forms a gate opening below the gate trench (now filled by gate structure 240).

[0038] Gate structures 240 are then formed in the gate trenches and gate openings. Forming the gate structures 240 includes forming an interface layer to enclose the channel members 208. The interface layer may include silicon oxide or other suitable materials. The interface layer may be formed using suitable methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), thermal oxidation, or other suitable methods. In one embodiment, the interface layer is formed by thermal oxidation and is therefore formed only on the surface of the channel members 208. That is, the interface layer does not extend along the sidewall surfaces of the gate spacers 214a and does not extend along the sidewall surfaces of the inner spacer members 218. In another embodiment, the interface layer is formed by ALD and is therefore conformally formed on the surface of the precursor structure 200. That is, the interface layer also extends along the sidewall surfaces of the gate spacers 214a and the sidewall surfaces of the inner spacer members 218. After forming the interface layers, a dielectric layer is formed over the precursor structure 200 to enclose each channel member 208. In one embodiment, the dielectric layer is conformally deposited over the precursor structure 200. To facilitate the description of a layer having a substantially uniform thickness over the various regions, the term "conformal ground" may be used herein. In some embodiments, the dielectric layer is a high-k dielectric layer because its dielectric constant is greater than that of silicon dioxide (~3.9). In some embodiments, the dielectric layer may comprise titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The dielectric constant of the high-k dielectric layer is greater than that of the gate spacer 214a. The dielectric layer and the interface layer can be collectively referred to as the gate dielectric layer. In some embodiments, the gate dielectric layer and the isolation components (e.g., the first isolation component 203a and the second isolation component 203b) are mixed at the interface between the gate dielectric layer and the isolation components.

[0039] The formation of each gate structure 240 also includes forming a gate electrode over the gate dielectric layer. The gate electrode can be deposited over the gate dielectric layer using ALD, physical vapor deposition (PVD), CVD, electron beam evaporation, or other suitable methods. The gate electrode can comprise a single-layer or optionally multi-layer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a liner layer, a wetting layer, an adhesive layer, a metal alloy, or a combination of metal silicides. For example, the gate electrode can comprise titanium nitride, aluminum titanium nitride, aluminum titanium nitride, tantalum nitride, aluminum tantalum nitride, aluminum tantalum carbide, tantalum carbonitride, aluminum, tungsten, nickel, titanium, ruthenium, cobalt, platinum, tantalum carbide, silicon tantalum nitride, copper, other refractory metals, or other suitable metallic materials or combinations thereof. Furthermore, in the case where the semiconductor structure 200 includes n-type transistors and p-type transistors, different gate electrodes can be formed for the n-type transistors and p-type transistors respectively, and these can comprise different work function metal layers (e.g., for providing different n-type and p-type work function metal layers). In various embodiments, the gate electrode may include a titanium-containing metal layer. In some embodiments, such as Figure 11A As shown, the gate electrode includes one or more slits 240s.

[0040] refer to Figure 1 , Figures 12A to 12B and Figures 13A to 13B Method 100 includes a block 122, wherein a first opening 246a and a second opening 246b are formed, respectively extending into a first cap 236a and a second cap 236b. In an exemplary process, regarding Figures 12A to 12B An etch stop layer 242 and a second ILD layer 244 are formed over the gate structure 240 and the source / drain components 220. The etch stop layer 242 may comprise silicon nitride and can be formed by any suitable deposition process. The formation and composition of the second ILD layer 244 are similar to those of the first ILD layer 228, and for simplicity, repeated descriptions are omitted. (See reference...) Figures 13A to 13B A mask element (not shown) can be formed above the second ILD layer 244, and then a combination of photolithography and etching processes can be performed to form a first opening 246a in the first region 200A and a second opening 246b in the second region 200B. After performing the combination of photolithography and etching processes, the second layer 226b can be etched through CESL 226, while the first layer 226a of CESL 226 is essentially left unetched. That is, the first layer 226a of CESL 226 can indicate the end point of the etching, and the etching process can stop when the first layer 226a of CESL 226 is exposed. The first opening 246a and the second opening 246b have the same depth. Since the second cap 236b formed in the second region 200B is thicker than the portion of the first cap 236a formed directly above the source / drain component 220, ... Figure 13A As shown, when viewed from the Y direction, the first cap 236b is almost completely removed, while the second cap 236b is partially removed. Figure 13B As shown, when viewed from the X direction, a portion of the first cap 236a located directly above the first isolation member 203a is partially removed. CESL 226 has a portion that directly contacts the source / drain member 220 and the first dielectric cap 236a. The inner surface of this portion of CESL 226 directly contacts the source / drain member 220, and the outer surface of this portion of CESL 226 directly contacts the first dielectric cap 236a.

[0041] After forming the first opening 246a and the second opening 246b, refer to Figures 14A to 14B A dielectric barrier layer 248 can be formed to extend along the sidewalls of the first opening 246a and the second opening 246b to enhance the isolation between the conductive component to be formed and the gate structure 240. The formation of the dielectric barrier layer 248 may include depositing a dielectric material layer (e.g., silicon nitride (SiN), silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN)) over the substrate 202 (including in the first opening 246a and the second opening 246b) and etching back the dielectric material to form the dielectric barrier layer 248 extending along the sidewalls of the first opening 246a and the second opening 246b.

[0042] refer to Figure 1 and Figures 15A to 15B Method 100 includes block 124, wherein an etching process 247 is performed to vertically extend a first opening 246a to expose a source / drain component 220. The etching process 247 can stop when the top surface of the source / drain component 220 is exposed. In some other embodiments, such as Figures 14A to 14BAs shown, etching process 247 can also remove the top portion of the source / drain component 220 to increase the contact area between the source / drain component 220 and the conductive components formed thereon. The etchant of etching process 247 can etch the first cap 236a and the second cap 236b, CESL 226, and ILD layer 228b. In an embodiment, etching process 247 is dry etching, and the etchant of etching process 247 can be the same as the etchant of etching process 232, and includes a combination of hydrogen fluoride (HF) and ammonia (NH3). The flow rate ratio of hydrogen fluoride (HF) to ammonia (NH3) in etching process 247 is greater than that in etching process 232. That is, the flow rate ratio of hydrogen fluoride (HF) to ammonia (NH3) in etching process 247 is greater than about 6:1. If the ratio is less than approximately 6:1, the ammonia (NH3) content in the etchant gas may be too low to remove a portion of the first layer 226a of CESL 226 exposed by the first trench 230a. Etching process 247 etches the ILD layer 228b and the first layer 226a of CESL 226 at a first rate, and etches the first cap 236a and the second cap 236b at a second rate less than the first rate. Since the source / drain component 220 is not covered by the first dielectric cap 236a, while a portion of the ILD layer 228b above the second region 200B is covered by the second cap 236b before etching process 247, the degree of recess of the ILD layer 228b above the second region 200B during etching process 247 is reduced compared to some prior art. Therefore, the source / drain contacts (e.g., formed in the second region 200B and above the second isolation component 203b) are... Figure 21A The second source / drain contact 252 shown will have a reduced depth, thereby reducing the parasitic capacitance associated with the source / drain contact 252 in the second region 200B. In various embodiments, the etch selectivity between the first ILD layer 228 and the second layer 226b of CESL 226 relative to etch process 232 is higher than the etch selectivity between the first cap 236a and the first layer 226a of CESL 226 relative to etch process 247. The etch rate difference between etch process 232 etching the first ILD layer 228 and the second layer 226b of CESL 226 is greater than the etch rate difference between etch process 247 etching the first cap 236a and the first layer 226a of CESL 226.

[0043] After etching process 247 is performed, the first opening 246a and the second opening 246b can be referred to as the first opening 246a' and the second opening 246b', respectively. When viewed from the Y direction, as shown... Figure 15AAs shown, the first opening 246a' extends through CESL226 and the first cap 236a to expose the source / drain component 220. The first opening 246a' has a depth D5 directly above the source / drain component 220. When viewed from the Y direction, as... Figure 15A As shown, the second opening 246b' extends through CESL 226, the second cap 236b, and into the first ILD layer 228. The second opening 246b' has a depth D6 directly above the second isolation member 203b. Depth D6 is greater than depth D5. The bottom surface of the second opening 246b' may be coplanar with or below the top surface 208t, and may be coplanar with or above the top surface of the channel member directly below the topmost one of the channel members 208 (e.g., the middle one of the channel members 208). Figure 15B As shown, when viewed from the X direction, the first opening 246a' has a depth D7 directly above the first isolation member 203a. In an embodiment, the first opening 246a (as shown) Figure 14B As shown, the width W1 along the Y direction is greater than the second opening 246b (as shown). Figure 14A As shown, the width W2 along the X direction means that the etching process 247 can etch the portion of the first ILD layer 228b exposed by the first opening 246a at a higher rate than the portion of the first ILD layer 228b exposed by the second opening 246b, and the depth D6 can be less than the depth D7. In some embodiments, when viewed from the X direction, the depth of the second opening 246b can be substantially equal to the depth D7.

[0044] refer to Figure 1 and Figures 16A to 16BMethod 100 includes block 126, wherein a first S / D contact 250 is formed in a first opening 246a' in a first region 200A, and a second source / drain contact 252 is formed in a second opening 246b' in a second region 200B. A silicide layer 249 may be formed in the first opening 246a' and the first region 200A. To form the silicide layer 249, a metal layer (via ALD, CVD, and / or other deposition processes) is deposited over the precursor structure 200 (including in the first opening 246a' and the second opening 246b'), and then an annealing process is performed to induce a silicide reaction between the metal layer and the source / drain components 220. Excess portions of the metal layer where the silicide layer 249 is not formed may be removed. Suitable metal layers may include titanium, tantalum, nickel, cobalt, or tungsten. In embodiments where the metal layer includes nickel and the source / drain component 220 includes silicon-germanium, the silicide layer 249 includes nickel silicide, nickel germanide, and nickel-germanium silicon. In some other embodiments, the silicide layer 249 may include titanium silicide, tantalum silicide, cobalt silicide, or tungsten silicide. In these embodiments, the conductivity of the silicide layer 249 is greater than the conductivity of the source / drain component 220.

[0045] After forming the silicide layer 249, a conductive layer can be deposited over the precursor structure 200 to fill the first opening 246a' and the second opening 246b'. The conductive layer may include aluminum, rhodium, ruthenium, copper, iridium, or tungsten. A planarization process (such as CMP) can then be performed to remove excess portions of the conductive layer over the second ILD layer 242, thereby forming a first S / D contact 250 in the first opening 246a' of the first region 200A and a second S / D contact 252 in the second opening 246b' of the second region 200B. In some other alternative embodiments, such as... Figures 21A to 21BAs shown, the planarization process can be stopped upon reaching the top surface of the etch stop layer 242 or upon removing the etch stop layer 242. The first S / D contact 250 typically follows the shape of the first opening 246a', and the second S / D contact 252 typically follows the shape of the second opening 246b'. When viewed from the Y direction, the depth of the second S / D contact 252 is greater than the depth of the first S / D contact 250. The top surface of the first S / D contact 250 is coplanar with the top surface of the second S / D contact 252. When viewed from the Y direction, the bottom surface of the second S / D contact 252 may be coplanar with or below the top surface 208t of the topmost of the channel members 208, and above the top surface of the bottommost of the channel members 208. The first S / D contact 250 is electrically coupled to the source / drain member 220 through the silicide layer 249. Although the second S / D contact 252 is not formed above the source / drain component 220, it is formed together with the first S / D contact 250 by performing a common process, and therefore can be referred to as a source / drain contact. In the embodiment, the conductivity of the first source / drain contact 250 and the second source / drain contact 252 is greater than the conductivity of the silicide layer 249, and the conductivity of the silicide layer 245 is greater than the conductivity of the source / drain component 220.

[0046] refer to Figure 1 , Figure 17 and Figures 18A to 18B Method 100 includes block 128, in which further processes are performed. Figure 17 A partial top view of the precursor structure 200 is depicted. Figure 18A and Figure 18B Depicting along Figure 17 The diagram shows a partial cross-sectional view of the precursor structure 100 taken along lines A-A' and B-B'. This further process may include forming a gate via 256 and a source / drain via 258 in the dielectric structure 254. The dielectric structure 254 may resemble a combination of an etch stop layer 242 and a second ILD layer 244. This further process may also include forming a first multilayer interconnect (MLI) structure (not shown) above the precursor structure 200 and / or forming a second multilayer interconnect (MLC) structure (not shown) below the precursor structure 200. Each of the first MLI structure and the second MLI structure may include various interconnect components (such as vias and wires) disposed in the dielectric layers (such as etch stop layers and ILD layers). In some embodiments, vias are vertical interconnect components configured as interconnect device level contacts.

[0047] In some other embodiments, the parameters and duration of the etching process 247 can be varied to adjust the contours of the first S / D contact 250 and the second S / D contact 252. For example, in Figures 19A to 19B In the alternative embodiment shown, etching process 247 can be configured to etch the first layer 226a of CESL 226, while substantially leaving the source / drain components 220 unetched. The ILD layer 228b is lightly etched. In this alternative embodiment, the first S / D contact 250 extends through the first cap 236a, and the second S / D contact 252 extends through the second cap 236b. Figure 19A In the cross-sectional view shown, the bottom surface of the second S / D contact 252 is lower than the bottom surface of the first S / D contact 250, and higher than or coplanar with the top surface 208t of the topmost member of the channel member 208. In another embodiment, the duration of the etching process 247 can be shortened such that the first S / D contact 250 extends through the first layer 226a of the CESL 226 without extending through the first cap 236a, and the second S / D contact 252 can be disposed above or extend into the second cap 236b.

[0048] exist Figures 20A to 20B In another alternative embodiment shown, the CESL 226 can be recessed during etching process 247 or another etching process, thereby increasing the contact area between the source / drain component 220 and the silicide layer 249. For example... Figure 20B As shown, CESL 226 is perpendicularly spaced from the first cap 236a. In this illustrated embodiment, the source / drain component 220 is substantially unetched. In some other embodiments, the source / drain component 220 may be recessed, and the contours of the source / drain component 220 and the silicide layer 249 may be similar to... Figures 18A to 18B The outline shown.

[0049] Reference Figures 16A to 16B In the described embodiment, the planarization process for finalizing the structure of the first S / D contact 250 and the second S / D contact 252 stops on the top surface of the second ILD layer 244. Figures 21A to 21B In another alternative embodiment shown, the planarization process may stop on the top surface of the etch stop layer 242. In some other embodiments, the planarization process may also remove the etch stop layer 242 and stop on the top surface of the first cap 236a. This disclosure includes multiple embodiments, and the various embodiments may be combined in different ways, all of which are within the scope of this disclosure.

[0050] As referenced above Figure 15A The bottom surface of the second opening 246b' may be coplanar with the channel member (e.g., the middle one of the channel members 208) located directly below the topmost one of the channel members 208. Figures 22A to 22BThis alternative embodiment is depicted in which the bottom surface of the second source / drain contact 252 is substantially coplanar with the bottom surface of the channel member (e.g., the middle one of the channel members 208) located directly below the topmost one of the channel members 208.

[0051] While not intended to be limiting, one or more embodiments of this disclosure provide numerous benefits for semiconductor structures and their formation. For example, this disclosure provides a method for reducing the depth of an S / D contact formed adjacent to the edge of an active region and above an isolation component. By reducing the depth of the S / D contact, the parasitic capacitance between the S / D contact and adjacent conductive components (e.g., a gate structure) can be reduced. In embodiments, the coupling capacitance between the S / D contact and the gate structure is reduced by 9%, and the effective parasitic capacitance of the semiconductor structure is reduced by 2%. Furthermore, the materials of the first and second dielectric caps (e.g., a nitride layer) are more etch-resistant than the material of the first ILD layer (e.g., an oxide layer), thus reducing the risk of gate structure protrusion. As a result, the performance of the semiconductor structure (e.g., ring oscillator (RO) performance, reliability) can be improved. Moreover, the above embodiments are described based on semiconductor structures including gate-all-around (GAA) transistors. However, it should be understood that the concepts of this disclosure can be applied to semiconductor structures including complementary field-effect transistors (CFETs) (e.g., CFETs with vertically stacked N-type and P-type transistors), semiconductor structures including fin structure transistors (e.g., FinFETs), semiconductor structures including fork-plate transistors, or various combinations thereof.

[0052] This disclosure provides numerous different embodiments. Semiconductor structures and methods of fabricating them are disclosed herein. In one exemplary aspect, this disclosure relates to a method. The method includes: receiving a precursor structure comprising: a plurality of nanostructures located above a substrate; a gate structure located above the plurality of nanostructures; the gate structure including a gate dielectric layer located above the plurality of nanostructures and a gate electrode located above the gate dielectric layer; source / drain components coupled to the plurality of nanostructures; and an interlayer dielectric (ILD) layer located above the substrate; selectively removing a portion of the ILD layer above the source / drain components to form a trench, wherein the bottom surface of the trench is lower than the top surface of the source / drain components; forming a dielectric cap in the trench and on the ILD layer, wherein the dielectric cap and the ILD layer comprise different compositions; and forming source / drain contacts extending through the dielectric cap to couple to the source / drain components, wherein the conductivity of the source / drain contacts is greater than the conductivity of the source / drain components.

[0053] In some embodiments, forming the source / drain contact may include performing a first etching process to recess the dielectric cap without exposing the top surface of the source / drain component, thereby forming an opening, and performing a second etching process to extend the opening vertically, thereby exposing the top surface of the source / drain component. In some embodiments, the method may further include forming a dielectric liner extending along the sidewalls of the opening prior to performing the second etching process. In some embodiments, the precursor structure may further include an etch stop layer disposed between the source / drain component and the ILD layer, wherein the etch stop layer is not completely removed from the top surface of the source / drain component during the first etching process. In some embodiments, the bottom surface of the dielectric cap is substantially coplanar with the top surface of the topmost of a plurality of nanostructures. In some embodiments, the ILD layer may include an oxide, and the dielectric cap may include silicon nitride. In some embodiments, selectively removing a portion of the ILD layer above the source / drain component may include performing an etching process in which the etchant includes hydrogen fluoride (HF) and ammonia (NH3). In some embodiments, the flow rate ratio of hydrogen fluoride (HF) to ammonia (NH3) is between about 6:1 and about 1:10. In some embodiments, the source / drain components are configured to be adjacent to a plurality of nanostructures along a direction, and the precursor structure may further include an isolation component configured to be adjacent to the source / drain components along the direction, and the ILD layer further extends into the isolation component. In some embodiments, the method may further include forming a conductive component directly above the isolation component, the conductive component extending through a dielectric cap, and in a cross-sectional view, the bottom surface of the conductive component being lower than the bottom surface of the source / drain contacts.

[0054] In another exemplary aspect, this disclosure relates to a method. The method includes forming an active region extending along a first direction, the active region including a channel region and source / drain components adjacent to the channel region; forming an isolation component adjacent to an end portion of the active region along the first direction; depositing an etch stop layer over the source / drain components and the isolation component; forming a dielectric layer on the etch stop layer; selectively removing a top portion of the dielectric layer to expose a top surface of the etch stop layer; after selective removal, forming a dielectric cap over the etch stop layer, wherein the dielectric cap and the dielectric layer comprise different components; and forming a conductive component extending through the dielectric cap and located over the isolation component, the conductive component having a conductivity greater than that of the source / drain components.

[0055] In some embodiments, the method may further include forming source / drain contacts over source / drain components, wherein, in a cross-sectional view, the conductive components and the source / drain contacts have different depths. In some embodiments, the method may further include: after forming a dielectric cap, performing a first etching process to recess the dielectric cap to expose the top surface of an etch stop layer, and performing a second etching process to etch through the etch stop layer to expose the source / drain components, wherein performing the first and second etching processes also forms a trench over an isolation component, a conductive component is formed in the trench, and a source / drain contact electrically coupled to the source / drain components is formed over the source / drain components. In some embodiments, selectively removing the top portion of the dielectric layer may include performing a third etching process, the etchant of which comprises a combination of hydrogen fluoride (HF) and ammonia (NH3). In some embodiments, the flow rate ratio of hydrogen fluoride (HF) to ammonia (NH3) is between about 6:1 and about 1:10. In some embodiments, the dielectric layer may include a first portion extending over a source / drain component and a second portion extending over an isolation component, the first portion having a first thickness, the second portion having a second thickness greater than the first thickness, and the thickness of the top portion of the dielectric layer not less than the first thickness.

[0056] In another exemplary aspect, this disclosure relates to a semiconductor structure. The semiconductor structure includes: an active region extending longitudinally along a first direction, the active region including a channel region and source / drain components adjacent to the channel region; a gate structure located above the channel region and extending along a second direction different from the first direction; source / drain contacts located above the source / drain components and electrically coupled to the source / drain components; an isolation component in contact with an end portion of the active region; a dielectric layer extending above the isolation component; a dielectric cap located on the dielectric layer, wherein the dielectric cap and the dielectric layer comprise different compositions; and a conductive component extending through the dielectric cap.

[0057] In some embodiments, the conductive components and source / drain contacts have different depths in the cross-sectional view. In some embodiments, the semiconductor structure may further include an etch stop layer extending along the sidewalls of the dielectric layer, wherein the top surface of the etch stop layer is higher than the top surface of the dielectric cap in the cross-sectional view. In some embodiments, the semiconductor structure may further include a dielectric liner configured to enhance isolation between the gate structure and the conductive components.

[0058] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and alterations can be made to them herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor structure, comprising: Receiving precursor structure, the precursor structure comprising: Multiple nanostructures are located above the substrate. A gate structure is located above the plurality of nanostructures, the gate structure comprising a gate dielectric layer located above the plurality of nanostructures and a gate electrode located above the gate dielectric layer. Source / drain components, coupled to the plurality of nanostructures, and An interlayer dielectric (ILD) layer is located above the substrate; A portion of the interlayer dielectric layer above the source / drain components is selectively removed to form a trench, wherein the bottom surface of the trench is lower than the top surface of the source / drain components; A dielectric cap is formed in the trench and on the interlayer dielectric layer, wherein the dielectric cap and the interlayer dielectric layer comprise different components; and A source / drain contact is formed, the source / drain contact extending through the dielectric cap to couple to the source / drain component, wherein the conductivity of the source / drain contact is greater than the conductivity of the source / drain component.

2. The method according to claim 1, wherein, The formation of the source / drain contact includes: Perform a first etching process to recess the dielectric cap and thus conceal the top surface of the source / drain components, thereby forming an opening; and A second etching process is performed to extend the opening vertically, thereby exposing the top surface of the source / drain components.

3. The method according to claim 2, further comprising: Prior to performing the second etching process, a dielectric liner extending along the sidewall of the opening is formed.

4. The method according to claim 2, wherein, The precursor structure also includes: An etch stop layer is disposed between the source / drain components and the interlayer dielectric layer. During the first etching process, the etch stop layer was not completely removed from the top surface of the source / drain component.

5. The method according to claim 1, wherein, The bottom surface of the dielectric cap is substantially coplanar with the top surface of the topmost nanostructure among the plurality of nanostructures.

6. The method according to claim 1, wherein, The interlayer dielectric layer comprises an oxide, and the dielectric cap comprises silicon nitride.

7. The method according to claim 6, wherein, The selective removal of the portion of the interlayer dielectric layer above the source / drain components includes performing an etching process in which the etchant comprises hydrogen fluoride (HF) and ammonia (NH3).

8. The method according to claim 6, wherein, The ratio of the flow rate of hydrogen fluoride (HF) to the flow rate of ammonia (NH3) is between about 6:1 and about 1:

10.

9. A method for forming a semiconductor structure, comprising: An active region is formed extending along a first direction, the active region including a channel region and source / drain components adjacent to the channel region; An isolation component is formed that connects to the end portion of the active region along the first direction; An etch stop layer is deposited over the source / drain components and the isolation components; A dielectric layer is formed on the etch stop layer; Selectively remove the top portion of the dielectric layer to expose the top surface of the etch stop layer; Following the selective removal, a dielectric cap is formed over the etch stop layer, wherein the dielectric cap and the dielectric layer comprise different components; and A conductive component is formed extending through the dielectric cap and located above the isolation component, wherein the conductivity of the conductive component is greater than the conductivity of the source / drain component.

10. A semiconductor structure comprising: An active region extends longitudinally along a first direction, the active region including a channel region and source / drain components adjacent to the channel region; A gate structure is located above the channel region and extends along a second direction different from the first direction; Source / drain contacts are located above the source / drain components and electrically coupled to the source / drain components; An isolation component is connected to the end portion of the active region; A dielectric layer extends above the isolation component; A dielectric cap is located on the dielectric layer, wherein the dielectric cap and the dielectric layer comprise different components; as well as A conductive component extends through the dielectric cap.

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