Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a manufacturing method thereof, the method comprising: providing a substrate, the substrate having a first conductive type transistor and a second conductive type transistor formed thereon; forming a contact hole etching stop layer covering both; wherein the contact hole etching stop layer has a first type stress, and the contact hole etching stop layer comprises a first region covering the first conductive type transistor and a second region covering the second conductive type transistor; forming a mask layer covering the first region and exposing the second region; performing a modification treatment on the exposed second region, converting part of the thickness of the second region into a modified layer, and leaving an unconverted part of the second region at the bottom of the modified layer, the modified layer having a second type stress; and removing the mask layer. The application enables the two conductive type transistors to obtain corresponding type stress which is beneficial to the improvement of the carrier mobility of the self type, and realizes the common improvement of the electrical performance of different conductive type transistors on the same substrate.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] In semiconductor integrated circuit manufacturing processes, as technology nodes continue to shrink, stress engineering is widely used to improve device performance to meet design requirements.

[0003] Taking the fabrication of contact holes in complementary metal-oxide-semiconductor (CMOS) devices as an example, after forming N-type MOS devices and P-type MOS devices on the substrate, a silicon nitride layer covering the N-type MOS devices and P-type MOS devices needs to be deposited using plasma-enhanced chemical vapor deposition (PECVD). This silicon nitride layer serves as an etch stop layer in the subsequent contact hole etching process. Furthermore, because the silicon nitride layer fabricated using PCVD typically possesses inherent tensile stress, it can improve the carrier mobility within the channel of the N-type MOS device, thereby improving the electrical performance of the N-type MOS device.

[0004] However, for P-type MOS devices located on the same substrate, since compressive stress is beneficial to their performance improvement, the tensile stress introduced by the globally deposited silicon nitride layer will reduce the hole carrier mobility in the channel of the P-type MOS device, thereby causing the electrical performance of the P-type MOS device to degrade. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, this application provides a method for manufacturing a semiconductor device, comprising: A substrate is provided on which a first conductivity type transistor and a second conductivity type transistor are formed; wherein the first conductivity type transistor and the second conductivity type transistor have opposite conductivity types; A contact hole etch stop layer is formed covering the first conductivity type transistor and the second conductivity type transistor; wherein the contact hole etch stop layer has a first type stress, and the contact hole etch stop layer includes a first region covering the first conductivity type transistor and a second region covering the second conductivity type transistor; A mask layer is formed, which covers a first region of the contact hole etch stop layer and exposes a second region of the contact hole etch stop layer; The second region of the exposed contact hole etching stop layer is modified by converting a portion of the thickness of the second region into a modified layer, and retaining an unconverted portion of the second region at the bottom of the modified layer. The modified layer has a second type of stress; wherein the first type of stress and the second type of stress are opposite in type. Remove the mask layer.

[0007] In some embodiments of this application, the first conductivity type transistor is an N-type MOS device and the second conductivity type transistor is a P-type MOS device, the first type of stress is tensile stress and the second type of stress is compressive stress.

[0008] In some embodiments of this application, the material of the contact hole etch stop layer includes nitrides, and the material of the modified layer includes oxides.

[0009] In some embodiments of this application, the modification treatment of the second region of the exposed contact hole etch stop layer includes: The second region of the exposed contact hole etch stop layer is subjected to hydrogen plasma treatment and oxidation treatment in sequence.

[0010] In some embodiments of this application, the first conductivity type transistor is a P-type MOS device and the second conductivity type transistor is an N-type MOS device, the first type of stress is compressive stress and the second type of stress is tensile stress.

[0011] In some embodiments of this application, the contact hole etch stop layer is formed using a plasma-enhanced chemical vapor deposition process.

[0012] In some embodiments of this application, the thickness of the modified layer is greater than the thickness of the unconverted portion of the second region retained at the bottom of the modified layer.

[0013] In some embodiments of this application, after removing the mask layer, the manufacturing method further includes: An interlayer dielectric layer is formed in the first region of the contact hole etching stop layer and on the modified layer; Perform planarization on the interlayer dielectric layer; The interlayer dielectric layer is etched until it penetrates the underlying modified layer and the contact hole etch stop layer to form contact holes that expose the corresponding regions of the first conductivity type transistor and the second conductivity type transistor.

[0014] This application further provides a semiconductor device, comprising: A substrate on which a first conductivity type transistor and a second conductivity type transistor are formed, wherein the first conductivity type transistor and the second conductivity type transistor have opposite conductivity types; A contact hole etch stop layer covers the first conductivity type transistor and the second conductivity type transistor. The contact hole etch stop layer has a first type of stress. The contact hole etch stop layer includes a first region covering the first conductivity type transistor and a second region covering the second conductivity type transistor. A modified layer is located on the second region, and the top surface of the modified layer is flush with the top surface of the first region; wherein the modified layer has a second type of stress, and the first type of stress is the opposite of the second type of stress.

[0015] In some embodiments of this application, the thickness of the modified layer is greater than the thickness of the second region.

[0016] The semiconductor device and its manufacturing method disclosed in this application overcome the limitations of contact hole etch stop layers with a single type of stress globally deposited in related technologies. While ensuring that the contact hole etch stop layer plays a reliable etch stop role in subsequent processes, it enables transistors with two opposite conductivity types to obtain corresponding types of stress that are beneficial to their own carrier mobility improvement. This avoids the problem of reduced carrier mobility and electrical performance degradation in the channel of one type of transistor caused by the introduction of a single stress globally, and achieves the common improvement of electrical performance of transistors with different conductivity types on the same substrate. Attached Figure Description

[0017] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0018] In the attached image: Figures 1A-1D A flowchart illustrating the manufacturing process of contact holes in complementary metal-oxide-semiconductor devices in the related art is shown.

[0019] Figure 2 A flowchart illustrating a method for manufacturing a semiconductor device according to one specific embodiment of this application is shown.

[0020] Figures 3A-3F This illustration shows a cross-sectional schematic diagram of a semiconductor device obtained by sequentially implementing a method for manufacturing a semiconductor device according to a specific embodiment of this application. Detailed Implementation

[0021] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0022] It should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0023] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0024] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0025] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0026] In related technologies, such as Figures 1A-1D As shown, the manufacturing process of contact holes in complementary metal-oxide-semiconductor devices is as follows: First, such as Figure 1A As shown, a substrate is provided, and N-type MOS devices and P-type MOS devices are formed on the substrate; After that, as Figure 1B As shown, a silicon nitride layer 110 covering the N-type MOS device and the P-type MOS device is deposited by plasma-enhanced chemical vapor deposition as an etch stop layer for subsequent contact hole etching process. The silicon nitride layer 110 has tensile stress, which can improve the carrier mobility in the channel of the N-type MOS device and improve the electrical performance of the N-type MOS device. Next, as Figure 1C As shown, an interlayer dielectric layer 120 is deposited on the silicon nitride layer 110, and the global planarization of the interlayer dielectric layer 120 is achieved by a chemical mechanical polishing process. Subsequently, as Figure 1D As shown, the photolithography and etching process of the contact hole 130 is performed, using the previously formed silicon nitride layer as the etching stop layer.

[0027] However, for P-type MOS devices located on the same substrate, since compressive stress is beneficial to their performance improvement, the tensile stress introduced by the globally deposited silicon nitride layer 110 will reduce the hole carrier mobility in the channel of the P-type MOS device, thereby causing the electrical performance of the P-type MOS device to degrade.

[0028] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0029] Example 1 Below, for reference Figure 2 A method for manufacturing a semiconductor device according to an embodiment of this application is described. For example... Figure 2As shown, a method for manufacturing a semiconductor device may include the following steps: Step S1: Provide a substrate on which a first conductivity type transistor and a second conductivity type transistor are formed; wherein the first conductivity type transistor and the second conductivity type transistor have opposite conductivity types. Step S2: Form a contact hole etch stop layer covering the first conductivity type transistor and the second conductivity type transistor; wherein the contact hole etch stop layer has a first type of stress, and the contact hole etch stop layer includes a first region covering the first conductivity type transistor and a second region covering the second conductivity type transistor; Step S3: Form a mask layer that covers the first region of the contact hole etch stop layer and exposes the second region of the contact hole etch stop layer; Step S4: Modify the second region of the exposed contact hole etching stop layer by converting a portion of the thickness of the second region into a modified layer, and retaining an unconverted portion of the second region at the bottom of the modified layer. The modified layer has a second type of stress; wherein the first type of stress and the second type of stress are opposite in type. Step S5: Remove the mask layer.

[0030] The manufacturing method of this embodiment, after forming a contact hole etch stop layer with a first type of stress, uses a mask layer to cover the first region of the contact hole etch stop layer and exposes the second region of the contact hole etch stop layer. Then, the exposed second region is modified to convert part of its thickness into a modified layer with the opposite second type of stress, while retaining the unconverted part at the bottom. This overcomes the limitation of globally depositing a contact hole etch stop layer with a single type of stress in related technologies. Under the premise of ensuring that the contact hole etch stop layer plays a reliable etch stop role in subsequent processes, it enables transistors with two opposite conductivity types to obtain corresponding types of stress that are beneficial to their own carrier mobility improvement. This avoids the problem of reducing the carrier mobility and degrading the electrical performance in the channel of one type of transistor due to the introduction of a single stress globally, and achieves the common improvement of the electrical performance of transistors with different conductivity types on the same substrate.

[0031] The manufacturing method described above will be explained in more detail below.

[0032] First, step S1 is performed to provide a substrate on which a first conductivity type transistor and a second conductivity type transistor are formed; wherein the first conductivity type transistor and the second conductivity type transistor have opposite conductivity types.

[0033] The substrate can be any suitable substrate, such as a bulk silicon substrate, or at least one of the following materials: Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or it can be a double-side polished wafer (DSP), or a ceramic substrate such as alumina, a quartz substrate, or a glass substrate.

[0034] In one specific embodiment, the substrate is preferably a silicon substrate with a (110) crystal phase, which helps to precisely and effectively control the carrier mobility in the channels of transistors of different conductivity types by applying tensile or compressive stress in subsequent processes.

[0035] On a substrate, a first conductivity type transistor and a second conductivity type transistor are formed through semiconductor front-end processing. Both include structures such as a gate, a source, and a drain. The first conductivity type transistor is one of an N-type MOS device with electrons as the majority carrier and a P-type MOS device with holes as the majority carrier. The second conductivity type transistor is the other of an N-type MOS device with electrons as the majority carrier and a P-type MOS device with holes as the majority carrier.

[0036] Next, step S2 is performed to form a contact hole etch stop layer covering the first conductivity type transistor and the second conductivity type transistor; wherein the contact hole etch stop layer has a first type of stress, and the contact hole etch stop layer includes a first region covering the first conductivity type transistor and a second region covering the second conductivity type transistor.

[0037] Specifically, commonly used deposition processes in the field, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), can be used to form a contact hole etch stop layer covering the first conductivity type transistor and the second conductivity type transistor. Plasma-enhanced chemical vapor deposition is preferred for forming the contact hole etch stop layer.

[0038] The contact hole etch stop layer can be artificially divided into a first region covering the first type of transistor and a second region covering the second type of transistor. This division is only for ease of description and does not represent that there is an actual physical interface between the two.

[0039] It should be noted that before the subsequent modification treatment of the second region of the contact hole etch stop layer, the entire contact hole etch stop layer (including the first and second regions) exhibits Type I stress. After the subsequent modification treatment of the second region of the contact hole etch stop layer, a portion of the thickness of the second region is transformed into a modified layer with Type II stress, while the first region of the contact hole etch stop layer and the untransformed portion of the second region retained at the bottom of the modified layer remain unchanged and still exhibit Type I stress. Specifically, Type I stress and Type II stress are opposite in type; Type I stress is one of tensile stress and compressive stress, while Type II stress is the other of tensile stress and compressive stress.

[0040] Furthermore, to improve carrier mobility within the channels of the first and second conductivity type transistors, the stress type of the first region of the contact hole etch stop layer should match the conductivity type of the first conductivity type transistor. Similarly, after subsequent modification of the second region of the contact hole etch stop layer, the type of the second stress in the modified layer (resulting from a portion of its thickness) should also match the conductivity type of the second conductivity type transistor. For example, when the first conductivity type transistor is an N-type MOS device and the second conductivity type transistor is a P-type MOS device, the corresponding first stress is tensile stress, and the second stress is compressive stress; conversely, when the first conductivity type transistor is a P-type MOS device and the second conductivity type transistor is an N-type MOS device, the corresponding first stress is compressive stress, and the second stress is tensile stress.

[0041] Next, step S3 is performed to form a mask layer that covers the first region of the contact hole etch stop layer and exposes the second region of the contact hole etch stop layer.

[0042] In the specific process implementation, photolithography is typically used to prepare and form this mask layer. Specifically, firstly, a layer of photoresist material is uniformly coated on the entire surface of the contact hole etch stop layer; then, the photoresist layer is exposed using a photomask with a preset pattern; finally, the photoresist layer on the surface of the second region of the contact hole etch stop layer is removed by a development process, and the photoresist layer remaining on the surface of the first region of the contact hole etch stop layer constitutes the aforementioned mask layer.

[0043] Next, step S4 is performed to modify the second region of the exposed contact hole etching stop layer, converting part of the thickness of the second region into a modified layer, and retaining the unconverted part of the second region at the bottom of the modified layer. The modified layer has a second type of stress; wherein the first type of stress and the second type of stress are opposite in type.

[0044] Specifically, when the first conductivity type transistor is an N-type MOS device and the second conductivity type transistor is a P-type MOS device, the first type of stress in the first region of the contact hole etch stop layer is tensile stress, which improves the electron carrier mobility in the N-type MOS device channel. To avoid the tensile stress introduced by the globally deposited contact hole etch stop layer reducing the hole carrier mobility in the P-type MOS device channel, this embodiment modifies the second region of the exposed contact hole etch stop layer, converting a portion of the thickness of the second region into a modified layer. This modified layer then exhibits compressive stress, thereby improving the hole carrier mobility in the P-type MOS device channel. Conversely, when the first conductivity type transistor is a P-type MOS device and the second conductivity type transistor is an N-type MOS device, the first type of stress in the first region of the contact hole etch stop layer is compressive stress, which improves the hole carrier mobility in the P-type MOS device channel. To avoid the compressive stress introduced by the globally deposited contact hole etch stop layer reducing the electron carrier mobility in the N-type MOS device channel, this embodiment modifies the second region of the exposed contact hole etch stop layer, converting a portion of the thickness of the second region into a modified layer. This modified layer then exhibits tensile stress, thereby improving the electron carrier mobility in the N-type MOS device channel. This allows both N-type and P-type MOS devices to obtain stresses conducive to improving their own carrier mobility, achieving a combined improvement in the electrical performance of transistors with different conductivity types on the same substrate.

[0045] It is worth noting that, in order to make the second region of the contact hole etching stop layer exhibit the second type of stress dominance as a whole, the thickness of the modified layer can be greater than the thickness of the unconverted portion of the second region retained at the bottom of the modified layer.

[0046] In addition, the unconverted second region retained at the bottom of the modified layer, together with the unmodified first region, can continue to serve as a qualified contact hole etching stop layer, playing a blocking and protective role in subsequent contact hole etching processes, and preventing the underlying active area and gate structure from being etched and damaged.

[0047] Next, step S5 is performed to remove the mask layer.

[0048] In specific process implementation, when the mask layer uses photoresist material, plasma ashing is usually used to oxidize and decompose the photoresist polymer into volatile gases. Then, a wet cleaning process (such as SPM cleaning solution of sulfuric acid and hydrogen peroxide) is used to thoroughly remove any photoresist by-products or organic particles that may remain on the surface.

[0049] By performing this removal step, the first region of the unconverted contact hole etch stop layer is fully exposed again. Thus, a thin film with a differentiated stress distribution is formed on the same substrate surface: the region above the first conductivity type transistor retains the original first type stress, while the region above the second conductivity type transistor exhibits a modified layer that, after chemical conversion, primarily displays the opposite second type stress, along with the unconverted second region retained at the bottom.

[0050] Next, after removing the mask layer, the manufacturing method further includes: forming an interlayer dielectric layer on the first region of the contact hole etch stop layer and the modification layer; performing a planarization process on the interlayer dielectric layer; and etching the interlayer dielectric layer until it penetrates the underlying modification layer and the contact hole etch stop layer to form contact holes that expose the corresponding regions of the first conductivity type transistor and the second conductivity type transistor.

[0051] In the specific implementation of the process, commonly used deposition processes in this field, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), can be used to form an interlayer dielectric layer on the first region of the contact hole etch stop layer and the modified layer. The material of the interlayer dielectric layer can be an oxide, such as silicon dioxide, and there is no limitation on this.

[0052] Due to the presence of underlying three-dimensional structures such as transistors, the surface of the deposited interlayer dielectric layer typically exhibits an uneven morphology. Therefore, planarization of the interlayer dielectric layer is subsequently required. Chemical mechanical polishing (CMP) is commonly used in the art to remove excess interlayer dielectric material from the surface, eliminating morphological height differences and thus providing a smooth surface for subsequent contact hole etching processes.

[0053] Contact hole etching typically involves two stages in practice. The first stage is the main etching stage, where a thicker interlayer dielectric layer and modification layer are etched downwards. During this stage, the first region of the contact hole etch stop layer and the unconverted portion of the modification layer at the bottom act as etch stoppers. Because there is a significant etch selectivity between the interlayer dielectric layer and modification layer (e.g., silicon dioxide) and the contact hole etch stop layer (e.g., silicon nitride), excessive downward etching by the plasma is effectively prevented, thus protecting the underlying active regions and gate structures from etching damage. The second stage is the breakthrough etching stage, where the chemiluminescence of the etching gas is switched to continue etching downwards and penetrate the aforementioned contact hole etch stop layer, exposing the corresponding conductive regions of the source, drain, or gate of the first and second conductivity types of transistors. The contact holes formed at this point provide the foundation for subsequent filling with conductive metals (e.g., tungsten or cobalt) to construct the electrical connection between the transistor and the upper interconnect metal lines.

[0054] In one specific embodiment, the tensile stress introduced by the globally deposited contact hole etch stop layer reduces the hole carrier mobility in the channel of a P-type MOS device as an example.

[0055] like Figure 3A As shown, a first conductivity type transistor and a second conductivity type transistor are first formed on the substrate, wherein the first conductivity type transistor is an N-type MOS device and the second conductivity type transistor is a P-type MOS device.

[0056] Next, as Figure 3B As shown, a contact hole etch stop layer 210 is formed to cover N-type MOS devices and P-type MOS devices. The contact hole etch stop layer 210 includes a first region covering the N-type MOS devices and a second region covering the P-type MOS devices. The first type of stress of the contact hole etch stop layer 210 is tensile stress.

[0057] For example, the contact hole etch stop layer 210 is preferably made of a nitride, such as silicon nitride. During the deposition process, by controlling the reaction parameters, a highly compact chemical bond structure can be formed within the resulting nitride film, accompanied by a volume shrinkage trend, thereby exhibiting significant tensile stress on a macroscopic scale. Of course, this application does not limit the material of the contact hole etch stop layer 210, as long as the material can serve as an etch stop in subsequent processes and can introduce tensile stress. Furthermore, the thickness of the contact hole etch stop layer 210 is typically controlled within a certain range to balance the provision of tensile stress with the requirements of subsequent contact hole etching processes. For example, the thickness of the contact hole etch stop layer 210 can be set between 200 angstroms and 400 angstroms, preferably 300 angstroms, but is not limited thereto.

[0058] Because the contact hole etch stop layer 210 has tensile stress, it can improve the electrical performance of N-type MOS devices. However, it should also be noted that for P-type MOS devices located on the same substrate, compressive stress is more beneficial to their performance. The tensile stress introduced by the globally deposited contact hole etch stop layer 210 will actually reduce the hole carrier mobility in the channel of the P-type MOS device, thereby causing the electrical performance of the P-type MOS device to degrade.

[0059] To avoid the tensile stress introduced by the globally deposited contact hole etch stop layer 210 reducing the hole carrier mobility in the channel of the P-type MOS device, such as... Figure 3C As shown, in this embodiment, a mask layer 220 is then formed covering the first region of the contact hole etch stop layer 210, which exposes the second region of the contact hole etch stop layer 210.

[0060] Subsequently, as Figures 3D to 3FAs shown, the second region of the exposed contact hole etching stop layer 210 is modified by converting part of the thickness of the second region into a modified layer 211, and the second type of stress of the modified layer 211 is compressive stress.

[0061] Specifically, such as Figures 3D to 3F As shown, the second region of the exposed contact hole etch stop layer 210 is modified, including sequentially performing plasma treatment and oxidation treatment on the second region of the exposed contact hole etch stop layer 210. First, as... Figure 3D As shown, plasma treatment is performed on the second region of the exposed contact hole etch stop layer 210. Specifically, the plasma treatment can be hydrogen plasma treatment, where hydrogen plasma bombards the second region of the exposed contact hole etch stop layer 210 to enhance the chemical reactivity of the surface layer of the second region. Of course, this application does not exclude any other suitable plasma treatment methods besides hydrogen plasma treatment; subsequently, as... Figure 3E As shown, the second region after plasma treatment is oxidized in an oxygen-containing or oxygen-rich environment, causing a chemical transformation of the surface layer of the second region into a modified layer 211 of an oxide material (e.g., silicon dioxide). This modified layer 211 has compressive stress. Simultaneously, a thin, untransformed portion of the second region is retained at the bottom of the modified layer 211. Then, as... Figure 3F As shown, the mask layer 220 is removed.

[0062] On the one hand, by converting a portion of the thickness of the second region of the contact hole etch stop layer 210 into a modified layer 211 with compressive stress, the hole carrier mobility in the channel of the underlying P-type MOS device can be improved, thus enhancing the electrical performance of the P-type MOS device. Meanwhile, the first region of the contact hole etch stop layer 210 is shielded by the mask layer 220 and remains unmodified, retaining tensile stress. This improves the electron carrier mobility in the channel of the underlying N-type MOS device, enhancing its electrical performance. Consequently, both the N-type and P-type MOS devices can obtain stresses of the corresponding type that are beneficial to their own carrier mobility, achieving a combined improvement in the electrical performance of transistors of different conductivity types on the same substrate. On the other hand, the unconverted portion of the second region retained at the bottom of the modified layer 211, together with the unmodified first region, can continue to serve as a qualified contact hole etch stop layer 210, playing a blocking and protective role in subsequent contact hole etching processes, preventing the underlying active region and gate structures from being etched and damaged.

[0063] Furthermore, during this modification process, the thickness of the modified layer 211 can be controlled by precisely adjusting process parameters (such as plasma processing power, gas flow rate, and oxidation reaction time). For example, when the total thickness of the contact hole etching stop layer 210 is approximately 300 angstroms, the thickness of the second region from top to bottom of approximately 280 angstroms can be controlled by adjusting process parameters to transform it into a modified layer 211 with a second type of stress (such as compressive stress). At the same time, an unconverted portion of the second region of approximately 20 angstroms is retained at the bottom of the modified layer 211.

[0064] Similarly, in another case, when the first conductivity type transistor is a P-type MOS device and the second conductivity type transistor is an N-type MOS device, the specific methods for avoiding the reduction of electron carrier mobility in the channel of the N-type MOS device by the compressive stress introduced by the globally deposited contact hole etch stop layer can be referred to the detailed description of the above embodiments, and will not be repeated here.

[0065] This concludes the description of the key steps in the semiconductor device manufacturing method of this application. The complete semiconductor device manufacturing method may also include other steps, which will not be elaborated here. It is worth mentioning that the order of the above steps can be adjusted without conflict.

[0066] Based on the above description, the semiconductor device manufacturing method according to the embodiments of this application, after forming a contact hole etch stop layer with a first type of stress, uses a mask layer to cover the first region of the contact hole etch stop layer and exposes the second region of the contact hole etch stop layer. Then, the exposed second region is modified to convert part of its thickness into a modified layer with the opposite second type of stress, while retaining the unconverted part at the bottom. This overcomes the limitation of globally depositing a contact hole etch stop layer with a single type of stress in related technologies. Under the premise of ensuring that the contact hole etch stop layer plays a reliable etch stop role in subsequent processes, it enables transistors with two opposite conductivity types to obtain corresponding types of stress that are beneficial to their own carrier mobility improvement. This avoids the problem of reducing the carrier mobility and degrading the electrical performance in the channel of one type of transistor due to the introduction of a single stress globally, and achieves the common improvement of the electrical performance of transistors with different conductivity types on the same substrate.

[0067] Example 2 According to another aspect of this application, a semiconductor device is provided. Specifically, the semiconductor device of this application includes: A substrate on which a first conductivity type transistor and a second conductivity type transistor are formed, wherein the first conductivity type transistor and the second conductivity type transistor have opposite conductivity types; A contact hole etch stop layer covers a first conductivity type transistor and a second conductivity type transistor. The contact hole etch stop layer has a first type of stress and includes a first region covering the first conductivity type transistor and a second region covering the second conductivity type transistor. A modified layer is located on the second region, and the top surface of the modified layer is flush with the top surface of the first region; wherein the modified layer has a second type of stress, and the first type of stress and the second type of stress are opposite in type.

[0068] In some embodiments, the first conductivity type transistor is an N-type MOS device and the second conductivity type transistor is a P-type MOS device, the first type of stress is tensile stress and the second type of stress is compressive stress.

[0069] In some embodiments, the contact hole etch stop layer is made of nitride, and the modified layer is made of oxide.

[0070] In some embodiments, the first conductivity type transistor is a P-type MOS device and the second conductivity type transistor is an N-type MOS device, the first type of stress is compressive stress and the second type of stress is tensile stress.

[0071] In some embodiments, the thickness of the modified layer is greater than the thickness of the unconverted portion of the second region retained at the bottom of the modified layer.

[0072] It is understood that the semiconductor device in this embodiment can be manufactured by the method in the aforementioned embodiment one. In order to avoid repetition, only a brief description is given for the same components and structures as in the aforementioned embodiment one. For specific explanations and descriptions, please refer to the description in embodiment one.

[0073] Although exemplary embodiments have been described herein with reference to the accompanying drawings, it should be understood that the above exemplary embodiments are merely illustrative and are not intended to limit the scope of this application. Various changes and modifications can be made therein by those skilled in the art without departing from the scope and spirit of this application. All such changes and modifications are intended to be included within the scope of this application as claimed in the appended claims.

[0074] Similarly, it should be understood that, in order to simplify this application and aid in understanding one or more aspects of the application, various features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, the point of application is that the corresponding technical problem can be solved with fewer features than all of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0075] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0076] It should be noted that the above embodiments are illustrative of this application and not limiting of it, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses should not be construed as limiting the claims. The use of the words first, second, and third, etc., does not indicate any order. These words can be interpreted as names.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided on which a first conductivity type transistor and a second conductivity type transistor are formed; wherein the first conductivity type transistor and the second conductivity type transistor have opposite conductivity types; A contact hole etch stop layer is formed covering the first conductivity type transistor and the second conductivity type transistor; wherein the contact hole etch stop layer has a first type stress, and the contact hole etch stop layer includes a first region covering the first conductivity type transistor and a second region covering the second conductivity type transistor; A mask layer is formed, which covers a first region of the contact hole etch stop layer and exposes a second region of the contact hole etch stop layer; The second region of the exposed contact hole etching stop layer is modified by converting a portion of the thickness of the second region into a modified layer, and retaining an unconverted portion of the second region at the bottom of the modified layer. The modified layer has a second type of stress; wherein the first type of stress and the second type of stress are opposite in type. Remove the mask layer.

2. The manufacturing method as described in claim 1, characterized in that, The first type of transistor is an N-type MOS device and the second type of transistor is a P-type MOS device. The first type of stress is tensile stress and the second type of stress is compressive stress.

3. The manufacturing method as described in claim 2, characterized in that, The contact hole etching stop layer is made of nitride, and the modified layer is made of oxide.

4. The manufacturing method as described in claim 2 or 3, characterized in that, The modification treatment of the second region of the exposed contact hole etch stop layer includes: The second region of the exposed contact hole etch stop layer is subjected to hydrogen plasma treatment and oxidation treatment in sequence.

5. The manufacturing method as described in claim 1, characterized in that, The first type of transistor is a P-type MOS device and the second type of transistor is an N-type MOS device. The first type of stress is compressive stress and the second type of stress is tensile stress.

6. The manufacturing method as described in claim 1, characterized in that, The contact hole etching stop layer is formed using plasma-enhanced chemical vapor deposition.

7. The manufacturing method as described in claim 1, characterized in that, The thickness of the modified layer is greater than the thickness of the unconverted portion of the second region retained at the bottom of the modified layer.

8. The manufacturing method as described in claim 1, characterized in that, After removing the mask layer, the manufacturing method further includes: An interlayer dielectric layer is formed in the first region of the contact hole etching stop layer and on the modified layer; Perform planarization on the interlayer dielectric layer; The interlayer dielectric layer is etched until it penetrates the underlying modified layer and the contact hole etch stop layer to form contact holes that expose the corresponding regions of the first conductivity type transistor and the second conductivity type transistor.

9. A semiconductor device, characterized in that, include: A substrate on which a first conductivity type transistor and a second conductivity type transistor are formed, wherein the first conductivity type transistor and the second conductivity type transistor have opposite conductivity types; A contact hole etch stop layer covers the first conductivity type transistor and the second conductivity type transistor. The contact hole etch stop layer has a first type of stress. The contact hole etch stop layer includes a first region covering the first conductivity type transistor and a second region covering the second conductivity type transistor. A modified layer is located on the second region, and the top surface of the modified layer is flush with the top surface of the first region; wherein the modified layer has a second type of stress, and the first type of stress is the opposite of the second type of stress.

10. The semiconductor device as claimed in claim 9, characterized in that, The thickness of the modified layer is greater than the thickness of the second region.

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