A BCD device and a method of fabricating the same

Abstract

The application provides a BCD device and a preparation method thereof, the BCD device comprising a substrate, a first deep trench isolation structure, a second deep trench isolation structure and an ESD device, wherein the substrate comprises a cell region and a terminal region, the cell region comprises a low-voltage device region and a high-voltage device region, the first deep trench isolation structure and the second deep trench isolation structure are arranged in the cell region, the first deep trench isolation structure surrounds the low-voltage device region, the second deep trench isolation structure surrounds the high-voltage device region, and the ESD device is arranged in the cell region and between the first deep trench isolation structure and the second deep trench isolation structure, and the ESD device comprises an emitter, an emitter lead-out region, a base, a base region and a collector. The BCD device of the application has both high-voltage isolation function and electrostatic protection function, and effectively saves the layout area occupied by the required isolation high-voltage and electrostatic protection structure in an integrated circuit.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing technology, and relates to a BCD device and its preparation method. Background Technology

[0002] In BCD integrated circuit technology, power double-diffused metal-oxide-semiconductor (DMOS) devices typically need to withstand high operating voltages. To prevent the DMOS device from adversely affecting adjacent devices under high-voltage operating conditions, and to avoid the phenomenon where adjacent devices break down before the DMOS device does, a dedicated isolation structure needs to be designed around the DMOS device. Commonly used isolation methods mainly include shallow trench isolation, deep trench isolation, and ion-implanted terminal ring structures, or a combination of these structures, to surround the DMOS device, thereby forming an effective voltage-resistant isolation region between the DMOS device and adjacent devices. Furthermore, as the voltage withstand requirements of DMOS devices increase, the lateral dimensions of the isolation structure need to be increased accordingly.

[0003] On the other hand, electrostatic discharge (ESD) protection is an indispensable part of integrated circuit design. ESD devices are typically integrated into critical locations such as chip input / output ports and power pins to quickly conduct during electrostatic shocks, discharging transient large currents to ground and protecting internal core circuits from damage. Existing ESD devices are usually designed based on existing photomask combinations on standard CMOS process platforms. Common structures include parasitic bipolar transistors, diodes, thyristors, and gate-grounded NMOS transistors. For circuits with higher protection requirements, additional dedicated ESD photomasks are often needed. The design of ESD devices requires attention to the following points: First, ESD devices occupy a large area, sometimes up to 30% in the input / output region. Second, the introduction of ESD devices increases parasitic capacitance, affecting the integrity of high-speed signals. Third, some structures, such as thyristors and gate-grounded NMOS transistors, have potential latch-up risks and need to be avoided. Furthermore, to ensure process compatibility, ESD devices should use structures achievable through standard processes as much as possible, and their robustness should be verified through ESD simulation and post-fabrication testing. Furthermore, and more importantly, all ports of existing ESD devices are located on the same side of the front of the chip, which limits the flexibility of layout design and increases the area occupied by the input and output regions.

[0004] Currently, in BCD integrated circuit design, the terminal isolation structure of DMOS devices and ESD devices are usually designed independently, each occupying an independent chip area. As the withstand voltage and protection levels increase, their area overhead increases significantly. This method of separating the isolation structure and ESD devices results in low overall chip area utilization and makes it difficult to further reduce manufacturing costs.

[0005] Therefore, how to provide a BCD device and its fabrication method that can achieve effective isolation of high-voltage devices while also taking into account electrostatic discharge protection functions, and significantly reduce the total area overhead of both, has become an important problem that needs to be solved by those skilled in the art.

[0006] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a BCD device and its fabrication method, which solves the problem that the isolation structure and electrostatic discharge device are set separately in the prior art, resulting in low overall chip area utilization and difficulty in reducing manufacturing costs.

[0008] To achieve the above and other related objectives, the present invention provides a BCD device, comprising:

[0009] The substrate includes a cellular region and a terminal region surrounding the cellular region, the cellular region including a low-voltage device region and a high-voltage device region spaced apart;

[0010] A first deep trench isolation structure and a second deep trench isolation structure are spaced apart in the cell region and extend from the upper surface of the cell region into the cell region. The first deep trench isolation structure forms a first ring around the low-voltage device region, and the second deep trench isolation structure forms a second ring around the high-voltage device region.

[0011] An ESD device is disposed in the cell region and between the first deep trench isolation structure and the second deep trench isolation structure. The ESD device includes an emitter, an emitter lead-out region, a base, a base region, and a collector. The base region extends from the upper surface of the cell region into the cell region. The emitter lead-out region is formed on a portion of the upper surface of the base region. The emitter is located on the front side of the substrate and is electrically connected to the emitter lead-out region. The base is located on the front side of the substrate and is electrically connected to another portion of the upper surface of the base region. The collector is located on the back side of the substrate and is electrically connected to the cell region.

[0012] Optionally, a third deep trench isolation structure is provided between the terminal region and the cell region, the third deep trench isolation structure extending from the upper surface of the substrate into the substrate and forming a third ring around the cell region.

[0013] Optionally, there may be multiple ESD devices, with at least one ESD device disposed between the first deep trench isolation structure and the third deep trench isolation structure, and at least one ESD device disposed between the second deep trench isolation structure and the third deep trench isolation structure.

[0014] Optionally, the width of the first deep trench isolation structure ranges from 0.01 μm to 100 μm, the width of the second deep trench isolation structure ranges from 0.01 μm to 100 μm, and the width of the third deep trench isolation structure ranges from 0.01 μm to 100 μm.

[0015] Optionally, the substrate and the emitter lead-out region are of a first conductivity type, and the base region is of a second conductivity type opposite to the first conductivity type. The first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0016] Optionally, the ESD device further includes a base lead-out region of a second conductivity type, the base lead-out region being formed on the upper surface of another portion of the base region and spaced apart from the emitter lead-out region, the base being electrically connected to the base lead-out region.

[0017] Optionally, the resistivity of the substrate is in the range of 0.001 Ω·cm to 1 Ω·cm.

[0018] This invention also provides a method for fabricating a BCD device, comprising the following steps:

[0019] A substrate of a first conductivity type is provided, the substrate comprising a cell region and a terminal region surrounding the cell region, the cell region comprising a low-voltage device region and a high-voltage device region spaced apart;

[0020] A first deep trench isolation structure and a second deep trench isolation structure are formed in the cell region. The first deep trench isolation structure extends from the upper surface of the cell region into the cell region and forms a first ring around the low-voltage device region. The second deep trench isolation structure extends from the upper surface of the cell region into the cell region and forms a second ring around the high-voltage device region.

[0021] The ESD device is formed in the region between the first deep trench isolation structure and the second deep trench isolation structure.

[0022] Optionally, forming the ESD device includes the following steps:

[0023] Ion implantation is performed on the cell region located between the first deep trench isolation structure and the second deep trench isolation structure to form a base region of a second conductivity type, which is opposite to the first conductivity type.

[0024] Ion implantation is performed on a portion of the upper surface of the base region to form an emitter lead-out region of the first conductivity type, thereby exposing a portion of the base region;

[0025] Ion implantation is performed on the upper surface of the base region that is not covered by the emitter lead-out region to form a base lead-out region of the second conductivity type;

[0026] The back side of the substrate is ground, and a collector electrode electrically connected to the cell region is formed on the back side of the substrate.

[0027] Optionally, the method further includes the steps of forming an emitter and a base, wherein the emitter is formed on the front side of the substrate and electrically connected to the emitter lead-out region, and the base is formed on the front side of the substrate and electrically connected to the base lead-out region.

[0028] As described above, the BCD device of the present invention includes a substrate, a first deep trench isolation structure, a second deep trench isolation structure, and an ESD device. The substrate includes a cell region and a terminal region surrounding the cell region. The cell region includes a low-voltage device region and a high-voltage device region spaced apart. The first deep trench isolation structure and the second deep trench isolation structure are spaced apart within the cell region and extend from the upper surface of the cell region into the cell region. The first deep trench isolation structure forms a first ring surrounding the low-voltage device region, and the second deep trench isolation structure forms a second ring surrounding the high-voltage device region. The ESD device is disposed within the cell region and between the first deep trench isolation structure and the second deep trench isolation structure. The ESD device includes an emitter, an emitter lead-out region, a base, a base region, and a collector. The base region extends from the upper surface of the cell region into the cell region. The emitter lead-out region is formed on a portion of the upper surface of the base region. The emitter is located on the front side of the substrate and electrically connected to the emitter lead-out region. The base is located on the front side of the substrate and electrically connected to another portion of the upper surface of the base region. The collector is located on the back side of the substrate and electrically connected to the cell region. The BCD device of this invention combines high-voltage isolation and electrostatic discharge (ESD) protection functions. It effectively isolates high-voltage devices and provides ESD protection for integrated circuits, significantly reducing the layout area required for both high-voltage isolation and ESD protection structures. Furthermore, the fabrication method of this BCD device is fully compatible with BCD integrated circuit processes. It can utilize existing deep trench isolation processes to form the required deep trench isolation structure and use existing ion implantation processes to form the emitter, base, and base regions. This eliminates the need for additional photomasks, allowing ESD devices to be formed during the integrated circuit manufacturing process, thus reducing process development costs and manufacturing complexity. Attached Figure Description

[0029] Figure 1 The diagram shown is a schematic of an existing isolation structure.

[0030] Figure 2 The image shown is a top view of the BCD device of this invention.

[0031] Figure 3 The diagram shown is a cross-sectional view of the BCD device of the present invention (along...). Figure 2 (in the AA' direction).

[0032] Figure 4 Shown is another cross-sectional view of the BCD device of the present invention (along... Figure 2 (in the direction of BB').

[0033] Figure 5 Displayed as in Figure 3 A schematic diagram of the structure obtained after forming low-voltage and high-voltage devices in the structure.

[0034] Figure 6 The image shown is a top view of the substrate used in the fabrication method of the BCD device of the present invention.

[0035] Figure 7 The image shown is a top view of the structure obtained after forming the first deep trench isolation structure and the second deep trench isolation structure in the fabrication method of the BCD device of the present invention.

[0036] Figure 8 The image shown is a top view of the structure obtained after forming the base region in the fabrication method of the BCD device of the present invention.

[0037] Figure 9 The image shown is a top view of the structure obtained after forming the emitter lead-out region in the fabrication method of the BCD device of the present invention.

[0038] Figure 10 The image shown is a top view of the structure obtained after forming the base lead-out region in the fabrication method of the BCD device of the present invention.

[0039] Figure 11 The diagram shown is a simulation of the lateral withstand voltage and current-voltage curves of the BCD device of the present invention.

[0040] Explanation of reference numerals in the attached figures: 101, 201, substrate; 102, deep trench isolation structure; 103, 206, low-voltage device; 104, 207, high-voltage device; 105, 204, ESD device; 1051, source; 1052, drain; 202, first deep trench isolation structure; 203, second deep trench isolation structure; 2041, emitter; 2042, emitter lead-out region; 2043, base; 2044, base region; 2045, collector; 2046, base lead-out region; 205, third deep trench isolation structure; I, cell region; II, termination region; a, low-voltage device region; b, high-voltage device region; W1, width of the first deep trench isolation structure; W2, width of the second deep trench isolation structure; W3, width of the third deep trench isolation structure. Detailed Implementation

[0041] Please see Figure 1 The diagram illustrates a conventional isolation structure, including a substrate 101 and a deep trench isolation structure 102. A low-voltage device 103, a high-voltage device 104, and an ESD device 105 are spaced apart on the substrate 101. The deep trench isolation structure 102 is located within the substrate 101 and surrounds the high-voltage device 104. The deep trench isolation structure 102 and the ESD device 105 are independent of each other, each occupying an independent chip area. Furthermore, as the withstand voltage and protection levels increase, their area overhead increases significantly. This method of separating the isolation structure from the electrostatic discharge device results in a large overall chip area. Additionally, the source 1051 and drain 1052 of the ESD device 105 are both located on the same side of the chip's front surface, further increasing the layout area.

[0042] Based on this, the present invention provides a BCD device and its fabrication method, which can achieve effective isolation of high voltage devices while taking into account electrostatic discharge protection function, reduce the total area required for high voltage isolation and electrostatic discharge protection of integrated circuits, and further save the layout area of ​​the front electrode of the substrate by placing the collector of the ESD device on the back side of the substrate.

[0043] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0044] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0045] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0046] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0047] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0048] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0049] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0050] Please see Figures 2 to 4 , Figure 2 The image shown is a top view of the BCD device of the present invention. Figure 3 The diagram shown is a cross-sectional view of the BCD device of the present invention (along...). Figure 2 (in the AA' direction) Figure 4 Shown is another cross-sectional view of the BCD device of the present invention (along... Figure 2 The BCD device (in the BB' direction) includes a substrate 201, a first deep trench isolation structure 202, a second deep trench isolation structure 203, and an ESD device 204. The substrate 201 includes a cell region I and a terminal region II surrounding the cell region I. The cell region I includes a low-voltage device region a and a high-voltage device region b spaced apart. The first deep trench isolation structure 202 and the second deep trench isolation structure 203 are spaced apart within the cell region I and extend from the upper surface of the cell region I into the cell region I. The first deep trench isolation structure 202 forms a first ring surrounding the low-voltage device region a, and the second deep trench isolation structure 203 forms a second ring surrounding the high-voltage device region b. The ESD device 204 is disposed within the cell region. The ESD device 204, located in region I and between the first deep trench isolation structure 202 and the second deep trench isolation structure 203, includes an emitter 2041, an emitter lead-out region 2042, a base 2043, a base region 2044, and a collector 2045. The base region 2044 extends from the upper surface of the cell region I into the cell region I. The emitter lead-out region 2042 is formed on a portion of the upper surface of the base region 2044. The emitter 2041 is located on the front side of the substrate 201 and is electrically connected to the emitter lead-out region 2042. The base 2043 is located on the front side of the substrate 201 and is electrically connected to another portion of the upper surface of the base region 2044. The collector 2045 is located on the back side of the substrate 201 and is electrically connected to the cell region I.

[0051] It should be noted that, in order to more clearly illustrate the positions of the low-voltage device region a and the high-voltage device region b, in Figures 2 to 4 In the process, the low-voltage device region a and the high-voltage device region b are pattern-filled to represent the well regions required for the low-voltage device and the high-voltage device, respectively. Subsequently... Figures 5 to 10 Similarly, pattern filling was applied to the low-voltage device region a and the high-voltage device region b.

[0052] Specifically, the BCD device forms the ESD device 204 between the two deep trench isolation rings, the first deep trench isolation structure 202 and the second deep trench isolation structure 203. The two deep trench isolation rings form a physical withstand voltage barrier in the lateral direction, preventing the electric field from spreading from the high-voltage device region b to adjacent regions, thus achieving effective high-voltage isolation. Simultaneously, when the chip port is subjected to electrostatic discharge, the voltage of the ESD device 204 rapidly rises to the trigger voltage, subsequently undergoing avalanche breakdown and entering a hysteresis conduction state, forming a low-impedance current path. This allows the transient large current to be discharged from the emitter 2041 through the substrate 201 to the collector 2045, thereby protecting the core circuitry inside the cell region I. Therefore, this BCD device integrates the terminal isolation structure with the ESD device 204 into a single design, enabling the same physical structure to simultaneously provide both high-voltage isolation and electrostatic discharge protection. The first deep trench isolation structure 202 and the second deep trench isolation structure 203, while serving as isolation structures, also define the lateral boundaries of the ESD device 204, achieving overlap and reuse of the two functions in the physical structure. This reduces the layout size of the high-voltage isolation and electrostatic discharge protection isolation structures required for the integrated circuit. Furthermore, by directly leading the collector 2045 out from the back of the low-resistivity substrate 201, there is no need to arrange collector 2045 contacts and metal wiring on the front of the chip, significantly reducing the layout size of the electrode distribution and saving chip area.

[0053] As an example, the ESD device 204 is selected from a vertical bipolar transistor.

[0054] As an example, a third deep trench isolation structure 205 is provided between the terminal region II and the cell region I. The third deep trench isolation structure 205 extends from the upper surface of the substrate 201 into the substrate 201 and forms a third ring around the cell region I.

[0055] As an example, there are multiple ESD devices 204, with at least one ESD device 204 disposed between the first deep trench isolation structure 202 and the third deep trench isolation structure 205, and at least one ESD device 204 disposed between the second deep trench isolation structure 203 and the third deep trench isolation structure 205.

[0056] Specifically, at least two ESD devices 204 located on both sides of the low-voltage device region a are provided between the first deep trench isolation structure 202 and the third deep trench isolation structure 205, and at least two ESD devices 204 located on both sides of the high-voltage device region b are provided between the second deep trench isolation structure 203 and the third deep trench isolation structure 205.

[0057] As an example, the width W1 of the first deep trench isolation structure 202 ranges from 0.01 μm to 100 μm, the width W2 of the second deep trench isolation structure 203 ranges from 0.01 μm to 100 μm, and the width W3 of the third deep trench isolation structure 205 ranges from 0.01 μm to 100 μm.

[0058] As an example, the substrate 201 and the emitter lead-out region 2042 have a first conductivity type, and the base region 2044 has a second conductivity type that is opposite to the first conductivity type.

[0059] Specifically, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0060] As an example, the ESD device 204 further includes a base lead-out region 2046 of a second conductivity type, the base lead-out region 2046 being formed on another portion of the upper surface of the base region 2044 and spaced apart from the emitter lead-out region 2042, the base 2043 being electrically connected to the base lead-out region 2046.

[0061] As an example, the resistivity of the substrate 201 ranges from 0.001 Ω·cm to 1 Ω·cm.

[0062] For example, please refer to Figure 5 The low-voltage device region a is provided with a low-voltage device 206, and the high-voltage device region b is provided with a high-voltage device 207.

[0063] In other embodiments, a method for fabricating a BCD device is also provided, comprising the following steps:

[0064] S1: Please refer to Figure 6 A substrate 201 of a first conductivity type is provided, the substrate 201 including a cell region I and a terminal region II surrounding the cell region I, the cell region I including a low-voltage device region a and a high-voltage device region b spaced apart.

[0065] S2: Please refer to Figure 7 A first deep trench isolation structure 202 and a second deep trench isolation structure 203 are formed in the cell region I. The first deep trench isolation structure 202 extends from the upper surface of the cell region I into the cell region I and forms a first ring around the low-voltage device region a. The second deep trench isolation structure 203 extends from the upper surface of the cell region I into the cell region I and forms a second ring around the high-voltage device region b.

[0066] S3: Please refer to S3 again. Figure 3 and Figure 4 This forms the region between the first deep trench isolation structure 202 and the second deep trench isolation structure 203, forming the ESD device 204.

[0067] As an example, forming the ESD device 204 includes the following steps:

[0068] (1) Please refer to Figure 8 Ion implantation is performed on the cell region I located between the first deep trench isolation structure 202 and the second deep trench isolation structure 203 to form a base region 2044 of a second conductivity type, which is opposite to the first conductivity type.

[0069] (2) Please refer to Figure 9 Ion implantation is performed on a portion of the upper surface of the base region 2044 to form an emitter lead-out region 2042 of the first conductivity type, thereby exposing a portion of the base region 2044.

[0070] (3) Please refer to Figure 10 Ion implantation is performed on the upper surface of the base region 2044, which is exposed but not covered by the emitter lead-out region 2042, to form a base lead-out region 2046 of the second conductivity type.

[0071] (4) Please refer to the following: Figure 3 The back side of the substrate 201 is ground, and a collector electrode 2045 electrically connected to the cell region I is formed on the back side of the substrate 201.

[0072] For example, please refer to [link / reference]. Figure 2 It also includes the steps of forming an emitter 2041 and a base 2043, wherein the emitter 2041 is formed on the front side of the substrate 201 and electrically connected to the emitter lead-out region 2042, and the base 2043 is formed on the front side of the substrate 201 and electrically connected to the base lead-out region 2046.

[0073] Specifically, the above BCD device fabrication method can utilize the photomask and process in the existing BCD process steps. Depending on the ESD protection level of the actual circuit, different protection levels correspond to different photomask opening combinations, which need to be adjusted. However, the number of photomask layers will not increase during the actual fabrication process after adjustment.

[0074] For example, the above BCD device fabrication method can be based on BCD integrated circuit technology, fabricating two deep trench isolation rings on a low resistivity N-type substrate 201, and then utilizing the high-voltage device 207 well region ( Figure 8In the pattern filling portion of region b of the medium- and high-voltage device, such as the P-well implantation process, the base region 2044 of the ESD device 204 is formed simultaneously. During the N-type source-drain implantation step in the BCD integrated circuit process, the emitter lead-out region 2042 is formed, and during the P-type source-drain implantation step, the base lead-out region 2046 is formed. Finally, the collector 2045 is directly led out from the back side of the thinned substrate 201. In this way, the formation of the entire structure of the ESD device 204 does not depend on an additional photomask. It can be achieved only by using the epitaxial growth, deep trench etching and filling, and conventional ion implantation processes in the standard BCD process flow, avoiding the increase in process development complexity and reducing the device fabrication cost.

[0075] To clearly demonstrate the withstand voltage and electrostatic discharge protection capabilities of the BCD device of this invention, simulations of its lateral withstand voltage and trigger hysteresis current-voltage curves were performed. Please refer to [link to relevant documentation]. Figure 11 Simulation results show that the lateral withstand voltage of this BCD device can exceed 40 volts, meeting the high voltage isolation requirements. At the same time, its current-voltage characteristics exhibit a hysteresis effect, with a trigger voltage of about 30 volts and a sustaining voltage of about 15 volts, which can effectively provide electrostatic discharge protection for devices with voltages of 5 to 12 volts.

[0076] In summary, the BCD device of the present invention includes a substrate, a first deep trench isolation structure, a second deep trench isolation structure, and an ESD device. The substrate includes a cell region and a terminal region surrounding the cell region. The cell region includes a low-voltage device region and a high-voltage device region spaced apart. The first deep trench isolation structure and the second deep trench isolation structure are spaced apart within the cell region and extend from the upper surface of the cell region into the cell region. The first deep trench isolation structure forms a first ring surrounding the low-voltage device region, and the second deep trench isolation structure forms a second ring surrounding the high-voltage device region. The ESD device is disposed within the cell region and between the first deep trench isolation structure and the second deep trench isolation structure. The ESD device includes an emitter, an emitter lead-out region, a base, a base region, and a collector. The base region extends from the upper surface of the cell region into the cell region. The emitter lead-out region is formed on a portion of the upper surface of the base region. The emitter is located on the front side of the substrate and electrically connected to the emitter lead-out region. The base is located on the front side of the substrate and electrically connected to another portion of the upper surface of the base region. The collector is located on the back side of the substrate and electrically connected to the cell region. The BCD device of this invention combines high-voltage isolation and electrostatic discharge (ESD) protection functions. It effectively isolates high-voltage devices and provides ESD protection for integrated circuits, significantly reducing the layout area required for both high-voltage isolation and ESD protection structures. Furthermore, the fabrication method of this BCD device is fully compatible with BCD integrated circuit processes. It can utilize existing deep trench isolation processes to form the required deep trench isolation structure and existing ion implantation processes to form the emitter, base, and base regions. This eliminates the need for additional photomasks, allowing the ESD device to be formed during the integrated circuit manufacturing process, reducing process development costs and manufacturing complexity. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.

[0077] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A BCD device, characterized in that, include: The substrate includes a cellular region and a terminal region surrounding the cellular region, the cellular region including a low-voltage device region and a high-voltage device region spaced apart; A first deep trench isolation structure and a second deep trench isolation structure are spaced apart in the cell region and extend from the upper surface of the cell region into the cell region. The first deep trench isolation structure forms a first ring around the low-voltage device region, and the second deep trench isolation structure forms a second ring around the high-voltage device region. At least one ESD device is disposed in the cell region and between the first deep trench isolation structure and the second deep trench isolation structure. The ESD device includes an emitter, an emitter lead-out region, a base, a base region, and a collector. The base region extends from the upper surface of the cell region into the cell region. The emitter lead-out region is formed on a portion of the upper surface of the base region. The emitter is located on the front side of the substrate and is electrically connected to the emitter lead-out region. The base is located on the front side of the substrate and is electrically connected to another portion of the upper surface of the base region. The collector is located on the back side of the substrate and is electrically connected to the cell region.

2. The BCD device according to claim 1, characterized in that: A third deep trench isolation structure is provided between the terminal region and the cell region. The third deep trench isolation structure extends from the upper surface of the substrate into the substrate and forms a third ring around the cell region.

3. The BCD device according to claim 2, characterized in that: The number of ESD devices is multiple, with at least one ESD device disposed between the first deep trench isolation structure and the third deep trench isolation structure, and at least one ESD device disposed between the second deep trench isolation structure and the third deep trench isolation structure.

4. The BCD device according to claim 2, characterized in that: The width range of the first deep trench isolation structure is 0.01μm to 100 μm, the width range of the second deep trench isolation structure is 0.01μm to 100 μm, and the width range of the third deep trench isolation structure is 0.01μm to 100 μm.

5. The BCD device according to claim 1, characterized in that: The substrate and the emitter lead-out region are of a first conductivity type, and the base region is of a second conductivity type opposite to the first conductivity type. The first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

6. The BCD device according to claim 5, characterized in that: The ESD device further includes a base lead-out region of a second conductivity type, the base lead-out region being formed on the upper surface of another portion of the base region and spaced apart from the emitter lead-out region, the base being electrically connected to the base lead-out region.

7. The BCD device according to claim 1, characterized in that: The resistivity of the substrate ranges from 0.001 Ω·cm to 1 Ω·cm.

8. A method for fabricating a BCD device, characterized in that, Includes the following steps: A substrate of a first conductivity type is provided, the substrate comprising a cell region and a terminal region surrounding the cell region, the cell region comprising a low-voltage device region and a high-voltage device region spaced apart; A first deep trench isolation structure and a second deep trench isolation structure are formed in the cell region. The first deep trench isolation structure extends from the upper surface of the cell region into the cell region and forms a first ring around the low-voltage device region. The second deep trench isolation structure extends from the upper surface of the cell region into the cell region and forms a second ring around the high-voltage device region. The ESD device is formed in the region between the first deep trench isolation structure and the second deep trench isolation structure.

9. The method for fabricating a BCD device according to claim 8, characterized in that, The formation of the ESD device includes the following steps: Ion implantation is performed on the cell region located between the first deep trench isolation structure and the second deep trench isolation structure to form a base region of a second conductivity type, which is opposite to the first conductivity type. Ion implantation is performed on a portion of the upper surface of the base region to form an emitter lead-out region of a first conductivity type, thereby exposing a portion of the base region; Ion implantation is performed on the upper surface of the base region that is not covered by the emitter lead-out region to form a base lead-out region of the second conductivity type; The back side of the substrate is ground, and a collector electrode electrically connected to the cell region is formed on the back side of the substrate.

10. The method for fabricating a BCD device according to claim 9, characterized in that: It also includes the steps of forming an emitter and a base, wherein the emitter is formed on the front side of the substrate and electrically connected to the emitter lead-out region, and the base is formed on the front side of the substrate and electrically connected to the base lead-out region.

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