Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same are provided. The semiconductor device can include a first dielectric layer in contact with a lower surface of a semiconductor structure, a first semiconductor layer located over the first dielectric layer, and a source / drain region located over the first semiconductor layer. The first dielectric layer can be located between a first portion of the semiconductor structure and a second portion of the semiconductor structure. The semiconductor device can also include a first semiconductor nanostructure located over a top surface of the first portion of the semiconductor structure, and a gate structure located around the first semiconductor nanostructure. The first semiconductor layer can extend from a sidewall of the first portion of the semiconductor structure to a sidewall of the second portion of the semiconductor structure. The source / drain region is in contact with a sidewall of the first semiconductor nanostructure.

Description

Technical Field

[0001] The embodiments of the present invention relate to semiconductor devices and methods for forming the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. They are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material on a semiconductor substrate, and then using photolithography to pattern the various material layers to form circuit components and elements on them.

[0003] The semiconductor industry continuously increases the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, allowing more components to be integrated into a given area. However, as the minimum feature size decreases, other problems arise that need to be addressed. Summary of the Invention

[0004] One aspect of this invention provides a semiconductor device, comprising: a first dielectric layer in contact with a lower surface of a semiconductor structure, wherein the first dielectric layer is located between a first portion and a second portion of the semiconductor structure; a first semiconductor layer above the first dielectric layer, wherein the first semiconductor layer extends from a sidewall of the first portion of the semiconductor structure to a sidewall of the second portion of the semiconductor structure; a source / drain region above the first semiconductor layer; a first semiconductor nanostructure above the top surface of the first portion of the semiconductor structure, wherein the source / drain region is in contact with a sidewall of the first semiconductor nanostructure; a gate structure surrounding the first semiconductor nanostructure, wherein a first portion of the gate structure is located between the first semiconductor nanostructure and the semiconductor structure, wherein a second portion of the gate structure is located above the top surface of the first semiconductor nanostructure, wherein the gate structure includes a gate electrode and a gate dielectric layer, and wherein the gate electrode includes a titanium-based material; and a gate spacer along a sidewall of the second portion of the gate structure, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer.

[0005] Another aspect of the present invention provides a method for forming a semiconductor device, the method comprising: etching a recess in a semiconductor structure; forming a first dielectric layer in contact with the bottom surface of the recess; growing a first epitaxial structure over the first dielectric layer, wherein the first epitaxial structure is located on a first sidewall and a second sidewall of the recess, and wherein the first sidewall of the recess faces the second sidewall of the recess; growing a second epitaxial structure over the first epitaxial structure, wherein the second epitaxial structure is doped with a dopant, wherein the second epitaxial structure includes a first portion and a second portion, wherein the first portion has a first concentration of the dopant, and wherein the second portion has a second concentration of the dopant different from the first concentration of the dopant; and forming a conductive contact over the second epitaxial structure, wherein the conductive contact is electrically connected to the second epitaxial structure, and wherein the conductivity of the conductive contact is greater than the conductivity of the second epitaxial structure.

[0006] Another aspect of the present invention provides a method for forming a semiconductor device, the method comprising: forming a semiconductor fin; forming an isolation region, wherein, in a first cross-sectional view, the isolation region is located on a first sidewall of the semiconductor fin, wherein the isolation region comprises a material having a dielectric constant in the range of 3 to 5; forming a recess in the semiconductor fin, wherein, in a second cross-sectional view, the recess exposes a second sidewall and a third sidewall of the semiconductor fin, and wherein the first cross-sectional view is perpendicular to the second cross-sectional view; forming a first semiconductor nanostructure above the semiconductor fin; and forming a first dielectric layer in the recess, wherein... In the second cross-sectional view, the top surface of the first dielectric layer is located below the top surface of the semiconductor fin; a first semiconductor layer is grown above the first dielectric layer from the second sidewall and the third sidewall of the semiconductor fin, and wherein, in the second cross-sectional view, the top surface of the first semiconductor layer is located below the bottom surface of the first semiconductor nanostructure; source / drain regions are grown from the first semiconductor layer and the first semiconductor nanostructure; a contact etch stop layer is formed above the source / drain regions; and an interlayer dielectric layer is formed above the contact etch stop layer, wherein the contact etch stop layer and the interlayer dielectric layer comprise different materials. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0008] Figure 1A three-dimensional diagram of a semiconductor device including a nanostructured field-effect transistor (nanoFET) according to some embodiments is shown;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 6C , Figure 7A , Figure 7B , Figure 7C , Figure 8A , Figure 8B , Figure 8C , Figure 9A , Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E , Figure 12F , Figure 12G , Figure 13A , Figure 13B , Figure 13C , Figure 13D , Figure 14A , Figure 14B , Figure 14C , Figure 15A , Figure 15B , Figure 15C , Figure 16A , Figure 16B , Figure 16C , Figure 17A , Figure 17B , Figure 17C , Figure 18A , Figure 18B , Figure 18C , Figure 19A , Figure 19B , Figure 19C , Figure 20A , Figure 20B , Figure 20C , Figure 21A , Figure 21B ,and Figure 21C These are diagrams illustrating intermediate processes in the fabrication of semiconductor devices, including nanoFETs, according to some embodiments.

[0010] Figure 22A , Figure 22B ,and Figure 22C These are diagrams of semiconductor devices including nanoFETs according to some embodiments;

[0011] Figure 23A , Figure 23B ,and Figure 23C This is a diagram of a semiconductor device including a nanoFET according to some embodiments. Detailed Implementation

[0012] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0014] Various embodiments provide semiconductor devices and methods for forming the same. The semiconductor device may include a nanostructure stack above a semiconductor fin structure, a gate structure surrounding the individual nanostructures of the nanostructure stack, and source / drain regions located above the semiconductor fin structure and on the sidewalls of the nanostructure stack. By forming a dielectric layer between the source / drain regions and the semiconductor fin structure, sufficient electrical isolation can be provided to reduce the risk of current leakage between the source / drain regions and the semiconductor fin structure during operation of the semiconductor device. By forming a semiconductor layer between the dielectric layer and the source / drain regions, additional growth sites can be provided to improve the quality of the source / drain regions. As a result, the performance and reliability of the semiconductor device can be improved.

[0015] Some of the embodiments discussed herein are described in the context of semiconductor devices including nanoFETs. However, various embodiments can be applied to dies that replace or are combined with nanoFETs and include other types of transistors (e.g., FinFETs, VFETs, CFETs, planar transistors, etc.).

[0016] Figure 1 A three-dimensional diagram of a semiconductor device including a nanoFET (e.g., nanowire FET, nanosheet FET, etc.) is shown. The nanoFET includes a nanostructure 55 (e.g., nanosheet, nanowire, etc.) located on a substrate 50 (e.g., a semiconductor substrate) and above fins 66, wherein the nanostructure 55 serves as a channel region for the nanoFET. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Shallow trench isolation (STI) regions 68 are disposed between adjacent fins 66, which may protrude above and from adjacent STI regions 68. Although the STI regions 68 are described / shown as separated from the substrate 50, the term "substrate" as used herein may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an STI region. Additionally, although the bottom of the fin 66 is shown as a single continuous material with the substrate 50, the bottom of the fin 66 and / or the substrate 50 may include a single material or multiple materials. In this context, fin 66 refers to the portion extending between adjacent STI regions 68. The gate dielectric layer 100 is located above the top surface of the fin 66 and extends along the top, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 102 is located above the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the opposite sides of the gate dielectric layer 100 and the gate electrode 102, on the fin 66.

[0017] Figure 1 Reference sections used in subsequent figures are also shown. Reference section A-A' is along the longitudinal axis of the gate electrode 102 and along a direction, for example, perpendicular to the current direction between the epitaxial source / drain regions 92 of the nanoFET. Reference section B-B' is parallel to reference section A-A' and extends through the epitaxial source / drain regions 92 of the multiple nanoFETs. Reference section C-C' is perpendicular to reference section A-A' and parallel to the longitudinal axis of the fins 66 of the nanoFET, for example, along the current direction between the epitaxial source / drain regions 92 of the nanoFET. For clarity, subsequent figures refer to these reference sections.

[0018] Figures 2 to 21C This is a diagram of an intermediate process in the fabrication of a semiconductor device, including a nanoFET, according to some embodiments. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A ,and Figure 21A It shows along Figure 1 The cross-sectional view of reference section A-A' shown in the figure. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12B , Figure 13B , Figure 13D , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B ,and Figure 21B It shows along Figure 1 The cross-sectional view of reference section B-B' shown is shown. Figure 6C , Figure 7C , Figure 8C , Figure 9C , Figure 10C , Figure 11C , Figure 12C , Figure 12D , Figure 12E , Figure 12F , Figure 12G , Figure 13C , Figure 14C , Figure 15C , Figure 16C , Figure 17C , Figure 18C , Figure 19C , Figure 20C ,and Figure 21C It shows along Figure 1 The cross-sectional view of the reference section C-C' shown is shown.

[0019] exist Figure 2In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, etc., and may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulating layer is disposed on the substrate, typically a silicon or glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, germanium tin, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0020] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device such as an NMOS transistor, for example, an n-type nanoFET, and the p-type region 50P can be used to form a p-type device such as a PMOS transistor, for example, a p-type nanoFET. The n-type region 50N can be physically separated from the p-type region 50P (as shown by separator 20), and any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P can be disposed.

[0021] Still in Figure 2In this process, a multilayer stack 64 is formed over a substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A-51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A-53C (collectively referred to as second semiconductor layers 53). For illustrative purposes, and as discussed in more detail below, the first semiconductor layer 51 may be removed, and the second semiconductor layer 53 may be patterned to form the channel region of the nanoFET in the n-type region 50N and the p-type region 50P. In some embodiments, the first semiconductor layer 51 is removed, and the second semiconductor layer 53 is patterned to form the channel region of the nanoFET in the n-type region 50N, and the second semiconductor layer 53 is removed, and the first semiconductor layer 51 is patterned to form the channel region of the nanoFET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 is removed, and the first semiconductor layer 51 is patterned to form the channel region of the nanoFET in the n-type region 50N; the first semiconductor layer 51 is removed, and the second semiconductor layer 53 is patterned to form the channel region of the nanoFET in the p-type region 50P. In some embodiments, the second semiconductor layer 53 is removed, and the first semiconductor layer 51 is patterned to form the channel region of the nanoFET in both the n-type region 50N and the p-type region 50P.

[0022] For illustrative purposes, the multilayer stack 64 is shown as a three-layer assembly comprising each of a first semiconductor layer 51 and a second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each layer of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), and molecular beam epitaxy (MBE). In various embodiments, the first semiconductor layer 51 may be formed using a first semiconductor material such as silicon germanium, and the second semiconductor layer 53 may be formed using a second semiconductor material different from the first semiconductor material, such as silicon.

[0023] The first semiconductor material and the second semiconductor material can be materials with high etch selectivity to each other. This allows the first semiconductor layer 51 of the first semiconductor material to be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the nanoFET. Similarly, in embodiments where the second semiconductor layer 53 is removed and the first semiconductor layer 51 is patterned to form the channel region, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the nanoFET.

[0024] exist Figure 3 In some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 can be formed in multilayer stack 64 and substrate 50, respectively, by etching trenches in multilayer stack 64 and substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic. By etching multilayer stack 64 to form nanostructures 55, first nanostructures 52A-52C (collectively referred to as first nanostructures 52) can be further defined from first semiconductor layer 51, and second nanostructures 54A-54C (collectively referred to as second nanostructures 54) can be defined from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 can be collectively referred to as nanostructure 55.

[0025] The fin 66 and nanostructure 55 can be patterned using any suitable method. For example, one or more lithography processes, including dual patterning or multiple patterning processes, can be used to pattern the fin 66 and nanostructure 55. Typically, dual patterning or multiple patterning processes combine lithography and self-alignment processes, allowing the creation of patterns with smaller pitches, for example, compared to those achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin 66.

[0026] For the purpose of explanation, Figure 3 The fins 66 in the n-type region 50N and the p-type region 50P are shown to have substantially equal widths. In some embodiments, the width of the fin 66 in the n-type region 50N may be greater than or less than the width of the fin 66 in the p-type region 50P. Additionally, although each of the fins 66 and nanostructures 55 is shown to have a uniform width throughout, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls such that the width of each of the fins 66 and / or nanostructures 55 increases continuously along the direction toward the substrate 50. In such embodiments, each of the nanostructures 55 may have a different width and be trapezoidal in shape.

[0027] exist Figure 4In the substrate 50, a shallow trench isolation (STI) region 68 is formed adjacent to fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50, fin 66, and nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide such as silicon oxide, a nitride such as silicon nitride, or a combination thereof, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. The insulating material can have a dielectric constant in the range of about 3 to about 5. Other insulating materials formed by any acceptable process can be used. Once the insulating material is formed, an annealing process can be performed. Although the insulating material is shown as a single layer, some embodiments may use multiple layers.

[0028] The removal process can then be applied to the insulating material to remove excess insulating material above the nanostructure 55. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etching back, or combinations thereof, can be used. The planarization process exposes the nanostructure 55 such that, after the planarization process is complete, the top surfaces of the nanostructure 55 and the insulating material can be substantially flush. The insulating material can then be recessed to form the STI region 68. The insulating material can be recessed such that the upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude from between adjacent STI regions 68. An acceptable etching process, such as an etching process that is selective to the material of the insulating material and etches the material of the insulating material at a faster rate than etching the material of the fins 66 and the nanostructure 55, can be used to recess the STI region 68. For example, when the insulating material is an oxide, dilute hydrofluoric acid can be used. After the removal process, the top surface of the STI region 68 can have a flat surface, a convex surface, a concave surface, or a combination thereof, as shown.

[0029] The above is about Figures 2 to 4 The described process is an example of how the fin 66 and nanostructure 55 are formed. In some embodiments, the fin 66 and / or nanostructure 55 can be formed using a mask and epitaxial growth process. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, such that the dielectric layer is recessed and the epitaxial structure protrudes from the dielectric layer to form the fin 66 and / or nanostructure 55. The epitaxial structure can include alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In embodiments where the epitaxial structure is grown, the epitaxially grown material can be in-situ doped during growth, which avoids prior and / or subsequent implantation, although in-situ doping and implantation doping can be used together.

[0030] Additionally, for illustrative purposes, the first semiconductor layer 51 (and the resulting first nanostructure 52) is shown and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N, and the second semiconductor layer 53 (and the resulting second nanostructure 54) is shown and discussed herein as comprising the same material in the p-type region 50P and the n-type region 50N. In some embodiments, the first semiconductor layer 51 may comprise different materials in the p-type region 50P and the n-type region 50N. In some embodiments, the second semiconductor layer 53 may comprise different materials in the p-type region 50P and the n-type region 50N. In some embodiments, the first semiconductor layer 51 may comprise different materials in the p-type region 50P and the n-type region 50N, and the second semiconductor layer 53 may comprise different materials in the p-type region 50P and the n-type region 50N.

[0031] In addition, Figure 4 In this process, suitable wells (not shown separately) can be formed in fin 66, nanostructure 55, and / or STI region 68. In embodiments with different well types, photoresist or other masks (not shown separately) can be used to implement different implantation steps for n-type region 50N and p-type region 50P. For example, photoresist can be formed over fin 66 and STI region 68 in n-type region 50N and p-type region 50P. The photoresist is patterned to expose p-type region 50P. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in p-type region 50P, and the photoresist can be used as a mask to substantially prevent n-type impurities from being implanted into n-type region 50N. The n-type impurity can be phosphorus, arsenic, antimony, etc., implanted in this region, with a concentration of about 10. 13 atoms / cm 3 To about 10 14 atoms / cm 3 Within the specified range. After implantation, the photoresist is removed, for example, through an acceptable ashing process.

[0032] After or before implantation of the p-type region 50P, photoresist or other masks (not shown separately) are formed over the fins 66, nanostructures 55, and STI regions 68 in both the p-type and n-type regions 50P and 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can be used as a mask to substantially prevent the implantation of p-type impurities into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, etc., implanted in the region at a concentration of approximately 10. 13 atoms / cm 3 To about 1014 atoms / cm 3 Within the range. After implantation, the photoresist can be removed, for example, by an acceptable ashing process. After implantation in the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which can avoid implantation, although in-situ doping and implantation doping can be used together.

[0033] exist Figure 5 In this process, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 can be, for example, silicon oxide, silicon nitride, or combinations thereof, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed above the dummy dielectric layer 70, and a mask layer 74 is formed above the dummy gate layer 72. The dummy gate layer 72 can be deposited above the dummy dielectric layer 70 and then planarized, for example, by CMP. The mask layer 74 can be deposited above the dummy gate layer 72. The dummy gate layer 72 can be a conductive or non-conductive material and can be selected from the group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (polycrystalline SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 can be made of other materials that have high etch selectivity for etching the isolation region. The mask layer 74 may include, for example, silicon nitride, silicon oxynitride, etc. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed on the n-type region 50N and the p-type region 50P. It should be noted that, for illustrative purposes, the dummy dielectric layer 70 is shown as covering only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 may be deposited such that the dummy dielectric layer 70 covers the STI region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0034] Figures 6A to 21C Various additional processes in the fabrication of semiconductor devices including nanoFETs according to some embodiments are illustrated. Figures 6A to 22C Features of one or both of the n-type region 50N and the p-type region 50P are shown. Figures 6A to 6C In this process, a mask 78, a dummy gate 76, and a dummy gate dielectric 71 are formed. The dummy gate 76 and the dummy gate dielectric 71 can be collectively referred to as the dummy gate structure. Suitable photolithography and etching processes can be used to etch the mask layer 74 (see [link to image]). Figure 5The mask 78 is patterned to form a mask 78. Then, using a suitable etching process, the pattern of the mask 78 is transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form dummy gate 76 and dummy gate dielectric 71, respectively. The dummy gate 76 covers the fin 66 and the corresponding channel region of the corresponding nanostructure 55 above it. The pattern of the mask 78 can be used to separate each of the dummy gates 76 from its adjacent dummy gates 76. The dummy gates 76 may also have a length direction substantially perpendicular to the length direction of the corresponding fin 66.

[0035] exist Figures 7A to 7C In this process, a spacer 81 is formed. The spacer 81 may also be referred to as a gate spacer. The spacer 81 can self-align with the subsequently formed source / drain regions and protect the dummy gate dielectric 71 and dummy gate 76 during subsequent etching processes. The spacer 81 can be a single layer of one material or multiple sublayers of different materials with different etching rates. In some embodiments, the spacer 81 comprises two sublayers of different materials with different etching rates, which may be selected from silicon carbide, silicon carbonitride, etc. The spacer layer can be formed by thermal oxidation or a suitable deposition process such as CVD, ALD, etc., and then patterned by a suitable etching process such as isotropic etching (e.g., wet etching) or anisotropic etching (e.g., dry etching) to form the spacer 81.

[0036] Spacer layers can be formed on: the top surface of STI region 68; the top surface and sidewalls of fin 66, nanostructure 55, and mask 78; and the sidewalls of dummy gate 76 and dummy gate dielectric 71. After the etching process, spacer 81 can remain on the top surface of STI region 68, and on the sidewalls of fin 66 and nanostructure 55, as shown below. Figure 7B As shown in the diagram. After the etching process, spacer 81 can remain on the top surface of nanostructure 55, as well as on the sidewalls of mask 78, dummy gate 76, and dummy gate dielectric 71, as shown. Figure 7C As shown in the image.

[0037] exist Figures 8A to 8C In this structure, a first recess 86 is formed in the fin 66 and the nanostructure 55. The first recess 86 can extend through the first nanostructure 52 and the second nanostructure 54 and enter into the fin 66. Figure 8B As shown, the bottom surface of the first recess 86 can be concave, and the bottom surface of the first recess 86 can be located below the top surface of the STI region 68. For example... Figure 8CAs shown, the first recess 86 can expose the sidewalls of the fin 66, which may be referred to as the sidewalls of the first recess 86. The first recess 86 can be formed by partially removing the fin 66 and the nanostructure 55 using an anisotropic etching process such as RIE, NBE, etc. During the etching process used to form the first recess 86, the spacer 81 and the mask 78 can mask portions of the fin 66, the nanostructure 55, and the substrate 50. A single etching process or multiple etching processes can be used to etch the individual layers of the nanostructure 55 and / or the fin 66. A timed etching process can be used to stop etching after the first recess 86 reaches the desired depth.

[0038] exist Figures 9A to 9C In the process, a portion of the first nanostructure 52 exposed by the first recess 86 is removed to form the second recess 88. Although in Figure 9C In the diagram, the sidewall of the first nanostructure 52 adjacent to the second recess 88 is shown as straight, but the sidewall can be concave or convex. A portion of the first nanostructure 52 can be removed using an isotropic etching process such as wet etching. In embodiments where the first nanostructure 52 includes silicon, germanium, etc., and the second nanostructure 54 includes silicon, silicon carbide, etc., tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc., can be used to etch the first nanostructure 52.

[0039] exist Figures 10A to 10C An internal spacer 90 is formed in the second recess 88. The internal spacer 90 can provide electrical insulation between the subsequently formed source / drain regions and the subsequently formed gate structure, as discussed in more detail below. The internal spacer 90 can extend along the sidewalls of the first nanostructure 52 and partially contact the top and bottom surfaces of the previously exposed second nanostructure 54. This can be achieved by... Figures 9A to 9C An internal spacer layer (not shown separately) is deposited on top of the structure shown, and then etched to form the internal spacer 90. The internal spacer layer can be deposited using suitable deposition processes such as CVD, ALD, etc. The internal spacer layer may include a dielectric material, such as silicon nitride. The material of the internal spacer layer may have a dielectric constant (k) less than about 3.5. The internal spacer layer can be etched using anisotropic etching processes such as RIE, NBE, etc., to form the internal spacer 90. The outer wall of the internal spacer 90 is... Figure 10C The inner spacer 90 is shown as straight and flush with the sidewall of the second nanostructure 54. As an example, in some embodiments, the outer sidewall of the inner spacer 90 may extend beyond (e.g., convex) the sidewall of the second nanostructure 54, or be recessed from (e.g., concave) the sidewall of the second nanostructure 54.

[0040] exist Figures 11A to 11CIn this process, a dielectric layer 91 is formed on the bottom surface of the first recess 86. The dielectric layer 91 provides electrical isolation and reduces the risk of current leakage between the subsequently formed epitaxial source / drain regions and the fin 66, as described in more detail below. The dielectric layer 91 can be formed of silicon oxide, silicon nitride, silicon carbonitride, aluminum oxide, etc. The dielectric layer 91 can be formed by first depositing a conformal dielectric layer on the exposed surface of the first recess 86 using a suitable deposition process such as CVD, FCVD, ALD, PVD, etc., and then removing the upper portion of the conformal dielectric layer using a suitable etching process such as a dry etching process using fluorine plasma as an etchant. The remaining portion of the conformal dielectric layer on the bottom surface of the first recess 86 can be referred to as the dielectric layer 91.

[0041] like Figure 11C As shown, the top surface of dielectric layer 91 may be concave and located below the top surface of fin 66. Dielectric layer 91 may cover the lower portion of the sidewall of the first recess 86. After the dielectric layer 91 is formed, the upper portion of the sidewall of the first recess 86 may remain exposed. Dielectric layer 91 may have a thickness T1 at its centerline. Thickness T1 may be greater than 1 nm, which can provide sufficient electrical isolation between the subsequently formed epitaxial source / drain regions and fin 66, as described in more detail below. The portion of fin 66 with the upper portion of the sidewall of the first recess 86 may have a thickness T2, which may also be referred to as the height of the upper portion of the sidewall. Thickness T2 may be in the range of about 8 nm to about 12 nm, for example, 10 nm. The second nanostructure 54 may have a thickness T3, which may also be referred to as the height of the second nanostructure 54. Thickness T3 may be in the range of about 3 nm to about 7 nm, for example, 5 nm. The ratio of thickness T2 to thickness T3 can be in the range of about 1.8 to about 2.2, for example 2.

[0042] exist Figures 12A to 12C In this process, a semiconductor layer 93 may be formed in the first recess 86 and above the dielectric layer 91. The semiconductor layer 93 may be undoped and contain no dopants. The semiconductor layer 93 may extend from the sidewall of the first recess 86 to the opposite sidewall of the first recess 86. The semiconductor layer 93 may be suspended above the dielectric layer 91, and an air gap 95 (e.g., a void) may be located between the semiconductor layer 93 and the dielectric layer 91, separating them. The semiconductor layer 93 can improve the quality of the subsequently formed epitaxial source / drain region by providing more growth sites, as described in more detail below. The air gap 95 can provide additional electrical isolation between the subsequently formed epitaxial source / drain region and the fin 66, as described in more detail below.

[0043] like Figure 12CAs shown, the top and bottom surfaces of semiconductor layer 93 can be concave. The top surface of semiconductor layer 93 can be located below the top surface of fin 66. The top surface of semiconductor layer 93 can be located below the bottom surface of the second nanostructure 54A. Semiconductor layer 93 can have a thickness T4 at its centerline. Semiconductor layer 93 can cover the upper part of the sidewall of the first recess 86. As a result, semiconductor layer 93 can have a thickness T2 at its ends. Air gap 95 can have an elliptical shape. Air gap 95 can have a thickness T5 at its centerline. Thickness T5 can be greater than about 5 nm. Thickness T1 can be greater than thickness T5. Thickness T4 can be greater than thickness T5.

[0044] Semiconductor layer 93 may comprise a material that is the same as or similar to fin 66, such as silicon, germanium, silicon-germanium, germanium-tin, gallium arsenide, etc. Semiconductor layer 93 may be epitaxially grown from the sidewalls of fin 66 exposed by the first recess 86 (e.g., the upper portion of the sidewall of the first recess 86) using a suitable epitaxial growth process, such as VPE, MBE, CVD epitaxy, etc. In some embodiments, the epitaxial growth process of semiconductor layer 93 may include a growth step and a removal step. During the growth step, dichlorosilane may be used as a precursor, and hydrochloric acid may be used as an etchant; the concentration of the precursor may be greater than the concentration of the etchant. After the growth step, the crystalline material grown from the sidewalls of fin 66 exposed by the first recess 86 may merge to form semiconductor layer 93, while the crystalline material grown from the sidewalls of the second nanostructure 54 may bulge toward each other without merging, possibly because thickness T2 is greater than thickness T3. During the removal step, silane may be used as a precursor, and hydrochloric acid may be used as an etchant; the concentration of the precursor may be less than the concentration of the etchant. The removal step can last for a shorter time than the growth step. After the removal step, the crystalline material grown from the sidewalls of the second nanostructure 54 can be removed, and the semiconductor layer 93 can remain substantially intact.

[0045] Figures 12D to 12G It shows some embodiments Figure 12C A detailed view of region 97 of the cross-sectional view shown in the image. (See also...) Figures 12D to 12G As shown, after the formation of semiconductor layer 93, the second nanostructure 54 may have a convex sidewall recessed from the sidewall of the internal spacer 90, possibly due to a removal step in the epitaxial growth process of semiconductor layer 93. The top of fin 66 may have a length L1. The second nanostructure 54A may have a length L2, which is less than the length L1. The ratio of length L1 to length L2 may be in the range of about 2 to about 1000. The second nanostructure 54B may have a length L3, which is less than the length L2. The second nanostructure 54C may have a length L4, which is less than the length L3. Figure 12DIn the embodiment shown, the sidewalls of the second nanostructure 54 have a circular profile. Figure 12E In the embodiment shown, the sidewalls of the second nanostructure 54 have a trapezoidal profile. Figure 12F In the embodiment shown, the sidewalls of the second nanostructure 54 have a circular trapezoidal profile. Figure 12G In the embodiment shown, the sidewalls of the second nanostructure 54 have a triangular profile.

[0046] exist Figures 13A to 13C In the first recess 86 and above the semiconductor layer 93, an epitaxial source / drain region 92 is formed. The epitaxial source / drain region 92 can refer to either the source or the drain individually or collectively, depending on the context. The epitaxial source / drain region 92 can be epitaxially grown from the sidewalls of the second nanostructure 54 and the top surface of the semiconductor layer 93 using a range of suitable epitaxial growth processes, such as VPE, MBE, CVD epitaxy, etc. Since the top surface of the semiconductor layer 93 can provide additional growth sites for the epitaxial source / drain region 92, the quality of the epitaxial source / drain region 92 can be improved. The dielectric layer 91 and the gas gap 95 provide electrical isolation and reduce the risk of current leakage between the epitaxial source / drain region 92 and the fin 66 during the operation of the subsequently formed semiconductor device. As a result, the performance and reliability of the subsequently formed semiconductor device can be improved.

[0047] In some embodiments, the epitaxial source / drain region 92 can apply stress to the second nanostructure 54, thereby improving performance. For example... Figure 13C As shown, epitaxial source / drain regions 92 are formed in the first recess 86, such that each dummy gate 76 is disposed between corresponding pairs of adjacent epitaxial source / drain regions 92. The epitaxial source / drain regions 92 may be located on the sidewalls of the second nanostructure 54, the internal spacer 90, and the spacer 81, and on the top surface of the semiconductor layer 93. The top surface of the epitaxial source / drain regions 92 may be located above the top surface of the second nanostructure 54C and may have facets.

[0048] An epitaxial source / drain region 92 in an n-type region 50N, such as an NMOS region, can be formed by masking, for example, the p-type region 50P of a PMOS region. Next, the epitaxial source / drain region 92 is epitaxially grown in the n-type region 50N, within the first recess 86. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material on which tensile strain is applied, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc.

[0049] An epitaxial source / drain region 92 in a p-type region 50P, such as a PMOS region, can be formed by masking, for example, the n-type region 50N of an NMOS region. Next, the epitaxial source / drain region 92 is epitaxially grown in the p-type region 50P, within the first recess 86. The epitaxial source / drain region 92 can comprise any acceptable material suitable for a p-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material on which compressive strain is applied, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, etc.

[0050] The epitaxial source / drain region 92, the second nanostructure 54, and / or the substrate 50 can be implanted with dopant to form the source / drain region, similar to the previously discussed process for forming lightly doped source / drain regions, followed by an annealing process. The source / drain region can have a size of approximately 1 x 10⁻⁶. 19 atoms / cm 3 With approximately 1x10 21 atoms / cm 3 The impurity concentrations between these values. The n-type and / or p-type impurities used for the source / drain regions can be any impurities previously discussed. In some embodiments, the epitaxial source / drain regions 92 can be in-situ doped during growth.

[0051] As a result of the epitaxial process used to form epitaxial source / drain regions 92 in the n-type region 50N and p-type region 50P, the upper portion of the epitaxial source / drain regions 92 may have facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these facets result in the merging of adjacent epitaxial source / drain regions 92 of the same nanoFET, as by Figure 13B As shown. In some embodiments, after the epitaxial process is completed, adjacent epitaxial source / drain regions 92 remain separated, as indicated by... Figure 13D As shown.

[0052] The epitaxial source / drain region 92 may include one or more semiconductor material layers. In some embodiments, the epitaxial source / drain region 92 includes a first pad layer 92A located on the sidewalls of the second nanostructure 54 and the top surface of the semiconductor layer 93, a second pad layer 92B located on the first pad layer 92A, and a filling layer 92C located on the second pad layer 92B, such as... Figure 13C As shown in the diagram, the first pad layer 92A, the second pad layer 92B, and the fill layer 92C can be formed of different semiconductor materials and / or can be doped to different dopant concentrations. The first pad layer 92A can be grown first, the second pad layer 92B can be grown on the first pad layer 92A, and the fill layer 92C can be grown on the second pad layer 92B.

[0053] exist Figures 14A to 14C In Figures 12A to 12C A first interlayer dielectric (ILD) 96 is deposited over the structure shown. The first ILD 96 can be formed of a dielectric material and can be deposited by any suitable method such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other insulating materials formed by any acceptable process can be used. A contact etch stop layer (CESL) 94 may be provided between the first ILD 96 and the epitaxial source / drain region 92, mask 78, and spacer 81. The CESL 94 may include a dielectric material different from that of the first ILD 96, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which has a different etch rate than the material of the first ILD 96.

[0054] exist Figures 15A to 15C In this process, a planarization process such as CMP can be implemented to make the top surfaces of the first ILD 96 and CESL 94 flush with the top surface of the dummy gate 76 or the mask 78. The planarization process can also remove the mask 78 on the dummy gate 76, as well as portions of the spacer 81 along the sidewalls of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, spacer 81, first ILD 96, and CESL 94 are flush within the range of process variations. Therefore, the top surface of the dummy gate 76 is exposed through the first ILD 96. In some embodiments, the mask 78 can be retained, in which case the planarization process makes the top surfaces of the first ILD 96 and CESL 94 flush with the top surfaces of the mask 78 and the spacer 81.

[0055] exist Figures 16A to 16C In one or more etching processes, the dummy gate 76 and dummy gate dielectric 71 are removed to form the third recess 98. In some embodiments, the dummy gate 76 and dummy gate dielectric 71 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases, which selectively etches the dummy gate 76 and dummy gate dielectric 71 at a faster rate than etching the first ILD 96 and / or spacer 81. Each of the third recesses 98 exposes a portion of the nanostructure 55 and / or is located on top of a portion of the nanostructure 55, which serves as a channel region in the subsequently completed nanoFET. The portion of the nanostructure 55 that can serve as a channel region is disposed between adjacent pairs of epitaxial source / drain regions 92. During the etching process, the dummy gate dielectric 71 can serve as an etch stop layer when the dummy gate 76 is removed, and the dummy gate dielectric 71 can be removed after the removal of the dummy gate 76.

[0056] exist Figures 17A to 17CIn this process, the first nanostructure 52, which extends the third recess 98, can be removed. Removing the first nanostructure 52 may include using a suitable etching process, such as an isotropic etching process. The etching process can selectively remove material from the first nanostructure 52 without significantly removing material from the second nanostructure 54, the fin 66, or the internal spacer 90. In embodiments where the first nanostructure 52 comprises silicon-germanium and the second nanostructure 54 comprises silicon, an etching process using tetramethylammonium hydroxide (TMAH), ammonia (NH4OH), or the like is used to remove the first nanostructure 52.

[0057] exist Figures 18A to 18C In the third recess 98 and the fourth recess 101, a gate dielectric layer 100 and a gate electrode 102 are formed. The gate dielectric layer 100 can be conformally deposited in the third recess 98 and the fourth recess 101. The gate dielectric layer 100 can be formed on the top surface and sidewalls of the substrate 50, and on the top surface, sidewalls, and bottom surface of the second nanostructure 54. The gate dielectric layer 100 can also be deposited on the top surface of the first ILD 96, CESL 94, spacer 81, and STI region 68, and on the sidewalls of spacer 81 and internal spacer 90. The gate dielectric layer 100 can be completely separated from CESL 94 by spacer 81, and the gate dielectric layer 100 can be completely separated from the first ILD 96 by CESL 94 and spacer 81.

[0058] In some embodiments, the gate dielectric layer 100 includes one or more dielectric layers, such as oxides, metal oxides, or combinations thereof. In some embodiments, the gate dielectric may include a silicon oxide layer and a metal oxide layer above the silicon oxide layer. In some embodiments, the gate dielectric layer 100 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 100 may have a dielectric constant (k) value greater than about 7.0, and may include metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The dielectric constant of the gate dielectric layer 100 may be greater than the dielectric constant of the spacer 81. The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. The method of forming the gate dielectric layer 100 may include molecular beam deposition (MBD), ALD, PECVD, etc.

[0059] Gate electrodes 102 are deposited over the gate dielectric layer 100 and fill the remaining portion of the third recess 98. Gate electrodes 102 may comprise a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although... Figure 18A and Figure 18CA single-layer gate electrode 102 is shown, but the gate electrode 102 may include any number of pad layers, any number of power function tuning layers, and filler material. Any combination of layers constituting the gate electrode 102 may be deposited between adjacent second nanostructures 54 and between the second nanostructure 54A and the substrate 50.

[0060] The formation of the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer 100 in each region is formed of the same material, and the formation of the gate electrode 102 can also occur simultaneously, such that the gate electrode 102 in each region is formed of the same material. In some embodiments, the gate dielectric layer 100 in each region can be formed using different processes, such that the gate dielectric layer 100 can be made of different materials and / or have different numbers of layers, and / or the gate electrode 102 in each region can be formed using different processes, such that the gate electrode 102 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0061] After filling the third recess 98, a planarization process, such as CMP, can be performed to remove excess material from the gate dielectric layer 100 and the gate electrode 102, which are located above the top surface of the first ILD 96. The material of the gate electrode 102 and the remaining portion of the gate dielectric layer 100 can be collectively referred to as the gate structure 103.

[0062] exist Figures 19A to 19C In this process, the gate structure 103 is recessed, and a gate mask 104 is formed in the recess. A second ILD 106 is formed over the first ILD 96 and the gate mask 104. The recess can be formed directly over the gate structure 103 and between the opposite portion of the spacer 81. The gate mask 104 may include one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, etc. A planarization process can be performed to remove excess material from the gate mask 104. The second ILD 106 can be formed using dielectric materials such as PSG, BSG, BPSG, USG, etc., and can be deposited using any suitable method such as CVD, PECVD, FCVD, etc. A CESL 105 can be provided before the deposition of the second ILD 106. The CESL 105 may include a dielectric material having a different etch rate than the material of the second ILD 106, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0063] exist Figures 20A to 20CIn this process, the second ILD 106, CESL 105, the first ILD 96, CESL 94, and the gate mask 104 are patterned to form a fifth recess 108, exposing the top surface of the epitaxial source / drain region 92 and the gate structure 103. The fifth recess 108 can be formed by etching using a series of anisotropic etching processes such as RIE, NBE, etc. During the series of etching processes, a mask such as photoresist can be formed over the second ILD 106 and patterned to mask portions of the second ILD 106. In some embodiments, the fifth recess 108 extends into the epitaxial source / drain region 92 and / or some of the gate structures, and the bottom of the fifth recess 108 may be flush with (e.g., at the same level or at the same distance from the substrate 50) the top surface of the epitaxial source / drain region 92 and the gate structure, or lower (e.g., closer to the substrate 50) the top surface of the epitaxial source / drain region 92 and the gate structure.

[0064] After the fifth recess 108 is formed, a first silicide region 110 is formed above the epitaxial source / drain region 92. The first silicide region 110 may be electrically connected to the epitaxial source / drain region 92. In some embodiments, the first silicide region 110 is formed by first depositing a metal (not shown separately) capable of reacting with the semiconductor material (e.g., silicon, silicon-germanium, germanium) of the underlying epitaxial source / drain region 92 to form a silicide or germanide region, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof, over the exposed portion of the epitaxial source / drain region 92, and then performing a first thermal annealing process to form the first silicide region 110. Then, unreacted portions of the deposited metal are removed, for example, by an etching process. Although the first silicide region 110 is referred to as a silicide region, the first silicide region 110 may also be a germanide region or a silicon-germanium region (e.g., a region comprising both silicide and germanide).

[0065] exist Figures 21A to 21C In the fifth recess 108, source / drain contacts 112 and gate contacts 114 are formed; these can also be referred to as conductive contacts. Figures 21A to 21C The structure shown is referred to as semiconductor device 120. The source / drain contact 112 and gate contact 114 may each include one or more layers, such as a barrier layer, a diffusion layer, and a filler material. The material of the source / drain contact 112 may have a higher conductivity than the material of the underlying epitaxial source / drain region 92. In some embodiments, the source / drain contact 112 and gate contact 114 each include a barrier layer and a conductive material. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, etc.

[0066] Gate contact 114 can be electrically connected to gate electrode 102, and source / drain contact 112 can be electrically connected to first silicide region 110. First silicide region 110 can be considered as part of source / drain contact 112. A planarization process, such as CMP, can be performed to remove excess material from the surface of second ILD 106. After the planarization process, the top surfaces of second ILD 106, source / drain contact 112, and gate contact 114 are flush within the process variation range.

[0067] Figures 22A to 22C This is a cross-sectional view of a semiconductor device 120 according to some embodiments, which is similar to Figures 21A to 21C The embodiment of semiconductor device 120 shown herein, wherein the same reference numerals denote the same components formed by the same process. Figures 22A to 22C In the embodiment of the semiconductor device 120 shown, the semiconductor layer 93 and the dielectric layer 91 are in contact, and no air gap is formed between the semiconductor layer 93 and the dielectric layer 91. The top surface of the semiconductor layer 93 may be concave, and the bottom surface of the semiconductor layer 93 may be convex.

[0068] Figures 23A to 23C This is a cross-sectional view of a semiconductor device 120 according to some embodiments, which is similar to Figures 21A to 21C The embodiment of semiconductor device 120 shown herein, wherein the same reference numerals denote the same components formed by the same process. Figures 23A to 23C In the embodiment of the semiconductor device 120 shown, the top surface of the semiconductor layer 93 is located above the top surface of the fin 66 and below the bottom surface of the second nanostructure 54A. The bottom surface of the semiconductor layer 93 may be concave, and the top surface of the semiconductor layer 93 may be convex with a recess near the centerline of the semiconductor layer 93.

[0069] The embodiments disclosed herein have several advantageous features. By forming a dielectric layer 91, sufficient electrical isolation can be provided to reduce the risk of current leakage between the epitaxial source / drain regions 92 and the fins 66 during operation of the semiconductor device 120. By forming a semiconductor layer 93 over the dielectric layer 91, the quality of the epitaxial source / drain regions 92 can be improved. As a result, the performance and reliability of the semiconductor device 120 can be improved.

[0070] In an embodiment, the semiconductor device includes: a first dielectric layer in contact with the lower surface of a semiconductor structure, wherein the first dielectric layer is located between a first portion and a second portion of the semiconductor structure; a first semiconductor layer above the first dielectric layer, wherein the first semiconductor layer extends from a sidewall of the first portion of the semiconductor structure to a sidewall of the second portion of the semiconductor structure; a source / drain region above the first semiconductor layer; a first semiconductor nanostructure above the top surface of the first portion of the semiconductor structure, wherein the source / drain region is in contact with a sidewall of the first semiconductor nanostructure; a gate structure surrounding the first semiconductor nanostructure, wherein a first portion of the gate structure is located between the first semiconductor nanostructure and the semiconductor structure, wherein a second portion of the gate structure is located above the top surface of the first semiconductor nanostructure, wherein the gate structure includes a gate electrode and a gate dielectric layer, and wherein the gate electrode includes a titanium-based material; and a gate spacer along the sidewall of the second portion of the gate structure, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer. In an embodiment, the first semiconductor layer covers the sidewalls of the first portion and the second portion of the semiconductor structure. In one embodiment, the air gap is located between the first semiconductor layer and the first dielectric layer. In another embodiment, the first portion of the gate structure contacts the top surface of the first portion of the semiconductor structure and the bottom surface of the first semiconductor nanostructure, wherein the top surface of the first semiconductor layer is located below the bottom surface of the first semiconductor nanostructure. In another embodiment, the top surface of the first semiconductor layer is located below the top surface of the first portion of the semiconductor structure. In yet another embodiment, the top surface of the first semiconductor layer is located above the top surface of the first portion of the semiconductor structure. In yet another embodiment, the first portion of the semiconductor structure has a greater thickness than the first semiconductor nanostructure along a direction perpendicular to the top surface of the first portion of the semiconductor structure. In yet another embodiment, the first portion of the semiconductor structure has a greater width than the first semiconductor nanostructure along a direction parallel to the top surface of the first portion of the semiconductor structure.

[0071] In an embodiment, a method for forming a semiconductor device includes: etching a recess in a semiconductor structure; forming a first dielectric layer in contact with the bottom surface of the recess; growing a first epitaxial structure over the first dielectric layer, wherein the first epitaxial structure is located on a first sidewall and a second sidewall of the recess, and wherein the first sidewall of the recess faces the second sidewall of the recess; growing a second epitaxial structure over the first epitaxial structure, wherein the second epitaxial structure is doped with a dopant, wherein the second epitaxial structure includes a first portion and a second portion, wherein the first portion has a first concentration of dopant, and wherein the second portion has a second concentration of dopant different from the first concentration; and forming a conductive contact over the second epitaxial structure, wherein the conductive contact is electrically connected to the second epitaxial structure, and wherein the conductivity of the conductive contact is greater than the conductivity of the second epitaxial structure. In an embodiment, the top surface of the first dielectric layer and the bottom surface of the first epitaxial structure are separated by a gap. In an embodiment, the top surface of the first dielectric layer is in contact with the bottom surface of the first epitaxial structure. In an embodiment, the top surface of the first dielectric layer is concave. In one embodiment, the bottom surface of the first epitaxial structure is concave. In another embodiment, the method further includes forming a first semiconductor nanostructure above the top surface of the semiconductor structure, wherein the second epitaxial structure is located on the sidewall of the first semiconductor nanostructure, and wherein the first epitaxial structure has a greater thickness than the first semiconductor nanostructure.

[0072] In an embodiment, a method of forming a semiconductor device includes: forming a semiconductor fin; forming an isolation region, wherein, in a first cross-sectional view, the isolation region is located on a first sidewall of the semiconductor fin, wherein the isolation region comprises a material having a dielectric constant in the range of 3 to 5; forming a recess in the semiconductor fin, wherein, in a second cross-sectional view, the recess exposes a second sidewall and a third sidewall of the semiconductor fin, and wherein, the first cross-sectional view is perpendicular to the second cross-sectional view; forming a first semiconductor nanostructure above the semiconductor fin; forming a first dielectric layer in the recess, wherein, in the second cross-sectional view, the top surface of the first dielectric layer is located below the top surface of the semiconductor fin; growing a first semiconductor layer from the second sidewall and the third sidewall of the semiconductor fin, above the first dielectric layer, and wherein, in the second cross-sectional view, the top surface of the first semiconductor layer is located below the bottom surface of the first semiconductor nanostructure; growing source / drain regions from the first semiconductor layer and the first semiconductor nanostructure; forming a contact etch stop layer above the source / drain regions; and forming an interlayer dielectric layer above the contact etch stop layer, wherein the contact etch stop layer and the interlayer dielectric layer comprise different materials. In one embodiment, the bottom surface of the first semiconductor layer is suspended above the top surface of the first dielectric layer. In another embodiment, in a second cross-sectional view, the bottom surface of the first semiconductor layer is concave, and the top surface of the first dielectric layer is concave. In another embodiment, the height of the second sidewall of the semiconductor fin is greater than the height of the first semiconductor nanostructure. In another embodiment, in a first cross-sectional view, the first semiconductor layer is in contact with the isolation region. In yet another embodiment, the method further includes forming a second semiconductor nanostructure over the first semiconductor nanostructure, wherein, in a second cross-sectional view, the second semiconductor nanostructure has a smaller length than the first semiconductor nanostructure.

[0073] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: A first dielectric layer is in contact with the lower surface of the semiconductor structure, wherein the first dielectric layer is located between a first portion of the semiconductor structure and a second portion of the semiconductor structure; A first semiconductor layer is located above the first dielectric layer, wherein the first semiconductor layer extends from the sidewall of the first portion of the semiconductor structure to the sidewall of the second portion of the semiconductor structure; The source / drain region is located above the first semiconductor layer; A first semiconductor nanostructure is located above the top surface of the first portion of the semiconductor structure, wherein the source / drain region is in contact with the sidewall of the first semiconductor nanostructure. A gate structure is located around the first semiconductor nanostructure, wherein a first portion of the gate structure is located between the first semiconductor nanostructure and the semiconductor structure, wherein a second portion of the gate structure is located above the top surface of the first semiconductor nanostructure, wherein the gate structure includes a gate electrode and a gate dielectric layer, and wherein the gate electrode comprises a titanium-based material; and A gate spacer along the sidewall of the second portion of the gate structure, wherein the dielectric constant of the gate dielectric layer is greater than the dielectric constant of the gate spacer.

2. The semiconductor device according to claim 1, wherein, The first semiconductor layer covers the sidewalls of the first portion of the semiconductor structure and the sidewalls of the second portion of the semiconductor structure.

3. The semiconductor device according to claim 1, wherein, The air gap is located between the first semiconductor layer and the first dielectric layer.

4. The semiconductor device according to claim 1, wherein, The first portion of the gate structure is in contact with the top surface of the first portion of the semiconductor structure and the bottom surface of the first semiconductor nanostructure, wherein the top surface of the first semiconductor layer is located below the bottom surface of the first semiconductor nanostructure.

5. The semiconductor device according to claim 4, wherein, The top surface of the first semiconductor layer is located below the top surface of the first portion of the semiconductor structure.

6. The semiconductor device according to claim 4, wherein, The top surface of the first semiconductor layer is located above the top surface of the first portion of the semiconductor structure.

7. The semiconductor device according to claim 1, wherein, Along a direction perpendicular to the top surface of the first portion of the semiconductor structure, the first portion of the semiconductor structure has a greater thickness than the first semiconductor nanostructure.

8. The semiconductor device according to claim 1, wherein, Along a direction parallel to the top surface of the first portion of the semiconductor structure, the first portion of the semiconductor structure has a wider width than the first semiconductor nanostructure.

9. A method for forming a semiconductor device, the method comprising: Etching recesses into semiconductor structures; A first dielectric layer is formed that contacts the bottom surface of the recess; A first epitaxial structure is grown above the first dielectric layer, wherein the first epitaxial structure is located on a first sidewall of the recess and a second sidewall of the recess, and wherein the first sidewall of the recess faces the second sidewall of the recess. A second epitaxial structure is grown over the first epitaxial structure, wherein the second epitaxial structure is doped with a dopant, wherein the second epitaxial structure comprises a first portion and a second portion, wherein the first portion has a first concentration of the dopant, and wherein the second portion has a second concentration of the dopant different from the first concentration of the dopant; and A conductive contact is formed above the second epitaxial structure, wherein the conductive contact is electrically connected to the second epitaxial structure, and wherein the conductivity of the conductive contact is greater than the conductivity of the second epitaxial structure.

10. A method of forming a semiconductor device, the method comprising: Forming semiconductor fins; An isolation region is formed, wherein, in a first cross-sectional view, the isolation region is located on a first sidewall of the semiconductor fin, wherein the isolation region comprises a material having a dielectric constant in the range of 3 to 5; A recess is formed in the semiconductor fin, wherein, in a second cross-sectional view, the recess exposes a second sidewall and a third sidewall of the semiconductor fin, and wherein the first cross-sectional view is perpendicular to the second cross-sectional view; A first semiconductor nanostructure is formed above the semiconductor fin; A first dielectric layer is formed in the recess, wherein, in the second cross-sectional view, the top surface of the first dielectric layer is located below the top surface of the semiconductor fin; A first semiconductor layer is grown over the first dielectric layer from the second sidewall and the third sidewall of the semiconductor fin, wherein, in the second cross-sectional view, the top surface of the first semiconductor layer is located below the bottom surface of the first semiconductor nanostructure; Source / drain regions are grown from the first semiconductor layer and the first semiconductor nanostructure; A contact etch stop layer is formed above the source / drain regions; and An interlayer dielectric layer is formed above the contact etch stop layer, wherein the contact etch stop layer and the interlayer dielectric layer comprise different materials.

Images