A method for manufacturing a micro light emitting diode driving backplane

Abstract

The application provides a preparation method of a micro light emitting diode driving backboard and the driving backboard. The preparation method forms a driving backboard precursor on a glass substrate; the driving backboard precursor comprises a driving circuit layer and a passivation layer covering the driving circuit layer, the driving circuit layer comprises a source-drain layer for connecting a micro light emitting diode, and the source-drain layer for connecting the micro light emitting diode comprises a pad; a light-absorbing flat layer is formed on the passivation layer covering the driving circuit layer; the light-absorbing flat layer adopts a black light-absorbing color resistance material; an opening exposing the pad is prepared on the light-absorbing flat layer through a photoetching process, and a driving backboard finished product is obtained, so that the process cost is reduced and the post-process flow is simplified.

Description

Technical Field

[0001] This application relates to the field of LED display technology, and more specifically, to a method for fabricating a micro light-emitting diode driving backplane. Background Technology

[0002] MicroLED (Micro Light Emitting Diode) display technology has wide applications in the display field due to its advantages such as wide color gamut, fast response speed, high brightness, and long lifespan. Glass-based TFT driving technology combines MicroLED with TFT driving circuits on a glass substrate, becoming the mainstream solution for large-size MicroLED displays. The glass substrate has an ultra-flat surface and a low coefficient of thermal expansion, effectively improving the detail and stability of the displayed image and supporting seamless splicing, capable of supporting MicroLED displays exceeding 100 inches. However, due to the light transmittance of the glass substrate, to address the reflection from the glass and the driving backplane, existing processes typically add a black barrier after the mass transfer process to reduce the blackness of the black states, thereby significantly improving the contrast ratio of MicroLEDs.

[0003] However, existing processes typically require a separate black blocking process after transfer, and involve cutting large glass substrates into smaller sizes (usually about 10 inches) before processing. This not only increases costs but also makes subsequent processes cumbersome. Summary of the Invention

[0004] In view of this, the purpose of this application is to provide a method for fabricating a micro light-emitting diode driving backplane, which integrates a blackening process into the glass substrate process, effectively simplifying the subsequent process flow and reducing the process cost.

[0005] This application provides a method for fabricating a micro LED driving backplane, the method comprising: A driving backplane precursor is formed on a glass substrate; the driving backplane precursor includes a driving circuit layer and a passivation layer covering the driving circuit layer, the driving circuit layer includes a source-drain layer for connecting a micro light-emitting diode, and the source-drain layer for connecting the micro light-emitting diode includes pads. A light-absorbing planarization layer is formed on the passivation layer covering the driving circuit layer; the light-absorbing planarization layer is made of black light-absorbing color resist material. An opening exposing the pads is formed on the light-absorbing planarization layer using a photolithography process to obtain the finished drive backplane.

[0006] In some embodiments, in the method for fabricating the micro LED driving backplane, the thickness of the light-absorbing planarization layer is 1 μm to 20 μm, and the reflectivity of the light-absorbing planarization layer is less than 5%.

[0007] In some embodiments, the thickness of the light-absorbing planarization layer in the method for fabricating the micro LED driving backplane is determined based on the thickness of the last layer of metal traces in the driving backplane precursor. When the thickness of the last layer of metal traces in the front of the drive backplate is less than or equal to 1.8 μm, the thickness of the light-absorbing planarization layer is a first preset thickness value; the first preset thickness value is 2 μm to 3 μm. When the thickness of the last metal trace of the drive backplate front body is greater than 1.8 μm, the thickness of the light-absorbing planarization layer is the sum of the thickness of the last metal trace and the second preset thickness value.

[0008] In some embodiments, the method for fabricating the micro-LED driving backplane, after forming an opening exposing the pads on the light-absorbing planarization layer by photolithography, the method further includes: A barrier planarization layer is formed on the light-absorbing planarization layer, and the barrier planarization layer is processed by photolithography to form a barrier structure surrounding the micro light-emitting diodes connected to the pads; the barrier planarization layer is made of black light-absorbing color resist material.

[0009] In some embodiments, in the method for fabricating the micro LED driving backplate, the height of the retaining wall is 5 μm to 20 μm; When the micro LED is a flip chip, the barrier is not lower than the micro LED; or the barrier is lower than the micro LED and the height difference is within a preset height difference range.

[0010] In some embodiments, in the method for fabricating the micro-LED driving backplane, the step of forming an opening exposing the pads on the light-absorbing planarization layer by photolithography includes: Based on the parameters of the micro light-emitting diode, when forming an opening that exposes the pad on the light-absorbing planarization layer by photolithography, at least a portion of the light-absorbing planarization layer in the region directly below the micro light-emitting diode is removed simultaneously.

[0011] In some embodiments, the method for fabricating the micro LED driving backplane further includes: The resulting drive backplane is divided into multiple sub-sub-substrates.

[0012] In some embodiments, a micro LED driving backplane is also provided, the micro LED driving backplane comprising: a driving backplane front body and a light-absorbing planarization layer; The driving backplane front body includes a glass substrate, a driving circuit layer and a passivation layer covering the driving circuit layer. The driving circuit layer is disposed on the glass substrate and includes a source-drain layer for connecting micro light-emitting diodes. The source-drain layer includes pads. The light-absorbing planarization layer is disposed on the passivation layer. The light-absorbing planarization layer is made of black light-absorbing color resist material. An opening is formed on the light-absorbing planarization layer to expose the pads. The light-absorbing planarization layer is prepared on the passivation layer covering the driving circuit layer, and the opening exposing the pads is formed on the light-absorbing planarization layer by photolithography.

[0013] In some embodiments, in the micro LED driving backplane, a barrier structure is further provided on the light-absorbing planarization layer, the barrier structure surrounds the micro LED connected to the pad, and the barrier structure is made of the black light-absorbing color resist material.

[0014] In some embodiments, in the micro LED driving backplane, the thickness of the barrier structure is 5 μm to 20 μm; and the thickness of the light-absorbing planarization layer is 1 μm to 20 μm.

[0015] This application provides a method for fabricating a micro LED driving backplane and the driving backplane itself. The fabrication method involves forming a driving backplane precursor on a glass substrate. The driving backplane precursor includes a driving circuit layer and a passivation layer covering the driving circuit layer. The driving circuit layer includes source / drain layers for connecting the micro LEDs, and the source / drain layers for connecting the micro LEDs include pads. A light-absorbing planarization layer is formed on the passivation layer covering the driving circuit layer. The light-absorbing planarization layer uses a black light-absorbing color resist material. An opening exposing the pads is formed on the light-absorbing planarization layer using photolithography to obtain the finished driving backplane. The finished driving backplane can be divided into multiple sub-substrates, thereby integrating the blackening process into the driving backplane process. Compared to a process without blackening, the contrast ratio can be significantly improved, reaching up to 1,000,000:1. Compared to conventional back-end blackening processes, integrating the blackening process into G6 (1500mm × 1850mm) and G8.5 (2200mm × 1850mm) specifications significantly improves the driving backplane process. Direct implementation on large-format glass substrates such as 2500 not only significantly reduces manufacturing costs but also effectively simplifies subsequent processes, thus achieving a MicroLED driving backplane that combines low cost and high contrast. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A comparison diagram showing the presence or absence of a blackening process in existing technologies is presented; Figure 2 A schematic cross-sectional view of a backplate without a blackening process in the prior art is shown; Figure 3 A top view of a backplate without a blackening process in the prior art is shown; Figure 4 A flowchart illustrating the fabrication method of the micro LED driving backplane described in the embodiments of this application is shown; Figure 5 This diagram illustrates the relationship between the thickness and reflectivity of the light-absorbing planarization layer described in an embodiment of this application. Figure 6 A schematic diagram illustrating the effect of the light-absorbing planarization layer described in this application on LED bonding is shown.

[0018] Figure 7 This document shows a schematic diagram of the shielding metal layer described in an embodiment of this application. Figure 8 A schematic diagram of the buffer layer and amorphous silicon layer described in an embodiment of this application is shown; Figure 9 A schematic diagram of the polycrystalline silicon layer described in an embodiment of this application is shown; Figure 10 A schematic diagram of the gate insulating layer and gate layer described in an embodiment of this application is shown; Figure 11 A schematic diagram of the interlayer dielectric layer connection hole according to an embodiment of this application is shown; Figure 12 A schematic diagram of the first source-drain layer in an embodiment of this application is shown; Figure 13 A schematic diagram of the first passivation layer and the first planarization layer in an embodiment of this application is shown; Figure 14 A schematic diagram of the second source / drain layer according to an embodiment of this application is shown; Figure 15 A schematic diagram of the second passivation layer and the second planarization layer in an embodiment of this application is shown. Figure 16 A cross-sectional schematic diagram of a driving backplate with transferred Micro LEDs as described in an embodiment of this application is shown; Figure 17This illustration shows a top view of a driving backplate with transferred Micro LEDs as described in an embodiment of this application. Figure 18 A cross-sectional schematic diagram of the drive backplate with the BM cutout under the LED described in the embodiment of this application is shown; Figure 19 A cross-sectional schematic diagram of the drive back plate for preparing a thick retaining wall according to an embodiment of this application is shown. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the accompanying drawings in this application are for illustrative and descriptive purposes only and are not intended to limit the scope of protection of this application. Furthermore, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate operations implemented according to some embodiments of this application. It should be understood that the operations in the flowcharts may not be implemented in sequence, and steps without logical contextual relationships may be reversed or implemented simultaneously. In addition, those skilled in the art, guided by the content of this application, may add one or more other operations to the flowcharts, or remove one or more operations from the flowcharts.

[0020] Furthermore, the described embodiments are merely some, not all, of the embodiments of this application. The components of the embodiments of this application described and illustrated herein can typically be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0021] It should be noted that the term "comprising" will be used in the embodiments of this application to indicate the presence of the features declared thereafter, but does not exclude the addition of other features.

[0022] MicroLED (Micro Light Emitting Diode) display technology has wide applications in the display field due to its advantages such as wide color gamut, fast response speed, high brightness, and long lifespan. Glass-based TFT driving technology combines MicroLED with TFT driving circuits on a glass substrate, becoming the mainstream solution for large-size MicroLED displays. The glass substrate has an ultra-flat surface and a low coefficient of thermal expansion, effectively improving the detail and stability of the displayed image and supporting seamless splicing, capable of supporting MicroLED displays exceeding 100 inches. However, due to the light transmittance of the glass substrate, to address the reflection from the glass and the driving backplane, existing processes typically add a black barrier after the mass transfer process to reduce the blackness of the black states, thereby significantly improving the contrast ratio of MicroLEDs.

[0023] Please refer to Figure 1 , Figure 1 The image shows a comparison of the microLED with and without a blackening process; the left side shows the top surface of the microLED after mass transfer without the blackening process, and the right side shows the top surface with added black blocking; it can be seen that the contrast of the microLED with blackening process is significantly improved.

[0024] The top surface is the front of the drive backplane (that is, the surface facing upwards after all the circuitry is completed).

[0025] Conventional backplane manufacturing processes typically require a separate black blocking process after transfer, and often involve cutting large glass substrates into smaller sizes (usually around 10 inches). This is not only costly but also complicates subsequent processes. Without a blackening process, the metallic reflection from the backplane will result in insufficient blackness, reducing contrast by two orders of magnitude, as shown below. Figure 2 and Figure 3 As shown, Figure 2 A schematic cross-sectional view of the back panel without the blackening process is shown. Figure 3 A top view of the back panel without the blackening process is shown.

[0026] Based on this, this application provides a method for fabricating a micro LED driving backplane and a driving backplane. The fabrication method involves forming a driving backplane precursor on a glass substrate. The driving backplane precursor includes a driving circuit layer and a passivation layer covering the driving circuit layer. The driving circuit layer includes source and drain layers for connecting the micro LEDs, and the source and drain layers for connecting the micro LEDs include pads. A light-absorbing planarization layer is formed on the passivation layer covering the driving circuit layer. The light-absorbing planarization layer uses a black light-absorbing color resist material. An opening exposing the pads is formed on the light-absorbing planarization layer using a photolithography process to obtain a finished driving backplane. The finished driving backplane can be divided into multiple sub-substrates, thereby integrating the blackening process into the driving backplane process. Compared with no blackening process, the contrast ratio can be significantly improved, reaching up to 1,000,000:1. Compared with conventional back-end blackening processes, by integrating the blackening process into G6 (1500mm × 1850mm) and G8.5 (2200mm × 1850mm) specifications, the contrast ratio can be significantly improved. Direct implementation on large-format glass substrates such as 2500 not only significantly reduces manufacturing costs but also effectively simplifies subsequent processes, thus achieving a MicroLED driving backplane that combines low cost and high contrast.

[0027] Please refer to Figure 4 , Figure 4 A flowchart illustrating the fabrication method of the micro LED driving backplane according to an embodiment of this application is shown; the fabrication method of the micro LED driving backplane includes the following steps S401-S403: S401. A driving backplane precursor is formed on a glass substrate; the driving backplane precursor includes a driving circuit layer and a passivation layer covering the driving circuit layer, the driving circuit layer includes a source-drain layer for connecting a micro light-emitting diode, and the source-drain layer for connecting the micro light-emitting diode includes pads. S402. A light-absorbing planarization layer is formed on the passivation layer covering the driving circuit layer; the light-absorbing planarization layer is made of black light-absorbing color resist material. S403. An opening exposing the pads is formed on the light-absorbing planarization layer by photolithography to obtain the finished drive backplane.

[0028] In some embodiments, in the method for preparing the micro LED driving backplane, the glass substrate is a large-size glass substrate such as G6 or G8. The preparation method further includes: The resulting drive backplane is divided into multiple sub-sub-substrates.

[0029] The light-absorbing planarization layer uses black light-absorbing color resist material, which can effectively absorb ambient light and avoid reflection from the metal traces (such as source and drain layers) in the driver backplane, so that the display achieves a pure black effect when in black mode; compared with the driver backplane without blackening treatment, the contrast ratio can be improved by 2 orders of magnitude, reaching 1,000,000:1, which significantly improves the display quality.

[0030] The black light-absorbing color resist material is placed above the passivation layer, that is, on the top layer of the drive backplate, which can block the reflection of the lower metal traces to the greatest extent and achieve the best blackening effect.

[0031] The light-absorbing planarization layer is integrated into the drive backplane manufacturing process using a black light-absorbing color resist material and is directly applied to a G6-sized (1500mm × 1850mm) glass substrate. A single G6 substrate can be divided into approximately 80 10-inch-sized sub-substrates. Compared to the existing technology of dividing and then blackening, the blackening process can be completed on the G6 production line simultaneously, eliminating the need to process each sub-substrate individually, thus significantly improving production efficiency.

[0032] The photolithography process used for the light-absorbing planarization layer is compatible with the existing driving backplane manufacturing process and can be implemented directly using existing G6 production line equipment without the need for additional large-scale equipment investment.

[0033] The driving circuit layer can adopt active driving or passive driving methods. Active driving includes any one of IC driving, oxide semiconductor driving, low temperature polycrystalline silicon driving or low temperature polycrystalline oxide driving. There is no need to limit the specific driving method and film structure, and it can adapt to the needs of various MicroLED display products.

[0034] In some embodiments, the thickness of the light-absorbing planarization layer is 1 μm to 20 μm, and the reflectivity of the light-absorbing planarization layer is less than 5%.

[0035] In some embodiments, in the method for fabricating the micro LED driving backplane, the thickness of the light-absorbing planarization layer is determined based on the thickness of the last layer of metal traces in the driving backplane precursor. When the thickness of the last layer of metal traces in the front of the drive backplate is less than or equal to 1.8 μm, the thickness of the light-absorbing planarization layer is a first preset thickness value; the first preset thickness value is 2 μm to 3 μm. When the thickness of the last metal trace of the drive backplate front body is greater than 1.8 μm, the thickness of the light-absorbing planarization layer is the sum of the thickness of the last metal trace and the second preset thickness value.

[0036] For example, the first preset thickness value is 2μm, and the second preset thickness value is 0.5μm.

[0037] Please refer to Figure 5 , Figure 5 A schematic diagram showing the relationship between the thickness and reflectivity of the light-absorbing planarization layer is shown; When the thickness of the light-absorbing planarization layer is between 0.1 and 1 μm, its reflectivity decreases at the fastest rate, and the thickness plays an important role. When the thickness is between 1.5 μm and 3 μm, the rate of reflectivity decrease slows down, and the effect of the thickness weakens. When the thickness is greater than 3 μm, the rate of reflectivity decrease is very low.

[0038] Based on this, from the perspective of reflectivity, the preferred thickness of the light-absorbing planarization layer is 0.7µm to 3µm, and from the perspective of flatness, the preferred thickness of the light-absorbing planarization layer is 2µm or more. From the perspective of cost, the thinner the PLN2, the better. Therefore, in some embodiments, a thickness of 2µm to 3µm is preferred, which can stably meet the reflectivity requirements, while also meeting the flatness requirements and cost control needs, thus achieving the optimal balance between reflectivity, flatness, and cost.

[0039] The thickness of the light-absorbing planarization layer can be adjusted to adapt to the thickness of the last metal trace. When the thickness of the last metal trace is large (e.g., greater than 1.8 μm), the thickness of the light-absorbing planarization layer is increased accordingly (e.g., metal trace thickness + 0.5 μm, metal 3 μm, then the thickness of the light-absorbing planarization layer is 3.5 μm) to ensure coverage and flatness. A flatness of 2 μm for the light-absorbing planarization layer is suitable for the thickness of the last metal trace being less than 1.8 μm. This thickness adaptation design allows the equipment process to be applicable to different metal trace thickness schemes, exhibiting good process compatibility. In some embodiments, the method for fabricating the micro-LED driving backplane, after forming an opening exposing the pads on the light-absorbing planarization layer by photolithography, the method further includes: A barrier planarization layer is formed on the light-absorbing planarization layer, and the barrier planarization layer is processed by photolithography to form a barrier structure surrounding the micro light-emitting diodes connected to the pads; the barrier planarization layer is made of black light-absorbing color resist material.

[0040] In some embodiments, in the method for fabricating the micro LED driving backplate, the height of the retaining wall is 5μm-20μm.

[0041] When the micro LED is a flip chip, the barrier is not lower than the micro LED; or the barrier is lower than the micro LED and the height difference is within a preset height difference range.

[0042] In some embodiments, the preset height difference ranges from 0 μm to 1 μm. In other words, the thickness of a typical flip-chip mass transfer LED is around 10µm (with substrates such as glass and sapphire). Therefore, the thickness of the barrier can be greater than, equal to, or slightly less than the height of the LED after bonding.

[0043] The preparation method described in this application further provides a barrier structure on the light-absorbing planarization layer, and the barrier structure is also made of black light-absorbing color resist material. On the basis of the light-absorbing planarization layer completely blocking the reflection of the lower metal layer, physical isolation is further formed between adjacent micro light-emitting diodes. This can effectively absorb and block the side light emitted by the micro light-emitting diodes, avoid light crosstalk between adjacent LED units, thereby improving the display effect and avoiding color deviation and contrast reduction caused by light crosstalk.

[0044] In embodiments with a barrier structure, the barrier structure and the light-absorbing planarization layer work together to provide optical isolation, further reducing optical crosstalk between adjacent pixels and improving color purity and display quality. The thickness of the barrier structure can be flexibly selected according to the actual height of the micro LED chip; when the barrier thickness is close to the LED height, the optical crosstalk isolation effect is excellent without wasting material. Simultaneously, with the barrier structure in place, the thickness of the light-absorbing planarization layer can be appropriately reduced while still meeting the requirements for metal trace coverage, thereby lowering material costs.

[0045] It should be noted that for LEDs with substrates, the thickness is often tens or even hundreds of micrometers, so the effect of the barrier is relatively limited.

[0046] In some embodiments, in the method for fabricating the micro-LED driving backplane, the step of forming an opening exposing the pads on the light-absorbing planarization layer by photolithography includes: Based on the parameters of the micro light-emitting diode, when forming an opening that exposes the pad on the light-absorbing planarization layer by photolithography, at least a portion of the light-absorbing planarization layer in the region directly below the micro light-emitting diode is removed simultaneously.

[0047] In some embodiments, at least a portion of the light-absorbing planarization layer in the region directly below the micro LED is completely removed.

[0048] Beneath the micro LED chip lies a relatively thick planarization layer (approximately 20 μm thick). Since MicroLEDs typically employ a flip-chip structure, when the LED structure (pads and protrusions) is small, the LED can easily become stuck on the planarization layer during bonding. The planarization layer acts as a fulcrum. However, when the LED structure (pads and protrusions) is relatively large, this is not a problem. Please refer to [reference needed]. Figure 6 , Figure 6 A schematic diagram illustrating the effect of the light-absorbing planarization layer described in this application on LED bonding is shown.

[0049] To address the issue of poor bonding caused by the light-absorbing planarization layer, this application example removes part or all of the light-absorbing planarization layer directly below the micro LED while opening the window. This reduces the adverse effect of the light-absorbing planarization layer thickness on the bonding height, improves the adhesion and pressure uniformity of the bonding interface, and thus enhances the bonding effect of mass transfer.

[0050] Since the local removal of the light-absorbing planarization layer is achieved simultaneously in the same photolithography step that forms the pad opening, rather than adding a separate photolithography or etching process after the window is opened, the achievement of this technology effect hardly increases the additional process steps, equipment investment and labor costs. While improving bonding yield and reliability, it maintains the advantage of low cost.

[0051] The following describes how the technical solution is implemented using a simplified LTPS process for the AA display area, specifically including the following process flow.

[0052] Step A1: Fabrication of the shielding metal layer: A shield metal layer of molybdenum (Mo) with a thickness of 100 nm is deposited on a glass substrate using a magnetron sputtering process, and then the corresponding pattern is formed using a photolithography process.

[0053] Please refer to Figure 7 , Figure 7 A schematic diagram of the shielding metal layer described in an embodiment of this application is shown.

[0054] Step A2: Fabrication of the buffer layer and amorphous silicon layer (Buffer + a-Si): A silicon nitride / silicon oxide / amorphous silicon composite layer with thicknesses of 100 nm / 300 nm / 50 nm was continuously deposited using chemical vapor deposition (CVD). The silicon nitride and silicon oxide stack served as a buffer layer, while the amorphous silicon layer (a-Si) served as the active layer. The layers were then subjected to a high-temperature annealing process at 450 °C for hydrogen removal, followed by cleaning with hydrofluoric acid (HF) to remove the surface oxide film.

[0055] Please refer to Figure 8 , Figure 8 A schematic diagram of the buffer layer and amorphous silicon layer described in an embodiment of this application is shown.

[0056] Step A3: Fabrication of a polycrystalline silicon layer (p-Si): The amorphous silicon layer (a-Si) is transformed into a crystalline polycrystalline silicon layer (p-Si) using an excimer laser annealing (ELA) process. Doping is then performed according to process requirements, and finally, the polycrystalline silicon layer is patterned using photolithography to define the active region of the driving transistor.

[0057] Please refer to Figure 9 , Figure 9 A schematic diagram of the polycrystalline silicon layer described in an embodiment of this application is shown.

[0058] Step A4. Fabrication of the gate insulating layer and gate layer (GI + Gate): A gate insulating layer (GI) of silicon oxide (SiO) with a thickness of 120 nm is deposited using chemical vapor deposition (CVD) (a stacked structure of silicon oxide and silicon nitride can also be used). Subsequently, a gate layer of molybdenum (Mo) with a thickness of 300 nm is deposited using magnetron sputtering. Finally, the gate pattern is formed using photolithography, during which doping and lightly doped drain (LDD) etching are performed.

[0059] Please refer to Figure 10 , Figure 10 A schematic diagram of the gate insulating layer and gate layer described in an embodiment of this application is shown.

[0060] Step A5. Fabricate interlayer dielectric layer connection vias (SD1 vias): Interlayer dielectric (ILD) layers of silicon oxide / silicon nitride were deposited using chemical vapor deposition (CVD) with thicknesses of 200 nm and 200 nm, respectively. Activation was then achieved through rapid thermal annealing (RTA). Contact holes were formed using photolithography, and residual silicon oxide within the holes was removed by cleaning with a buffered oxide etchant (BOE).

[0061] Please refer to Figure 11 , Figure 11 A schematic diagram of the interlayer dielectric layer connection hole described in an embodiment of this application is shown.

[0062] Step A6. Fabricate the first source / drain layer (SD1): The first source / drain layer (SD1) was deposited using a magnetron sputtering process. The material was a titanium / aluminum / titanium (Ti / Al / Ti) stack with thicknesses of 50 nm / 600 nm / 50 nm, respectively. Finally, the corresponding pattern was formed using a photolithography process to serve as the first source / drain electrode for driving the transistor.

[0063] The first source-drain layer (SD1) is the first source-drain metal trace layer in the "driving circuit layer" described in the embodiments of this application.

[0064] Please refer to Figure 12 , Figure 12 A schematic diagram of the first source-drain layer in an embodiment of this application is shown.

[0065] Step A7. Prepare the first passivation layer and the first planarization layer (PVX1 + PLN1): The first passivation layer (PVX1, Passivation 1) was deposited using chemical vapor deposition (CVD) with a thickness of 300 nm using silicon nitride (SiN). The first planarization layer (PLN1, Planarization Layer 1) with a thickness of 2.5 μm was then fabricated using photolithography and cured at 250 °C. Finally, via etching was performed using photolithography down to the first source / drain layer (SD1).

[0066] Please refer to Figure 13 , Figure 13 A schematic diagram of the first passivation layer and the first planarization layer in an embodiment of this application is shown.

[0067] Step A8. Fabricate the second source / drain layer (SD2): The second source / drain layer (SD2) is deposited using magnetron sputtering, with a molybdenum / copper (Mo / Cu) stack of 50 nm and 2000 nm thicknesses, respectively (a thicker copper layer can also be prepared using electroplating). Finally, the corresponding pattern is formed using photolithography. Depending on the backplane process requirements, the routing of a third source / drain layer (SD3) or a fourth source / drain layer (SD4) can be selected.

[0068] The second source-drain layer is one of the specific implementations of the "source-drain layer for connecting micro light-emitting diodes" of the driving circuit layer described in the embodiments of this application. The uppermost metal surface (pad area) of the second source-drain layer is used for subsequent connection of micro light-emitting diodes.

[0069] Please refer to Figure 14 , Figure 14 A schematic diagram of the second source-drain layer in an embodiment of this application is shown.

[0070] Step A9. Prepare the second passivation layer PVX2 and the second planarization layer PLN2 (the second planarization layer is the light-absorbing planarization layer, and the second passivation layer is the "passivation layer covering the driving circuit layer" described in the embodiments of this application): The second passivation layer (PVX2, Passivation 2) was deposited using chemical vapor deposition (CVD) with a thickness of 300 nm using silicon nitride (SiN). The second planarization layer (PLN2, Planarization Layer 2, i.e., light-absorbing planarization layer) was then prepared using photolithography and cured at high temperature. Finally, it was etched using photolithography to expose the pad areas of the second source / drain layer (SD2).

[0071] Please refer to Figure 15 , Figure 15 This illustration shows a schematic diagram of the second passivation layer and the second planarization layer in an embodiment of this application. Figure 15 As can be seen, the first planarization layer (i.e., the light-absorbing planarization layer) is black.

[0072] The second planarization layer PLN2 (i.e., light-absorbing planarization layer) is set after the last metal trace (i.e., the second source-drain layer SD2). It uses black light-absorbing color resist material (BM, Black Matrix), with a reflectivity of less than 5% and a thickness ranging from 1μm to 20μm. This makes the exposed substrate surface in the light-emitting area, except for the micro light-emitting diode pads, black, thereby achieving high-contrast display.

[0073] Step A10. Mass transfer of the rear-end miniature LED: The microLED chip is transferred to the aforementioned driving backplane using a mass transfer process, so that the electrodes of the microLED are bonded to the corresponding pads.

[0074] The transfer method and bonding method are not specifically limited. Any one of electromagnetic force transfer, van der Waals force transfer, laser transfer or elastic imprint transfer can be used. The bonding method can be any one of eutectic bonding, thermo-press bonding or laser-assisted bonding.

[0075] Please refer to Figure 16 , Figure 16 A cross-sectional schematic diagram of a driving backplate with transferred Micro LEDs as described in an embodiment of this application is shown.

[0076] Please refer to Figure 17 , Figure 17 This is a top view schematic diagram of a driving backplate with transferred Micro LEDs as described in an embodiment of this application.

[0077] In some embodiments, the BM of PLN2 under the LED is hollowed out to avoid poor bonding of Micro LED when the BM thickness is too thick.

[0078] Please refer to Figure 18 , Figure 18 A cross-sectional schematic diagram of the drive backplate with the BM cutout of the PLN2 under the LED described in the embodiment of this application is shown.

[0079] In some embodiments, a thick barrier wall with a thickness of 5-20 μm is fabricated on the PLN2 BM using a photo process to reduce light crosstalk at the bottom of the LED.

[0080] Please refer to Figure 19 , Figure 19 A cross-sectional schematic diagram of the drive back plate for preparing a thick retaining wall according to an embodiment of this application is shown.

[0081] Based on the same inventive concept, this application also provides a driving backplate corresponding to a method for preparing a micro light-emitting diode driving backplate. Since the principle of the driving backplate in this application is similar to the preparation method described above, the implementation of the driving backplate can refer to the implementation of the preparation method, and the repeated parts will not be described again.

[0082] This application provides a miniature LED driving backplane. Please refer to... Figure 16 , Figure 16 A schematic diagram of the structure of the micro LED driving backplane described in an embodiment of this application is shown; as follows: Figure 16 As shown, the micro LED driving backplane includes a driving backplane front body and a light-absorbing planarization layer 1903; The driving backplane front body includes a glass substrate 1901, a driving circuit layer and a passivation layer 1902 covering the driving circuit layer. The driving circuit layer is disposed on the glass substrate 1901 and includes a source-drain layer for connecting micro light-emitting diodes. The source-drain layer includes pads. The light-absorbing planarization layer 1903 is disposed on the passivation layer 1902. The light-absorbing planarization layer 1903 is made of black light-absorbing color resist material. An opening is formed on the light-absorbing planarization layer 1903 to expose the pads. The light-absorbing planarization layer 1903 is prepared on the passivation layer 1902 covering the driving circuit layer, and the opening exposing the pads is formed on the light-absorbing planarization layer 1903 by photolithography.

[0083] Please refer to Figure 19In the aforementioned micro LED driving backplane, a barrier structure 1904 is further provided on the light-absorbing planarization layer 1903. The barrier structure 1904 surrounds the micro LED connected to the pad, and the barrier structure 1904 is made of the black light-absorbing color resist material.

[0084] In some embodiments, in the micro LED driving backplane, the thickness of the barrier structure 1904 is 5 μm to 20 μm; and the thickness of the light-absorbing planarization layer 1903 is 1 μm to 20 μm. In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0085] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. In addition, the terms "first", "second", "third", etc. are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0086] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The protection scope of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application. All should be covered within the protection scope of this application. Therefore, the protection scope of this application should be determined by the protection scope of the claims.

Claims

1. A method for fabricating a micro light-emitting diode driving backplane, characterized in that, The preparation method includes: A driving backplane precursor is formed on a glass substrate; the driving backplane precursor includes a driving circuit layer and a passivation layer covering the driving circuit layer, the driving circuit layer includes a source-drain layer for connecting a micro light-emitting diode, and the source-drain layer for connecting the micro light-emitting diode includes pads. A light-absorbing planarization layer is formed on the passivation layer covering the driving circuit layer; the light-absorbing planarization layer is made of black light-absorbing color resist material. An opening exposing the pads is formed on the light-absorbing planarization layer using photolithography to obtain the finished drive backplane.

2. The method for fabricating a micro LED driving backplane according to claim 1, characterized in that, The thickness of the light-absorbing planarization layer is 1 μm to 20 μm, and the reflectivity of the light-absorbing planarization layer is less than 5%.

3. The method for fabricating a micro LED driving backplane according to claim 2, characterized in that: The thickness of the light-absorbing planarization layer is determined based on the thickness of the last layer of metal traces in the front body of the drive backplate. When the thickness of the last layer of metal traces in the drive backplate front body is less than or equal to 1.8 μm, the thickness of the light-absorbing planarization layer is a first preset thickness value; the first preset thickness value is 2 μm to 3 μm. When the thickness of the last metal trace of the drive backplate front body is greater than 1.8 μm, the thickness of the light-absorbing planarization layer is the sum of the thickness of the last metal trace and the second preset thickness value.

4. The method for fabricating a micro LED driving backplane according to claim 1, characterized in that, After forming an opening exposing the pads on the light-absorbing planarization layer using a photolithography process, the method further includes: A barrier planarization layer is formed on the light-absorbing planarization layer, and the barrier planarization layer is processed by photolithography to form a barrier structure surrounding the micro light-emitting diodes connected to the pads; the barrier planarization layer is made of black light-absorbing color resist material.

5. The method for fabricating a micro LED driving backplane according to claim 4, characterized in that, The height of the retaining wall is 5μm to 20μm; When the micro LED is a flip chip, the barrier is not lower than the micro LED; or the barrier is lower than the micro LED and the height difference is within a preset height difference range.

6. The method for fabricating a micro LED driving backplane according to claim 1, characterized in that, The process of forming an opening exposing the pads on the light-absorbing planarization layer using photolithography includes: Based on the parameters of the micro light-emitting diode, when forming an opening that exposes the pad on the light-absorbing planarization layer by photolithography, at least a portion of the light-absorbing planarization layer in the region directly below the micro light-emitting diode is removed simultaneously.

7. The method for fabricating a micro LED driving backplane according to claim 1, characterized in that, The preparation method further includes: The resulting drive backplane is divided into multiple sub-sub-substrates.

8. A miniature light-emitting diode driving backplane, characterized in that, include: Drive the backplate front and the light-absorbing planarization layer; The driving backplane front body includes a glass substrate, a driving circuit layer and a passivation layer covering the driving circuit layer. The driving circuit layer is disposed on the glass substrate and includes a source-drain layer for connecting micro light-emitting diodes. The source-drain layer includes pads. The light-absorbing planarization layer is disposed on the passivation layer, and the light-absorbing planarization layer is made of black light-absorbing color resist material. The light-absorbing planarization layer has an opening that exposes the pads. The light-absorbing planarization layer is prepared on the passivation layer covering the driving circuit layer, and the opening exposing the pads is formed on the light-absorbing planarization layer by photolithography.

9. The micro LED driving backplane according to claim 8, characterized in that, A barrier structure is also provided on the light-absorbing planarization layer. The barrier structure surrounds the micro light-emitting diodes connected to the pads. The barrier structure is made of the black light-absorbing color resist material.

10. The micro LED driving backplane according to claim 9, characterized in that, The thickness of the retaining wall structure is 5 μm to 20 μm; the thickness of the light-absorbing planarization layer is 1 μm to 20 μm.

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