Display panel, electronic device including the same, and manufacturing method for display panel

Abstract

The present application relates to a display panel, an electronic device including the same, and a manufacturing method for the display panel. The display panel includes a base layer, a light emitting element layer disposed on the base layer and including a light emitting element, and a circuit layer disposed on the base layer and including a thin film transistor electrically connected to the light emitting element. The thin film transistor includes a gate electrode, a channel overlapping the gate electrode and including an oxide semiconductor, a source electrode disposed on a first end of the channel, a drain electrode disposed on a second end of the channel opposite the first end, and an interposed layer disposed between the channel and the source electrode and between the channel and the drain electrode. The interposed layer includes a dipole layer disposed on the channel and an oxygen diffusion prevention layer disposed on the dipole layer.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2025-0037257, filed on March 24, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates herein to display panels, electronic devices including the same, and methods for manufacturing display panels, and more particularly, to display panels including thin-film transistors, electronic devices including display panels, and methods for manufacturing display panels including thin-film transistors. Background Technology

[0004] Various multimedia electronic devices, such as televisions, mobile phones, tablet computers, navigation systems, and game consoles, include an active area that activates in response to electrical signals. These electronic devices can detect externally applied pressure and simultaneously provide information to the user by displaying various images via the active area.

[0005] Electronic devices may include light-emitting elements having organic light-emitting materials or quantum dots and pixel circuitry for controlling electrical signals applied to the light-emitting elements. Pixel circuitry may include thin-film transistors. As the channel length of thin-film transistors continues to decrease with the miniaturization of electronic devices, research is underway to reduce the contact resistance between the channel and the electrodes. Summary of the Invention

[0006] This disclosure provides a display panel including thin-film transistors with reduced contact resistance.

[0007] This disclosure also provides electronic devices including thin-film transistors with reduced contact resistance.

[0008] This disclosure also provides a method for manufacturing a display panel including thin-film transistors with reduced contact resistance.

[0009] According to an embodiment of the present invention, a display panel includes: a substrate layer; a light-emitting element layer disposed on the substrate layer and including a light-emitting element; and a circuit layer disposed on the substrate layer and including a thin-film transistor electrically connected to the light-emitting element. The thin-film transistor includes: a gate electrode; a channel overlapping the gate electrode and including an oxide semiconductor; a source electrode disposed at a first end of the channel; a drain electrode disposed at a second end of the channel opposite to the first end; and an insertion layer disposed between the channel and the source electrode and between the channel and the drain electrode. The insertion layer includes: a dipole layer disposed on the channel; and an oxygen diffusion prevention layer disposed on the dipole layer.

[0010] In one embodiment, the dipole layer may be directly disposed on the channel, and the dipole layer may include metal oxides of the channel in which oxygen vacancies are formed to dope the channel.

[0011] In one embodiment, the oxygen diffusion prevention layer may be directly disposed between the dipole layer and the source electrode and between the dipole layer and the drain electrode, and the oxygen diffusion prevention layer may include a metal oxide that blocks oxygen from diffusing from the channel to the source electrode and the drain electrode.

[0012] In one implementation, the oxygen diffusion prevention layer may have a thickness that allows electron tunneling.

[0013] In an embodiment, the oxygen diffusion prevention layer may have a thickness in the range of less than or equal to about 3 nm.

[0014] In an embodiment, the oxygen diffusion prevention layer may have a thickness in the range of less than or equal to about 1 nm.

[0015] In an embodiment, the oxygen diffusion prevention layer may include at least one compound selected from Al2O3, TiO2, ZnO, MgO and HfO2.

[0016] In an embodiment, the dipole layer may include at least one compound selected from ITO, ZnO, HfZrO and TiO2.

[0017] In an embodiment, the channel may include at least one of ITZO, IGZO, TZO, ATZO, and ZnO.

[0018] In an embodiment, the circuit layer may further include a gate insulating film disposed between the gate electrode and the channel.

[0019] According to an embodiment of the present invention, an electronic device includes: a display module; and a window disposed on the display module. The display module includes: a substrate layer; a light-emitting element layer disposed on the substrate layer and including a light-emitting element; and a circuit layer disposed on the substrate layer and including a thin-film transistor electrically connected to the light-emitting element. The thin-film transistor includes: a gate electrode; a channel overlapping the gate electrode and including an oxide semiconductor; a source electrode disposed at a first end of the channel; a drain electrode disposed at a second end of the channel opposite to the first end; and an insertion layer disposed between the channel and the source electrode and between the channel and the drain electrode. The insertion layer includes: a dipole layer disposed on the channel; and an oxygen diffusion prevention layer disposed on the dipole layer.

[0020] In one embodiment, the dipole layer may include a metal oxide in which oxygen vacancies are formed to dope the channel.

[0021] In one embodiment, the oxygen diffusion prevention layer may include a metal oxide that blocks oxygen from diffusing from the channel to the source and drain electrodes.

[0022] In an implementation, the electronic device may further include at least one of a processor, a memory, and a power module.

[0023] In implementation, the electronic device may be a television, monitor, outdoor billboard, desktop personal computer, laptop computer, personal digital assistant, car dashboard, center console, navigation system, in-vehicle mirror display, game console, mobile phone (or smartphone), tablet computer, smartwatch, smart glasses, head-mounted display, or camera.

[0024] According to an embodiment of the present invention, a method for manufacturing a display panel includes: forming a channel comprising an oxide semiconductor; forming an insertion layer on the channel; and forming a source electrode and a drain electrode on the insertion layer. The insertion layer is disposed between the source electrode and the channel and between the drain electrode and the channel. Forming the insertion layer includes: forming a dipole layer on the channel, and simultaneously forming an oxygen diffusion prevention layer while reducing the dipole layer using a reducing metal precursor.

[0025] In this implementation, the insertion layer can be formed using an atomic layer deposition (ALD) process.

[0026] In one embodiment, the dipole layer may include a metal oxide in which oxygen vacancies are formed to dope the channel.

[0027] In one embodiment, the oxygen diffusion prevention layer may include a metal oxide that blocks oxygen from diffusing from the channel to the source and drain electrodes.

[0028] In one implementation, the oxygen diffusion prevention layer may have a thickness that allows electron tunneling. Attached Figure Description

[0029] The accompanying drawings are included to provide a further understanding of non-limiting embodiments of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the inventive concept and, together with the description, serve to explain the principles of these embodiments. In the drawings:

[0030] Figure 1 A block diagram of an electronic device according to an embodiment of the present invention;

[0031] Figure 2 Schematic diagrams of various electronic devices according to embodiments of the present invention;

[0032] Figure 3 A combined perspective view of an electronic device according to an embodiment of the present invention;

[0033] Figure 4 An exploded perspective view of an electronic device according to an embodiment of the present invention;

[0034] Figure 5 A cross-sectional view illustrating an electronic device according to an embodiment of the concept of the present invention;

[0035] Figure 6 A cross-sectional view illustrating an electronic device according to an embodiment of the concept of the present invention;

[0036] Figure 7 A cross-sectional view illustrating a portion of an electronic device according to an embodiment of the present invention;

[0037] Figure 8 A cross-sectional view illustrating a portion of an electronic device according to an embodiment of the present invention;

[0038] Figure 9 A cross-sectional view illustrating the structure of an oxide semiconductor layer-electrode according to an embodiment of the present invention;

[0039] Figure 10A A cross-sectional view illustrating the structure of the oxide semiconductor layer-electrode according to Example 1, which is an embodiment of the present invention.

[0040] Figure 10B A TEM image of a cross-section of the structure of the oxide semiconductor layer-electrode according to Example 1, which is an embodiment of the present invention.

[0041] Figure 10C The results of measurements on a cross-section of the oxide semiconductor layer-electrode structure according to an embodiment of the present invention are shown.

[0042] Figure 10D The results of measurements on a cross-section of the oxide semiconductor layer-electrode structure according to an embodiment of the present invention are shown.

[0043] Figure 11A A cross-sectional view illustrating the structure of the oxide semiconductor layer-electrode according to Comparative Example 1;

[0044] Figure 11B This is a TEM image of a cross-section of the oxide semiconductor layer-electrode structure according to Comparative Example 1;

[0045] Figure 11C The results of measuring the titanium atom distribution on a cross section of the oxide semiconductor layer-electrode structure according to Comparative Example 1 are shown;

[0046] Figure 11D The results of measuring the oxygen atom distribution on a cross section of the oxide semiconductor layer-electrode structure according to Comparative Example 1 are shown;

[0047] Figure 12A A cross-sectional view illustrating the structure of the oxide semiconductor layer-electrode according to Example 2, which is an embodiment of the present invention.

[0048] Figure 12B The results of measuring the contact resistance between the oxide semiconductor layer and the electrode according to an embodiment of the present invention are shown;

[0049] Figure 13A A cross-sectional view illustrating the structure of the oxide semiconductor layer-electrode according to Comparative Example 2;

[0050] Figure 13B The results of measuring the contact resistance between the oxide semiconductor layer and the electrode according to Comparative Example 2 are shown; and

[0051] Figures 14A to 14E A cross-sectional view illustrating one step of a method for manufacturing a display panel according to an embodiment of the present invention. Detailed Implementation

[0052] In this specification, it will be understood that when an element (or area, layer, or part, etc.) is referred to as being "on," "connected to," or "attached to" another element (or area, layer, or part, etc.), it may be directly disposed on, directly connected to, or directly attached to another element (or area, layer, or part, etc.), or other elements may be disposed in between. When an element is referred to as being "directly on," "directly connected to," or "directly attached to" another element, there may be no intermediary element.

[0053] The same reference numerals or symbols refer to the same elements throughout the drawings. In order to effectively describe the technical content, the scale and dimensions (e.g., thickness) of the elements may be enlarged. As used herein, the term "and / or" includes any and all combinations of one or more of the associated enumerated elements.

[0054] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, the elements are not limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. For example, without departing from the scope of the inventive concept, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion. Similarly, the second element, component, region, layer, or portion may be referred to as the first element, component, region, layer, or portion. In this specification, the singular expressions “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0055] Additionally, terms such as "below," "under," "on the lower side," "above," "on top," or "on the upper side" are used to describe the relationships between the elements illustrated in the accompanying drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0056] It will be further understood that, when used in this specification, the terms “comprises,” “includes,” “has,” and / or “comprising,” “including,” “having” indicate the presence of the described features, quantities, steps, operations, elements, components, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, elements, components, and / or combinations thereof.

[0057] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in commonly used dictionaries, shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an ideal or overly formal sense unless expressly so defined herein.

[0058] Hereinafter, non-limiting embodiments of the present invention will be described with reference to the accompanying drawings.

[0059] This invention relates to a display panel comprising a thin-film transistor having an insertion layer including a dipole layer and an oxygen diffusion prevention layer. The dipole layer may be disposed between an oxide semiconductor layer and an electrode. Oxygen vacancies are formed in the dipole layer and doped into the oxide semiconductor layer. The dipole layer reduces the contact resistance between the oxide semiconductor layer and the electrode.

[0060] An oxygen diffusion prevention layer can be disposed between the oxide semiconductor layer and the electrode to prevent Fermi level pinning of the metal. The oxygen diffusion prevention layer can be formed on the dipole layer using an atomic layer deposition (ALD) process. In the ALD process, oxygen vacancies can be formed in the dipole layer using a reducing precursor material. The reducing precursor material can include a metal precursor, examples of which include an aluminum precursor, and examples of an aluminum precursor include trimethylaluminum (TMA).

[0061] Because the oxygen diffusion prevention layer is formed on the dipole layer, oxygen diffusion can be prevented by doping the dipole layer with oxygen vacancies, which in turn prevents the formation of metal oxide layers and prevents surface defects, thereby reducing contact resistance.

[0062] Figure 1 This is a block diagram of an electronic device ED according to an embodiment of the present invention.

[0063] refer to Figure 1 An electronic device (e.g., an electronic device) ED according to an embodiment of the present invention may include a display module DM, a processor PC, a memory MM, and a power module PM.

[0064] In an implementation, the processor PC may include at least one of a central processing unit (CPU), an application processor, a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0065] The memory MM can store data information required for the operation of the processor PC or the display module DM. When the processor PC runs the application stored in the memory MM, video data signals and / or input control signals can be transmitted to the display module DM, and the display module DM can process the received signals to output video information (e.g., image display information) through the display screen.

[0066] The power module (PM) may include: a power supply module, such as a power adapter or battery device; and a power conversion module, which converts the power supplied by the power supply module to generate the power required for the operation of the electronic device (ED).

[0067] At least one of the components of the previously described electronic device ED may be included in the display device according to the embodiments described later. Additionally, some of the individual modules included in a functional module may be included in the display device, and other modules may be provided separately from the display device. For example, the display device may include a display module DM, and a processor PC, a memory MM, and a power module PM may be provided in the electronic device ED as devices other than the display device.

[0068] Figure 2 This is a schematic diagram of various electronic devices (e.g., electronic apparatuses) according to embodiments of the present invention. In this document, the terms "electronic device" and "electronic apparatus" are used interchangeably.

[0069] refer to Figure 2Various electronic devices employing the display module DM according to embodiments of the present invention may include not only electronic devices for displaying images (such as mobile phones (or smartphones) ED-1a, tablet PCs ED-1b, laptops ED-1c, TVs ED-1d, and desktop monitors ED-1e), but also wearable electronic devices (such as smart glasses ED-2a, head-mounted displays ED-2b, and smartwatches ED-2c) and electronic devices for vehicles ED-3 (such as in-vehicle mirror displays, car dashboards, center consoles, and central information displays (CIDs) mounted on the dashboard). For example, electronic devices may be outdoor billboards, personal computers (such as desktop PCs), personal digital assistants, cameras, etc. However, embodiments of the present invention are not limited to these, and electronic devices employing display devices (e.g., electronic devices) may include various other small, medium, and large display devices.

[0070] Figure 3 This is a combined perspective view of an electronic device ED according to an embodiment of the present invention. Figure 4 An exploded perspective view of an electronic device ED according to an embodiment of the present invention. Figure 5 and Figure 6 Cross-sectional views of electronic devices ED according to embodiments of the present invention are shown for illustrative purposes.

[0071] Figures 3 to 6 The electronic device ED, as illustrated in the embodiments of the present invention, can be activated in response to an electrical signal. For example, in embodiments, the electronic device ED may be a mobile phone, tablet computer, monitor, television, navigation system (e.g., car navigation system), game console, or wearable device, but the embodiments of the present invention are not limited to these. Figure 3 The electronic device ED is explained as a mobile phone.

[0072] According to the embodiments, the electronic device ED can display at least one moving image and / or still image through the effective area AA-ED. For example, in Figure 3 In the embodiments shown, the images are software application icons and clock, temperature, and calendar windows. However, embodiments of the inventive concept are not limited to this, and the images can be of various different themes. The effective area AA-ED may include a flat surface defined in a first direction DR1 and a second direction DR2. In embodiments, the effective area AA-ED may further include a curved surface bent from at least one side of the flat surface defined in the first direction DR1 and the second direction DR2.

[0073] The peripheral area NAA-ED (e.g., in a plan view) is adjacent to the active area AA-ED. For example, in one embodiment, the peripheral area NAA-ED may (e.g., in a plan view) surround the active area AA-ED. Accordingly, the shape of the active area AA-ED may be substantially defined by the peripheral area NAA-ED. However, embodiments of the inventive concept are not necessarily limited to this, and the peripheral area NAA-ED may also be disposed adjacent only to one side of the active area AA-ED, or the peripheral area NAA-ED may be omitted. An electronic device ED according to embodiments of the inventive concept may (e.g., in a plan view) include active areas AA-ED of various shapes, and is not necessarily limited to any one embodiment.

[0074] Figure 3 An electronic device ED according to an embodiment includes two curved surfaces bent from corresponding sides of a flat surface defined by a first direction DR1 and a second direction DR2. However, the shape of the effective area AA-ED is not limited to this. For example, the effective area AA-ED may consist only of the flat surface, and the effective area AA-ED may further include curved surfaces bent from at least two sides of the flat surface, for example, four curved surfaces bent from four sides of the flat surface, respectively.

[0075] exist Figure 3 The first direction DR1 to the fourth direction DR4 are illustrated in the following figures, and the directions indicated by the first direction DR1 to the fourth direction DR4 described in this specification may be relative concepts and may therefore be changed to other directions.

[0076] In this specification, the first direction DR1 and the second direction DR2 may intersect each other, and the third direction DR3 may be the normal direction of the plane defined by the first direction DR1 and the second direction DR2. The fourth direction DR4 may be the normal direction of the plane defined by the first direction DR1 and the second direction DR2, and may be a direction opposite to the third direction DR3.

[0077] The thickness direction of the electronic device ED can be a third direction DR3 parallel to the normal direction of the plane defined by the first direction DR1 and the second direction DR2. In this specification, the front surface (e.g., the upper surface) and the rear surface (e.g., the lower surface) of each of the components constituting the electronic device ED can be defined based on the third direction DR3.

[0078] In this specification, "in a plane" and "in a plan view" can mean observed in a plane defined by a first direction DR1 and a second direction DR2. In this specification, "overlapping" can mean overlapping in a plane, unless otherwise specifically defined.

[0079] An electronic device ED according to an embodiment may include a display module DM. The display module DM may be a component that generates images and detects pressure applied from the outside (e.g., the external environment). The display module DM according to an embodiment includes a display panel DP. The display module DM according to an embodiment may further include a sensor layer TP disposed on the display panel DP and an optical layer RCL disposed on the sensor layer TP. However, embodiments of the present invention are not limited thereto, and the sensor layer TP or the optical layer RCL may be omitted in embodiments.

[0080] The active area AA and the peripheral area NAA can be defined in the display module DM. The active area AA can be an area that is activated in response to an electrical signal. The peripheral area NAA can be (e.g., in a plan view) an area placed adjacent to at least one side of the active area AA.

[0081] The effective region AA can correspond to Figure 3 The effective area AA-ED of the electronic device ED is explained in the text. The peripheral area NAA can correspond to Figure 3 The peripheral area NAA-ED of the electronic device ED is explained in the text.

[0082] refer to Figure 4 The effective area AA may include multiple light-emitting areas PXA-R, PXA-G, and PXA-B. For example, an electronic device ED according to an embodiment may include a first light-emitting area PXA-R, a second light-emitting area PXA-G, and a third light-emitting area PXA-B. In an embodiment, the first light-emitting area PXA-R may be a red light-emitting area emitting red light, the second light-emitting area PXA-G may be a green light-emitting area emitting green light, and the third light-emitting area PXA-B may be a blue light-emitting area emitting blue light. However, the embodiments of the present invention are not limited to this, and the number of light-emitting areas and the color emitted by each of the light-emitting areas may vary.

[0083] In this implementation, the first to third light-emitting regions PXA-R, PXA-G, and PXA-B can be separated from each other and do not overlap on a plane. For example, the non-light-emitting region NPXA can be disposed between adjacent light-emitting regions PXA-R, PXA-G, and PXA-B.

[0084] Figure 4 The example illustrates how the luminescent regions PXA-R, PXA-G, and PXA-B are arranged in a stripe pattern. For instance, in... Figure 4 In the electronic device ED according to the embodiment described herein, the light-emitting areas may be arranged alternately along the second direction DR2 in the order of the first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B.

[0085] The arrangement of the luminescent regions PXA-R, PXA-G, and PXA-B is not limited to [specific configuration]. Figure 4The arrangement described herein, and the order in which the first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B are arranged, can be provided in various combinations, for example, according to the display quality characteristics required by the electronic device ED. For example, in an embodiment, the arrangement of the light-emitting areas PXA-R, PXA-G, and PXA-B can be pentiole. ® Arrangement or Diamond Pixel ® Layout.

[0086] In embodiments, the areas of the multiple light-emitting areas PXA-R, PXA-G, and PXA-B that emit light within different wavelength ranges may be different from each other. The area may refer to the area as viewed from a plane defined by a first direction DR1 and a second direction DR2. However, the embodiments of the present invention are not limited to this, and in some embodiments, the light-emitting areas PXA-R, PXA-G, and PXA-B may have the same area as each other. Furthermore, the area ratio may be adjusted differently depending on the display quality characteristics required by the electronic device ED, and the light-emitting areas PXA-R, PXA-G, and PXA-B may be provided on the plane in different shapes.

[0087] Figure 4 It is explained that each of the light-emitting areas PXA-R, PXA-G, and PXA-B has a quadrilateral shape on the plane, but the embodiments of the present invention are not limited to this, and each of the light-emitting areas PXA-R, PXA-G, and PXA-B may have another polygonal shape or a circular shape on the plane, etc.

[0088] The outer region NAA may (e.g., in a plan view) surround the effective region AA. However, embodiments of the inventive concept are not necessarily limited to this, and are related to... Figure 4 Due to differences in the explanations provided, a portion of the peripheral area NAA can be omitted. The drive circuitry or drive lines used to drive the active area AA can be located within the peripheral area NAA.

[0089] Reference Figure 6 In one embodiment, the peripheral region NAA may include a bend BA that is bendable relative to a bend axis BX extending in one direction. For example, in one embodiment, the bend axis BX may extend in a second direction DR2. A bend portion protective layer BPL may be disposed in the bend BA. The bend portion protective layer BPL may protect circuit layers CL and the like disposed in the peripheral region NAA. The bend portion protective layer BPL may prevent cracking of components, including circuit layers CL and the like exposed from the bend portion BA. In one embodiment, the bend portion protective layer BPL may include at least one material selected from acrylate polymers, silicone polymers, and imide polymers. However, embodiments of the inventive concept are not necessarily limited thereto.

[0090] and Figure 6 As explained in the previous description, the bend protection layer BPL may be connected to or overlap with the edge of the optical layer RCL. Additionally, some components of the optical layer RCL may extend to the bend BA to provide the bend protection layer BPL. Furthermore, the bend protection layer BPL may be omitted in some embodiments.

[0091] In this embodiment, the display panel DP may be a component for generating images. In this embodiment, the display panel DP may be a light-emitting display panel, and for example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, a quantum dot display panel, a micron-LED display panel, or a nano-LED display panel. Hereinafter, for the sake of brevity, the display panel DP according to this embodiment will be described as an organic light-emitting display panel.

[0092] Figure 5 This can be used as an illustrative explanation corresponding to Figure 4 A cross-sectional view of the section along line I-I'. (Reference) Figure 5 and Figure 6 In an embodiment, the display panel DP may include a substrate layer BS, a circuit layer CL, a light-emitting element layer EDL, and a packaging layer TFE.

[0093] The substrate layer BS can be a component providing a substrate surface on which the circuit layer CL is disposed. The substrate layer BS can be a rigid substrate or a flexible substrate that can be bent, folded, or rolled. In embodiments, the substrate layer BS can be a glass substrate, a metal substrate, or a polymer substrate, etc. However, the embodiments of the present invention are not limited to these, and the substrate layer BS can be an inorganic layer, an organic layer, or a composite material layer.

[0094] The circuit layer CL can be disposed on the substrate layer BS (e.g., directly disposed on a third-party DR3). The circuit layer CL may include insulating layers, semiconductor patterns, conductive patterns, and signal lines, etc. In an embodiment, the insulating layer, semiconductor layer, and conductive layer can be formed on the substrate layer BS by coating, deposition, etc., and then the insulating layer, semiconductor layer, and conductive layer can be selectively patterned by multiple cycles of an etching process (e.g., photolithography). Subsequently, semiconductor patterns, conductive patterns, and signal lines included in the circuit layer CL can be formed.

[0095] The light-emitting element layer (EDL) can be disposed on the circuit layer (CL) (e.g., directly disposed on the third-party DR3). The light-emitting element layer (EDL) may include the light-emitting element (EMD) (see...). Figure 7 and Figure 8 For example, light-emitting elements (EMD) (see...) Figure 7 and Figure 8This may include organic light-emitting materials, inorganic light-emitting materials, organic-inorganic light-emitting materials, quantum dots, micron LEDs, or nano LEDs.

[0096] The encapsulation layer TFE may be disposed on the light-emitting element layer EDL (e.g., directly disposed thereon). The encapsulation layer TFE may cover the light-emitting element layer EDL. The encapsulation layer TFE may be disposed in the effective area AA in which the light-emitting element layer EDL is disposed, and may be configured to extend to the peripheral area NAA in which the light-emitting element layer EDL is not disposed.

[0097] In this embodiment, the encapsulation layer TFE protects the light-emitting element layer EDL from moisture, oxygen, and foreign matter (such as dust particles). The encapsulation layer TFE according to an embodiment of the present invention will be described in more detail later.

[0098] A sensor layer TP can be positioned on the display panel DP (e.g., on a third-party DR3). The sensor layer TP can detect external input applied from the outside (e.g., the external environment). External input can be user input. User input can include various types of external input, such as a part of the user's body, light, heat, pen, or pressure. External input can be direct touch or hovering.

[0099] In one embodiment, the sensor layer TP can be formed on the display panel DP through a continuous process. In this embodiment, the sensor layer TP can be directly disposed on the display panel DP. Here, "directly disposed" can mean that no intermediary component is disposed between the sensor layer TP and the display panel DP. For example, it can be disposed between the sensor layer TP and the display panel DP without a separate adhesive member. For example, the sensor layer TP can be (e.g., on a third-party DR3) directly disposed on the encapsulation layer TFE of the display panel DP. In another embodiment, the sensor layer TP can be bonded to the display panel DP via an adhesive member. The adhesive member can include a general-purpose adhesive or glue.

[0100] An optical layer RCL can be disposed on the sensor layer TP. In some embodiments, the optical layer RCL can be directly disposed on the sensor layer TP. For example, the optical layer RCL can be formed on the sensor layer TP through a continuous process. The optical layer RCL can reduce the reflectivity of external light incident from outside the display module DM. The optical layer RCL may include a polarizing layer or a color filter layer. However, embodiments of the present invention are not limited to this, and the optical layer RCL may be omitted in some embodiments.

[0101] According to an embodiment of the present invention, the sensor layer TP can be omitted. In this embodiment, the optical layer RCL can be directly disposed on the display panel DP. In this embodiment, the position of the sensor layer TP can be interchanged with the position of the optical layer RCL.

[0102] The electronic device ED may further include a driver unit DM-M electrically connected to the display module DM. The driver unit DM-M may be electrically connected to the display panel DP and the sensor layer TP. The driver unit DM-M may include a driver chip IC. The driver chip IC can generate or process all kinds of electrical signals, and the driver chip IC may be electrically connected to the display panel DP and the sensor layer TP, and thus control the display panel DP and the sensor layer TP.

[0103] The driving unit DM-M may further include a flexible circuit board FB and a driving circuit board MB. The flexible circuit board FB may be electrically connected to the display panel DP and the sensor layer TP on one side, and electrically connected to the driving circuit board MB on the other side. The driving chip IC may be disposed on the flexible circuit board FB. In this embodiment, the flexible circuit board FB may also be referred to as a chip-on-film (CoF). Alternatively, unlike what is illustrated in the figures, the driving chip IC may also be disposed on the substrate layer BS of the display module DM.

[0104] Figure 4 The driver unit DM-M is connected to one side of the display module DM and is not folded, but as... Figure 6 As explained in the text, in the electronic device ED according to the embodiment, the drive unit DM-M can be configured by bending BD in the fourth direction DR4. (See reference...) Figure 6 The drive unit DM-M can be bent to overlap with the display panel DP on a flat surface.

[0105] The electronic device ED according to an embodiment may further include a window WM disposed on a display module DM. The window WM may cover the entire outer side of the display module DM. The window WM may be attached to the display module DM via an adhesive layer AP.

[0106] The window WM may have a shape corresponding to the shape of the display module DM. In the electronic device ED according to the embodiment, the window WM may include an optically transparent insulating material. The window WM may be a glass substrate or a polymer substrate. For example, the window WM may be a chemically strengthened glass substrate.

[0107] The window WM can be divided into a transmissive portion TA and a bezel portion BZA. The transmissive portion TA may be the portion corresponding to the effective area AA of the display module DM, and the bezel portion BZA may be the portion corresponding to the peripheral area NAA of the display module DM. The bezel portion BZA may define the shape of the transmissive portion TA. The bezel portion BZA may be adjacent to the transmissive portion TA and may (e.g., in a plan view) surround the transmissive portion TA. However, embodiments of the inventive concept are not limited to those illustrated in the drawings, and the bezel portion BZA may also be provided adjacent to only one side of the transmissive portion TA, and a portion of the bezel portion BZA may be omitted.

[0108] Figure 7 and Figure 8Cross-sectional views illustrating a portion of an electronic device ED according to an embodiment of the present invention.

[0109] Figure 7 For corresponding Figure 4 A cross-sectional view of section II-II'. Figure 7 The multiple light-emitting regions PXA-R, PXA-G, and PXA-B, and the non-light-emitting region NPXA, according to the embodiments, are explained. Figure 8 Explanation Figure 7 This is part of the electronic devices ED explained in the text. Figure 8 The first light-emitting region PXA-R and the non-light-emitting region NPXA are explained according to the implementation method.

[0110] refer to Figure 7 and Figure 8 The electronic device ED according to the embodiment may include a display panel DP, a sensor layer TP disposed on the display panel DP (e.g., directly disposed on a third-party DR3 thereon), and an optical layer RCL disposed on the sensor layer TP (e.g., directly disposed on a third-party DR3 thereon).

[0111] In an implementation, the display panel DP may include (for example, on a third-party DR3) a substrate layer BS, a circuit layer CL, a light-emitting element layer EDL, and a packaging layer TFE stacked in sequence.

[0112] The substrate BS can be a glass substrate, a metal substrate, or a polymer substrate, etc. However, the embodiments of the present invention are not limited to these, and the substrate BS can be an inorganic layer, an organic layer, or a composite material layer.

[0113] The base layer BS can have a single-layer or multi-layer structure. For example, in embodiments where the base layer BS has a multi-layer structure, the base layer BS can also have a three-layer structure consisting of a synthetic resin layer, an adhesive layer, and a synthetic resin layer. In particular, the synthetic resin layer may include a polyimide resin. Additionally, the synthetic resin layer may include at least one material selected from acrylate resins, methacrylate resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyamide resins, and perylene resins. In this specification, "~~ type" resin refers to a functional group including "~~".

[0114] A circuit layer CL is disposed on a substrate layer BS (e.g., directly disposed on a third-direction DR3). The circuit layer CL may include a buffer layer BFL. In an embodiment, the buffer layer BFL may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. For example, in the buffer layer BFL, two or more layers selected from silicon oxide layers, silicon nitride layers, and silicon oxynitride layers may be alternately stacked (e.g., on a third-direction DR3).

[0115] The gate electrode G1 may be disposed on the buffer layer BFL (e.g., directly disposed thereon on the third-direction DR3). The gate electrode G1 may be part of a metal pattern. The gate electrode G1 may (e.g., on the third-direction DR3) overlap with the active portion A1, which will be described later. In embodiments, the gate electrode G1 may include titanium (Ti), silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), etc., but is not necessarily limited to these.

[0116] The first insulating layer 10 may be disposed on the buffer layer BFL (e.g., directly disposed on the third-direction DR3). The first insulating layer 10 may overlap with multiple pixels and may cover the gate electrode G1. The first insulating layer 10 may be referred to as a gate insulating film. The first insulating layer 10 may be disposed between the gate electrode G1 and the active portion A1. The first insulating layer 10 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multilayer structure. In an embodiment, the first insulating layer 10 may include at least one compound selected from alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 may be a single-layer silicon oxide layer. Not only can the first insulating layer 10 be an inorganic layer and / or an organic layer and have a single-layer structure or a multilayer structure, but the other insulating layers of the circuit layer CL, which will be described later, are also like this. Inorganic layers may include at least one of the above-described materials, but are not limited thereto. In an embodiment, the circuit layer CL may include a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, a fifth insulating layer 50, and a sixth insulating layer 60.

[0117] The active portion A1 may be disposed on the first insulating layer 10 (e.g., directly disposed thereon on the third-party DR3). The active portion A1 may be referred to as channel A1. The active portion A1 may include a metal oxide. The active portion A1 may include a semiconductor oxide. For example, in an embodiment, the active portion A1 may include at least one compound selected from indium tin zinc oxide (ITZO), indium gallium zinc oxide (IGZO), tin zinc oxide (TZO), aluminum tin zinc oxide (ATZO), and zinc oxide (ZnO).

[0118] Source electrode S1 and drain electrode D1 may be disposed on the active portion A1. In an embodiment, source electrode S1 may be disposed at one end of the active portion A1 (e.g., on the first side in a plan view). Drain electrode D1 may be disposed at the other end of the active portion A1 (e.g., on the second side opposite to the first side in a plan view). Source electrode S1 and drain electrode D1 may extend from the active portion A1 in opposite directions in cross-section. The active portion A1 may be referred to as channel A1.

[0119] The transistor TR according to an embodiment of the present invention further includes an insertion layer ITL. The insertion layer ITL may be disposed between channel A1 and source electrode S1, and between channel A1 and drain electrode D1. Because the insertion layer ITL is disposed between channel A1 and source electrode S1, channel A1 and source electrode S1 can be separated and do not directly contact each other. Because the insertion layer ITL is disposed between channel A1 and drain electrode D1, channel A1 and drain electrode D1 can be separated and do not directly contact each other.

[0120] In an embodiment, the insertion layer ITL includes a dipole layer ITL1 and an oxygen diffusion prevention layer ITL2. The dipole layer ITL1 may be disposed on the channel A1 (e.g., directly disposed thereon). The dipole layer ITL1 may be directly disposed on the channel A1 to cover the channel A1. The oxygen diffusion prevention layer ITL2 may be disposed on the dipole layer ITL1 (e.g., directly disposed thereon). The oxygen diffusion prevention layer ITL2 may be directly disposed on the dipole layer ITL1 to cover the dipole layer ITL1. For example, the oxygen diffusion prevention layer ITL2 may be directly disposed between the dipole layer ITL1 and the source electrode S1, and directly disposed between the dipole layer ITL1 and the drain electrode D1. Reference will be made later. Figure 9 Describe the Insertion Layer (ITL) in detail.

[0121] In one embodiment, each pixel may have an equivalent circuit comprising multiple transistors, a capacitor, and a light-emitting element. However, the embodiments of the present invention are not limited to this, and the equivalent circuit of a pixel can vary in various forms. Figure 8 The illustration includes a transistor TR and a light-emitting element EMD in the pixel. In an implementation, the transistor TR may be a thin-film transistor.

[0122] The second insulating layer 20 may be disposed on the first insulating layer 10 and may cover the source electrode S1 and the drain electrode D1. In an embodiment, the second insulating layer 20 may be an inorganic layer and / or an organic layer, and may have a single-layer structure or a multilayer structure including at least one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer.

[0123] The third insulating layer 30 may be disposed on the second insulating layer 20 (e.g., directly disposed on the third directional DR3), and may have a single-layer structure or a multilayer structure including at least one of a silicon oxide layer, a silicon nitride layer and a silicon oxynitride layer.

[0124] The first connection electrode CNE1 may be disposed on the third insulating layer 30 (e.g., directly disposed on the third directional DR3). In an embodiment, the first connection electrode CNE1 may be connected to the connection signal line SCL through a contact hole CNT-1 passing through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30.

[0125] The fourth insulating layer 40 may be disposed on the third insulating layer 30 (e.g., directly disposed on the third directional DR3). In embodiments, the fourth insulating layer 40 may have a single-layer structure or a multilayer structure including at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0126] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 (e.g., directly disposed on the third-party DR3). The fifth insulating layer 50 may be an organic layer.

[0127] The second connecting electrode CNE2 may be disposed on the fifth insulating layer 50 (e.g., directly disposed on the third-direction DR3). In an embodiment, the second connecting electrode CNE2 may be connected to the first connecting electrode CNE1 through a contact hole CNT-2 passing through the fourth insulating layer 40 and the fifth insulating layer 50.

[0128] The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 and cover the second connecting electrode CNE2. The sixth insulating layer 60 may be an organic layer.

[0129] The light-emitting element layer EDL, including the light-emitting element EMD, can be disposed on the circuit layer CL (e.g., directly disposed on the third-party DR3). The light-emitting element layer EDL may include a pixel-defining film PDL and a light-emitting element EMD, the light-emitting element EMD including a functional layer EL disposed in an opening OP defined in the pixel-defining film PDL.

[0130] In an embodiment, the light-emitting element EMD may include a first electrode AE, a functional layer EL, and a second electrode CE. The functional layer EL may include a light-emitting layer EML (not shown). Additionally, the functional layer EL may further include a hole transport region and an electron transport region. The first electrode AE ​​may be disposed on a sixth insulating layer 60 (e.g., directly disposed on a third-direction DR3). In an embodiment, the first electrode AE ​​may be connected to a second connecting electrode CNE2 via a contact hole CNT-3 passing through the sixth insulating layer 60. In an embodiment, the first electrode AE ​​may include at least one selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Sn, and Zn, a compound selected from two or more of these, a mixture selected from two or more of these, or an oxide thereof.

[0131] The first electrode AE ​​can be a transmission electrode, a transmission-reflection electrode, or a reflection electrode. In embodiments where the first electrode AE ​​is a transmission electrode, the first electrode AE ​​can include a transparent metal oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc.

[0132] In embodiments where the first electrode AE ​​is a transmissive or reflective electrode, the first electrode AE ​​may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca (e.g., a stacked structure of LiF and Ca), LiF / Al (e.g., a stacked structure of LiF and Al), Mo, Ti, W, or compounds thereof or mixtures thereof (e.g., mixtures of Ag and Mg). Optionally, the first electrode AE ​​may have a multilayer structure including a reflective or transmissive film comprising the materials mentioned above, and a transparent conductive film comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. For example, the first electrode AE ​​may have a three-layer structure of ITO / Ag / ITO, but is not limited thereto.

[0133] The pixel-defining film PDL can be disposed on the sixth insulating layer 60 (e.g., directly disposed on the third-party DR3) and can cover a portion of the first electrode AE.

[0134] The pixel defining film (PDL) may have an opening (OP) defined therein. The opening (OP) of the pixel defining film (PDL) may expose at least a portion of the first electrode (AE). For example, in one embodiment, the pixel defining film (PDL) may cover the edge of the first electrode (AE) and expose the central portion of the first electrode (AE).

[0135] In an implementation, the light-emitting region PXA-R is defined as a portion corresponding to the first electrode AE ​​exposed by the opening OP. The non-light-emitting region NPXA may (e.g., in a plan view) surround the light-emitting region PXA-R. For example, a pixel-defining film PDL may define the light-emitting regions PXA-R, PXA-G, and PXA-B. The light-emitting regions PXA-R, PXA-G, and PXA-B, as well as the non-light-emitting region NPXA, may be distinguished by the pixel-defining film PDL.

[0136] In an implementation, the pixel-defining film (PDL) may also include multiple sub-pixel-defining films stacked in the thickness direction.

[0137] In embodiments, the pixel-defining film (PDL) may include a polymer resin. For example, the pixel-defining film PDL may include a polyacrylate resin or a polyimide resin. In addition to the polymer resin, the pixel-defining film PDL may further include inorganic materials. The pixel-defining film PDL may include a light-absorbing material, or include a black pigment and / or a black dye. A pixel-defining film PDL including a black pigment and / or a black dye can provide a black pixel-defining film. In embodiments, carbon black may be used as a black pigment or a black dye, but the embodiments of the present invention are not necessarily limited thereto.

[0138] In addition, the pixel-defining film (PDL) may include inorganic materials. For example, the pixel-defining film (PDL) may include silicon nitride, silicon oxide, or silicon oxynitride.

[0139] The functional layer EL can be (e.g., on the third-party DR3) disposed on the first electrode AE. Figure 7 and Figure 8 The invention illustrates that the functional layer EL is provided by patterning within the opening OP, but embodiments of the invention are not limited thereto. In some embodiments, the functional layer EL may be provided to overlap with a plurality of light-emitting regions PXA-R, PXA-G, and PXA-B and a non-light-emitting region NPXA.

[0140] In one embodiment, an emissive layer EML (not shown) included in the functional layer EL may be separately provided to each of the emissive regions PXA-R, PXA-G, and PXA-B. Multiple separate emissive layers EML (not shown) may be provided to the emissive regions PXA-R, PXA-G, and PXA-B separated by a pixel-defined film PDL. In one embodiment, the multiple emissive layers EML (not shown) may each emit light of at least one color selected from red, green, and blue. However, embodiments of the inventive concept are not limited thereto, and the emissive layer EML (not shown) may also extend to the multiple emissive regions PXA-R, PXA-G, and PXA-B, as well as the non-emissive region NPXA, and be provided as a common layer. In this embodiment, the emissive layer EML (not shown) may provide blue light or white light. The emissive layer EML (not shown) may include an organic light-emitting material or may include quantum dots.

[0141] In one embodiment, the hole transport region and the electron transport region may be jointly disposed in the light-emitting regions PXA-R, PXA-G, and PXA-B, as well as the non-light-emitting region NPXA. However, the embodiments of the present invention are not limited thereto, and the hole transport region and the electron transport region may be patterned and provided corresponding to the light-emitting regions PXA-R, PXA-G, and PXA-B.

[0142] A hole transport region may be disposed (e.g., on a third-direction DR3) between the first electrode AE ​​and the light-emitting layer EML (not shown). In an embodiment, the hole transport region may include a hole transport layer and may further include a hole injection layer. An electron transport region may be disposed (e.g., on a third-direction DR3) between the light-emitting layer EML (not shown) and the second electrode CE. In an embodiment, the electron transport region may include an electron transport layer and may further include an electron injection layer.

[0143] In this embodiment, the emissive layer EML (not shown) may include a fluorescent or phosphorescent material that emits red, green, or blue light. Alternatively, the emissive layer EML (not shown) may include a metal-organic composite as the emissive material. The emissive layer EML (not shown) may also include quantum dots as the emissive material.

[0144] The second electrode CE may be disposed on the functional layer EL (e.g., on the third-direction DR3). The second electrode CE may have a monolithic shape and extend to the light-emitting regions PXA-R, PXA-G, and PXA-B and the non-light-emitting region NPXA, and be configured as a common layer. In embodiments, the second electrode CE may include at least one selected from Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Sn, Na, and Zn, a compound selected from two or more of these, a mixture selected from two or more of these, or an oxide thereof.

[0145] The second electrode CE can be a transmission electrode, a transmission-reflection electrode, or a reflection electrode. In embodiments where the second electrode CE is a transmission electrode, the second electrode CE may include a transparent metal oxide, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc.

[0146] In embodiments where the second electrode CE is a transmissive or reflective electrode, the second electrode CE may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, Yb, W, Na, or compounds or mixtures thereof (e.g., AgMg, AgYb, MgYb, AgLi, or AgNa), or have a multilayer structure such as LiF / Ca (a stacked structure of LiF and Ca) or LiF / Al (a stacked structure of LiF and Al). Optionally, the second electrode CE may have a multilayer structure including a reflective or transmissive film comprising the materials mentioned above, and a transparent conductive film comprising indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), etc. For example, the second electrode CE may include the above-mentioned metallic materials, a combination of two or more metallic materials selected from the above-mentioned metallic materials, or oxides of the above-mentioned metallic materials, etc.

[0147] In an embodiment, the light-emitting element layer (EDL) may further include a capping layer (CPL) disposed on the light-emitting element (EMD). The capping layer (CPL) may be disposed on the second electrode (CE) (e.g., directly disposed on the third-direction electrode (DR3)). The capping layer (CPL) may include a single-layer structure or a multi-layer structure.

[0148] In embodiments, the capping layer CPL can be an inorganic layer or an organic layer. For example, in embodiments where the capping layer CPL comprises an inorganic material, the inorganic material may include SiON or SiN. x SiO y Alkali metal compounds (such as LiF) and alkaline earth metal compounds (such as MgF2). For example, in embodiments where the capping layer CPL includes an organic material, the organic material may contain N,N'-bis(naphthyl-1-yl)-N,N'-bis(phenyl)-2,2'-dimethylbenzidine (α-NPD), N,N'-bis(naphthyl-1-yl)-N,N'-diphenyl-benzidine (NPB), N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine (TPD), 4 ,4',4"-[tris(3-methylphenyl)phenylamino]triphenylamine (m-MTDATA), tris(8-hydroxyquinoline)aluminum (Alq3), copper phthalocyanine (CuPc), N4,N4,N4',N4'-tetra(biphenyl-4-yl)biphenyl-4,4'-diamine (TPD15), 4,4',4"-tris(carbazole-9-yl)triphenylamine (TCTA), etc., or may contain epoxy resin or acrylate (such as methacrylate).

[0149] The capping layer CPL can be used as a buffer layer to protect the light-emitting element (EMD) and the like disposed beneath the capping layer CPL. In an embodiment, the capping layer CPL may have a refractive index greater than or equal to about 1.6. For example, the refractive index of the capping layer CPL may be about 1.9. Because the capping layer CPL has a refractive index of about 1.9, the light-emitting element layer EDL may have increased light extraction efficiency, etc.

[0150] The upper surface of the light-emitting element layer (EDL) can be determined by the shape of the pixel-defining film (PDL) and the light-emitting element layer (EDL). For example, the upper surface of the light-emitting element layer (EDL) can be non-uniform and may have steps. The height of the upper surface of the light-emitting element layer (EDL) based on the substrate layer (BS) can vary in the light-emitting regions PXA-R, PXA-G, and PXA-B, and the non-light-emitting region NPXA. The steps formed due to the non-uniform upper surface of the light-emitting element layer (EDL) can be planarized by the encapsulation layer (TFE).

[0151] The encapsulation layer TFE can be disposed on the light-emitting element layer EDL (e.g., directly disposed on the third-party DR3). In an embodiment, the encapsulation layer TFE includes a first inorganic layer INL1 disposed on the light-emitting element layer EDL, an organic layer OL disposed on the first inorganic layer INL1, and a second inorganic layer INL2 disposed on the organic layer OL.

[0152] The encapsulation layer TFE protects the light-emitting element layer EDL from moisture, oxygen, and other contaminants by including a first inorganic layer INL1 and a second inorganic layer INL2. The encapsulation layer TFE may include an organic layer OL to cover steps or curved surfaces of the light-emitting element layer EDL. Additionally, the encapsulation layer TFE may include an organic layer OL to protect the light-emitting element layer EDL from foreign matter (such as dust particles).

[0153] In embodiments, the first inorganic layer INL1 and the second inorganic layer INL2 may comprise at least one compound selected from silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, and aluminum oxide. However, the materials of the first inorganic layer INL1 and the second inorganic layer INL2 are not limited to the examples above.

[0154] Organic layers (OLs) can include acrylate compounds, epoxy compounds, etc. However, the materials used for organic layers (OLs) are not limited to the examples above.

[0155] The sensor layer TP can be disposed on the display panel DP (e.g., directly disposed on the third-direction DR3). In an embodiment, the sensor layer TP can be (e.g., on the third-direction DR3) directly disposed on the second inorganic layer INL2. The sensor layer TP can be referred to as a sensor, an input sensing layer, or an input sensing panel. The sensor layer TP may include a sensing substrate layer BS-TP, a first conductive layer ML1, a sensing insulating layer IPV, and a second conductive layer ML2.

[0156] The sensing substrate layer BS-TP can be directly disposed on the display panel DP (e.g., on the third-direction DR3). In an embodiment, the sensing substrate layer BS-TP can be an inorganic layer comprising at least one compound selected from silicon nitride, silicon oxynitride, and silicon oxide. Optionally, the sensing substrate layer BS-TP can also be an organic layer comprising epoxy resin, acrylate resin, or imide resin. The sensing substrate layer BS-TP can have a monolayer structure or a multilayer structure in which multiple layers are stacked along the third-direction DR3.

[0157] The first conductive layer ML1 and the second conductive layer ML2 may each have a single-layer structure, or they may have a multilayer structure in which multiple layers are stacked along a third direction DR3. The single-layer conductive layer may include a metal layer or a transparent conductive layer. In embodiments, the metal layer may include Mo, Ag, Ti, Cu, Al, or alloys thereof. The transparent conductive layer may include transparent conductive oxides, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), zinc peroxide (ZnO2), and indium zinc tin oxide (IZTO). The transparent conductive layer may also include conductive polymers (such as PEDOT), metal nanowires, graphene, etc.

[0158] The multilayer conductive layer may include a metal layer. In an embodiment, the metal layer may have a three-layer structure, such as Ti / Al / Ti. The multilayer conductive layer may include at least one metal layer and at least one transparent conductive layer.

[0159] The sensing insulating layer IPV may be disposed (e.g., on a third-direction DR3) between the first conductive layer ML1 and the second conductive layer ML2. The sensing insulating layer IPV may include an inorganic film. In an embodiment, the inorganic film may include at least one compound selected from alumina, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0160] The sensing insulating layer IPV may include an organic film. In an embodiment, the organic film may include at least one material selected from acrylate resins, methacrylate resins, polyisoprene resins, vinyl resins, epoxy resins, urethane resins, cellulose resins, siloxane resins, polyimide resins, polyamide resins, and perylene resins.

[0161] The optical layer RCL can be disposed on the sensor layer TP (e.g., directly disposed on the third-party DR3). For example, the optical layer RCL can be formed on the sensor layer TP through a continuous process. However, the embodiments of the present invention are not limited to this.

[0162] The optical layer RCL can also be formed by including pigments and / or dyes. In an embodiment, the optical layer RCL may include multiple filter components that transmit light of different wavelength ranges. The multiple filter components that transmit light of different wavelength ranges may be respectively arranged corresponding to the light-emitting regions PXA-R, PXA-G, and PXA-B separated by the non-light-emitting region NPXA.

[0163] The optical layer RCL may further include a release layer BM. The material constituting the release layer BM is not particularly limited, as long as it absorbs light. The release layer BM may be a black layer, and according to embodiments, the release layer BM may include a black colorant. The black colorant may include black dyes and / or black pigments. The black colorant may include carbon black, metals (such as chromium), or oxides thereof.

[0164] The separation layer BM can cover the second conductive layer ML2 of the sensor layer TP. The separation layer BM can prevent external light from being reflected on the second conductive layer ML2.

[0165] However, the embodiments of the present invention are not limited to this, and at least one of the sensor layer TP and the optical layer RCL may be omitted.

[0166] Figure 9 A cross-sectional view illustrating the structure of an oxide semiconductor layer-electrode (SLM) according to an embodiment of the present invention. For ease of description, Figure 9 illustrative explanation Figure 8 Some components of the transistor TR. Figure 9 The components of the oxide semiconductor layer-electrode (SLM) structure can be used with... Figure 8 The transistors TR in the transistors are stacked in the same order as the corresponding components. In particular, Figure 9 The oxide semiconductor layer OSC corresponds to Figure 8 Channel A1, and Figure 9 The electrode ME corresponds to Figure 8 The source electrode S1 or the drain electrode D1. Figure 9 The insertion layer ITL and Figure 8 The insertion layer ITL is the same. (Previous reference) Figure 8 The same description of channel A1 can be applied to the oxide semiconductor layer OSC, and previous references Figure 8 The same description of the source electrode S1 and drain electrode D1 can be applied to the electrode ME. Additionally, in embodiments, the oxide semiconductor layer OSC may include an oxide semiconductor and may include at least one compound selected from, for example, ITZO, IGZO, TZO, ATZO, and ZnO.

[0167] refer to Figure 9 An intercalation layer (ITL) is disposed between the oxide semiconductor layer (OSC) and the electrode (ME). The intercalation layer (ITL) may include a dipole layer (ITL1) and an oxygen diffusion prevention layer (ITL2). Because the intercalation layer (ITL) includes both the dipole layer (ITL1) and the oxygen diffusion prevention layer (ITL2), the contact resistance between the oxide semiconductor layer (OSC) and the electrode (ME) can be reduced compared to a comparative embodiment that does not include such an intercalation layer (ITL) between the oxide semiconductor layer (OSC) and the electrode (ME).

[0168] The dipole layer ITL1 can be disposed on the oxide semiconductor layer OSC. In an embodiment, the dipole layer ITL1 can be directly disposed on the oxide semiconductor layer OSC. Because the dipole layer ITL1 is disposed between the oxide semiconductor layer OSC and the electrode ME, the contact resistance between the oxide semiconductor layer OSC and the electrode ME can be reduced.

[0169] In one embodiment, the dipole layer ITL1 can be doped by forming oxygen vacancies in the dipole layer ITL1, thus increasing electron mobility and doping the oxide semiconductor layer OSC. Unlike the embodiments of the present invention, when oxygen vacancies are formed in the dipole layer ITL1 through thermal annealing or plasma treatment for forming the dipole layer ITL1, a thick metal oxide layer can be formed between the dipole layer ITL1 and the electrode ME by the diffusion of oxygen from the oxide semiconductor layer OSC, significantly increasing contact resistance. Alternatively, defects on the surface of the dipole layer ITL1 caused by plasma can hinder electron transfer, thereby increasing contact resistance. However, according to embodiments of the present invention, the formation of a metal oxide layer and surface defects can be prevented by forming an oxygen diffusion prevention layer ITL2, which will be described later, on the dipole layer ITL1.

[0170] The dipole layer ITL1 may comprise a metal oxide. The dipole layer ITL1 may comprise a metal oxide that forms oxygen vacancies to dope the oxide semiconductor layer OSC. For example, in one embodiment, the dipole layer ITL1 may comprise at least one compound selected from ITO, ZnO, HfZrO, and TiO2. Additionally, the dipole layer ITL1 may have a thickness t1 in the range of about 1 nm to about 10 nm, but is not necessarily limited thereto.

[0171] An oxygen diffusion prevention layer ITL2 may be disposed on the dipole layer ITL1 (e.g., directly disposed thereon). During the formation of the oxygen diffusion prevention layer ITL2 on the dipole layer ITL1, oxygen diffusion is prevented by doping oxygen vacancies in the dipole layer ITL1, thereby preventing the formation of a metal oxide layer and preventing surface defects, thus reducing contact resistance.

[0172] In one embodiment, the oxygen diffusion prevention layer ITL2 can be formed on the dipole layer ITL1 (e.g., directly on it) using an atomic layer deposition (ALD) process. In the ALD process, the dipole layer ITL1 can be reduced using a reducing precursor material, and oxygen vacancies can be formed in the dipole layer ITL1.

[0173] Furthermore, an oxygen diffusion prevention layer ITL2 can be disposed between the oxide semiconductor layer OSC and the electrode ME to prevent Fermi level pinning of the metal. Unlike the embodiments of the present invention, in a comparative embodiment where the oxygen diffusion prevention layer ITL2 is not disposed between the oxide semiconductor layer OSC and the electrode ME, allowing direct contact between the oxide semiconductor layer OSC and the electrode ME, the electron wavefunction of the metal included in the electrode ME can be fixed in the band gap of the semiconductor included in the oxide semiconductor layer OSC, thereby forming a metal-induced gap state (MIGS). When a metal-induced gap state is formed, Fermi level pinning can occur, where the Fermi level of the metal is fixed at the charge neutral level (CNL) of the semiconductor. If Fermi level pinning occurs, the contact resistance between the oxide semiconductor layer OSC and the electrode ME can increase. Therefore, according to the embodiments of the present invention, by providing an oxygen diffusion prevention layer ITL2 between the oxide semiconductor layer OSC and the electrode ME, the electron wavefunction of the metal being fixed in the metal-induced gap state of the semiconductor band gap can be prevented, and Fermi level pinning can be prevented. The oxygen diffusion prevention layer ITL2 may include a material with a high band gap capable of preventing Fermi level pinning in metals.

[0174] The oxygen diffusion prevention layer ITL2 may include a metal oxide. The oxygen diffusion prevention layer ITL2 may include a metal oxide that blocks oxygen from diffusing from the oxide semiconductor layer OSC to the electrode ME. In an embodiment, the oxygen diffusion prevention layer ITL2 may include at least one compound selected from Al2O3, TiO2, ZnO, MgO, and HfO2. Additionally, the oxygen diffusion prevention layer ITL2 may have a thickness t2 that allows electron tunneling (e.g., the length on a third-direction DR3). If the thickness t2 is greater, the oxygen diffusion prevention layer ITL2 may serve as an insulating layer. For example, in an embodiment, the thickness t2 of the oxygen diffusion prevention layer ITL2 may be less than or equal to about 3 nm. In an embodiment, the thickness t2 of the oxygen diffusion prevention layer ITL2 may be less than or equal to about 1 nm.

[0175] Figure 10A A cross-sectional view illustrating the structure of the oxide semiconductor layer-electrode SLM-1 according to Example 1, which is an embodiment of the present invention. Figure 10B Transmission electron microscope (TEM) image of a cross section of the structure of the oxide semiconductor layer-electrode SLM-1 according to Example 1, which is an embodiment of the present invention. Figure 10C The results show the distribution of titanium atoms on a cross section of the structure of the oxide semiconductor layer-electrode SLM-1 according to an embodiment of the present invention. Figure 10D The results show the results of measuring the oxygen atom distribution on a cross section of the structure of the oxide semiconductor layer-electrode SLM-1 according to an embodiment of the present invention.

[0176] refer to Figure 10A The structure of the oxide semiconductor layer-electrode SLM-1 according to Example 1 has an oxygen diffusion prevention layer ITL2 included between the oxide semiconductor layer OSC and the electrode ME (e.g., directly therebetween).

[0177] refer to Figure 10B According to the oxide semiconductor layer-electrode SLM-1 of Example 1 (see Figure 10A The structure can have an IGZO / Al2O3 / Ti stacked structure as an example. In particular, it is illustrated that in this structure, Figure 10A The oxide semiconductor layer OSC comprises IGZO, the electrode ME comprises Ti, and the oxygen diffusion prevention layer ITL2 comprises Al2O3. The bright area between the IGZO layer and the Ti layer shown in the figures corresponds to the region where Al2O3 is disposed. Figure 10B In the accompanying diagrams below, the white bars represent the scale.

[0178] refer to Figure 10C As can be seen, in the oxide semiconductor layer-electrode SLM-1 according to Example 1 (see Figure 10A In the structure of ), titanium atoms (Ti) are distributed in the electrode ME (see Figure 10A (in the area)

[0179] refer to Figure 10D As can be seen, in the oxide semiconductor layer-electrode SLM-1 according to Example 1 (see Figure 10A In the structure of ), oxygen atoms (O) are only distributed in the oxide semiconductor layer OSC (see Figure 10A ) zone and oxygen diffusion prevention layer ITL2 (see Figure 10A In the region. For example, it can be seen that because it includes the oxygen diffusion prevention layer ITL2 (see Figure 10A Therefore, it prevents oxygen atoms included in the oxide semiconductor layer OSC from diffusing into the electrode ME region.

[0180] Figure 11A A cross-sectional view illustrating the structure of the oxide semiconductor layer-electrode SLM-r1 according to Comparative Example 1. Figure 11B This is a TEM image of a cross-section of the structure of the oxide semiconductor layer-electrode SLM-r1 according to Comparative Example 1. Figure 11C The results of measuring the titanium atom distribution on a cross section of the structure of the oxide semiconductor layer-electrode SLM-r1 according to Comparative Example 1 are shown. Figure 11D The results of measuring the oxygen atom distribution on a cross section of the structure of the oxide semiconductor layer-electrode SLM-r1 according to Comparative Example 1 are shown.

[0181] refer to Figure 11AUnlike the structure of the oxide semiconductor layer-electrode SLM-1 according to Example 1, the structure of the oxide semiconductor layer-electrode SLM-r1 according to Comparative Example 1 does not include an oxygen diffusion prevention layer ITL2 between the oxide semiconductor layer OSC and the electrode ME (see Comparative Example 1). Figure 10A The structure of ).

[0182] refer to Figure 11B According to the oxide semiconductor layer-electrode SLM-r1 of Comparative Example 1 (see Figure 11A The structure can have an IGZO / Ti stack structure as an example. Specifically, it is illustrated that in this structure, Figure 11A The oxide semiconductor layer OSC includes IGZO, and the electrode ME includes Ti.

[0183] refer to Figure 11C As can be seen, in the oxide semiconductor layer-electrode SLM-r1 according to Comparative Example 1 (see... Figure 11A In the structure of ), titanium atoms (Ti) are distributed in the electrode ME (see Figure 11A (in the area)

[0184] refer to Figure 11D As can be seen, in the oxide semiconductor layer-electrode SLM-r1 according to Comparative Example 1 (see... Figure 11A In the structure of ), oxygen atoms (O) are distributed not only in the oxide semiconductor layer OSC (see Figure 11A It is also distributed in the electrode ME region (see) Figure 11A In the region. For example, unlike Example 1, it can be seen that because the oxygen diffusion prevention layer ITL2 is not included (see Figure 10A Therefore, oxygen atoms, including those in the oxide semiconductor layer OSC, diffuse into the electrode ME region. Thus, it can be inferred that in the structure of the oxide semiconductor layer-electrode SLM-r1 according to Comparative Example 1, a thick metal oxide layer is formed between the oxide semiconductor layer OSC and the electrode ME.

[0185] Figure 12A A cross-sectional view illustrating the structure of the oxide semiconductor layer-electrode SLM-2 according to Example 2, which is an embodiment of the present invention. Figure 12B The results of measuring the contact resistance between the oxide semiconductor layer OSC and the electrode ME according to an embodiment of the present invention are shown. Figure 13A A cross-sectional view illustrating the structure of the oxide semiconductor layer-electrode SLM-r2 according to Comparative Example 2. Figure 13B The results of measuring the contact resistance between the oxide semiconductor layer OSC and the electrode ME according to Comparative Example 2 are shown.

[0186] refer to Figure 12AThe oxide semiconductor layer-electrode SLM-2 according to Embodiment 2 has a structure that includes an oxide semiconductor layer OSC and an electrode ME disposed on a substrate SUB, and includes an insertion layer ITL disposed between the oxide semiconductor layer OSC and the electrode ME (e.g., directly therebetween). The insertion layer ITL includes a dipole layer ITL1 disposed on the oxide semiconductor layer OSC (e.g., directly thereon) and an oxygen diffusion prevention layer ITL2 disposed on the dipole layer ITL1 (e.g., directly thereon). In the structure of the oxide semiconductor layer-electrode SLM-2 according to Embodiment 2, the oxide semiconductor layer OSC includes IGZO, the dipole layer ITL1 includes ZnO, the oxygen diffusion prevention layer ITL2 includes Al2O3, and the electrode ME includes Ti. The distances L1, L2, L3, and L4 between the electrodes ME can be approximately 10 μm, approximately 20 μm, approximately 50 μm, and approximately 70 μm, respectively. The distance between the electrodes ME can be referred to as the length L of the oxide semiconductor layer OSC.

[0187] refer to Figure 12B In order to obtain the oxide semiconductor layer-electrode SLM-2 according to Example 2 (see Example 2), Figure 12A The contact resistance between the oxide semiconductor layer OSC and the electrode ME is measured, and the total resistance R is calculated based on the length L of the oxide semiconductor layer OSC × the width W of the oxide semiconductor layer OSC. 总 The value of the contact resistance can be derived using the transmission line method (TLM). The total resistance can be represented by the following equation 1.

[0188] [Equation 1]

[0189]

[0190] In Equation 1 above, R 总 For oxide semiconductor layer-electrode SLM-2 (see Figure 12A The total resistance of the structure, R ch R is the resistance of the oxide semiconductor layer OSC. c R is the contact resistance between the oxide semiconductor layer OSC and the electrode ME. 片 Let W be the sheet resistance of the oxide semiconductor layer OSC, W be the width of the oxide semiconductor layer OSC, and L be the length of the oxide semiconductor layer OSC.

[0191] Here, when the width W of the oxide semiconductor layer OSC is fixed and the electrodes ME are spaced differently, causing the length L of the oxide semiconductor layer OSC to vary, the resistance R of the oxide semiconductor layer OSC... ch The change, but the contact resistance R c Constant. For example, such as Figure 12BIn the context of the oxide semiconductor layer OSC, with the length L of the OSC layer as the X-axis and the total resistance R as the X-axis... 总 When the value of the oxide semiconductor layer OSC is multiplied by the width W of the OSC layer, and the Y-axis is the contact resistance R, c This can be derived from the Y-axis intercept value. Accordingly, the contact resistance R according to Example 2... c It is derived to be approximately 44Ω.

[0192] refer to Figure 13A The oxide semiconductor layer-electrode SLM-r2 according to Comparative Example 2 has a structure including an oxide semiconductor layer OSC disposed on a substrate SUB and electrodes ME. In the structure of the oxide semiconductor layer-electrode SLM-r2 according to Comparative Example 2, the oxide semiconductor layer OSC includes IGZO, and the electrodes ME include Ti. The distances L1, L2, L3, and L4 between the electrodes ME can be approximately 10 μm, approximately 20 μm, approximately 50 μm, and approximately 70 μm, respectively. The distance between the electrodes ME can be referred to as the length L of the oxide semiconductor layer OSC.

[0193] refer to Figure 13B In order to obtain the oxide semiconductor layer-electrode SLM-r2 according to Comparative Example 2 (see Comparative Example 2), Figure 13A The contact resistance between the oxide semiconductor layer OSC and the electrode ME was measured, and the total resistance R was determined based on the length L × width W of the oxide semiconductor layer OSC. 总 The value of the contact resistance can be derived using the method previously described for Example 2. Based on the contact resistance R of Comparative Example 2... c It is derived to be approximately 156Ω.

[0194] refer to Figures 12A to 13B As can be seen, compared with the contact resistance of Comparative Example 2, in which the oxide semiconductor layer OSC and the electrode ME are in direct contact with each other without an intercalation layer ITL disposed therebetween, the contact resistance of Example 2, in which the intercalation layer ITL is disposed between the oxide semiconductor layer OSC and the electrode ME, is reduced by about 72%.

[0195] Figures 14A to 14E A cross-sectional view illustrating one step of a method for manufacturing a display panel according to an embodiment of the present invention.

[0196] The method for manufacturing a display panel according to the embodiment may include: forming a channel A1 in step S100 (see... Figure 8 In steps S210, S220 and S230, an insertion layer ITL is formed on channel A1 (see...). Figure 8 ), and in step S300, a source electrode S1 is formed on the insertion layer ITL (see Figure 8 ) and drain electrode D1 (see Figure 8 ).

[0197] For ease of description, Figures 14A to 14E Explanation corresponds to Figure 8 The oxide semiconductor layer OSC of the channel A1, and corresponding to Figure 8 The source electrode S1 or drain electrode D1 is the electrode ME. Additionally, as an example, the oxide semiconductor layer OSC comprises IGZO, the dipole layer ITL1 comprises ZnO, the oxygen diffusion prevention layer ITL2 comprises Al2O3, and the electrode ME comprises Ti.

[0198] refer to Figure 14A The method for manufacturing a display panel according to an embodiment may include forming a channel A1 in step S100 (see...). Figure 8 In step S100, channel A1 is formed (see...). Figure 8 This step can be the formation of an oxide semiconductor layer (OSC). For example, in an embodiment, the oxide semiconductor layer (OSC) can be formed as an IGZO layer.

[0199] refer to Figures 14B to 14D The method for manufacturing a display panel according to an embodiment may include forming an insertion layer ITL in steps S210, S220, and S230. Forming the insertion layer ITL in steps S210, S220, and S230 may include forming a dipole layer ITL1 in step S210 and forming an oxygen diffusion prevention layer ITL2 in steps S220 and S230. In this embodiment, the dipole layer ITL1 and the oxygen diffusion prevention layer ITL2 may each be formed using an ALD process.

[0200] Figure 14B The illustrative explanation of step S210 involves forming a dipole layer ITL1. The dipole layer ITL1 can be formed on an oxide semiconductor layer OSC using an ALD process. For example, in an embodiment, the dipole layer ITL1 can be formed as a ZnO layer.

[0201] Figure 14C and Figure 14D The formation of the oxygen diffusion prevention layer ITL2 in steps S220 and S230 is illustrated schematically. The oxygen diffusion prevention layer ITL2 can be formed on the dipole layer ITL1 using an ALD process. For example, in an embodiment, the oxygen diffusion prevention layer ITL2 can be formed as an Al2O3 layer. During the formation of the oxygen diffusion prevention layer ITL2, doping can be achieved by using a reducing metal precursor to form oxygen vacancies in the dipole layer ITL1. For example, in an embodiment, trimethylaluminum (TMA) can be used as an aluminum precursor to form oxygen vacancies in the ZnO layer. Figure 14DThis section explains the state in which an oxygen diffusion prevention layer ITL2 is formed and a dipole is formed at the interface between the oxygen diffusion prevention layer ITL2 and the dipole layer ITL1. Accordingly, the oxide semiconductor layer OSC can have a doping effect.

[0202] refer to Figure 14E The method for manufacturing a display panel according to an embodiment may include forming a source electrode S1 on the intercalation layer ITL in step S300 (see...). Figure 8 ) and drain electrode D1 (see Figure 8 In step S300, the source electrode S1 is formed (see...). Figure 8 ) and drain electrode D1 (see Figure 8 This can be a step in forming the electrode ME. For example, the electrode ME can be formed as a Ti layer.

[0203] As previously described, the thin-film transistors included in the display panel conceived according to the present invention may have reduced contact resistance.

[0204] Furthermore, by incorporating thin-film transistors with reduced contact resistance, electronic devices according to embodiments of the present invention can have increased reliability.

[0205] Furthermore, the manufacturing method for a display panel according to embodiments of the present invention can provide a display panel including thin-film transistors with reduced contact resistance.

[0206] In the foregoing, non-limiting embodiments of the present invention have been described with reference to the present invention concept, and it will be understood by those skilled in the art or those of ordinary skill that various modifications and changes can be made to the present invention concept, as long as such modifications and changes do not depart from the spirit and technical scope of the present invention concept.

Claims

1. A display panel, comprising: basal layer; A light-emitting element layer is disposed on the substrate layer and includes a light-emitting element; and A circuit layer, disposed on the substrate layer and including thin-film transistors electrically connected to the light-emitting element, The thin-film transistor includes: Gate electrode, The channel overlaps with the gate electrode and comprises an oxide semiconductor. The source electrode is disposed at the first end of the channel. A drain electrode is disposed at the second end of the channel opposite to the first end, and An insertion layer is disposed between the channel and the source electrode and between the channel and the drain electrode, and The insertion layer includes: a dipole layer disposed on the channel; and an oxygen diffusion prevention layer disposed on the dipole layer.

2. The display panel according to claim 1, wherein: The dipole layer is directly disposed on the channel; and The dipole layer includes a metal oxide in which oxygen vacancies are formed to dope the channel.

3. The display panel according to claim 1, wherein: The oxygen diffusion prevention layer is directly disposed between the dipole layer and the source electrode, and between the dipole layer and the drain electrode; and The oxygen diffusion prevention layer comprises a metal oxide that blocks oxygen from diffusing from the channel to the source electrode and the drain electrode.

4. The display panel of claim 1, wherein the oxygen diffusion prevention layer has a thickness that allows electron tunneling.

5. The display panel according to claim 1, wherein the oxygen diffusion prevention layer has a thickness in the range of less than or equal to 3 nm.

6. The display panel according to claim 1, wherein the oxygen diffusion prevention layer has a thickness in the range of less than or equal to 1 nm.

7. The display panel according to claim 1, wherein the oxygen diffusion prevention layer comprises at least one compound selected from Al2O3, TiO2, ZnO, MgO and HfO2.

8. The display panel according to claim 1, wherein the dipole layer comprises at least one compound selected from ITO, ZnO, HfZrO and TiO2.

9. The display panel according to claim 1, wherein the channel comprises at least one compound selected from ITZO, IGZO, TZO, ATZO and ZnO.

10. The display panel according to claim 1, wherein the circuit layer further comprises: A gate insulating film is disposed between the gate electrode and the channel.

11. An electronic device, comprising: The display module includes: a display panel according to any one of claims 1 to 10; and The window is set on the display module.

12. The electronic device of claim 11, further comprising at least one of a processor, a memory, and a power module.

13. The electronic device of claim 11, wherein the electronic device is a television, monitor, outdoor billboard, desktop personal computer, laptop computer, personal digital assistant, automotive dashboard, center console, navigation system, in-vehicle mirror display, game console, mobile phone, tablet computer, smartwatch, smart glasses, head-mounted display, or camera.

14. A method for manufacturing a display panel, comprising: Forming a channel including oxide semiconductors; An insertion layer is formed on the channel; as well as A source electrode and a drain electrode are formed on the insertion layer, wherein the insertion layer is disposed between the source electrode and the channel and between the drain electrode and the channel. The formation of the insertion layer includes: forming a dipole layer on the channel, and forming an oxygen diffusion prevention layer while reducing the dipole layer using a reducing metal precursor.

15. The method of claim 14, wherein the insertion layer is formed by an atomic layer deposition process.

16. The method of claim 14, wherein the dipole layer comprises a metal oxide in which oxygen vacancies are formed to dope the channel.

17. The method of claim 14, wherein the oxygen diffusion prevention layer comprises a metal oxide that blocks oxygen from diffusing from the channel to the source electrode and the drain electrode.

18. The method of claim 14, wherein the oxygen diffusion prevention layer has a thickness that allows electron tunneling.

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