Array substrate, preparation method thereof and display panel

Abstract

The application relates to an array substrate, a preparation method thereof and a display panel. The array substrate comprises a first transistor and a second transistor, the first transistor comprises a first semiconductor layer and a first gate electrode, the second transistor comprises a second semiconductor layer and a second gate electrode, and the first semiconductor layer and the second semiconductor layer comprise different materials; the array substrate comprises a substrate, the first semiconductor layer, a first gate insulating layer, the second semiconductor layer, a second gate insulating layer, the first gate electrode and the second gate electrode, the first semiconductor layer is located on one side of the substrate; the first gate insulating layer is located on a side of the first semiconductor layer away from the substrate; the second semiconductor layer is located on a side of the first gate insulating layer away from the substrate; the second gate insulating layer is located on a side of the second semiconductor layer away from the substrate; and the first gate electrode and the second gate electrode are arranged in the same layer and located on a side of the second gate insulating layer away from the substrate. Therefore, the array substrate, the preparation method thereof and the display panel provided by the application can simplify the preparation process of the array substrate.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to an array substrate and its fabrication method, and a display panel. Background Technology

[0002] OLED (Organic Light Emitting Diode) display panels have many advantages, such as being all-solid-state, actively emitting light, having a fast response time, high contrast, no viewing angle limitations, and being able to achieve flexible displays. They are a new type of display technology that was developed in the mid-20th century and are widely used in people's daily production and life.

[0003] In related technologies, the display panel may include an array substrate, which may include low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) and metal-oxide-semiconductor (MODS) thin-film transistors (MODS). LTPS can serve as driving TFTs, exhibiting high mobility, reducing driving voltage, and enabling high refresh rates and high resolutions. MODS can serve as switching TFTs, with lower leakage current, allowing the display panel to maintain good display performance at low frame rates and reducing power consumption. However, the fabrication process of the aforementioned array substrates is relatively complex, resulting in high production costs. Summary of the Invention

[0004] Therefore, it is necessary to provide an array substrate, its fabrication method, and a display panel, which can simplify the fabrication process of the array substrate.

[0005] In a first aspect, embodiments of this application provide an array substrate, the array substrate including transistors, the transistors including a first transistor and a second transistor, the first transistor including a first semiconductor layer and a first gate, the second transistor including a second semiconductor layer and a second gate, wherein the first semiconductor layer and the second semiconductor layer include different materials; the array substrate includes a substrate, a first semiconductor layer, a first gate insulating layer, a second semiconductor layer, a second gate insulating layer, a first gate and a second gate, the first semiconductor layer being located on one side of the substrate; the first gate insulating layer being located on the side of the first semiconductor layer facing away from the substrate; the second semiconductor layer being located on the side of the first gate insulating layer facing away from the substrate; the second gate insulating layer being located on the side of the second semiconductor layer facing away from the substrate; the first gate and the second gate are disposed in the same layer and are located on the side of the second gate insulating layer facing away from the substrate.

[0006] Secondly, embodiments of this application also provide a method for fabricating an array substrate. The array substrate includes transistors, each transistor including a first transistor and a second transistor. The first transistor includes a first semiconductor layer and a first gate, and the second transistor includes a second semiconductor layer and a second gate. The first semiconductor layer and the second semiconductor layer are made of different materials. The fabrication method includes providing a substrate; forming a first semiconductor layer on one side of the substrate; forming a first gate insulating layer on the side of the first semiconductor layer away from the substrate; forming a second semiconductor layer on the side of the first gate insulating layer away from the substrate; forming a second gate insulating layer on the side of the second semiconductor layer away from the substrate; and forming a second conductive layer on the side of the second gate insulating layer away from the substrate. The second conductive layer includes a first gate and a second gate.

[0007] Thirdly, embodiments of this application also provide a display panel, including an array substrate as described in the first aspect, or an array substrate obtained by the method for preparing an array substrate as described in the second aspect.

[0008] The array substrate and its fabrication method, as well as the display panel provided in this application embodiment, allow for the simultaneous fabrication of the first and second gates by having the first gate and the second gate disposed in the same layer. This simplifies the fabrication process of the first and second gates and reduces the number of masks used, thus avoiding defects caused by an excessive number of masks and improving the yield of the array substrate. Furthermore, by providing a first gate insulating layer and a second gate insulating layer between the first semiconductor layer and the first gate, and by providing two gate insulating layers for the first transistor, the thickness of the gate insulating layer between the first semiconductor layer and the first gate is increased. This allows the first transistor to withstand higher gate voltages, improving its overvoltage and surge resistance capabilities and enhancing its long-term operational stability. Additionally, this results in a larger subthreshold swing (SS) of the first transistor. When the first transistor is configured as a driving transistor, the driving current of the driving transistor changes more smoothly with the gate voltage, allowing for precise control of the luminous brightness corresponding to different gray levels, avoiding gray-level breaks, improving display detail, and facilitating gray-level expansion of the display panel. By setting a second gate insulating layer between the second semiconductor layer and the second gate without setting a first gate insulating layer, the second transistor has a gate insulating layer, which makes the thickness of the gate insulating layer between the second semiconductor layer and the second gate smaller, resulting in a smaller subthreshold swing (SS) of the second transistor. This can improve the gate control capability of the second transistor, which is conducive to the rapid turn-on or turn-off of the second transistor, making the response speed of the second transistor fast and suitable for high refresh rate scenarios. Attached Figure Description

[0009] Figure 1 This is a cross-sectional view of the array substrate provided in an embodiment of this application.

[0010] Figure 2This is a top view of the first conductive layer provided in an embodiment of this application.

[0011] Figure 3 A top view of the first conductive layer and the first scan line provided in an embodiment of this application.

[0012] Figure 4 This is a top view of the multilayer conductive layer provided in an embodiment of this application.

[0013] Figure 5 Another top view of the first conductive layer provided in an embodiment of this application.

[0014] Figure 6 Another top view of the first conductive layer and the first scan line provided in an embodiment of this application.

[0015] Figure 7 Another top view of the multilayer conductive layer provided in the embodiments of this application.

[0016] Figure 8 This is a schematic flowchart illustrating the fabrication method of the array substrate provided in the embodiments of this application.

[0017] Figure 9 This is a schematic diagram of the structure after the substrate is provided, as provided in the embodiments of this application.

[0018] Figure 10 This is a schematic diagram of the structure after the formation of the first gate insulating layer, provided in an embodiment of this application.

[0019] Figure 11 This is a schematic diagram of the structure after the formation of the second gate insulating layer, provided in an embodiment of this application.

[0020] Figure 12 This is a schematic diagram of the structure after forming the first gate and the second gate, provided in an embodiment of this application.

[0021] Figure 13 This is a schematic diagram of the structure of the display device provided in the embodiments of this application.

[0022] Figure 14 The equivalent circuit diagram of the pixel circuit provided in the embodiments of this application is shown.

[0023] Figure 15 Another equivalent circuit diagram of the pixel circuit provided in the embodiments of this application.

[0024] Explanation of reference numerals in the attached figures:

[0025] 1. Display device; 10. Display panel; 100. Array substrate; 101. First transistor; 102. Second transistor; 103. Substrate; M1. First conductive layer; 111. First conductive structure; 112. Second conductive structure; MG. Second conductive layer; 121. First gate; 122. Second gate; 131. First semiconductor layer; 132. Second semiconductor layer; 141. First gate insulating layer; 142. Second gate insulating layer; 151. First electrode plate; 161. Capacitor dielectric layer; 162. Insulating buffer layer; 163. Insulating layer; 170. Pixel circuit; 170h. Pixel circuit row; 170h1. First pixel circuit row; 1 70h2, Second pixel circuit row; Scan1, First scan line; 180, Connecting component; 183, Third conductive structure; 1831, First sub-conductive structure; 1832, Second sub-conductive structure; 184, Fourth conductive structure; 1843, Third sub-conductive structure; 1844, Fourth sub-conductive structure; T11, First electrode; T12, Second electrode; GK1, First via; S1, First source region; G1, First channel region; D1, First drain region; S2, Second source region; G2, Second channel region; D2, Second drain region; MC, Third conductive layer; M4, Fourth conductive layer; A, First direction; B, Second direction; C, Third direction. Detailed Implementation

[0026] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0027] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0028] When describing positional relationships, unless otherwise specified, when an element, such as a layer, film, or substrate, is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate elements present. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate elements present.

[0029] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0030] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0031] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0032] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.

[0033] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0034] As described in the background section, LTPO technology utilizes both low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) and metal oxide (MO) thin-film transistors as transistors in pixel circuits. LTPO combines the advantages of these two types of transistors, contributing to improved display panel resolution and reduced power consumption. Because the oxide semiconductor (e.g., IGZO) of MO TFTs is highly sensitive and requires sophisticated processing, the bottom gate, polycrystalline silicon semiconductor layer, and top gate of the LTPS TFT can be fabricated first, followed by the bottom gate, oxide semiconductor layer, and top gate of the MO TFT. This ensures that the oxide semiconductor layer is fabricated after the bottom gate, polycrystalline silicon semiconductor layer, and top gate of the LTPS TFT.

[0035] However, the bottom gate, polysilicon semiconductor layer, and top gate of LTPS TFTs, as well as the bottom gate, oxide semiconductor layer, and top gate of MO TFTs, are fabricated separately, making the fabrication process of the array substrate more complex. Furthermore, each of these layers requires a separate mask for patterning, increasing the number of masks used. After fabricating each layer, thickness measurement, pattern size measurement, and defect detection are necessary, adding to the inspection steps. Each additional mask increases the cumulative overlay defect rate by 8%-12%, and a larger number of masks further increases the overlay defect rate, leading to a decrease in the yield of the array substrate.

[0036] Based on the aforementioned technical problems, the inventors discovered that by simultaneously fabricating the first and second gates in the same layer, the fabrication processes of the first and second gates can be simplified. Furthermore, this reduces the number of masks used, avoiding defects caused by an excessive number of masks and thus improving the yield of the array substrate. Additionally, by providing a first gate insulating layer and a second gate insulating layer between the first semiconductor layer and the first gate, and having two gate insulating layers on the first transistor, the thickness of the gate insulating layer between the first semiconductor layer and the first gate is increased. This allows the first transistor to withstand higher gate voltages, improving its overvoltage and surge resistance capabilities, resulting in stronger long-term operational stability. Moreover, this results in a larger subthreshold swing (SS) of the first transistor. When the first transistor is configured as a driving transistor, the driving current changes more smoothly with the gate voltage, allowing for precise control of the luminous brightness corresponding to different gray levels, avoiding gray-scale breaks, improving display detail, and facilitating gray-scale expansion of the display panel. By setting a second gate insulating layer between the second semiconductor layer and the second gate without setting a first gate insulating layer, the second transistor has a gate insulating layer, which makes the thickness of the gate insulating layer between the second semiconductor layer and the second gate smaller, resulting in a smaller subthreshold swing (SS) of the second transistor. This can improve the gate control capability of the second transistor, which is conducive to the rapid turn-on or turn-off of the second transistor, making the response speed of the second transistor fast and suitable for high refresh rate scenarios.

[0037] The above is the core idea of ​​this application. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0038] The following is in conjunction with the appendix Figure 1-13 The array substrate, its fabrication method, and the display panel provided in the embodiments of this application are described.

[0039] See Figure 1 This application provides an array substrate 100, which includes a plurality of transistors, including a first transistor 101 and a second transistor 102. The first transistor 101 includes a first semiconductor layer 131 and a first gate 121, and the second transistor 102 includes a second semiconductor layer 132 and a second gate 122. The first semiconductor layer 131 and the second semiconductor layer 132 are made of different materials.

[0040] For example, the material of the first semiconductor layer 131 includes silicon semiconductor, such as low-temperature polysilicon (LTPS). Thus, by making the material of the first semiconductor layer 131 low-temperature polysilicon, the first transistor 101 can be a low-temperature polysilicon thin-film transistor, which has high mobility and is beneficial for achieving high refresh rates and high resolutions.

[0041] For example, the material of the second semiconductor layer 132 includes oxide semiconductor, and the second transistor 102 can be an oxide thin film transistor with low leakage current, which can enable the display panel 10 to maintain good display effect at low frame rate and reduce the power consumption of the display panel 10.

[0042] For example, oxide semiconductor materials include indium oxide (In Oxide), indium zinc oxide (In-ZnOxide), indium tin oxide (In-SnOxide), indium titanium oxide (In-TiOxide), indium gallium oxide (In-GaOxide), indium aluminum gallium oxide (In-Ga-AlOxide), indium gallium tin oxide (In-Ga-SnOxide, also written as IGTO), gallium zinc oxide (Ga-ZnO, also written as GZO), aluminum zinc oxide (Al-ZnO, also written as AZO), indium aluminum zinc oxide (In-Al-ZnO, also written as IAZO), indium tin zinc oxide (In-Sn-ZnO, also written as ITZO), indium titanium zinc oxide (In-Ti-ZnOxide), and indium gallium zinc oxide (In-Ga-ZnO). One or more of the following: Indium gallium tin zinc oxide (In-Ga-Sn-ZnOxide, also written as IGZTO), Indium gallium aluminum zinc oxide (In-Ga-Al-Zn Oxide, also written as IGAZO, IGZAO or IAGZO), Gallium tin oxide (Ga-Sn Oxide), and Aluminum tin oxide (Al-Sn Oxide).

[0043] See Figure 1The array substrate 100 includes a substrate 103, on which transistors are disposed. The substrate 103 can provide support for the remaining film layers to be disposed subsequently. The array substrate 100 includes a first semiconductor layer 131, a first gate insulating layer 141, a second semiconductor layer 132, and a second gate insulating layer 142. The first semiconductor layer 131 is located on one side of the substrate 103, the first gate insulating layer 141 is located on the side of the first semiconductor layer 131 facing away from the substrate 103, the second semiconductor layer 132 is located on the side of the first gate insulating layer 141 facing away from the substrate 103, and the second gate insulating layer 142 is located on the side of the second semiconductor layer 132 facing away from the substrate 103. The first gate 121 and the second gate 122 are disposed in the same layer, and the first gate 121 and the second gate 122 are located on the side of the second gate insulating layer 142 facing away from the substrate 103. In this way, by disposing of the first gate 121 and the second gate 122 in the same layer, the first gate 121 and the second gate 122 can be fabricated simultaneously, which helps to simplify the fabrication process of the first gate 121 and the second gate 122. In addition, it can also reduce the number of masks used, which helps to avoid defects caused by an excessive number of masks, thereby improving the yield of the array substrate 100. Furthermore, by providing a first gate insulating layer 141 and a second gate insulating layer 142 between the first semiconductor layer 131 and the first gate 121, the first transistor 101 is provided with two gate insulating layers. This results in a larger thickness of the gate insulating layer between the first semiconductor layer 131 and the first gate 121, allowing the first transistor 101 to withstand higher gate voltages. This is beneficial for improving the overvoltage resistance and surge resistance of the first transistor 101, making its long-term operational stability stronger. In addition, it results in a larger subthreshold swing (SS) of the first transistor 101. When the first transistor 101 is configured as a driving transistor, the driving current of the driving transistor changes more smoothly with the gate voltage. This allows for precise control of the luminous brightness corresponding to different gray levels, avoiding gray level breaks, improving display detail, and facilitating the gray level expansion of the display panel 10. By providing a second gate insulating layer 142 between the second semiconductor layer 132 and the second gate 122 without providing a first gate insulating layer 141, the second transistor 102 has a gate insulating layer, which makes the thickness of the gate insulating layer between the second semiconductor layer 132 and the second gate 122 smaller, resulting in a smaller subthreshold swing (SS) of the second transistor 102. This can improve the gate control capability of the second transistor 102, which is beneficial for the second transistor 102 to turn on or off quickly, making the response speed of the second transistor 102 fast and suitable for high refresh rate scenarios.

[0044] In some embodiments, the hydrogen content of the first gate insulating layer 141 is greater than that of the second gate insulating layer 142. This results in a higher hydrogen content in the first gate insulating layer 141, which facilitates the diffusion of hydrogen from the first gate insulating layer 141 to the first semiconductor layer 131. This also facilitates the passivation of defects in the first semiconductor layer 131 formed from silicon semiconductors by hydrogen, thereby improving the electrical performance of the first transistor 101. In addition, the lower hydrogen content in the second gate insulating layer 142 helps to reduce the adverse effects of hydrogen diffusion from the second gate insulating layer 142 on the second semiconductor layer 132 formed from oxide semiconductors.

[0045] In some embodiments, the oxygen content of the first gate insulating layer 141 is less than that of the second gate insulating layer 142. This results in a higher hydrogen content in the oxygen in the second gate insulating layer 142, which is beneficial for the oxygen in the second gate insulating layer 142 to capture hydrogen in the second gate insulating layer 142, reducing the diffusion of hydrogen from the second gate insulating layer 142 to the second semiconductor layer 132 during high-temperature processing. It also helps to fill oxygen vacancies in the second semiconductor layer 132. In addition, the lower oxygen content of the first gate insulating layer 141 is beneficial for reducing the capture of hydrogen in the second gate insulating layer 142 by the oxygen in the first gate insulating layer 141, which is beneficial for the diffusion of hydrogen from the first gate insulating layer 141 to the first semiconductor layer 131 during high-temperature processing. It is also beneficial for the passivation of defects in the first semiconductor layer 131 formed by silicon semiconductor by hydrogen, thereby improving the electrical performance of the first transistor 101.

[0046] In some embodiments, the dielectric constant of the first gate insulating layer 141 is greater than that of the second gate insulating layer 142. This results in a larger dielectric constant of the first gate insulating layer 141, which can reduce the breakdown risk of the first transistor 101, improve surge and overvoltage resistance, and extend the service life of the first transistor 101. In addition, the dielectric constant of the second gate insulating layer 142 is smaller. The lower dielectric constant of the second gate insulating layer 142 is beneficial for the second transistor 102 to achieve fast turn-on / turn-off, thereby improving the response speed of the second transistor 102.

[0047] In some embodiments, the thickness of the first gate insulating layer 141 is less than the thickness of the second gate insulating layer 142. This allows the thickness of the first gate insulating layer 141 to be smaller, which helps to avoid the total thickness of the first gate insulating layer 141 and the second gate insulating layer 142 being too large, thereby preventing the total thickness of the gate insulating layer of the first transistor 101 from being too large. In addition, making the thickness of the second gate insulating layer 142 larger can prevent the thickness of the gate insulating layer of the second transistor 102 from being too small, which helps to reduce the breakdown risk of the second transistor 102 and extend the service life of the second transistor 102.

[0048] For example, the thickness of the first gate insulating layer 141 is in the range of 300 angstroms to 500 angstroms. This avoids the first gate insulating layer 141 being too thin, which is beneficial to increasing the total amount of hydrogen in the first gate insulating layer 141. This is beneficial to using the hydrogen in the first gate insulating layer 141 to passivate the defects in the first semiconductor layer 131. In addition, it avoids the first gate insulating layer 141 being too thick, thus avoiding the total thickness of the gate insulating layer of the first transistor 101 being too large.

[0049] For example, the thickness of the first gate insulating layer 141 can be 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms, 500 angstroms, or any value between 300 angstroms and 500 angstroms.

[0050] For example, the thickness of the second gate insulating layer 142 is in the range of 800 angstroms to 1500 angstroms. This avoids the second gate insulating layer 142 being too thin, which helps to reduce the breakdown risk of the second transistor 102 and extend the service life of the second transistor 102. In addition, it avoids the second gate insulating layer 142 being too thick, which helps to make the array substrate 100 thinner and lighter, and can improve the gate control capability of the second transistor 102.

[0051] For example, the thickness of the second gate insulating layer 142 can be 800 angstroms, 1000 angstroms, 1200 angstroms, 1400 angstroms, 1500 angstroms or any value between 800 angstroms and 1500 angstroms.

[0052] See Figure 1 , Figure 4 and Figure 7 In some embodiments, the array substrate 100 further includes a storage capacitor, which includes a first electrode 151 and a first gate 121. The array substrate 100 also includes a capacitor dielectric layer 161, located on the side of the first gate 121 and the second gate 122 facing away from the substrate 103. The first electrode 151 is located on the side of the capacitor dielectric layer 161 facing away from the substrate 103. The orthographic projection of the first gate 121 onto the substrate 103 overlaps with the orthographic projection of the first electrode 151 onto the substrate 103. The first gate 121 is configured as the second electrode of the storage capacitor. Thus, by using the first gate 121 as the second electrode of the storage capacitor, there is no need to separately fabricate the second electrode of the storage capacitor, which reduces the number of film layers and patterning steps in the array substrate 100, reduces the number of photomasks used, simplifies the overall fabrication process of the array substrate 100, and improves production efficiency and yield.

[0053] In other embodiments, the array substrate 100 further includes a storage capacitor, which includes a first electrode plate and a first gate 121. The first electrode plate of the storage capacitor is disposed on the same layer as the second semiconductor layer 132. In this way, the first gate 121 is constructed as the second electrode plate of the storage capacitor. There is no need to separately fabricate the second electrode plate of the storage capacitor, which can reduce the number of film layers and patterning steps of the array substrate 100, reduce the number of masks used, simplify the overall fabrication process of the array substrate 100, and improve production efficiency and fabrication yield. In addition, the first electrode plate 151 of the storage capacitor is directly fabricated simultaneously using the film layer on which the second semiconductor layer 132 is located, which helps to simplify the fabrication process of the first electrode plate 151 and the second semiconductor layer 132 of the storage capacitor.

[0054] See Figure 1 In some embodiments, the array substrate 100 includes an insulating buffer layer 162, a first conductive structure 111, and a second conductive structure 112. The insulating buffer layer 162 is located between the first semiconductor layer 131 and the substrate 103. Both the first conductive structure 111 and the second conductive structure 112 are located between the insulating buffer layer 162 and the substrate 103. The orthographic projection of the first conductive structure 111 on the substrate 103 overlaps with the orthographic projection of the first semiconductor layer 131 on the substrate 103. The orthographic projection of the second conductive structure 112 on the substrate 103 overlaps with the orthographic projection of the second semiconductor layer 132 on the substrate 103. The first conductive structure 111 and the second conductive structure 112 are disposed in the same layer, and both the first conductive structure 111 and the second conductive structure 112 are located in the first conductive layer M1. The insulating buffer layer 162 can prevent water and oxygen from penetrating through the substrate 103 and entering the transistor to cause corrosion. By disposing the second conductive structure 112 on the side of the second semiconductor layer 132 facing the substrate 103, the second conductive structure 112 can have a light-shielding effect, which can reduce the adverse effects of external light on the second semiconductor layer 132 formed by the oxide semiconductor. In addition, the first conductive structure 111 and the second conductive structure 112 can be connected to a fixed potential, so that the first conductive structure 111 and the second conductive structure 112 can shield electromagnetic interference, ensure signal integrity, and reduce the probability of display abnormalities in the display panel 10.

[0055] The first transistor 101 and the first conductive structure 111 are respectively disposed, and the orthographic projection of the first conductive structure 111 on the substrate 103 overlaps with the orthographic projection of the corresponding first semiconductor layer 131 on the substrate 103. The second transistor 102 and the second conductive structure 112 are respectively disposed, and the orthographic projection of the second conductive structure 112 on the substrate 103 overlaps with the orthographic projection of the corresponding second semiconductor layer 132 on the substrate 103.

[0056] Figures 2-7The dashed boxes in the diagram indicate the areas containing four pixel circuits 170 and the areas containing two pixel circuit rows 170h. In some embodiments, the array substrate 100 includes multiple pixel circuits 170, which can be arranged along a first direction A and a second direction B; for example, the multiple pixel circuits 170 can be arranged in an array. Pixel circuits 170 can be electrically connected to corresponding light-emitting devices to provide driving signals to the light-emitting devices. Each pixel circuit 170 can include multiple transistors and a storage capacitor. The multiple transistors of the pixel circuit 170 can include a first transistor 101 and a second transistor 102. Pixel circuits 170 can be 2T1C pixel circuits, 6T1C pixel circuits, etc. Figure 15 ), 7T1C pixel circuit or 8T1C pixel circuit ( Figure 14 The second transistor 102 can be a driving transistor, a threshold compensation transistor, or a reset transistor.

[0057] exist Figure 14 In the pixel circuit, transistors T1-T8 are included, where T4 and T5 can be MO TFTs, and T1, T2, T3, T6, T7, and T8 can be LTPS TFTs.

[0058] exist Figure 15 In the pixel circuit, transistors T1-T6 are included, where T2, T3, and T6 can be MO TFTs, and T1, T4, and T5 can be LTPS TFTs.

[0059] In some embodiments, the array substrate 100 includes a plurality of pixel circuit rows 170h arranged along a first direction A, the pixel circuit rows 170h include a plurality of pixel circuits 170 arranged along a second direction B, and the pixel circuit rows 170h include a first pixel circuit row 170h1.

[0060] See Figure 2 and Figure 5 In some examples, in the first pixel circuit row 170h1, the first conductive structure 111 corresponding to the first transistor 101 of each pixel circuit 170 is an integral structure. In this way, the potential of the entire row of first conductive structures 111 corresponding to the first pixel circuit row 170h1 can be consistent, resulting in better consistency of electric field shielding. In addition, it is beneficial to simplify the circuit wiring that provides fixed points to the entire row of first conductive structures 111, while reducing the number of vias in the display panel and saving panel wiring space.

[0061] See Figure 2 and Figure 3In some embodiments, pixel circuit row 170h further includes a second pixel circuit row 170h2, which is adjacent to the first pixel circuit row 170h1 along the first direction A. In the adjacent first pixel circuit row 170h1 and second pixel circuit row 170h2, the first conductive structure 111 corresponding to the first transistor 101 in the first pixel circuit row 170h1 and the first conductive structure 111 corresponding to the first transistor 101 in the second pixel circuit row 170h2 are spaced apart and separately arranged. The first conductive structure 111 corresponding to the first transistor 101 in the first pixel circuit row 170h1 and the first conductive structure 111 corresponding to the first transistor 101 in the second pixel circuit row 170h2 are independent of each other. Thus, a row of first conductive structures 111 corresponding to the first pixel circuit row 170h1 and a row of first conductive structures 111 corresponding to the second pixel circuit row 170h2 are spaced apart to leave wiring space, which can be used to arrange other traces.

[0062] See Figure 2 and Figure 3 In some embodiments, in the same pixel circuit row 170h, the second conductive structure 112 corresponding to the second transistor 102 in each pixel circuit 170 is an integral structure. This makes the potential of the entire row of second conductive structures 112 corresponding to the second pixel circuit row 170h2 consistent, resulting in better consistency of electric field shielding. In addition, it is beneficial to simplify the circuit wiring that provides fixed points to the entire row of second conductive structures 112.

[0063] See Figure 5 and Figure 6 In other embodiments, in the same pixel circuit row 170h, the second conductive structures 112 corresponding to the second transistors 102 of two adjacent pixel circuits 170 are spaced apart and separately arranged, that is, the second conductive structures 112 corresponding to the second transistors 102 in two adjacent pixel circuits 170 are independent of each other. In this way, in the same pixel circuit row 170h, the second conductive structures 112 corresponding to the second transistors 102 in two adjacent pixel circuits 170 are spaced apart to leave wiring space, which can be used to arrange other traces.

[0064] See Figure 3 and Figure 6 In some embodiments, the array substrate 100 further includes a first scan line Scan1, which extends along the second direction B, and the first scan line Scan1 is aligned with the second gate 122 in the first pixel circuit row 170h1. Figure 1The first scan line Scan1 is electrically connected to each of the second gates 122 in the first pixel circuit row 170h1, so that scan signals can be transmitted through the first scan line Scan1 to each of the second gates 122 in the first pixel circuit row 170h1. A portion of the first scan line Scan1 can be configured as a second gate 122. For example, the first scan line Scan1 and the second gates 122 in the first pixel circuit row 170h1 can be connected through a first via GK1 (…). Figure 7 Electrical connection. The first via GK1 can be located in the display area, or the first via GK1 can be located in the non-display area.

[0065] See Figure 5 and Figure 6 In other embodiments, in adjacent first pixel circuit rows 170h1 and second pixel circuit rows 170h2, the first conductive structure 111 corresponding to each first transistor 101 in the first pixel circuit row 170h1 and the first conductive structure 111 corresponding to each first transistor 101 in the second pixel circuit row 170h2 are integrated into one structure. In this way, the potentials of the two rows of first conductive structures 111 corresponding to the adjacent first pixel circuit rows 170h1 and second pixel circuit rows 170h2 are consistent, resulting in better consistency of electric field shielding. In addition, it is beneficial to simplify the circuit wiring that provides fixed points to the two rows of first conductive structures 111.

[0066] In some embodiments, in the corresponding second transistor 102 and the second conductive structure 112, the second conductive structure 112 is electrically connected to the second gate 122. In this way, the second gate 122 of the second transistor 102 can be constructed as the top gate of the second transistor 102, and the second conductive structure 112 can be constructed as the bottom gate of the second transistor 102. The second transistor 102 is a top-bottom dual-gate structure. The top-bottom dual-gate structure can enhance electric field control, make full use of the high mobility of the second semiconductor layer 132 formed by the oxide semiconductor, reduce threshold voltage drift, and help compensate for the instability problem of high mobility materials.

[0067] In some embodiments, the first transistor 101 may be a single-gate structure (e.g., a top-gate structure) or a dual-gate structure (e.g., a top-bottom dual-gate structure).

[0068] See Figure 5 and Figure 6In some embodiments, the first conductive layer M1 includes a connecting component 180. Two adjacent first conductive structures 111 along the first direction A are connected by the connecting component 180. For example, two adjacent first conductive structures 111 along the first direction A are connected by the connecting component 180 to form an integral structure. The connecting component 180 includes a third conductive structure 183 and a fourth conductive structure 184 arranged along the second direction B. The third conductive structure 183 includes a first sub-conductive structure 1831 and a second sub-conductive structure 1832. The fourth conductive structure 184 includes a third sub-conductive structure 1843 and a fourth sub-conductive structure 1844. The first sub-conductive structure 1831 and the third sub-conductive structure 1843 are arranged opposite each other along the second direction B. The second sub-conductive structure 1832 and the fourth conductive structure 1844 are arranged opposite each other along the second direction B. The distance between the first sub-conductive structure 1831 and the third conductive structure 1843 along the second direction B is a first distance. The distance between the second sub-conductive structure 1832 and the fourth conductive structure 1844 along the second direction B is a first distance. The distance is the second distance, and the first distance is smaller than the second distance. Thus, by setting the first distance to be smaller and the second distance to be larger, the distance between the first sub-conductive structure 1831 of one of the two adjacent connecting components 180 along the second direction B and the third sub-conductive structure 1843 of the other connecting component 180 can be larger. This allows the second conductive structure 112 to be positioned between the first sub-conductive structure 1831 of one of the two adjacent connecting components 180 along the second direction B and the third sub-conductive structure 1843 of the other connecting component 180, thereby providing more layout space for the second conductive structure 112 and improving the layout flexibility of the second conductive structure 112.

[0069] See Figure 1 Along the thickness direction of the substrate 103, the array substrate 100 may include a first conductive layer M1, a first semiconductor material layer, a second semiconductor material layer, a second conductive layer MG, a third conductive layer MC, and a fourth conductive layer M4 sequentially stacked on the substrate 103. An insulating layer 163 may be disposed between each adjacent pair of the first conductive layer M1, the first semiconductor material layer, the second semiconductor material layer, the second conductive layer MG, the third conductive layer MC, and the fourth conductive layer M4. The materials of any two insulating layers 163 may be the same or different.

[0070] For example, the first semiconductor material layer includes a first semiconductor layer 131, and the second semiconductor material layer includes a second semiconductor layer 132.

[0071] For example, the first conductive layer M1 may include a first conductive structure 111, a second conductive structure 112, and a connection component 180.

[0072] For example, the second conductive layer MG may include at least one of a first scan signal line, a second scan signal line, a second plate of a storage capacitor, a light emission control signal line, and the gate of each transistor.

[0073] For example, the third conductive layer MC may include the first electrode of the storage capacitor. The orthographic projection of the first electrode 151 of the storage capacitor on the substrate 103 overlaps with the orthographic projection of the second electrode of the storage capacitor on the substrate 103.

[0074] For example, the fourth conductive layer M4 may include a first electrode T11 and a second electrode T12 of each transistor. One of the first electrode T11 and the second electrode T12 is the source of the transistor, and the other of the first electrode T11 and the second electrode T12 is the drain.

[0075] See Figure 1 In some embodiments, the insulating layer 163 located between the first conductive layer M1 and the first semiconductor layer 131 is configured as at least one insulating buffer layer 163, for example, two insulating buffer layers 163. The two insulating buffer layers 163 include a first buffer layer and a second buffer layer, the first buffer layer and the second buffer layer being made of different materials.

[0076] For example, the material of at least one of the first buffer layer and the second buffer layer may include at least one of silicon oxide, silicon nitride, and calcium oxynitride.

[0077] See Figure 1 In some embodiments, the insulating layer 163 located between the first semiconductor layer 131 and the second semiconductor layer 132 is configured as a first gate insulating layer 141. The insulating layer 163 located between the second semiconductor layer 132 and the second conductive layer MG is configured as a second gate insulating layer 142. The insulating layer 163 located between the second conductive layer MG and the third conductive layer MC is configured as a capacitor dielectric layer 161.

[0078] For example, the material of any one of the first conductive layer M1, the second conductive layer MG, the third conductive layer MC, and the fourth conductive layer M4 may include metals, such as silver, aluminum, copper, molybdenum, titanium, etc., and metal compounds, such as metal nitrides, conductive oxides, etc.

[0079] See Figure 1 and Figure 2The array substrate 100 may have a first direction A, a second direction B, and a third direction C, all of which are different. The first direction A and the second direction B can be any two different directions parallel to the array substrate 100, and the third direction C can be any direction intersecting a plane parallel to the array substrate 100. For example, the first direction A, the second direction B, and the third direction C can be mutually perpendicular. Exemplarily, the first direction A can be the width direction of the array substrate 100, the second direction B can be the length direction of the array substrate 100, and the third direction C can be the thickness direction of the array substrate 100. The length, width, and thickness in the embodiments of this application are merely for descriptive convenience and do not imply any limitation on the dimensions. For example, the width can be greater than, equal to, or less than the length. The orientation of the array substrate 100 can be the same as the orientation of the display panel 10 and the substrate 103.

[0080] The following describes the fabrication method of the array substrate 100 provided in the embodiments of this application.

[0081] This application provides a method for fabricating an array substrate 100, which can be used to fabricate the array substrate 100 described in the above embodiments. The array substrate 100 includes a plurality of transistors, including a first transistor 101 and a second transistor 102. The first transistor 101 includes a first semiconductor layer 131 and a first gate 121, and the second transistor 102 includes a second semiconductor layer 132 and a second gate 122. The first semiconductor layer 131 and the second semiconductor layer 132 are made of different materials.

[0082] See Figure 8 The preparation method includes steps S100-S600.

[0083] Step S100: Provide a substrate.

[0084] See Figure 9 A substrate 103 is provided.

[0085] Step S200: A first semiconductor layer is formed on one side of the substrate.

[0086] See Figure 10 After providing a substrate 103, a first semiconductor layer 131 may be formed on one side of the substrate 103.

[0087] Step S300: A first gate insulating layer is formed on the side of the first semiconductor layer away from the substrate.

[0088] See Figure 10 After forming a first semiconductor layer 131 on one side of the substrate 103, a first gate insulating layer 141 may be formed on the side of the first semiconductor layer 131 opposite to the substrate 103.

[0089] Step S400: A second semiconductor layer is formed on the side of the first gate insulating layer that is away from the substrate.

[0090] See Figure 11 After forming a first gate insulating layer 141 on the side of the first semiconductor layer 131 away from the substrate 103, a second semiconductor layer 132 may be formed on the side of the first gate insulating layer 141 away from the substrate 103.

[0091] Step S500: A second gate insulating layer is formed on the side of the second semiconductor layer away from the substrate.

[0092] See Figure 11 After forming the second semiconductor layer 132 on the side of the first gate insulating layer 141 away from the substrate 103, the process may include forming the second gate insulating layer 142 on the side of the second semiconductor layer 132 away from the substrate 103.

[0093] Step S600: A second conductive layer is formed on the side of the second gate insulating layer away from the substrate. The second conductive layer includes a first gate and a second gate.

[0094] See Figure 12After forming a second gate insulating layer 142 on the side of the second semiconductor layer 132 away from the substrate 103, a second conductive layer MG may be formed on the side of the second gate insulating layer 142 away from the substrate 103. The second conductive layer MG includes a first gate 121 and a second gate 122. Thus, both the first gate 121 and the second gate 122 are formed by the second conductive layer MG. By setting the first gate 121 and the second gate 122 in the same layer, the first gate 121 and the second gate 122 can be fabricated simultaneously, which helps to simplify the fabrication process of the first gate 121 and the second gate 122. In addition, it can also reduce the number of masks used, which helps to avoid defects caused by an excessive number of masks, thereby improving the yield of the array substrate 100. Furthermore, by providing a first gate insulating layer 141 and a second gate insulating layer 142 between the first semiconductor layer 131 and the first gate 121, the first transistor 101 is provided with two gate insulating layers. This results in a larger thickness of the gate insulating layer between the first semiconductor layer 131 and the first gate 121, allowing the first transistor 101 to withstand higher gate voltages. This is beneficial for improving the overvoltage resistance and surge resistance of the first transistor 101, making its long-term operational stability stronger. In addition, it results in a larger subthreshold swing (SS) of the first transistor 101. When the first transistor 101 is configured as a driving transistor, the driving current of the driving transistor changes more smoothly with the gate voltage. This allows for precise control of the luminous brightness corresponding to different gray levels, avoiding gray level breaks, improving display detail, and facilitating the gray level expansion of the display panel 10. By providing a second gate insulating layer 142 between the second semiconductor layer 132 and the second gate 122 without providing a first gate insulating layer 141, the second transistor 102 has a gate insulating layer, which makes the thickness of the gate insulating layer between the second semiconductor layer 132 and the second gate 122 smaller, resulting in a smaller subthreshold swing (SS) of the second transistor 102. This can improve the gate control capability of the second transistor 102, which is beneficial for the second transistor 102 to turn on or off quickly, making the response speed of the second transistor 102 fast and suitable for high refresh rate scenarios.

[0095] In some embodiments, the process temperature for forming the first gate insulating layer 141 is greater than or equal to the process temperature for forming the second gate insulating layer 142. This results in a higher process temperature for the first gate insulating layer 141, which facilitates the diffusion of hydrogen from the first gate insulating layer 141 to the first semiconductor layer 131 and is beneficial for the passivation of defects in the first semiconductor layer 131 formed from silicon semiconductors by hydrogen. At the same time, the first gate insulating layer 141, which is prepared at a higher temperature, is prepared before the second semiconductor layer 132, which can prevent the high-temperature process of the first gate insulating layer 141 from directly affecting the temperature-sensitive second semiconductor layer 132. In addition, the process temperature of the second gate insulating layer 142 is lower. The lower process temperature of the second gate insulating layer 142, which is prepared after the second semiconductor layer 132, helps to reduce the adverse effects of temperature on the second semiconductor layer 132 during the preparation of the second gate insulating layer 142.

[0096] For example, the process temperature range for forming the first gate insulating layer 141 is 380°C-420°C. This avoids the process temperature for forming the first gate insulating layer 141 being too low, which is beneficial for hydrogen diffusion from the first gate insulating layer 141 to the first semiconductor layer 131 to passivate defects in the first semiconductor layer 131. It can also improve the film quality of the first gate insulating layer 141 (e.g., improve density). In addition, it avoids the process temperature for forming the first gate insulating layer 141 being too high, which is beneficial for reducing the adverse effects of the high-temperature process on the film layer of the array substrate 100 and reducing the manufacturing cost.

[0097] For example, the process temperature for forming the first gate insulating layer 141 can be 380°C, 390°C, 400°C, 410°C, 420°C, or any value between 380°C and 420°C.

[0098] For example, the process temperature range for forming the second gate insulating layer 142 is 280°C-380°C. This avoids the process temperature of forming the second gate insulating layer 142 being too low, which would affect the film quality of the second gate insulating layer 142. In addition, it avoids the process temperature of forming the second gate insulating layer 142 being too high, which would have an adverse effect on the second semiconductor layer 132.

[0099] For example, the process temperature for forming the second gate insulating layer 142 can be 280°C, 300°C, 320°C, 350°C, 380°C, or any value between 280°C and 380°C.

[0100] In some embodiments, the process gas used to form the first gate insulating layer 141 includes a hydrogen-containing gas. This is beneficial for increasing the hydrogen content in the first gate insulating layer 141, for the diffusion of hydrogen from the first gate insulating layer 141 to the first semiconductor layer 131, and for the passivation of defects in the first semiconductor layer 131 formed by the silicon semiconductor by hydrogen.

[0101] In some embodiments, the process gas used to form the second gate insulating layer 142 includes an oxygen-containing gas. This is beneficial for increasing the oxygen content in the second gate insulating layer 142, which helps the oxygen in the second gate insulating layer 142 capture hydrogen in the second gate insulating layer 142, reduces the diffusion of hydrogen from the second gate insulating layer 142 to the second semiconductor layer 132 during high-temperature processing, reduces the adverse effects of hydrogen diffusion from the second gate insulating layer 142 on the second semiconductor layer 132 formed by the oxide semiconductor, and also helps to compensate for oxygen vacancies in the second semiconductor layer 132.

[0102] In some embodiments, after forming the second conductive layer MG on the side of the second gate insulating layer 142 facing away from the substrate 103, a capacitor dielectric layer 161 may be formed on the side of the second conductive layer MG facing away from the substrate 103. Then, the array substrate 100 is heat-treated to allow hydrogen in the capacitor dielectric layer 161 to diffuse into the first semiconductor layer 131. Then, a first electrode 151 is formed on the side of the capacitor dielectric layer 161 facing away from the substrate 103. Thus, by heat-treating the array substrate 100 to allow hydrogen in the capacitor dielectric layer 161 to diffuse into the first semiconductor layer 131, it is beneficial to passivate defects in the first semiconductor layer 131 formed from silicon semiconductors. Exemplarily, the orthographic projection of the first gate 121 on the substrate 103 overlaps with the orthographic projection of the first electrode 151 on the substrate 103. The first gate 121 is configured as the second electrode of a storage capacitor. Thus, by using the first gate 121 as the second electrode of the storage capacitor, there is no need to separately prepare the second electrode of the storage capacitor. This reduces the number of film layers and patterning steps in the array substrate 100, reduces the number of mask plates used, simplifies the overall fabrication process of the array substrate 100, and improves production efficiency and fabrication yield.

[0103] See Figure 12 In some embodiments, the first semiconductor layer 131 includes a first source region S1, a first channel region G1, and a first drain region D1 arranged in sequence, and the second semiconductor layer 132 includes a second source region S2, a second channel region G2, and a second drain region D2 arranged in sequence. The orthographic projection of the first gate 121 on the substrate 103 overlaps (e.g., coincides) with the orthographic projection of the first channel region G1 on the substrate 103, and the orthographic projection of the second gate 122 on the substrate 103 overlaps (e.g., coincides) with the orthographic projection of the second channel region G2 on the substrate 103. After forming the second conductive layer MG on the side of the second gate insulating layer 142 away from the substrate 103, it may include using the first gate 121 and the second gate 122 as masks to simultaneously perform doping treatment on the first source region S1, the first drain region D1, the second source region S2 and the second drain region D2. In this way, the first gate 121 and the second gate 122 can be directly used as masks in the doping process, without the need to prepare additional masks separately, which helps to simplify the doping process and reduce the preparation cost.

[0104] The following describes the display panel 10 provided in the embodiments of this application ( Figure 13 (This will be explained.)

[0105] This application provides a display panel 10, which includes the array substrate 100 described in the above embodiments. The display panel 10 may include light-emitting units located on one side of the array substrate 100. The array substrate 100 may be electrically connected to the light-emitting units. There may be multiple light-emitting units. For example, multiple light-emitting units may be arranged in an array. The multiple light-emitting units include, but are not limited to, red light-emitting units, green light-emitting units, and blue light-emitting units. In other examples, the multiple light-emitting units may also include white light-emitting units.

[0106] For example, the light-emitting unit may include a first electrode, a light-emitting material layer, and a second electrode sequentially disposed along a path away from the array substrate 100. One of the first electrode and the second electrode may be an anode, and the other may be a cathode. This application embodiment uses an example where the first electrode is an anode and the second electrode is a cathode.

[0107] For example, the light-emitting unit may also include one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron injection layer (EIL), an electron transport layer (ETL), a hole block layer (HBL), and an electron block layer (EBL).

[0108] In some embodiments, the display panel 10 may include an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, a mini light-emitting diode display (Mini LED), or a micro light-emitting diode display (MicroLED), etc. This application uses an OLED display panel as an example for illustration.

[0109] The display device 1 provided in the embodiments of this application will be described below.

[0110] See Figure 13This application provides a display device 1, which includes the display panel 10 described in the above embodiments. Therefore, the display device 1 also has the beneficial effects of the display panel 10 described in the above embodiments. The similarities can be understood with reference to the explanation of the display panel 10 above, and will not be repeated here.

[0111] For example, the display device 1 can be a mobile phone or any electronic product with display function, including but not limited to the following categories: television, laptop, desktop monitor, tablet computer, digital camera, smart bracelet, smart glasses, vehicle display, industrial control equipment, medical display screen, touch interactive terminal, etc. This application embodiment does not make any special limitation in this regard.

[0112] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0113] The embodiments described above are merely examples of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

Claims

1. An array substrate, characterized in that, The array substrate includes: transistors, the transistors including a first transistor and a second transistor, the first transistor including a first semiconductor layer and a first gate, the second transistor including a second semiconductor layer and a second gate, wherein the first semiconductor layer and the second semiconductor layer are made of different materials; the array substrate further includes: substrate; The first semiconductor layer is located on one side of the substrate; The first gate insulating layer is located on the side of the first semiconductor layer that is away from the substrate; The second semiconductor layer is located on the side of the first gate insulating layer that is away from the substrate; The second gate insulating layer is located on the side of the second semiconductor layer that is away from the substrate; The first gate and the second gate are disposed in the same layer and are located on the side of the second gate insulating layer away from the substrate.

2. The array substrate according to claim 1, characterized in that, The hydrogen content of the first gate insulating layer is greater than the hydrogen content of the second gate insulating layer; and / or, The oxygen content of the first gate insulating layer is less than the oxygen content of the second gate insulating layer.

3. The array substrate according to claim 1, characterized in that, The dielectric constant of the first gate insulating layer is greater than that of the second gate insulating layer.

4. The array substrate according to any one of claims 1-3, characterized in that, The thickness of the first gate insulating layer is less than the thickness of the second gate insulating layer; and / or, The thickness of the first gate insulating layer ranges from 300 angstroms to 500 angstroms; and / or, The thickness of the second gate insulating layer ranges from 800 angstroms to 1500 angstroms.

5. The array substrate according to any one of claims 1-3, characterized in that, The array substrate further includes a storage capacitor, which includes a first electrode plate and a first gate. The array substrate further includes a capacitor dielectric layer, which is located on the side of the first gate and the second gate away from the substrate. The first electrode is located on the side of the capacitor dielectric layer opposite to the substrate, and the orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the first electrode on the substrate.

6. The array substrate according to any one of claims 1-3, characterized in that, The array substrate includes an insulating buffer layer, a first conductive structure, and a second conductive structure. The insulating buffer layer is located between the first semiconductor layer and the substrate, and both the first conductive structure and the second conductive structure are located between the insulating buffer layer and the substrate. Along the thickness direction of the display panel, the orthographic projection of the first conductive structure on the substrate overlaps with the orthographic projection of the corresponding first semiconductor layer on the substrate, and the orthographic projection of the second conductive structure on the substrate overlaps with the orthographic projection of the corresponding second semiconductor layer on the substrate; The first conductive structure and the second conductive structure are disposed in the same layer and are both located in the first conductive layer.

7. The array substrate according to claim 6, characterized in that, The array substrate includes a pixel circuit, and the pixel circuit includes a first transistor and a second transistor; The array substrate includes a plurality of pixel circuit rows arranged along a first direction, the pixel circuit rows include a plurality of pixel circuits arranged along a second direction, and the pixel circuit rows include a first pixel circuit row. In the first pixel circuit row, the first conductive structure corresponding to the first transistor of each pixel circuit is an integral structure.

8. The array substrate according to claim 7, characterized in that, The pixel circuit row further includes a second pixel circuit row, which is adjacent to the first pixel circuit row along the first direction. The first conductive structure corresponding to the first transistor in the first pixel circuit row is independent of the first conductive structure corresponding to the first transistor in the second pixel circuit row. In the same row of pixel circuits, the second conductive structure corresponding to the second transistor in each pixel circuit is an integral structure.

9. The array substrate according to claim 8, characterized in that, The array substrate further includes a first scan line extending along the second direction, and the first scan line is electrically connected to the second gate in the first pixel circuit row.

10. The array substrate according to claim 7, characterized in that, The pixel circuit row further includes a second pixel circuit row, which is adjacent to the first pixel circuit row along the first direction. The first conductive structure corresponding to the first transistor in the first pixel circuit row is an integral structure with the first conductive structure corresponding to the first transistor in the second pixel circuit row. In the pixel circuit described in the same row, the second conductive structures corresponding to two adjacent second transistors are independent of each other.

11. The array substrate according to claim 10, characterized in that, The second conductive structure is electrically connected to the second gate.

12. The array substrate according to claim 7, characterized in that, The first conductive layer includes a connection component, through which two adjacent first conductive structures along the first direction are connected; The connecting component includes a third conductive structure and a fourth conductive structure arranged along the second direction. The third conductive structure includes a first sub-conductive structure and a second sub-conductive structure, and the fourth conductive structure includes a third sub-conductive structure and a fourth conductive structure. The first sub-conductive structure and the third sub-conductive structure are arranged opposite each other along the second direction, and the second sub-conductive structure and the fourth sub-conductive structure are arranged opposite each other along the second direction. The distance between the first sub-conductive structure and the third sub-conductive structure along the second direction is a first distance, and the distance between the second sub-conductive structure and the fourth sub-conductive structure along the second direction is a second distance. The first distance is less than the second distance. The second conductive structure is located between the third sub-conductive structure of one of the two adjacent connecting components along the second direction and the first sub-conductive structure of the other.

13. The array substrate according to any one of claims 1-3, characterized in that, The array substrate further includes a storage capacitor, which includes a first electrode and a first gate. The first electrode of the storage capacitor is disposed on the same layer as the second semiconductor layer.

14. The array substrate according to any one of claims 1, characterized in that, The material of the first semiconductor layer includes silicon semiconductor; and / or, The material of the second semiconductor layer includes an oxide semiconductor.

15. A method for fabricating an array substrate, characterized in that, The array substrate includes transistors, each transistor including a first transistor and a second transistor. The first transistor includes a first semiconductor layer and a first gate, and the second transistor includes a second semiconductor layer and a second gate. The first semiconductor layer and the second semiconductor layer comprise different materials. The fabrication method includes: Provide a substrate; A first semiconductor layer is formed on one side of the substrate; A first gate insulating layer is formed on the side of the first semiconductor layer opposite to the substrate; A second semiconductor layer is formed on the side of the first gate insulating layer that is opposite to the substrate; A second gate insulating layer is formed on the side of the second semiconductor layer opposite to the substrate; A second conductive layer is formed on the side of the second gate insulating layer opposite to the substrate, and the second conductive layer includes a first gate and a second gate.

16. The method for fabricating an array substrate according to claim 15, characterized in that, The process temperature for forming the first gate insulating layer is greater than or equal to the process temperature for forming the second gate insulating layer; and / or, The process temperature range for forming the first gate insulating layer is 380°C-420°C; and / or, The process temperature range for forming the second gate insulating layer is 280°C-380°C; and / or, The process gas used to form the first gate insulating layer includes a hydrogen-containing gas; and / or, The process gas used to form the second gate insulating layer includes an oxygen-containing gas.

17. The method for fabricating an array substrate according to claim 15, characterized in that, After forming the second conductive layer on the side of the second gate insulating layer opposite to the substrate, the process includes: A capacitor dielectric layer is formed on the side of the second conductive layer opposite to the substrate; The array substrate is heated to allow hydrogen in the capacitor dielectric layer to diffuse into the first semiconductor layer; A first electrode is formed on the side of the capacitor dielectric layer opposite to the substrate.

18. The method for fabricating an array substrate according to claim 17, characterized in that, The first semiconductor layer includes a first source region, a first channel region, and a first drain region arranged in sequence; the second semiconductor layer includes a second source region, a second channel region, and a second drain region arranged in sequence; the orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the first channel region on the substrate; and the orthographic projection of the second gate on the substrate overlaps with the orthographic projection of the second channel region on the substrate. After forming the second conductive layer on the side of the second gate insulating layer opposite to the substrate, the process includes: Using the first gate and the second gate as masks, the first source region, the first drain region, the second source region, and the second drain region are simultaneously doped.

19. A display panel, characterized in that, The array substrate includes any one of the array substrates according to claims 1 to 14, or the array substrate prepared by any one of the array substrates according to claims 15 to 18.

Images