A back contact solar cell and a method of manufacturing the same

Abstract

The application discloses a back contact solar cell and a preparation method thereof. The back contact solar cell can include: a crystalline silicon substrate, a back surface of the crystalline silicon substrate including alternately arranged first conductive regions and second conductive regions, and an isolation region arranged between adjacent first conductive regions and second conductive regions; a tunneling oxide layer and a doped microcrystalline silicon layer arranged in the first conductive region from inside to outside; an intrinsic amorphous silicon layer and a doped amorphous silicon layer arranged in the second conductive region from inside to outside, and a conductive type of the doped microcrystalline silicon layer being opposite to a conductive type of the doped amorphous silicon layer. The back contact solar cell can better balance the doping concentration between the first conductive regions and the second conductive regions, so as to reduce a lateral carrier transport loss.

Description

Technical Field

[0001] This invention relates to a back-contact solar cell and its fabrication method. Background Technology

[0002] Currently, back-contact solar cells typically consist of a phosphorus-doped polycrystalline silicon layer and a boron-doped amorphous silicon layer disposed on the back side of a crystalline silicon substrate to achieve the collection and transport of different types of charge carriers. Specifically, the phosphorus-doped polycrystalline silicon layer collects and transports electron carriers, while the boron-doped amorphous silicon layer collects and transports hole carriers. However, because the deposition temperature of the phosphorus-doped polycrystalline silicon layer is no less than 600°C and it requires annealing activation at temperatures exceeding 900°C, this high-temperature treatment results in a relatively high phosphorus doping concentration in the phosphorus-doped polycrystalline silicon layer. In contrast, the deposition temperature of the boron-doped amorphous silicon layer is generally between 220°C and 260°C, resulting in a significantly lower boron doping concentration in the boron-doped amorphous silicon layer compared to the phosphorus doping concentration in the phosphorus-doped polycrystalline silicon layer.

[0003] Research has found that the doping concentration of boron-doped amorphous silicon layer in existing back-contact solar cells is asymmetrical with that of phosphorus-doped polycrystalline silicon layer, resulting in significant lateral carrier transport losses at the edge of the PN region. Summary of the Invention

[0004] In view of this, the present invention provides a back-contact solar cell and a method for fabricating the same. The back-contact solar cell, by combining a doped microcrystalline silicon layer in the first conductive region with a doped amorphous silicon layer in the second conductive region, can effectively balance the doping concentration between the doped microcrystalline silicon layer and the doped amorphous silicon layer with opposite conductivity types on the back side of the back-contact solar cell, reduce the difference in doping concentration between the doped microcrystalline silicon layer and the doped amorphous silicon layer, thereby effectively reducing the lateral carrier transport loss at the edge of the conductive region and improving the photoelectric conversion efficiency of the back-contact solar cell.

[0005] Specifically, the present invention provides the following technical solutions: In a first aspect, the present invention provides a back-contact solar cell, comprising: The back side includes a crystalline silicon substrate with alternating first and second conductive regions, and an isolation region is provided between adjacent first and second conductive regions; A tunneling oxide layer and a doped microcrystalline silicon layer are stacked from the inside to the outside in the first conductive region; An intrinsic amorphous silicon layer and a doped amorphous silicon layer are stacked from the inside to the outside in the second conductive region, wherein the conductivity type of the doped microcrystalline silicon layer is opposite to that of the doped amorphous silicon layer.

[0006] Secondly, embodiments of the present invention provide a method for preparing a back-contact solar cell, comprising: Step 1: Provide a crystalline silicon substrate, wherein the back side of the crystalline silicon substrate is divided into alternating initial first conductive regions and initial second conductive regions, and an initial isolation region is disposed between adjacent initial first conductive regions and initial second conductive regions; Step 2: Based on the initial first conductive region, a first conductive region is formed, the first conductive region comprising a tunneling oxide layer and a doped microcrystalline silicon layer stacked from the inside to the outside; based on the initial second conductive region, a second conductive region is formed, the second conductive region comprising an intrinsic amorphous silicon layer and a doped amorphous silicon layer stacked from the inside to the outside, and an isolation region located between the first conductive region and the second conductive region is formed based on the initial isolation region, wherein the conductivity type of the doped microcrystalline silicon layer is opposite to the conductivity type of the doped amorphous silicon layer.

[0007] The technical solution of the first aspect of the above invention has the following advantages or beneficial effects: The back-contact solar cell provided in this invention, through the combination of a tunneling oxide layer and a doped microcrystalline silicon layer in the first conductive region, and the combination of an intrinsic amorphous silicon layer and a doped amorphous silicon layer in the second conductive region, can ensure the passivation effect and carrier collection capability of the first and second conductive regions. At the same time, through the combination of the doped microcrystalline silicon layer in the first conductive region and the doped amorphous silicon layer in the second conductive region, it can effectively balance the doping concentration between the doped microcrystalline silicon layer and the doped amorphous silicon layer with opposite conductivity types on the back side of the back-contact solar cell, reduce the difference in doping concentration between the doped microcrystalline silicon layer and the doped amorphous silicon layer, thereby reducing the recombination and lateral transport of hole carriers at the edge of the conductive region, effectively reducing the lateral carrier transport loss at the edge of the conductive region, and improving the photoelectric conversion efficiency of the back-contact solar cell. Attached Figure Description

[0008] Figure 1 This is a partial cross-sectional structural diagram of the back-contact solar cell of the first structure provided in the embodiments of the present invention; Figure 2 This is a partial cross-sectional structural diagram of the second type of back-contact solar cell provided in the embodiments of the present invention; Figure 3 This is a schematic diagram of the main process of the back-contact solar cell provided in the embodiment of the present invention; Figure 4 This is a schematic diagram of a partial structural change corresponding to the first embodiment of step S302 provided in this invention; Figure 5 This is a schematic diagram of a partial structural change corresponding to the second embodiment of step S302 provided in the present invention.

[0009] The attached figures are labeled as follows: 10 - Crystalline silicon substrate; 11 - First conductive region; 11' - Initial first conductive region; 12 - Second conductive region; 12' - Initial second conductive region; 13 - Isolation region; 13' - Initial isolation region; 131 - First isolation region; 132 - Second isolation region; 20 - Tunneling oxide layer; 30 - Doped microcrystalline silicon layer; 31 - First doped microcrystalline silicon layer; 32 - Second doped microcrystalline silicon layer; 40 - Protective layer; 50 - Intrinsic amorphous silicon layer; 60 - Doped amorphous silicon layer; 61 - First doped amorphous silicon layer; 62 - Second doped amorphous silicon layer; 70 - Transparent conductive film layer; 80 - Metal electrode; 90 - Passivation antireflection layer. Detailed Implementation

[0010] In existing technologies, to address the low photoelectric conversion efficiency of conventional heterojunction solar cells (where the P-type functional region consists of an intrinsic amorphous silicon layer and a boron-doped amorphous silicon layer stacked from the inside out, and the N-type functional region consists of an intrinsic amorphous silicon layer and a phosphorus-doped amorphous silicon layer stacked from the inside out), the N-type functional region is designed as a tunneling passivation structure, i.e., a back-contact heterojunction solar cell. The N-type functional region of a back-contact heterojunction solar cell generally includes a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer stacked from the inside out, while the P-type functional region generally includes an intrinsic amorphous silicon layer and a boron-doped amorphous silicon layer stacked from the inside out. The phosphorus-doped polycrystalline silicon layer typically needs to be formed stepwise in a high-temperature diffusion furnace at a temperature not lower than 600°C. Specifically, a polycrystalline silicon layer is first formed, then phosphorus atoms are doped into the polycrystalline silicon layer to form a phosphorus-doped polycrystalline silicon layer, and simultaneously a phosphorus-silicon glass (PSG) layer is formed on the outside of the phosphorus-doped polycrystalline silicon layer. The PSG then needs to be removed. Furthermore, this phosphorus-doped polysilicon layer requires annealing activation at temperatures exceeding 900°C. Existing processes for forming phosphorus-doped polysilicon layers are complex, and the phosphorus-doped polysilicon layer is easily damaged during PSG removal. Current high-temperature phosphorus-doped polysilicon layer formation generally involves relatively high doping concentrations (typically not less than 1×10⁻⁶). 21 (atoms / cm³). As described in the background section, the doping concentration of the boron-doped amorphous silicon layer formed in the P-type functional region is much lower than that of the phosphorus-doped polycrystalline silicon layer in the N-type functional region (generally, the doping concentration of boron-doped amorphous silicon layer differs from that of phosphorus-doped polycrystalline silicon layer by four or five orders of magnitude). On the one hand, this difference in doping concentration leads to a large number of recombination of hole carriers in the phosphorus-doped polycrystalline silicon layer, resulting in the loss of laterally transported hole carriers, which in turn reduces the photoelectric conversion efficiency of heterojunction solar cells. On the other hand, the complex process of forming phosphorus-doped polycrystalline silicon layers not only leads to lower production efficiency of heterojunction solar cells, but also easily leads to poor passivation effect of the N-type functional region of heterojunction solar cells. In addition, the difference in doping concentration between the P-type and N-type functional regions results in an asymmetry in the efficiency of generating hole carriers and electron carriers, which easily leads to the accumulation of photogenerated carriers in the junction region.

[0011] To address the aforementioned problems of existing heterojunction passivated contact solar cells, this invention provides a novel back-contact solar cell structure and its fabrication method. This novel back-contact solar cell utilizes a doped amorphous silicon layer 60 and a doped microcrystalline silicon layer 30 with opposite conductivity types. This effectively balances the doping concentrations of the doped amorphous silicon layer 60 and the doped microcrystalline silicon layer 30, reducing the difference in doping concentration between them. This, in turn, reduces the recombination and lateral transport of hole carriers at the conductive region edges, effectively minimizing lateral carrier transport losses at the conductive region edges and improving the photoelectric conversion efficiency of the back-contact solar cell.

[0012] Specifically, such as Figure 1 and Figure 2 As shown, the back-contact solar cell provided in this embodiment of the invention may include: a crystalline silicon substrate 10 with alternating first conductive regions 11 and second conductive regions 12 on the back side, and an isolation region 13 provided between adjacent first conductive regions 11 and second conductive regions 12; a tunneling oxide layer 20 and a doped microcrystalline silicon layer 30 stacked from the inside to the outside of the first conductive region 11; and an intrinsic amorphous silicon layer 50 and a doped amorphous silicon layer 60 stacked from the inside to the outside of the second conductive region 12, wherein the conductivity type of the doped microcrystalline silicon layer 30 is opposite to that of the doped amorphous silicon layer 60.

[0013] The silicon substrate 10 can be an N-type silicon substrate or a P-type silicon substrate. Preferably, the silicon substrate 10 is an N-type silicon substrate to reduce defects in the silicon substrate.

[0014] It is worth noting that the first conductive region 11, the second conductive region 12, and the isolation region 13 on the back side of the crystalline silicon substrate 10 are determined by various functional film layers (tunneling oxide layer 20, doped microcrystalline silicon layer 30, intrinsic amorphous silicon layer 50, and doped amorphous silicon layer 60, etc.) located on the back side of the crystalline silicon substrate 10. Before these functional film layers were set, there were no partitions on the back side of the crystalline silicon substrate 10 itself.

[0015] The back-contact solar cell provided in this embodiment of the invention, through the cooperation of the tunneling oxide layer 20 and the doped microcrystalline silicon layer 30 in the first conductive region 11, and the cooperation of the intrinsic amorphous silicon layer 50 and the doped amorphous silicon layer 60 in the second conductive region 12, can ensure the passivation effect and carrier collection capability of the first conductive region 11 and the second conductive region 12. At the same time, through the cooperation of the doped microcrystalline silicon layer 30 in the first conductive region 11 and the doped amorphous silicon layer 60 in the second conductive region 12, the doping concentration between the doped microcrystalline silicon layer 30 and the doped amorphous silicon layer 60 with opposite conductivity types on the back side of the back-contact solar cell can be effectively balanced, reducing the difference in doping concentration between the doped microcrystalline silicon layer 30 and the doped amorphous silicon layer 60, thereby reducing the recombination and lateral transport of hole carriers at the edge of the conductive region, effectively reducing the lateral carrier transport loss at the edge of the conductive region, and improving the photoelectric conversion efficiency of the back-contact solar cell. The doping concentration balance between the doped microcrystalline silicon layer 30 and the doped amorphous silicon layer 60 can make the longitudinal and lateral charge carriers collected in the first conductive region 11 and the second conductive region 12 equivalent (i.e., the total amount of longitudinal and lateral charge carriers collected in the first conductive region 11 is equivalent to the total amount of longitudinal and lateral charge carriers collected in the second conductive region 12), thereby reducing the loss of lateral charge carriers.

[0016] Existing back-contact heterojunction solar cells utilize a combination of a tunneling oxide layer and a phosphorus-doped polycrystalline silicon layer in the N-type conductive region, and an intrinsic amorphous silicon layer and a boron-doped amorphous silicon layer in the P-type conductive region. A significant doping concentration difference exists between the phosphorus-doped polycrystalline silicon layer and the boron-doped amorphous silicon layer. This difference causes the phosphorus-doped polycrystalline silicon layer to collect electrons only in the longitudinal direction (i.e., the thickness direction of the back-contact heterojunction solar cell), while the boron-doped amorphous silicon layer can collect hole carriers both longitudinally and laterally. In other words, the hole carrier collection capability of the boron-doped amorphous silicon layer is significantly greater than that of the phosphorus-doped polycrystalline silicon layer. This results in a significant difference in electron carrier collection between the N-type and P-type conductive regions. The doped microcrystalline silicon layer 30 provided in this embodiment of the invention can be formed at a lower temperature. The lower temperature allows the doped microcrystalline silicon layer 30 to have a lower doping concentration (compared to the doped polycrystalline silicon layer) and can effectively control the doping range of the doped atoms in the doped microcrystalline silicon layer 30. This balances the doping concentration between the doped microcrystalline silicon layer 30 and the doped amorphous silicon layer 60, enabling the first conductive region 11 to collect not only lateral carriers but also longitudinal carriers, thereby reducing lateral carrier loss and improving the photoelectric conversion efficiency of the back contact solar cell.

[0017] In addition, the doped microcrystalline silicon layer 30 can increase the amount of H atoms it contains, thereby improving the passivation effect and the turn-on voltage of the back contact solar cell.

[0018] The tunneling oxide layer 20 has a thickness of 0.5nm to 3nm. For example, the thickness of the tunneling oxide layer 20 can be 0.5nm, 1nm, 1.5nm, 2nm, 2.5nm or 3nm, etc.

[0019] The doped microcrystalline silicon layer 30 can be an N-type doped microcrystalline silicon layer, and correspondingly, the doped amorphous silicon layer 60 is a P-type doped amorphous silicon layer; the doped microcrystalline silicon layer 30 can also be a P-type doped microcrystalline silicon layer, and correspondingly, the doped amorphous silicon layer 60 is an N-type doped amorphous silicon layer. For the N-type doped microcrystalline silicon layer or the N-type doped amorphous silicon layer, the N-type doped atoms can be phosphorus atoms or arsenic atoms; for the P-type doped amorphous silicon layer or the P-type doped microcrystalline silicon layer, the P-type doped atoms can be boron atoms or gallium atoms. Preferably, the doped microcrystalline silicon layer 30 can be an N-type doped microcrystalline silicon layer, and correspondingly, the doped amorphous silicon layer 60 can be a P-type doped amorphous silicon layer. By combining the N-type doped microcrystalline silicon layer and the P-type doped amorphous silicon layer, the conductivity and carrier collection capability of the first conductive region 11 can be effectively improved, and the N-type doped microcrystalline silicon layer can be prevented from being exposed in the isolation region 13, which helps to reduce leakage current in the isolation region 13.

[0020] Furthermore, in one embodiment of the present invention, as... Figure 1 and Figure 2 As shown, the aforementioned back-contact solar cell may further include: a transparent conductive film layer 70 disposed on the outside of the doped microcrystalline silicon layer 30 in the first conductive region 11 and on the outside of the doped amorphous silicon layer 60 in the second conductive region 12; and a metal electrode 80 disposed on the first conductive region 11 and the second conductive region 12 and electrically connected to the transparent conductive film layer 70.

[0021] Furthermore, in a preferred embodiment of the present invention, such as Figure 1 and Figure 2 As shown, the back-contact solar cell may also include a passivation antireflection layer 90 disposed on the front side of the crystalline silicon substrate 10 to improve light utilization and reduce defects on the front side of the crystalline silicon substrate 10 to reduce carrier recombination.

[0022] In this embodiment of the invention, the isolation region 13 can have various structures. Specifically, the first structure of the isolation region 13 is to directly expose the back side of the crystalline silicon substrate 10. The second structure of the isolation region 13 is as follows: Figure 1 and Figure 2 As shown, the tunneling oxide layer 20 and the doped microcrystalline silicon layer 30 extend into a portion of the isolation region 13, and the intrinsic amorphous silicon layer 50 and the doped amorphous silicon layer 60 extend into the isolation region 13. Based on the second structure of the isolation region 13, it can be as follows... Figure 1As shown, the aforementioned transparent conductive film layer 70 does not extend to the isolation region 13, and can also be as follows: Figure 2 As shown, the transparent conductive film layer 70 can extend into a portion of the isolation region 13. That is, the isolation region 13 can not only electrically isolate the doped microcrystalline silicon layer 30 and the doped amorphous silicon layer 60, but also electrically isolate the transparent conductive film layer 70 located in the first conductive region 11 and the transparent conductive film layer 70 located in the second conductive region 12.

[0023] The back-contact solar cell provided in this embodiment of the invention mainly improves the structure of the combination of the doped microcrystalline silicon layer 30 and the doped amorphous silicon layer 60. The doped microcrystalline silicon layer 30 and the doped amorphous silicon layer 60 are described below.

[0024] Specifically, in the embodiments of the present invention, the doping concentration on the outer side of the doped microcrystalline silicon layer 30 is greater than that on the inner side, which increases the conductivity of the doped microcrystalline silicon layer 30 and can reduce the contact resistance between the doped microcrystalline silicon layer 30 and the transparent conductive film layer 70, thereby improving the carrier collection capability.

[0025] Furthermore, the doped microcrystalline silicon layer 30 may include a first doped microcrystalline silicon layer 31 and a second doped microcrystalline silicon layer 32 stacked from the inside out. The first doped microcrystalline silicon layer 31 contains uniformly distributed first doped atoms, and the second doped microcrystalline silicon layer 32 contains uniformly distributed first doped atoms. The doping concentration of the second doped microcrystalline silicon layer 32 is greater than that of the first doped microcrystalline silicon layer 31, increasing the conductivity of the doped microcrystalline silicon layer 30. This not only reduces the contact resistance between the doped microcrystalline silicon layer 30 and the transparent conductive film layer 70, but also ensures passivation while helping to reduce lateral carrier transport losses and carrier recombination due to the lower doping concentration of the first doped microcrystalline silicon layer 31. In addition, the uniform distribution of first doped atoms in the first doped microcrystalline silicon layer 31 and the second doped microcrystalline silicon layer 32 can stably reduce lateral carrier transport losses and ensure the reliability of the contact between the second doped microcrystalline silicon layer 32 and the transparent conductive film layer 70.

[0026] Preferably, the doping concentration of the first doped microcrystalline silicon layer 31 is 1×10⁻⁶. 16 atoms / cm³ ~1×10 19 atoms / cm³. For example, the doping concentration of the first doped microcrystalline silicon layer 31 can be 1×10⁻⁶ atoms / cm³. 16 atoms / cm³, 3×10 16 atoms / cm³, 5×10 16 atoms / cm³, 9×10 16 atoms / cm³, 1×10 17 atoms / cm³, 3×10 17 atoms / cm³, 5×10 17atoms / cm³, 9×10 17 atoms / cm³, 5×10 18 atoms / cm³, 9×10 18 atoms / cm³ or 1×10 19 atoms / cm³, etc. By controlling the doping concentration of the first doped microcrystalline silicon layer 31, the doping concentration of the first doped microcrystalline silicon layer 31 and the doped amorphous silicon layer 60 can be balanced to reduce lateral carrier transport losses.

[0027] In addition, the doping concentration of the second doped microcrystalline silicon layer 32 can be 5 × 10⁻⁶. 16 atoms / cm³, 1×10 17 atoms / cm³, 5×10 17 atoms / cm³, 8×10 17 atoms / cm³, 1×10 18 atoms / cm³, 5×10 18 atoms / cm³, 8×10 18 atoms / cm³, 1×10 19 atoms / cm³ or 5×10 19 By controlling the doping concentration of the second doped microcrystalline silicon layer 32, the contact resistance between the second doped microcrystalline silicon layer 32 and the transparent conductive film layer 70 can be effectively reduced, while ensuring that the doping concentration of the second doped microcrystalline silicon layer 32 and the first doped microcrystalline silicon layer 31 are relatively matched. This reduces the doping concentration gradient between the second doped microcrystalline silicon layer 32 and the first doped microcrystalline silicon layer 31, and avoids the accumulation of charge carriers at the interface between the second doped microcrystalline silicon layer 32 and the first doped microcrystalline silicon layer 31, thereby ensuring the charge carrier collection capability of the doped microcrystalline silicon layer 30 composed of the first doped microcrystalline silicon layer 31 and the second doped microcrystalline silicon layer 32.

[0028] Furthermore, the thickness of the first doped microcrystalline silicon layer 31 can be 10nm to 100nm. For example, the thickness of the first doped microcrystalline silicon layer 31 can be 10nm, 20nm, 30nm, 50nm, 70nm, 80nm or 100nm, etc. Preferably, the thickness of the first doped microcrystalline silicon layer 31 is 30nm to 70nm, so as to ensure that the first doped microcrystalline silicon layer 31 can be uniformly distributed in the first conductive region 11.

[0029] In addition, the thickness of the second doped microcrystalline silicon layer 32 can be 1nm to 10nm. For example, the thickness of the second doped microcrystalline silicon layer 32 can be 1nm, 3nm, 5nm, 8nm or 10nm, etc. Preferably, the thickness of the second doped microcrystalline silicon layer 32 is 1nm to 5nm, which can ensure that the second doped microcrystalline silicon layer 32 can be uniformly distributed in the first conductive region 11, and at the same time can effectively reduce the contact resistance between the second doped microcrystalline silicon layer 32 and the transparent conductive film layer 70, and can improve the carrier collection capability.

[0030] More preferably, the first doped microcrystalline silicon layer 31 may also include hydrogen atoms to further enhance the passivation effect of the first doped microcrystalline silicon layer 31.

[0031] In another embodiment of the present invention, the second doped microcrystalline silicon layer 32 may further include hydrogen atoms and oxygen atoms. The hydrogen and oxygen atoms work together to form reliable hydrogen bonds and other bonds between the second doped microcrystalline silicon layer 32 and the transparent conductive film layer 70, which can improve the bonding ability between the second doped microcrystalline silicon layer 32 and the transparent conductive film layer 70, further reduce the interface resistance between the second doped microcrystalline silicon layer 32 and the transparent conductive film layer 70, and ensure carrier transport.

[0032] The first doped microcrystalline silicon layer 31 and the second doped microcrystalline silicon layer 32 can be formed by low-temperature enhanced plasma chemical vapor deposition (PECVD), which allows the microcrystalline silicon and doping processes to be completed simultaneously and avoids the formation of a doped silicon glass layer. This effectively reduces the number of preparation steps for the first doped microcrystalline silicon layer 31 and the second doped microcrystalline silicon layer 32, and reduces the complexity of the process.

[0033] In this embodiment of the invention, the doping concentration on the outer side of the doped amorphous silicon layer 60 is greater than that on the inner side, so as to ensure the passivation effect of the doped amorphous silicon layer 60 while reducing the contact resistance between the doped amorphous silicon layer 60 and the transparent conductive film layer 70.

[0034] More specifically, the doped amorphous silicon layer 60 may include a first doped amorphous silicon layer 61 and a second doped amorphous silicon layer 62 stacked from the inside out. The second doped atoms in the first doped amorphous silicon layer 61 and the second doped amorphous silicon layer 62 are uniformly distributed, and the doping concentration of the second doped amorphous silicon layer 62 is greater than that of the first doped amorphous silicon layer 61. This not only reduces the contact resistance between the second doped amorphous silicon layer 62 and the transparent conductive film layer 70, but also the lower doping concentration of the first doped amorphous silicon layer 61 ensures passivation while helping to reduce carrier recombination. Furthermore, the uniform distribution of the second doped atoms in the first doped amorphous silicon layer 61 and the second doped amorphous silicon layer 62 ensures both the passivation effect and the reliability of the contact between the second doped microcrystalline silicon layer 32 and the transparent conductive film layer 70.

[0035] The doping concentration of the first doped amorphous silicon layer 61 can be 1×10⁻⁶. 16 atoms / cm³ ~1×10 19 atoms / cm³. For example, the doping concentration of the first doped amorphous silicon layer 61 can be 1×10⁻⁶ atoms / cm³. 16 atoms / cm³, 3×10 16 atoms / cm³, 5×10 16 atoms / cm³, 9×10 16 atoms / cm³, 1×10 17 atoms / cm³, 3×10 17 atoms / cm³, 5×10 17 atoms / cm³, 9×10 17 atoms / cm³, 5×10 18 atoms / cm³, 9×10 18 atoms / cm³ or 1×10 19 The doping concentration of the first doped amorphous silicon layer 61 can be controlled to ensure a balance between the doping concentrations of the first doped amorphous silicon layer 61 and the doped microcrystalline silicon layer 30, thereby reducing lateral carrier transport losses. Furthermore, the difference between the doping concentrations of the first doped amorphous silicon layer 61 and the first doped microcrystalline silicon layer 31 is no greater than 100 atoms / cm³. For example, the difference between the doping concentrations of the first doped amorphous silicon layer 61 and the first doped microcrystalline silicon layer 31 can be 5 atoms / cm³, 10 atoms / cm³, 15 atoms / cm³, 50 atoms / cm³, 80 atoms / cm³, or 100 atoms / cm³, etc., to ensure the balance of doping concentrations between the first doped amorphous silicon layer 61 and the first doped microcrystalline silicon layer 31, reduce hole carrier recombination, and decrease lateral transport hole carrier losses.

[0036] In addition, the doping concentration of the second doped amorphous silicon layer 62 is 5 × 10⁻⁶. 16 atoms / cm³ ~5×10 19 atoms / cm³. For example, the doping concentration of the second doped amorphous silicon layer 62 can be 5 × 10⁻⁶ atoms / cm³. 16 atoms / cm³, 1×10 17 atoms / cm³, 5×10 17 atoms / cm³, 8×10 17 atoms / cm³, 1×10 18 atoms / cm³, 5×10 18 atoms / cm³, 8×10 18 atoms / cm³, 1×1019 atoms / cm³ or 5×10 19 By controlling the doping concentration of the second doped amorphous silicon layer 62 (atoms / cm³, etc.), the conductivity of the second doped amorphous silicon layer 62 is ensured. This effectively reduces the contact resistance between the second doped amorphous silicon layer 62 and the transparent conductive film layer 70, while maintaining a good match between the doping concentrations of the second doped amorphous silicon layer 62 and the first doped amorphous silicon layer 61. This reduces the doping concentration gradient between the two layers, preventing carrier accumulation at the interface and ensuring the carrier collection capability of the doped amorphous silicon layer 60 formed by the first and second doped amorphous silicon layers 61. Furthermore, the difference between the doping concentration of the second doped amorphous silicon layer 62 and the doping concentration of the second doped microcrystalline silicon layer 32 is no greater than 10 atoms / cm³. For example, the difference between the doping concentration of the second doped amorphous silicon layer 62 and the doping concentration of the second doped microcrystalline silicon layer 32 is 1 atms / cm³, 3 atms / cm³, 5 atms / cm³, 8 atms / cm³, or 10 atms / cm³, etc., to further ensure the balance of doping concentration between the doped amorphous silicon layer 60 and the doped microcrystalline silicon layer 30.

[0037] Furthermore, the thickness of the first doped amorphous silicon layer 61 can be 10nm to 50nm. For example, the thickness of the first doped amorphous silicon layer 61 can be 10nm, 20nm, 30nm or 50nm, etc., to ensure that the first doped amorphous silicon layer 61 can be uniformly distributed in the second conductive region 12 and to ensure its passivation effect.

[0038] In addition, the thickness of the second doped amorphous silicon layer 62 can be 1nm to 10nm. For example, the thickness of the second doped amorphous silicon layer 62 can be 1nm, 3nm, 5nm, 8nm or 10nm, etc. This can ensure that the second doped amorphous silicon layer 62 can be uniformly distributed in the second conductive region 12, ensuring the conductivity and conductivity uniformity of the second doped amorphous silicon layer 62, so as to effectively reduce the contact resistance between the second doped amorphous silicon layer 62 and the transparent conductive film layer 70, and improve the carrier collection capability.

[0039] More preferably, the first doped amorphous silicon layer 61 may further include hydrogen atoms to further enhance the passivation effect of the first doped amorphous silicon layer 61.

[0040] In another embodiment of the present invention, the second doped amorphous silicon layer 62 may further include hydrogen atoms, oxygen atoms, and carbon atoms. These hydrogen atoms, oxygen atoms, and carbon atoms work together to form hydrogen bonds and other bonds with the transparent conductive film layer 70, thereby improving the bonding ability between the second doped amorphous silicon layer 62 and the transparent conductive film layer 70, improving interfacial contact, further reducing the interfacial resistance between the second doped amorphous silicon layer 62 and the transparent conductive film layer 70, and ensuring carrier transport. Specifically, through the interaction of hydrogen atoms, oxygen atoms, and carbon atoms, hydrogen atoms can form OH bonds with oxygen atoms, and can also form hydrogen bonds with the transparent conductive film layer 70; carbon atoms can connect the Si-C bonds in the second doped amorphous silicon layer 62 and oxygen atoms to form CO bonds, and oxygen atoms can further form MO covalent bonds with metal sites in the transparent conductive film layer 70. These three atoms together construct a continuous interfacial bonding system, significantly improving the bonding strength between the two layers and avoiding defects such as delamination and voids at the interface. Furthermore, hydrogen atoms can passivate the silicon dangling bonds of the second doped amorphous silicon layer 62, oxygen atoms fill the oxygen vacancy defects of the transparent conductive film layer 70, and carbon atoms alleviate the lattice mismatch stress of the two materials. The three simultaneously eliminate recombination centers at the interface from different dimensions, significantly reducing the interface defect state density and reducing the nonradiative recombination loss of charge carriers.

[0041] Based on the structure provided in any of the above embodiments, a second structure for the isolation region 13 is provided, such as Figure 1 and Figure 2 As shown, the isolation region 13 may include a first isolation region 131 near the first conductive region 11 and a second isolation region 132 near the second conductive region 12; the first isolation region 131 and the second isolation region 132 are side by side and adjacent. More specifically, the tunneling oxide layer 20 and the doped microcrystalline silicon layer 30 extend to the first isolation region 131; the intrinsic amorphous silicon layer 50 and the doped amorphous silicon layer 60 extend to the first isolation region 131 and the second isolation region 132, wherein the portion of the intrinsic amorphous silicon layer 50 extending to the second isolation region 132 is in contact with the crystalline silicon substrate 10, and the portion of the intrinsic amorphous silicon layer 50 extending to the first isolation region 131 is located outside the doped microcrystalline silicon layer 30. This ensures that the doped microcrystalline silicon layer 30 and the doped amorphous silicon layer 60 are electrically isolated in the isolation region 13, while also ensuring electrical isolation between the transparent conductive film layer 70 corresponding to the first conductive region 11 and the transparent conductive film layer 70 corresponding to the second conductive region 12, and effectively reduces leakage current in the isolation region 13.

[0042] In addition, by designing the first isolation region 131 and the second isolation region 132, the isolation effect of the isolation region 13 can be effectively improved, and the difficulty of the process operation can be reduced when removing the transparent conductive film layer 70 corresponding to the isolation region 13 or the second isolation region 132.

[0043] Preferably, the isolation region 13 includes a first isolation region 131 near the first conductive region 11 and a second isolation region 132 near the second conductive region 12, which cooperate with the doped amorphous silicon layer 60, including the first doped amorphous silicon layer 61 and the second doped amorphous silicon layer 62, as follows: Figure 1 and Figure 2 As shown, the second doped amorphous silicon layer 62 does not cover the second isolation region 132, which can effectively improve the isolation effect of the isolation region 13 and reduce the leakage risk of the isolation region 13.

[0044] The width of the first isolation region 131 is 50μm to 150μm. For example, the width of the first isolation region 131 can be 50μm, 80μm, 100μm, 120μm or 150μm, etc. By controlling the width of the first isolation region 131, the process operability can be improved, and the effective electrical isolation between the first conductive region 11 and the second conductive region 12 can be ensured.

[0045] The width of the second isolation region 132 is 60μm to 200μm. For example, the width of the second isolation region 132 can be 60μm, 80μm, 100μm, 120μm, 150μm, 180μm or 200μm, etc. By controlling the width of the second isolation region 132, it can be ensured that the transparent conductive film layer 70 corresponding to the second isolation region 132 can be removed accurately, reducing the difficulty of process operation.

[0046] The back side of the crystalline silicon substrate 10 corresponding to the portion of the second isolation region 132 close to the first isolation region 131 is located on the same plane as the back side of the crystalline silicon substrate 10 corresponding to the first isolation region 131. This makes the isolation region 13 form a stepped structure, which can not only form lateral electrical isolation in the horizontal direction, but also form longitudinal electrical isolation in the thickness direction of the back contact solar cell, greatly reducing the risk of leakage.

[0047] Furthermore, embodiments of the present invention provide a method for fabricating a back-contact solar cell. More specifically, this method is used to fabricate the back-contact solar cell provided in any of the above embodiments. Figure 3 As shown, the fabrication method of this back-contact solar cell may include the following steps: Step S301: Provide a crystalline silicon substrate 10, wherein the back side of the crystalline silicon substrate 10 is divided into alternating initial first conductive regions 11' and initial second conductive regions 12', and an initial isolation region 13' disposed between adjacent initial first conductive regions 11' and initial second conductive regions 12'.

[0048] The crystalline silicon substrate 10 can be an N-type crystalline silicon substrate or a P-type crystalline silicon substrate. Preferably, the crystalline silicon substrate 10 is an N-type crystalline silicon substrate.

[0049] It is worth noting that the back side of the crystalline silicon substrate 10 itself does not have an initial first conductive region 11', an initial second conductive region 12', and an initial isolation region 13'. Instead, the automated equipment used in the back contact solar cell fabrication process divides the back side of the crystalline silicon substrate 10 according to the size of the crystalline silicon substrate 10 and the width of the first conductive region 11, the second conductive region 12, and the isolation region 13 of the final fabricated back contact solar cell. The back side of the crystalline silicon substrate 10 itself does not have partitions.

[0050] Furthermore, the first conductive region 11, the second conductive region 12, and the isolation region 13 described below are determined by the various functional films (tunneling oxide layer 20, doped microcrystalline silicon layer 30, intrinsic amorphous silicon layer 50, and doped amorphous silicon layer 60, etc.) located on the back side of the crystalline silicon substrate 10, as well as the initial first conductive region 11', the initial second conductive region 12', and the initial isolation region 13', before these functional films are applied.

[0051] Step S302: Based on the initial first conductive region 11', a first conductive region 11 is formed, the first conductive region 11 includes a tunneling oxide layer 20 and a doped microcrystalline silicon layer 30 stacked from the inside to the outside; based on the initial second conductive region 12', a second conductive region 12 is formed, the second conductive region 12 includes an intrinsic amorphous silicon layer 50 and a doped amorphous silicon layer 60 stacked from the inside to the outside, and an isolation region 13 is formed between the first conductive region 11 and the second conductive region 12 based on the initial isolation region 13', wherein the conductivity type of the doped microcrystalline silicon layer 30 is opposite to the conductivity type of the doped amorphous silicon layer 60.

[0052] It should be noted that the first conductive region 11 can be consistent with the initial first conductive region 11', and the first conductive region 11 can also be a part of the initial first conductive region 11' (such as the middle region of the initial first conductive region 11'); the second conductive region 12 can be consistent with the initial second conductive region 12', and the second conductive region 12 can also be a part of the initial first conductive region 11' (such as the middle region of the initial first conductive region 11'); the isolation region 13 can be consistent with the initial isolation region 13', and the isolation region 13 can also be a combination of the edge regions of the initial isolation region 13' and the initial first conductive region 11'; the isolation region 13 can also be a combination of the edge regions of the initial isolation region 13' and the initial second conductive region 12'; the isolation region 13 can also be a combination of the edge regions of the initial isolation region 13', the initial second conductive region 12', and the initial first conductive region 11'.

[0053] In this step S302, the tunneling oxide layer 20 and the doped microcrystalline silicon layer 30 formed can extend to part of the isolation region 13, in addition to being located in the first conductive region 11.

[0054] In this step S303, the intrinsic amorphous silicon layer 50 and the doped amorphous silicon layer 60 formed can extend to part of the isolation region 13, in addition to being located in the second conductive region 12.

[0055] The above-described preparation method combines the doped microcrystalline silicon layer 30 formed in the first conductive region 11 with the doped amorphous silicon layer 60 formed in the second conductive region 12, so that the doping concentration of the first conductive region 11 matches the doping concentration of the second conductive region 12. This effectively balances the doping concentration between the first conductive region 11 and the second conductive region 12, which have opposite conductivity types on the back side of the back contact solar cell, and reduces the difference in doping concentration between the first conductive region 11 and the second conductive region 12. This reduces the recombination and lateral transport of hole carriers at the edge of the conductive region, thereby effectively reducing the lateral carrier transport loss at the edge of the conductive region and improving the photoelectric conversion efficiency of the back contact solar cell.

[0056] Furthermore, based on the initial first conductive region 11', the initial second conductive region 12', and the initial isolation region 13', the first conductive region 11, the second conductive region 12, and the isolation region 13 formed can more accurately control the width of the first conductive region 11, the second conductive region 12, and the isolation region 13 during the automated production of back contact solar cells, thereby ensuring the consistency of automated production of back contact solar cells and reducing the difficulty of controlling the size of the first conductive region 11, the second conductive region 12, and the isolation region 13.

[0057] The following details step S302, which involves constructing the first conductive region 11, the second conductive region 12, and the isolation region 13 for a back-contact solar cell based on the initial first conductive region 11', the initial second conductive region 12', the initial isolation region 13', the formed tunneling oxide layer 20, the doped microcrystalline silicon layer 30, the intrinsic amorphous silicon layer 50, and the doped amorphous silicon layer 60. Step S302 can have two specific implementation schemes.

[0058] Specifically, the first specific implementation of step S302 may include: steps S3021-1 to S3025-1, and the structural changes corresponding to the first specific implementation of step S302 are as follows: Figure 4 As shown.

[0059] Step S3021-1: A tunneling oxide layer 20, a first doped microcrystalline silicon layer 31, and a second doped microcrystalline silicon layer 32 are sequentially stacked from the inside to the outside on the back side of the crystalline silicon substrate 10. The first doped microcrystalline silicon layer 31 includes a uniformly distributed first doped atom, the second doped microcrystalline silicon layer 32 includes a uniformly distributed first doped atom, and the doping concentration of the second doped microcrystalline silicon layer 32 is greater than the doping concentration of the first doped microcrystalline silicon layer 31.

[0060] Step S3022-1: A protective layer 40 is formed on the outside of the second doped microcrystalline silicon layer 32.

[0061] Step S3023-1: Remove the protective layer 40 corresponding to the initial second conductive region 12' by laser etching.

[0062] Step S3024-1: Use an alkaline solution to remove the second doped microcrystalline silicon layer 32 and the first doped microcrystalline silicon layer 31 corresponding to the initial second conductive region 12, and remove the second doped microcrystalline silicon layer 32 and the first doped microcrystalline silicon layer 31 corresponding to the first edge region of the initial isolation region 13', and simultaneously remove the protective layer 40 corresponding to the first edge region, wherein the first edge region is close to the initial second conductive region.

[0063] It should be noted that the removal of the second doped microcrystalline silicon layer 32 and the first doped microcrystalline silicon layer 31 corresponding to the first edge region of the initial isolation region 13' is formed by etching the first edge region from the side with an alkaline solution. After removing the second doped microcrystalline silicon layer 32 and the first doped microcrystalline silicon layer 31 of the first edge region, the protective layer 40 corresponding to the first edge region can be removed simultaneously.

[0064] Step S3025-1: Use an acid solution to remove the tunneling oxide layer 20 corresponding to the initial second conductive region 12 and the tunneling oxide layer 20 corresponding to the first edge region, and remove the remaining protective layer 40.

[0065] This step can be performed using an HF solution for cleaning. Alternatively, step S3024-1 can also use an alkaline solution containing a texturing additive, which is a commonly used texturing additive. By using an alkaline solution containing a texturing additive, the tunneling oxide layer 20 corresponding to the initial second conductive region 12 can also be removed simultaneously in step S3024-1. Based on this, step S3025-1 uses an HF solution to remove the tunneling oxide layer 20 corresponding to the first edge region and removes the remaining protective layer 40.

[0066] In the first specific implementation of step S302 above, the first conductive region 11 is consistent with the initial first conductive region 11', the second conductive region 12 is the middle region of the initial second conductive region 12', and the isolation region 13 is composed of the edge regions of the initial isolation region 13' and the initial second conductive region 12'.

[0067] Additionally, a second specific implementation of step S302 may include steps S3021-2 to S3025-2, and the structural changes corresponding to this second specific implementation of step S302 are as follows: Figure 5 As shown.

[0068] Step S3021-2: A tunneling oxide layer 20, a first doped microcrystalline silicon layer 31, and a second doped microcrystalline silicon layer 32 are sequentially stacked from the inside to the outside on the back side of the crystalline silicon substrate 10.

[0069] Step S3022-2: A protective layer 40 is formed on the outside of the second doped microcrystalline silicon layer 32.

[0070] Step S3023-2: Use laser etching to remove the protective layer 40 corresponding to the initial second conductive region 12 and the initial isolation region 13'.

[0071] Step S3024-2: Use an alkaline solution to remove the second doped microcrystalline silicon layer 32, the first doped microcrystalline silicon layer 31, and the tunneling oxide layer 20 corresponding to the initial second conductive region 12 and the initial isolation region 13', and remove the second doped microcrystalline silicon layer 32 and the first doped microcrystalline silicon layer 31 corresponding to the second edge region of the initial first conductive region 11', and simultaneously remove the protective layer 40 corresponding to the second edge region, which is close to the initial isolation region 13'.

[0072] It should be noted that the removal of the second doped microcrystalline silicon layer 32 and the first doped microcrystalline silicon layer 31 corresponding to the second edge region of the initial first conductive region 11' is formed by etching the second edge region from the side with an alkaline solution. After removing the second doped microcrystalline silicon layer 32 and the first doped microcrystalline silicon layer 31 of the second edge region, the protective layer 40 corresponding to the second edge region can be removed simultaneously.

[0073] Step S3025-2: Use an acid solution to remove the tunneling oxide layer 20 corresponding to the initial second conductive region 12' and the initial isolation region 13', the tunneling oxide layer 20 corresponding to the second edge region, and remove the remaining protective layer 40.

[0074] Step S3025-2 can be cleaned using an HF solution. Alternatively, step S3024-2 can also use an alkaline solution containing a texturing additive, which is a commonly used texturing additive. By using an alkaline solution containing a texturing additive, step S3024-2 can also simultaneously remove the tunneling oxide layer 20 corresponding to the initial second conductive region 12' and the initial isolation region 13'. Based on this, step S3025-2 uses an HF solution to remove the tunneling oxide layer 20 corresponding to the second edge region and remove the remaining protective layer 40.

[0075] In the second specific implementation of step S302 above, the second conductive region 12 is consistent with the initial second conductive region 12', the first conductive region 11 is the middle region of the initial first conductive region 11', and the isolation region 13 is composed of the edge regions of the initial isolation region 13' and the initial first conductive region 11'.

[0076] Regardless of whether it's the first or second specific implementation of step S302, neither will form a doped silicon glass layer outside the second doped microcrystalline silicon layer 32, thus omitting the process of removing the doped silicon glass layer. Furthermore, the above-described processing steps can reduce damage to the remaining functional layers.

[0077] In one embodiment of the present invention, whether in step S3021-1 or step S3021-2, the tunneling oxide layer 20 is prepared by furnace tube thermal oxidation, which can ensure the passivation and tunneling effects of the tunneling oxide layer 20. The parameters used in the furnace tube thermal oxidation method for preparing the tunneling oxide layer 20 can be directly implemented using existing technologies and are not limited herein. It is worth noting that during the preparation of the tunneling oxide layer 20 by furnace tube thermal oxidation, a wrap-around coating corresponding to the tunneling oxide layer 20 is also formed on the front side of the crystalline silicon substrate 10. This wrap-around coating corresponding to the tunneling oxide layer 20 can be removed simultaneously in step S3025-1 or step S3025-2 without adding any additional processing steps.

[0078] In one embodiment of the present invention, both step S3021-1 and step S3021-2 may further include: under the conditions of reaction precursors H2, SiH4, and PH3, plasma chemical vapor deposition of a first doped microcrystalline silicon layer 31 and a second doped microcrystalline silicon layer 32. Preferably, the conditions for plasma chemical vapor deposition of the first doped microcrystalline silicon layer 31 in step S3021-1 or step S3021-2 may include: a flow rate ratio of H2, SiH4, and PH3 of 7:(2~5):(0.5~2), and a power of 15 mW / cm³. 2 ~35mW / cm 2 The pressure is 40Pa~80Pa. For example, the flow ratio of H2, SiH4, and PH3 can be 7:2:0.5, 7:3:1, or 7:5:2, etc.; the power can be 15mW / cm. 2 20mW / cm 2 25mW / cm 2 30mW / cm 2 Or 35mW / cm 2 The pressure can be 40Pa, 50Pa, 60Pa, 70Pa or 80Pa, etc.

[0079] In addition, the conditions for plasma chemical vapor deposition of the second doped microcrystalline silicon layer 32 include: a flow ratio of H2, SiH4, and PH3 of 7:(2~5):(2.5~5), and a power of 20 mW / cm³. 2 ~40mW / cm 2The pressure is 60Pa~150Pa. For example, the flow ratio of H2, SiH4, and PH3 can be 7:2:2.5, 7:3:3, 7:4:3, or 7:5:5, etc.; the power can be 20mW / cm. 2 25mW / cm 2 30mW / cm 2 35mW / cm 2 Or 40mW / cm 2 The pressure can be 60Pa, 70Pa, 80Pa, 100Pa, 120Pa, 130Pa or 150Pa, etc.

[0080] By selecting plasma chemical vapor deposition to form the first doped microcrystalline silicon layer 31 and the second doped microcrystalline silicon layer 32, it is possible to form the first doped microcrystalline silicon layer 31 and the second doped microcrystalline silicon layer 32 in one step. That is, doping is achieved simultaneously during the formation of microcrystalline silicon, rather than forming microcrystalline silicon first and then doping. This makes the first doped microcrystalline silicon layer 31 and the second doped microcrystalline silicon layer 32 more uniformly doped.

[0081] In addition, by adjusting the parameters of the plasma chemical vapor deposition, the thickness, doping concentration and doping uniformity of the first doped microcrystalline silicon layer 31 and the second doped microcrystalline silicon layer 32 can be effectively controlled, and the doping concentration of the second doped microcrystalline silicon layer 32 can be ensured to be greater than the doping concentration of the first doped microcrystalline silicon layer 31.

[0082] It should be noted that the above-mentioned selection of plasma chemical vapor deposition to form the first doped microcrystalline silicon layer 31 and the second doped microcrystalline silicon layer 32 will not form a coating layer on the front side of the crystalline silicon substrate 10, making the back contact solar cell fabrication process relatively simple.

[0083] In step S3022-1 or step S3022-2, a protective layer 40 is deposited using plasma chemical vapor deposition on the reaction precursor SiH4 and ammonia. This protective layer 40 is silicon nitride, which has good density. Silicon nitride can effectively block alkaline solution etching and can be removed by HF solution in subsequent processes, avoiding the need for laser etching. This ensures the integrity of the second doped microcrystalline silicon layer 32 in the first conductive region 11, thereby ensuring reliable contact between the second doped microcrystalline silicon layer 32 and the transparent conductive film layer 70 and reducing contact resistance.

[0084] The mass fraction of the alkaline solution used in step S3024-1 or step S3024-2 is 60% to 70%. For example, the mass fraction of the alkaline solution can be 60%, 65%, 66%, 68%, or 70%, etc. By controlling the mass fraction of the alkaline solution, the cleaning width of step S3024-1 or step S3024-2 can be effectively controlled. In conjunction with the previous steps, step S3024-1 can clean not only the initial second conductive region 12', but also the first edge region of the initial isolation region 13'. Similarly, step S3024-2 can clean not only the initial second conductive region 12' and the initial isolation region 13', but also the second edge region of the initial first conductive region 11', ensuring that the first or second edge region is cleaned thoroughly and reducing impurity residue.

[0085] Optionally, step S3024-1 or step S3024-2 further includes: simultaneously texturing the exposed portion of the back side of the crystalline silicon substrate 10. It is understood that for step S3024-1, texturing may be performed on the first edge regions of the initial second conductive region 12' and the initial isolation region 13'. For step S3024-2, texturing may be performed on the second edge regions of the initial second conductive region 12', the initial isolation region 13', and the initial first conductive region 11'.

[0086] In this embodiment of the invention, the HF solution used in step S3025-1 or step S3025-2 has a mass fraction of 14% to 20%. For example, the mass fraction of the HF solution can be 14%, 15%, 17%, 18%, or 20%, etc., which can ensure that the remaining protective layer 40 can be cleaned and avoid residue.

[0087] Furthermore, regardless of whether it is the first or the second specific implementation of step S302 above, step S302 may also include: Step S3026: An intrinsic amorphous silicon layer 50, a first doped amorphous silicon layer 61, and a second doped amorphous silicon layer 62 are sequentially stacked from the inside to the outside on the exposed back side of the crystalline silicon substrate 10 and the outside of the doped microcrystalline silicon layer 30. The second doped atoms in the first doped amorphous silicon layer 61 are uniformly distributed, and the second doped atoms in the second doped amorphous silicon layer 62 are uniformly distributed. The doping concentration of the second doped amorphous silicon layer 62 is greater than the doping concentration of the first doped amorphous silicon layer 61.

[0088] Understandably, in the first specific embodiment of step S302 above, the exposed back surface of the crystalline silicon substrate 10 is the first edge region of the initial second conductive region 12' and the initial isolation region 13'. In the second specific embodiment of step S302 above, the exposed back surface of the crystalline silicon substrate 10 is the second edge region of the initial second conductive region 12', the initial isolation region 13', and the initial first conductive region 11'.

[0089] Step S3027: Use a laser to remove at least the second doped amorphous silicon layer 62, the first doped amorphous silicon layer 61, and the intrinsic amorphous silicon layer 50 corresponding to the initial first conductive region 11' or the intermediate region corresponding to the initial first conductive region 11', to form the first conductive region 11.

[0090] Regarding the first specific implementation scheme of step S302 above, the structural changes of steps S3026 and S3027 are as follows: Figure 4 As shown, for the second specific implementation of step S302 above, the structural changes of steps S3026 and S3027 are as follows: Figure 5 As shown.

[0091] In step S3027, during the removal of the second doped amorphous silicon layer 62, the first doped amorphous silicon layer 61, and the intrinsic amorphous silicon layer 50 corresponding to the initial first conductive region 11' or the intermediate region corresponding to the initial first conductive region 11' using a laser, since the laser-treated area contains the second doped microcrystalline silicon layer 32 and the first doped microcrystalline silicon layer 31, the laser can thin the second doped microcrystalline silicon layer 32, ensuring the reliability of the contact between the second doped microcrystalline silicon layer 32 and the transparent conductive film layer 70 and a low contact resistance, while also ensuring the passivation effect and carrier transport capability of the doped microcrystalline silicon layer 30.

[0092] Optionally, step S3026 may include: depositing an intrinsic amorphous silicon layer 50 using plasma chemical vapor deposition (PCVD) under the conditions of reaction precursors H2 and SiH4. By selecting PCVD, the uniformity of the intrinsic amorphous silicon layer 50 can be ensured, thereby improving the passivation effect of the intrinsic amorphous silicon layer 50. Preferably, the conditions for PCVD of the intrinsic amorphous silicon layer 50 in step S3026 include: a flow ratio of H2 to SiH4 of (8~12):1, and a power of 10 mW / cm³. 2 ~25mW / cm 2 The pressure is 40Pa~150Pa; for example, the flow ratio of H2 to SiH4 can be 8:1, 9:1, 10:1, 11:1 or 12:1, etc.; the power can be 10mW / cm 2 15mW / cm 2 20mW / cm 2 Or 25mW / cm 2 The pressure can be 40Pa, 50Pa, 70Pa, 80Pa, 100Pa, 120Pa, 130Pa or 150Pa, etc.

[0093] Further, step S3026 may also include: depositing a first doped amorphous silicon layer 61 using plasma chemical vapor deposition under the conditions of reaction precursors H2, SiH4, and B2H6; optionally, the conditions for plasma chemical vapor deposition of the first doped amorphous silicon layer 61 in step S3026 include: a flow rate ratio of H2, SiH4, and B2H6 of (6~10):(2~5):1, and a power of 10 mW / cm³. 2 ~25mW / cm 2 The pressure is 40Pa~150Pa. For example, the flow ratio of H2, SiH4, and B2H6 can be 6:2:1, 10:2:1, 8:3:1, 9:4:1, or 10:5:1, etc.; the power can be 10mW / cm. 2 15mW / cm 2 20mW / cm 2 Or 25mW / cm 2 The pressure can be 40Pa, 50Pa, 70Pa, 80Pa, 100Pa, 120Pa, 130Pa or 150Pa, etc.

[0094] In addition, step S3026 further includes: depositing a second doped amorphous silicon layer 62 using plasma chemical vapor deposition under the conditions of reaction precursors H2, SiH4, B2H6, and CO2; optionally, the conditions for plasma chemical vapor deposition of the second doped amorphous silicon layer 62 in step S3026 include: a flow rate ratio of H2, SiH4, B2H6, and CO2 of (6~10):(2~4):(2~4):1, and a power of 15 mW / cm³. 2 ~30mW / cm 2 The pressure is 40Pa~150Pa. For example, the flow ratio of H2, SiH4, B2H6 and CO2 can be 6:2:2:1, 7:3:3:1, 8:3:3:1 or 10:4:4:1; the power can be 15mW / cm. 2 20mW / cm 2 Or 25mW / cm 2 The pressure can be 40Pa, 50Pa, 70Pa, 80Pa, 100Pa, 120Pa, 130Pa or 150Pa, etc.

[0095] By selecting plasma chemical vapor deposition to form the first doped amorphous silicon layer 61 and the second doped amorphous silicon layer 62, it is possible to form the first doped amorphous silicon layer 61 and the second doped amorphous silicon layer 62 in one step. That is, doping is achieved simultaneously during the formation of intrinsic amorphous silicon, rather than forming intrinsic amorphous silicon first and then doping. This makes the first doped amorphous silicon layer 61 and the second doped amorphous silicon layer 62 more uniformly doped.

[0096] In addition, by adjusting the parameters of the plasma chemical vapor deposition, the thickness, doping concentration and doping uniformity of the first doped amorphous silicon layer 61 and the second doped amorphous silicon layer 62 can be effectively controlled, and the doping concentration of the second doped amorphous silicon layer 62 can be guaranteed to be greater than that of the first doped amorphous silicon layer 61.

[0097] It should be noted that the above-mentioned selection of plasma chemical vapor deposition to form the first doped amorphous silicon layer 61 and the second doped amorphous silicon layer 62 avoids the formation of a coating around the front side of the crystalline silicon substrate 10, thus simplifying the back contact solar cell fabrication process. Furthermore, the first doped amorphous silicon layer 61 and the second doped amorphous silicon layer 62 can be fabricated in the same equipment as the first doped microcrystalline silicon layer 31 and the second doped microcrystalline silicon layer 32, reducing equipment investment costs and consequently lowering the cost of the back contact solar cell.

[0098] Furthermore, for the process of preparing the first doped microcrystalline silicon layer 31, the second doped microcrystalline silicon layer 32, the protective layer 40, the first doped amorphous silicon layer 61, and the second doped amorphous silicon layer 62 by plasma chemical vapor deposition, the required deposition temperature can be adjusted within the range of 120℃ to 250℃. For example, the deposition temperature can be 120℃, 150℃, 180℃, 200℃, 22℃, or 250℃. It should be noted that the deposition temperatures corresponding to the first doped microcrystalline silicon layer 31, the second doped microcrystalline silicon layer 32, the protective layer 40, the first doped amorphous silicon layer 61, and the second doped amorphous silicon layer 62 can be the same or different. By adjusting the deposition temperature within the range of 120℃ to 250℃, the formation process of the protective layer 40 can be prevented from affecting the doping concentration of the first doped microcrystalline silicon layer 31 and the second doped microcrystalline silicon layer 32. This deposition temperature, in conjunction with the protective layer 40, can also prevent the formation process of the first doped amorphous silicon layer 61 and the second doped amorphous silicon layer 62 from affecting the doping concentration of the first doped microcrystalline silicon layer 31 and the second doped microcrystalline silicon layer 32.

[0099] Further, based on any of the above embodiments, step S302 further includes: step S3028: forming a transparent conductive film layer 70 on the outside of the doped microcrystalline silicon layer 30 of the first conductive region 11, and on the outside of the doped amorphous silicon layer 60 of the initial second conductive region 12' and the initial isolation region 13', removing at least the transparent conductive film layer 70 corresponding to the edge region of the initial second conductive region 12', forming the second conductive region 12 and the isolation region 13, and forming metal electrodes 80 on the outside of the transparent conductive film layer 70 corresponding to the first conductive region 11 and the outside of the transparent conductive film layer 70 corresponding to the second conductive region 12, respectively. The structural change corresponding to this step S3028 is as follows: Figure 4 and Figure 5 As shown.

[0100] It is worth noting that step S3028, which removes the transparent conductive film layer 70, can be as follows: Figure 4 As shown, the transparent conductive film layer 70 corresponding to the isolation region 13 is removed. Alternatively, only a portion of the transparent conductive film layer 70 in the isolation region 13 may be removed (e.g., Figure 5 As shown, the transparent conductive film layer 70 corresponding to the initial isolation region 13' is removed, while the transparent conductive film layer 70 remains in the remaining area of ​​the isolation region 13 (i.e., the transparent conductive film layer 70 corresponding to the second insulating region of the initial first conductive region 11').

[0101] Additionally, step S302 may further include forming a passivation antireflection layer 90 on the front side of the crystalline silicon substrate 10. It is worth noting that the formation of the passivation antireflection layer 90 can be performed after step S3025-1 and before step S3026, or after step S3025-2 and before step S3026.

[0102] It is worth noting that, compared to the high-temperature control of the high-temperature annealing process included in the existing solar cell fabrication process, the high-temperature annealing process requires more precise control to ensure the activation of doped atoms and to achieve the required high doping concentration in the doped polycrystalline silicon layer. In the technical solution provided by the embodiments of the present invention, plasma chemical vapor deposition is completed at a lower temperature (120℃~250℃). The lower temperature and parameters such as gas flow rate, power, and pressure in the deposition process are easier to control. Therefore, compared to the high doping concentration of doped polycrystalline silicon in existing solar cells, the low doping concentration of the first doped microcrystalline silicon layer 31 and the second doped microcrystalline silicon layer 32 formed in this application are easier to control.

[0103] The technical solutions provided by the embodiments of the present invention will be described in detail below with an example and a comparative example.

[0104] Example

[0105] Step A1: Select an N-type crystalline silicon substrate. On the back side of the N-type crystalline silicon substrate, alternately arranged initial first conductive regions and initial second conductive regions are defined, as well as initial isolation regions disposed between adjacent initial first conductive regions and initial second conductive regions.

[0106] Step B1, Polishing: Clean the N-type silicon substrate with a 25% sodium hydroxide alkaline solution to form a double-sided polished N-type silicon substrate.

[0107] Step C1: Prepare a SiO2 tunneling oxide layer. A tunneling oxide layer with a thickness of 1 nm is prepared on the entire surface of an N-type crystalline silicon substrate using a furnace tube thermal oxidation method.

[0108] Step D1: Prepare an N-type doped microcrystalline layer using a low-temperature enhanced plasma chemical vapor deposition (PECVD) system at a power of 20 mW / cm². 2Under conditions of a pressure of 50 Pa, a flow ratio of H2, SiH4, and PH3 gases of 7:3:1, and a deposition temperature of 180 °C, a first N-type doped microcrystalline silicon layer was deposited on the tunneling oxide layer on the back side. Then, the power was adjusted to 25 mW / cm². 2 Under the conditions of a pressure of 50 Pa, a flow ratio of H2, SiH4 and PH3 gases of 7:3:3 and a deposition temperature of 180 °C, a second N-type doped microcrystalline silicon layer is deposited on the first N-type doped microcrystalline silicon layer. Then, a silicon nitride protective layer is deposited on the second N-type doped microcrystalline silicon layer using a PECVD device.

[0109] Step E1: First laser mold opening, using a 532nm laser to remove the silicon nitride protective layer of the initial second conductive region.

[0110] Step F1: Texturing. First, use a 16% HF solution to clean and remove the tunneling oxide layer on the front side of the N-type silicon substrate. Then, use a 66% NaOH alkaline solution containing texturing additives to texturize the second N-type doped microcrystalline silicon layer and the first N-type doped microcrystalline silicon layer in the area of ​​the N-type silicon substrate not covered by the silicon nitride protective layer, as well as the second N-type doped microcrystalline silicon layer and the first N-type doped microcrystalline silicon layer in the first edge region of the initial isolation area. Use a 16% HF acid solution to clean the texturized silicon surface and simultaneously remove the exposed tunneling oxide layer and the remaining silicon nitride protective layer in the corresponding area.

[0111] Step G1: Prepare a front passivation layer. Use a PECVD device to prepare a 3nm intrinsic amorphous silicon passivation layer, and then deposit a 70nm silicon nitride antireflection layer on the surface of the intrinsic amorphous silicon passivation layer.

[0112] Step H1: Use a PECVD device with a power of 15mW / cm². 2 Under conditions of 60 Pa pressure and a flow ratio of H2 to SiH4 gas of the reaction precursors of 10:1, an intrinsic hydrogenated amorphous silicon layer was deposited on the back side of an N-type crystalline silicon substrate, with the power adjusted to 15 mW / cm². 2 Under conditions of a pressure of 60 Pa and a flow ratio of H2, SiH4, and B2H6 gases of 8:3:1, a first P-type doped amorphous silicon layer was deposited on the intrinsic hydrogenated amorphous silicon layer, and the power was further adjusted to 20 mW / cm². 2 Under the conditions of a pressure of 70 Pa, a flow ratio of H2, SiH4, B2H6 and CO2 of 8:3:3:1 and a deposition temperature of 180 °C, a second P-type doped amorphous silicon layer is deposited on the first P-type doped amorphous silicon layer. The thickness of the intrinsic hydrogenated silicon-containing thin film is 3 nm, the thickness of the first P-type doped amorphous silicon layer is 30 nm, and the thickness of the second P-type doped amorphous silicon layer is 5 nm.

[0113] Step I1: Use a 532nm laser to remove the intrinsic hydrogenated amorphous silicon layer, the first P-type doped amorphous silicon layer, and the second P-type doped amorphous silicon layer in the first conductive region.

[0114] Step J1: Prepare a transparent conductive film layer (TCO) by depositing a TCO film layer on the back side of an N-type crystalline silicon substrate using a PVD device.

[0115] Step K1: Etching and printing. Using the designed and specified stencil, the TCO film layer of the initial isolation region and the second P-type doped amorphous silicon layer are etched away with etching paste to obtain the first conductive region, the second conductive region and the isolation region.

[0116] Step L1: Prepare the electrode by applying conductive silver paste to the first and second conductive regions respectively, and then drying and sintering it.

[0117] Comparative Example

[0118] Steps A2 to C1 are the same as in Example 1.

[0119] Step D2: Prepare a p-poly doped layer. Polysilicon is deposited on the surface of the tunneling oxide layer using low-temperature plasma chemical vapor deposition (LPCVD). Then, phosphorus diffusion is performed on the polysilicon using a furnace tube diffusion method at a diffusion temperature of 880℃, resulting in an N-type polycrystalline silicon doped layer with a thickness of 60 nm. Simultaneously, a phosphosilicate glass (PSG) layer is formed on the surface of the N-type doped polycrystalline silicon layer. A wraparound coating corresponding to the N-type doped polycrystalline silicon layer and a wraparound coating corresponding to the PSG layer are formed on the front side of the N-type crystalline silicon substrate.

[0120] Step E: Remove PSG. Use 5% HF to clean and remove the coating on the front side corresponding to the PSG layer and the PSG layer on the back side.

[0121] Step F, Preparation of silicon nitride protective layer: Using PECVD, at a deposition temperature of 450 degrees Celsius, and under the conditions of silane and ammonia as reaction precursors, a silicon nitride film with a thickness of 100 nm is deposited on the N-type doped polycrystalline silicon layer on the back side of the N-type crystalline silicon substrate. This film layer uses silane as the reaction gas.

[0122] Step G: First laser mold opening, using a 532nm laser to etch the P-type region on the back side of the N-type crystalline silicon substrate to remove the silicon nitride protective layer of the P-type region.

[0123] Step H, texturing: Use a 25% KOH solution to remove the wrap-around coating corresponding to the N-type doped polysilicon layer on the front side of the N-type crystalline silicon substrate and the exposed N-type doped polysilicon layer in the P-type region. Then use an HF solution to clean and remove the exposed tunneling oxide layer and the remaining silicon nitride protective layer in the corresponding areas.

[0124] Step 1: Prepare the front passivation layer. Use an ALD device to prepare a 1-5 nm aluminum oxide passivation layer on the front side of the N-type crystalline silicon substrate, and then deposit a 70 nm silicon nitride film on the surface of the aluminum oxide passivation layer.

[0125] Step J: Deposit a hydrogenated amorphous silicon layer and a P-type doped microcrystalline silicon layer on the back side using a PECVD device. The thickness of the intrinsic hydrogenated silicon thin film is 5 nm, and the thickness of the P-type doped microcrystalline layer is 30 nm.

[0126] Step K: Second laser mold opening, using a 532nm laser to remove the hydrogenated amorphous silicon layer and P-type doped microcrystalline layer on the surface of the N-type region on the back side of the N-type crystalline silicon substrate.

[0127] Steps L2 to N2 are the same as J1 to L1 in Example 1.

[0128] The short-circuit current density, open-circuit voltage, fill factor, and conversion efficiency of the batteries prepared in the above examples and comparative examples were tested using existing IV testing (current-voltage characteristic testing) methods. The test results are shown in Table 1 below.

[0129] Table 1

[0130] As can be seen from Table 1, compared with the back-contact heterojunction solar cell in the comparative example, the back-contact solar cell provided in the embodiments of the present invention can improve the short-circuit current density, open-circuit voltage, fill factor and conversion efficiency to varying degrees, indicating that the back-contact solar cell provided in the embodiments of the present invention can reduce lateral carrier transport losses.

[0131] The above steps are provided only to help understand the method, structure, and core ideas of this invention. Those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the scope of protection of the claims.

Claims

1. A back-contact solar cell, characterized in that, include: The back side includes a crystalline silicon substrate (10) with alternating first conductive regions (11) and second conductive regions (12), and an isolation region (13) is provided between adjacent first conductive regions (11) and second conductive regions (12). A tunneling oxide layer (20) and a doped microcrystalline silicon layer (30) are stacked from the inside to the outside in the first conductive region (11). An intrinsic amorphous silicon layer (50) and a doped amorphous silicon layer (60) are stacked from the inside to the outside in the second conductive region (12), wherein the conductivity type of the doped microcrystalline silicon layer (30) is opposite to that of the doped amorphous silicon layer (60).

2. The back-contact solar cell according to claim 1, characterized in that, The doping concentration on the outer side of the doped microcrystalline silicon layer (30) is greater than that on the inner side. Optionally, the doped microcrystalline silicon layer (30) comprises: A first doped microcrystalline silicon layer (31) and a second doped microcrystalline silicon layer (32) are stacked from the inside to the outside. The first doped microcrystalline silicon layer (31) includes a uniformly distributed first doped atom, and the second doped microcrystalline silicon layer (32) includes a uniformly distributed first doped atom. The doping concentration of the second doped microcrystalline silicon layer (32) is greater than that of the first doped microcrystalline silicon layer (31). Optionally, the doping concentration of the first doped microcrystalline silicon layer (31) is 1×10⁻⁶. 16 atoms / cm³ ~1×10 19 atoms / cm³; Optionally, the doping concentration of the second doped microcrystalline silicon layer (32) is 5 × 10⁻⁶. 16 atoms / cm³ ~5×10 19 atoms / cm³; Optionally, the thickness of the first doped microcrystalline silicon layer (31) is 10 nm to 100 nm, and preferably, the thickness of the first doped microcrystalline silicon layer (31) is 30 nm to 70 nm. Optionally, the thickness of the second doped microcrystalline silicon layer (32) is 1 nm to 10 nm, and preferably, the thickness of the second doped microcrystalline silicon layer (32) is 1 nm to 5 nm. Optionally, the first doped microcrystalline silicon layer (31) and the second doped microcrystalline silicon layer (32) include N-type doped atoms; Optionally, the first doped microcrystalline silicon layer (31) further includes hydrogen atoms; Optionally, the second doped microcrystalline silicon layer (32) also includes hydrogen atoms and oxygen atoms.

3. The back-contact solar cell according to claim 2, characterized in that, The doping concentration on the outer side of the doped amorphous silicon layer (60) is greater than that on the inner side; Optionally, the doped amorphous silicon layer (60) comprises: A first doped amorphous silicon layer (61) and a second doped amorphous silicon layer (62) are stacked from the inside to the outside. The second doped atoms in the first doped amorphous silicon layer (61) are uniformly distributed, and the second doped atoms in the second doped amorphous silicon layer (62) are uniformly distributed. The doping concentration of the second doped amorphous silicon layer (62) is greater than that of the first doped amorphous silicon layer (61). Optionally, the difference between the doping concentration of the first doped amorphous silicon layer (61) and the doping concentration of the first doped microcrystalline silicon layer (31) is not greater than 100 atoms / cm³. Optionally, the difference between the doping concentration of the second doped amorphous silicon layer (62) and the doping concentration of the second doped microcrystalline silicon layer (32) is not greater than 10 atoms / cm³. Optionally, the doping concentration of the first doped amorphous silicon layer (61) is 1×10⁻⁶. 16 atoms / cm³ ~1×10 19 atoms / cm³; Optionally, the doping concentration of the second doped amorphous silicon layer (62) is 5 × 10⁻⁶. 16 atoms / cm³ ~5×10 19 atoms / cm³; Optionally, the thickness of the first doped amorphous silicon layer (61) is 10 nm to 50 nm; Optionally, the thickness of the second doped amorphous silicon layer (62) is 1 nm to 10 nm; Optionally, the first doped amorphous silicon layer (61) and the second doped amorphous silicon layer (62) include P-type doped atoms as the first doping atoms; Optionally, the first doped amorphous silicon layer (61) further includes hydrogen atoms; Optionally, the second doped amorphous silicon layer (62) further includes hydrogen atoms, oxygen atoms, and carbon atoms.

4. The back-contact solar cell according to any one of claims 1 to 3, characterized in that, The isolation zone (13) includes a first isolation zone (131) near the first conductive zone (11) and a second isolation zone (132) near the second conductive zone (12). The tunneling oxide layer (20) and the doped microcrystalline silicon layer (30) extend to the first isolation region (131). The intrinsic amorphous silicon layer (50) and the doped amorphous silicon layer (60) extend to the first isolation region (131) and the second isolation region (132), wherein the portion of the intrinsic amorphous silicon layer (50) extending to the second isolation region (132) is in contact with the crystalline silicon substrate (10), and the portion of the intrinsic amorphous silicon layer (50) extending to the first isolation region (131) is located outside the doped microcrystalline silicon layer (30); optionally, the doped amorphous silicon layer (60) includes a structure of a first doped amorphous silicon layer (61) and a second doped amorphous silicon layer (62), wherein the second doped amorphous silicon layer (62) does not cover the second isolation region (132). Optionally, the width of the first isolation zone (131) is 50μm~150μm; Optionally, the width of the second isolation zone (132) is 60μm~200μm; Optionally, the back-contact solar cell further includes: a transparent conductive film layer (70) disposed on the outside of the doped microcrystalline silicon layer (30) in the first conductive region (11) and on the outside of the doped amorphous silicon layer (60) in the second conductive region (12); and a metal electrode (80) disposed on the first conductive region (11) and the second conductive region (12) and electrically connected to the transparent conductive film layer (70). Optionally, the back-contact solar cell further includes a passivation antireflection layer (90) disposed on the front side of the crystalline silicon substrate (10).

5. The back-contact solar cell according to claim 4, characterized in that, The back side of the crystalline silicon substrate (10) corresponding to the portion of the second isolation region (132) near the first isolation region (131) is on the same plane as the back side of the crystalline silicon substrate (10) corresponding to the first isolation region (131).

6. A method for preparing a back-contact solar cell according to any one of claims 1 to 5, characterized in that, include: Step 1: Provide a crystalline silicon substrate (10), wherein the back side of the crystalline silicon substrate (10) is divided into alternating initial first conductive regions (11') and initial second conductive regions (12'), and an initial isolation region (13') is disposed between adjacent initial first conductive regions (11') and initial second conductive regions (12'). Step 2: Based on the initial first conductive region (11'), a first conductive region (11) is formed, the first conductive region (11) comprising a tunneling oxide layer (20) and a doped microcrystalline silicon layer (30) stacked from the inside to the outside; based on the initial second conductive region (12'), a second conductive region (12) is formed, the second conductive region (12) comprising an intrinsic amorphous silicon layer (50) and a doped amorphous silicon layer (60) stacked from the inside to the outside, and an isolation region (13) is formed between the first conductive region (11) and the second conductive region (12) based on the initial isolation region (13'), wherein the conductivity type of the doped microcrystalline silicon layer (30) is opposite to the conductivity type of the doped amorphous silicon layer (60).

7. The preparation method according to claim 6, characterized in that, Step 2 includes: Steps 21-1 to 25-1: Step 21-1: A tunneling oxide layer (20), a first doped microcrystalline silicon layer (31), and a second doped microcrystalline silicon layer (32) are sequentially stacked from the inside to the outside on the back side of the crystalline silicon substrate (10). The first doped microcrystalline silicon layer (31) includes a uniformly distributed first doped atom, and the second doped microcrystalline silicon layer (32) includes a uniformly distributed first doped atom. The doping concentration of the second doped microcrystalline silicon layer (32) is greater than that of the first doped microcrystalline silicon layer (31). Step 22-1: Form a protective layer (40) on the outside of the second doped microcrystalline silicon layer (32); Step 23-1: Remove the protective layer (40) corresponding to the initial second conductive region (12') by laser etching. Step 24-1: Remove the second doped microcrystalline silicon layer (32) and the first doped microcrystalline silicon layer (31) corresponding to the initial second conductive region (12') using an alkaline solution, and remove the second doped microcrystalline silicon layer (32) and the first doped microcrystalline silicon layer (31) corresponding to the first edge region of the initial isolation region (13'), and simultaneously remove the protective layer (40) corresponding to the first edge region, wherein the first edge region is close to the initial second conductive region (12); and Step 25-1: Use an acid solution to remove the tunneling oxide layer (20) corresponding to the initial second conductive region (12) and the tunneling oxide layer (20) corresponding to the first edge region, and remove the remaining protective layer (40).

8. The preparation method according to claim 6, characterized in that, Step 2 includes: Steps 21-2 to 25-2: Step 21-2: A tunneling oxide layer (20), a first doped microcrystalline silicon layer (31), and a second doped microcrystalline silicon layer (32) are sequentially stacked from the inside to the outside on the back side of the crystalline silicon substrate (10). Step 22-2: Form a protective layer (40) on the outside of the second doped microcrystalline silicon layer (32); Step 23-2: Remove the protective layer (40) corresponding to the initial second conductive region (12') and the initial isolation region (13') by laser etching. Step 24-2: Remove the second doped microcrystalline silicon layer (32) and the first doped microcrystalline silicon layer (31) corresponding to the initial second conductive region (12') and the initial isolation region (13') using an alkaline solution, and remove the second doped microcrystalline silicon layer (32) and the first doped microcrystalline silicon layer (31) corresponding to the second edge region of the initial first conductive region (11'), and simultaneously remove the protective layer (40) corresponding to the second edge region, which is close to the initial isolation region (13'); and Step 25-2: Use an acid solution to remove the tunneling oxide layer (20) corresponding to the initial second conductive region (12') and the initial isolation region (13'), the tunneling oxide layer (20) corresponding to the second edge region, and remove the remaining protective layer (40).

9. The preparation method according to claim 7 or 8, characterized in that, Step 21-1 or Step 21-2 includes: preparing a tunneling oxide layer (20) using a furnace tube thermal oxidation method; Optionally, step 21-1 or step 21-2 further includes: under the conditions of reaction precursors H2, SiH4 and PH3, plasma chemical vapor deposition is used to deposit the first doped microcrystalline silicon layer (31) and the second doped microcrystalline silicon layer (32). Optionally, the conditions for plasma chemical vapor deposition of the first doped microcrystalline silicon layer (31) in step 21-1 or step 21-2 include: a flow ratio of H2, SiH4, and PH3 of 7:(2~5):(0.5~2), and a power of 15mW / cm³. 2 ~35mW / cm 2 The pressure is 40Pa~80Pa; Optionally, the conditions for plasma chemical vapor deposition of the second doped microcrystalline silicon layer (32) include: a flow ratio of H2, SiH4, and PH3 of 7:(2~5):(2.5~5), and a power of 20 mW / cm³. 2 ~40mW / cm 2 The pressure is 60Pa~150Pa; Optionally, in step 22-1 or step 22-2, the protective layer (40) is deposited by plasma chemical vapor deposition on the reaction precursor SiH4 and ammonia. Optionally, the mass fraction of the alkaline solution used in step 24-1 or step 24-2 is 60% to 70%. Optionally, the mass fraction of the acid solution used in step 25-1 or step 25-2 is 14% to 20%; Optionally, step 24-1 or step 24-2 may further include: simultaneously texturing the exposed portion of the back side of the crystalline silicon substrate (10).

10. The preparation method according to claim 7 or 8, characterized in that, Step 2 also includes: Step 26: An intrinsic amorphous silicon layer (50), a first doped amorphous silicon layer (61), and a second doped amorphous silicon layer (62) are sequentially stacked from the inside to the outside on the exposed back side of the crystalline silicon substrate (10) and the outside of the doped microcrystalline silicon layer (30). The first doped amorphous silicon layer (61) includes a uniformly distributed second doped atom, and the second doped amorphous silicon layer (62) includes a uniformly distributed second doped atom. The doping concentration of the second doped amorphous silicon layer (62) is greater than that of the first doped amorphous silicon layer (61). Step 27: Use a laser to remove at least the second doped amorphous silicon layer (62), the first doped amorphous silicon layer (61), and the intrinsic amorphous silicon layer (50) corresponding to the initial first conductive region (11') or the intermediate region corresponding to the initial first conductive region (11') to form the first conductive region (11). Optionally, step 26 includes: depositing the intrinsic amorphous silicon layer (50) using plasma chemical vapor deposition under the conditions of reaction precursors H2 and SiH4. Optionally, the conditions for plasma chemical vapor deposition of the intrinsic amorphous silicon layer (50) in step 26 include: a flow ratio of H2 to SiH4 of (8~12):1, and a power of 10 mW / cm². 2 ~25mW / cm 2 The pressure is 40Pa~150Pa; Optionally, step 26 further includes: under the conditions of reaction precursors H2, SiH4 and B2H6, plasma chemical vapor deposition of the first doped amorphous silicon layer (61). Optionally, the conditions for plasma chemical vapor deposition of the first doped amorphous silicon layer (61) in step 26 include: a flow rate ratio of H2, SiH4, and B2H6 of (6~10):(2~5):1, and a power of 10 mW / cm². 2 ~25mW / cm 2 The pressure is 40Pa~150Pa; Optionally, step 26 further includes: under the conditions of reaction precursors H2, SiH4, B2H6 and CO2, plasma chemical vapor deposition of the second doped amorphous silicon layer (62). Optionally, the conditions for plasma chemical vapor deposition of the second doped amorphous silicon layer (62) in step 26 include: a flow rate ratio of H2, SiH4, B2H6, and CO2 of (6~10):(2~4):(2~4):1, and a power of 15 mW / cm². 2 ~30mW / cm 2 The pressure is 40Pa~150Pa; Optionally, step 2 further includes: step 27, forming a transparent conductive film layer (70) on the outside of the doped microcrystalline silicon layer (30) of the first conductive region (11), on the outside of the doped amorphous silicon layer (60) of the initial second conductive region (12') and the initial isolation region (13'), removing at least the transparent conductive film layer (70) corresponding to the edge region of the initial second conductive region (12'), forming the second conductive region (12) and the isolation region (13), and forming metal electrodes (80) on the outside of the transparent conductive film layer (70) corresponding to the first conductive region (11) and the outside of the transparent conductive film layer (70) corresponding to the second conductive region (12), respectively.

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