A wafer-level single-crystal few-layer PtSe2 thin film and photodetector fabrication method based on interface diffusion-constrained pulsed selenization

Abstract

The application discloses a wafer-level monocrystal few-layer PtSe2 film and a photoelectric detector preparation method based on interface diffusion limited pulse selenization, and relates to the technical field of two-dimensional semiconductor film preparation. The method forms a nanoscale platinum precursor layer on a wafer substrate, determines the thickness of the platinum precursor layer according to the target PtSe2 film layer number, and determines the selenium source opening time, the selenium source closing time, the selenium source pulse duty ratio and the pulse cycle number according to the thickness; pulse selenization processing is carried out in a selenization reaction cavity, so that the equivalent selenium supply amount falls within the corresponding supply amount range, the Pt-Se interface reaction front advances in a diffusion limited state along the thickness direction, a wafer-level continuous few-layer PtSe2 film is formed, and a photoelectric detector is prepared. The application can improve the layer number consistency of the wafer-level few-layer PtSe2 film and the consistency of the channel region of the photoelectric detector.

Description

Technical Field

[0001] This invention relates to the field of two-dimensional semiconductor thin film preparation technology, and in particular to a wafer-level single-crystal few-layer PtSe2 thin film and photodetector preparation method based on interface diffusion-restricted pulsed selenization. Background Technology

[0002] PtSe2 is a layered transition metal chalcogenide compound with good air stability and layer-number-dependent electrical properties, making it suitable as a channel material for two-dimensional semiconductor thin films in photodetectors. In existing technologies, platinum precursor layer selenization is a common route for preparing PtSe2 thin films. Chinese patent document CN112510109B discloses a PtSe2 and CsPbI3 heterojunction photodetector and its fabrication method. This method involves depositing metallic platinum on a silicon substrate with a silicon dioxide insulating layer, selenizing the metallic platinum into a platinum diselenide layer using chemical vapor deposition, and then fabricating electrodes on the platinum diselenide layer. This disclosure indicates that by first forming a platinum layer and then performing selenization conversion, PtSe2 thin films for photodetectors can be obtained.

[0003] In device fabrication, PtSe2 thin films typically require the use of patterning and electrode fabrication processes to form testable semiconductor device structures. Chinese patent document CN110212025A discloses a field-effect transistor array based on platinum diselenide semiconductor and its fabrication method. This method involves forming a patterned ultrathin platinum layer using ion beam sputtering and a metal mask, followed by selenization in a tube furnace to generate patterned platinum diselenide, and then fabricating source and drain electrodes. Chinese patent document CN117888060A describes in its background section that existing technologies can form patterns using photolithography, deposit transition metals onto a substrate to form transition metal thin films, and then perform chalcogenization reactions under chemical vapor deposition to prepare large-area transition metal chalcogenide thin films. These process routes can achieve PtSe2 thin film formation and device fabrication, but the focus of process control usually lies in platinum layer deposition, selenization temperature, selenization time, and subsequent electrode fabrication.

[0004] For wafer-level few-layer PtSe2 thin film fabrication, the thickness of the platinum precursor layer directly affects the number and continuity of the selenized film. In existing platinum selenization processes, the selenium source supply conditions are typically set according to fixed reaction time or fixed atmosphere parameters, lacking a corresponding control relationship between the platinum precursor layer thickness and the selenium source pulse supply rate. When fabricating few-layer PtSe2 thin films, existing processes easily lead to inconsistent selenization progression in different regions, thus affecting the consistency of the number of wafer-level PtSe2 thin films within the predetermined device region and the response consistency of subsequent photodetectors. Therefore, it is necessary to provide a wafer-level few-layer PtSe2 thin film and photodetector fabrication method that determines the selenium source pulse control parameters based on the platinum precursor layer thickness and restricts the advancement of the Pt-Se interface reaction front. Summary of the Invention

[0005] The purpose of this invention is to provide a wafer-level single-crystal few-layer PtSe2 thin film and photodetector fabrication method based on interface diffusion-limited pulse selenization. This method can solve the problem of insufficient layer consistency of wafer-level few-layer PtSe2 thin films caused by the lack of corresponding control relationship between the thickness of the platinum precursor layer and the supply amount of the selenium source pulse, thereby achieving limited advancement of the Pt-Se interface reaction front and improved consistency of the photodetector channel region.

[0006] To achieve the above objectives, the present invention provides the following solution: A wafer-level single-crystal few-layer PtSe2 thin film and photodetector fabrication method based on interface diffusion-restricted pulsed selenization includes: A nanoscale platinum precursor layer is formed on a wafer substrate, and the thickness of the nanoscale platinum precursor layer is determined according to the number of target PtSe2 thin film layers. The selenium source pulse control parameters are determined based on the thickness of the platinum precursor layer. These parameters include the selenium source turn-on time, selenium source turn-off time, selenium source pulse duty cycle, and pulse cycle count. The selenium source pulse duty cycle is determined by the selenium source turn-on time and selenium source turn-off time. The wafer substrate with the nanoscale platinum precursor layer is placed in the selenization reaction chamber. The nanoscale platinum precursor layer is pulsed selenized according to the selenium source pulse control parameters, so that the equivalent selenium supply in a single pulse cycle falls into the supply range corresponding to the thickness of the platinum precursor layer, and the Pt-Se interface reaction front advances along the thickness direction of the nanoscale platinum precursor layer in a diffusion-restricted state. The nanoscale platinum precursor layer is transformed into a wafer-level continuous few-layer PtSe2 thin film, which has a single crystal orientation or quasi-single crystal orientation in the preset device region. An electrode electrically connected to a wafer-level continuous few-layer PtSe2 thin film is formed in a preset device region to obtain a photodetector with a wafer-level continuous few-layer PtSe2 thin film as the channel region.

[0007] Preferably, a nanoscale platinum precursor layer is formed on a wafer substrate, comprising: A platinum material layer is formed in the film deposition area of ​​the wafer substrate; The thickness distribution of the platinum material layer in the film-forming area is controlled according to the thickness of the platinum precursor layer; A platinum material layer whose thickness distribution satisfies the thickness of the platinum precursor layer is used as a nanoscale platinum precursor layer.

[0008] Preferably, determining the platinum precursor layer thickness of the nanoscale platinum precursor layer based on the target number of PtSe2 thin film layers includes: Establish the correspondence between the number of target PtSe2 thin film layers and the thickness of platinum precursor layer; Select the platinum precursor layer thickness corresponding to the target number of PtSe2 thin film layers based on the corresponding relationship; The selected platinum precursor layer thickness was used to determine the selenium source pulse control parameters.

[0009] Preferably, the selenium source pulse control parameters are determined based on the thickness of the platinum precursor layer, including: The supply range corresponding to the thickness of the platinum precursor layer is determined based on the thickness of the platinum precursor layer. The start and stop times of the selenium source are determined based on the supply range. The selenium source pulse duty cycle is determined based on the selenium source turn-on time and selenium source turn-off time. The number of pulse cycles is determined based on the thickness of the platinum precursor layer and the supply range.

[0010] Preferably, the duty cycle of the selenium source pulse satisfies: ; Where D is the selenium source pulse duty cycle. For the selenium source activation time, This refers to the selenium source shutdown time.

[0011] Preferably, the nanoscale platinum precursor layer is subjected to pulse selenization treatment according to the selenium source pulse control parameters, including: The nanoscale platinum precursor layer is pre-selenized according to the selenium source pulse control parameters, so that the initial Pt-Se reaction layer is formed on the side of the nanoscale platinum precursor layer close to the selenium source. According to the selenium source pulse control parameters, the nanoscale platinum precursor layer with the initial Pt-Se reaction layer is crystallized and selenized to advance the Pt-Se interface reaction front from the initial Pt-Se reaction layer into the interior of the nanoscale platinum precursor layer.

[0012] Preferably, ensuring that the equivalent selenium supply within a single pulse cycle falls within a supply range corresponding to the thickness of the platinum precursor layer includes: A single pulse cycle is formed by the time of one selenium source turn-on and the time of an adjacent selenium source turn-off. Within a single pulse cycle, the amount of selenium source introduced is controlled by the selenium source turn-on time, and the selenium source introduction interval is controlled by the selenium source turn-off time. Adjust the duty cycle of the selenium source pulse to ensure that the equivalent selenium supply falls within the supply range.

[0013] Preferably, the Pt-Se interfacial reaction front is advanced in a diffusion-restricted state along the thickness direction of the nanoscale platinum precursor layer, including: Within a single pulse cycle, the advance depth of the Pt-Se interface reaction front is made smaller than the remaining thickness of the nanoscale platinum precursor layer. Within multiple pulse cycles, the reaction front at the Pt-Se interface is advanced sequentially along the thickness direction of the nanoscale platinum precursor layer. Before the conversion of the nanoscale platinum precursor layer is completed, the Pt-Se interface reaction front is restricted to penetrate the nanoscale platinum precursor layer in one go.

[0014] Preferably, the wafer-level continuous few-layer PtSe2 thin film has a single-crystal orientation or quasi-single-crystal orientation within a predetermined device region, including: Layer number distribution and crystal orientation distribution are detected in the device forming region of a wafer-level continuous few-layer PtSe2 thin film. The region whose layer number distribution meets the target PtSe2 thin film layer number and whose crystal orientation distribution meets the orientation consistency requirement is defined as the preset device region; This allows the wafer-level continuous few-layer PtSe2 thin film within the preset device region to have a single-crystal orientation or a quasi-single-crystal orientation.

[0015] Preferably, forming an electrode electrically connected to a wafer-level continuous few-layer PtSe2 thin film in a predetermined device region includes: Determine the location of the channel region within the preset device area; Electrodes spaced apart are formed on both sides of the channel region. This allows for the formation of a channel region in a wafer-level continuous few-layer PtSe2 thin film located between the electrodes.

[0016] The present invention discloses the following beneficial effects: This invention forms a nanoscale platinum precursor layer on a wafer substrate and determines the thickness of the precursor layer based on the target number of PtSe2 thin film layers, thus freeing subsequent selenization processing from dependence solely on fixed time or atmosphere conditions. The thickness of the platinum precursor layer determines the amount of platinum source that can participate in the Pt-Se reaction, while the target number of PtSe2 thin film layers determines the required number of film layers after selenization. By establishing a correspondence between these two factors, the selenization process has a clear thickness basis, reducing localized insufficient selenization or layer number deviations caused by mismatches between the platinum source amount and the target number of layers.

[0017] This invention determines the selenium source turn-on time, selenium source turn-off time, selenium source pulse duty cycle, and pulse cycle number based on the thickness of the platinum precursor layer, thus making the selenium source pulse control parameters correspond to the thickness of the platinum precursor layer. Since the selenium source pulse duty cycle is determined by the selenium source turn-on and turn-off times, the selenium source supply within a single pulse cycle can be adjusted by the time parameter. Therefore, the equivalent selenium supply can fall within the supply range corresponding to the thickness of the platinum precursor layer, reducing the difference in selenization propagation caused by insufficient or excessive selenium source supply relative to the platinum precursor layer thickness.

[0018] This invention employs pulsed selenization treatment on a nanoscale platinum precursor layer according to selenium source pulse control parameters, enabling the Pt-Se interface reaction front to advance along the thickness direction of the nanoscale platinum precursor layer in a diffusion-restricted manner. The selenization reaction proceeds gradually in a front-advancing manner, with the reaction progression within a single pulse cycle limited by the equivalent selenium supply, thus preventing the Pt-Se interface reaction front from excessively penetrating the nanoscale platinum precursor layer in localized areas. This treatment method helps reduce the difference in selenization advancement across different regions within the wafer, thereby improving the layer uniformity of continuous few-layer PtSe2 thin films at the wafer level.

[0019] This invention transforms a nanoscale platinum precursor layer into a wafer-level continuous few-layer PtSe2 thin film, and ensures that the wafer-level continuous few-layer PtSe2 thin film has a single-crystal orientation or quasi-single-crystal orientation within a predetermined device region. This allows the channel region for subsequent electrode connections to be established within a thin film region with a relatively consistent orientation. After the electrodes are formed in the predetermined device region, the wafer-level continuous few-layer PtSe2 thin film located between the electrodes serves as the channel region of the photodetector. Since the number of thin film layers and the orientation state of the channel region are already defined by the aforementioned selenization process, the fundamental differences in the channel of the photodetector are reduced, which is beneficial for improving the response consistency of different devices on the same wafer. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart of a method provided in an embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram illustrating the pulsed selenization treatment and the advancement of the Pt-Se interface reaction front provided in an embodiment of the present invention.

[0023] Figure 3 A line graph showing the change in the supply propulsion ratio with the number of pulse cycles, provided for an embodiment of the present invention.

[0024] Figure 4 This is a schematic diagram of a photodetector structure provided in an embodiment of the present invention; Figure 5 The Raman spectrum of a wafer-level continuous few-layer PtSe2 thin film provided in an embodiment of the present invention.

[0025] Explanation of reference numerals in the attached figures: 1. Wafer substrate; 2. Wafer-level continuous few-layer PtSe2 thin film; 3. Electrode; 4. Channel region; 5. Incident light. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] Figure 1 The method flowchart provided in the embodiments of the present invention is as follows: Figure 1 As shown, this embodiment provides a wafer-level single-crystal few-layer PtSe2 thin film and photodetector fabrication method based on interface diffusion-restricted pulsed selenization, including: Step 100: Form a nanoscale platinum precursor layer on a wafer substrate, and determine the thickness of the nanoscale platinum precursor layer according to the number of target PtSe2 thin film layers. Step 200: Determine the selenium source pulse control parameters based on the thickness of the platinum precursor layer; the selenium source pulse control parameters include the selenium source turn-on time, the selenium source turn-off time, the selenium source pulse duty cycle, and the number of pulse cycles. The selenium source pulse duty cycle is determined by the selenium source turn-on time and the selenium source turn-off time. Step 300: Place the wafer substrate with the nanoscale platinum precursor layer in the selenization reaction chamber, and perform pulse selenization treatment on the nanoscale platinum precursor layer according to the selenium source pulse control parameters, so that the equivalent selenium supply in a single pulse cycle falls into the supply range corresponding to the thickness of the platinum precursor layer, and make the Pt-Se interface reaction front advance along the thickness direction of the nanoscale platinum precursor layer in a diffusion-restricted state. Figure 2 This is a schematic diagram illustrating the pulsed selenization treatment and the advancement of the Pt-Se interface reaction front provided in an embodiment of the present invention. Figure 2 The diagram shows the connection between the selenium source, the valve-controlled gas path, the bypass, and the selenization reaction chamber. The valve-controlled gas path is used to control the entry of the selenium-containing carrier gas into the selenization reaction chamber, and the bypass is used to switch the flow direction of the selenium-containing carrier gas during the pulse interval. A wafer substrate with a nanoscale platinum precursor layer is placed inside the selenization reaction chamber. Figure 2 The right side is a magnified view of a portion of the area. The magnified area shows the selenium source side, the platinum precursor layer, the initial Pt-Se reaction layer, and the wafer substrate from top to bottom. The multiple dashed lines inside the platinum precursor layer correspond to the positions of the Pt-Se interface reaction front after the first pulse, the second pulse, the third pulse, and subsequent pulses, respectively, and are used to indicate the stepwise advancement of the Pt-Se interface reaction front along the thickness direction of the platinum precursor layer.

[0029] Step 400: Convert the nanoscale platinum precursor layer into a wafer-level continuous few-layer PtSe2 thin film; the wafer-level continuous few-layer PtSe2 thin film has a single-crystal orientation or a quasi-single-crystal orientation in the preset device region; Step 500: Form an electrode in a preset device region that is electrically connected to a wafer-level continuous few-layer PtSe2 thin film to obtain a photodetector with a wafer-level continuous few-layer PtSe2 thin film as the channel region.

[0030] In this embodiment, the wafer substrate is used to support the nanoscale platinum precursor layer. The wafer substrate can be a silicon wafer with a silicon oxide insulating layer on its surface, or a sapphire wafer. When using a sapphire wafer, it is easier to obtain a uniformly oriented PtSe2 film deposition area within the predetermined device region. The target PtSe2 film layer number refers to the number of PtSe2 film layers required for the photodetector channel region. The platinum precursor layer thickness refers to the thickness of the platinum material layer deposited on the wafer substrate.

[0031] The selenium source turn-on time does not refer to the time during which the solid selenium source body is repeatedly heated, but rather to the duration during which the selenium-containing carrier gas enters the selenization reaction chamber. The selenium source turn-off time refers to the duration during which the selenium-containing carrier gas stops entering the selenization reaction chamber, or when the selenium-containing carrier gas switches to the bypass channel. The entry and exit of the selenium-containing carrier gas can be controlled by a valve-controlled gas path. The equivalent selenium supply refers to the amount of selenium source supplied to the reaction surface of the nanoscale platinum precursor layer within a single pulse cycle. The supply range refers to the allowable range of the equivalent selenium supply corresponding to the thickness of the platinum precursor layer. The Pt-Se interface reaction front refers to the reaction interface formed when selenium diffuses from the side of the nanoscale platinum precursor layer near the selenium source to the wafer substrate side and reacts with platinum.

[0032] Before determining the platinum precursor layer thickness, the required number of PtSe2 thin film layers in the photodetector channel region must be determined. When the channel dark current requirement is low, a smaller number of target PtSe2 thin film layers can be selected; when the channel resistance or light absorption requirement is high, the number of target PtSe2 thin film layers can be appropriately increased. After determining the target PtSe2 thin film layer number, the corresponding platinum precursor layer thickness can be selected. The correspondence between the target PtSe2 thin film layer number and the platinum precursor layer thickness can be pre-calibrated under the same wafer substrate type, the same selenization reaction chamber, and the same selenium source arrangement.

[0033] Table 1 shows a set of calibration relationships used in this embodiment. The values ​​in Table 1 are used to illustrate the selection method of the platinum precursor layer thickness. The corresponding relationships can be obtained again by changing the wafer substrate type, selenization reaction chamber size, or selenium source arrangement.

[0034] Table 1. Correspondence between the number of target PtSe2 thin film layers and the thickness of the platinum precursor layer

[0035] Taking a 3- to 4-layer channel region as an example, the corresponding platinum precursor layer thickness in Table 1 is 0.8 nm. During fabrication, a platinum material layer is deposited in the film-forming region of the wafer substrate. After the in-plane thickness distribution of the platinum material layer meets the thickness requirement corresponding to 0.8 nm, the platinum material layer serves as the nanoscale platinum precursor layer. If the channel region focuses on reducing dark current, the target PtSe2 thin film layer number can be selected as 2 to 3 layers, and the platinum precursor layer thickness is correspondingly selected as 0.6 nm. Through this thickness selection process, the platinum source amount is first established in correspondence with the target PtSe2 thin film layer number, and the subsequent selenium source pulse control parameters are then calculated around the platinum source amount.

[0036] Once the thickness of the platinum precursor layer is determined, it needs to be converted into the platinum precursor layer content per unit area. The platinum precursor layer content per unit area is determined according to the following formula: In the above formula, Platinum precursor layer content per unit area, in mol / cm² 2 ; This refers to the density of platinum, expressed in g / cm³. 3 ; The thickness of the platinum precursor layer is in cm. The value represents the molar mass of platinum, expressed in g / mol.

[0037] The stoichiometric ratio of platinum to selenium in PtSe2 is 1:2. The theoretical selenium supply required to convert a unit area of ​​platinum precursor layer into a PtSe2 thin film is determined by the following formula: In the above formula, The theoretical selenium supply per unit area, expressed in mol / cm². 2 . Used to determine the supply range. There are gas transport losses and surface adsorption differences within the selenization reaction chamber. This does not mean that all selenium sources in the selenization reaction chamber are absorbed by the nanoscale platinum precursor layer.

[0038] The equivalent selenium supply within a single pulse cycle can be calibrated under the same selenium source temperature, the same carrier gas flow rate, and the same reaction chamber pressure, with the following calibration relationship: In the above formula, Equivalent selenium supply per single pulse cycle, in mol / cm³ 2 ; The equivalent selenium supply rate obtained by calibration with standard plates is expressed in mol / (cm²). 2 ·s); The time for the selenium source to be turned on is measured in seconds (s). It can be determined from the selenization results of standard plates or the results of changes in the quality of selenium source, without directly using the theoretical evaporation rate of the selenium source itself.

[0039] Pulse cycle count Once selected, the supply range within a single pulse cycle is determined according to the following two formulas: In the two formulas above, This represents the lower limit of the equivalent selenium supply within a single pulse cycle. This represents the upper limit of the equivalent selenium supply within a single pulse cycle. This is the lower limit of the supply matching coefficient. To provide an upper limit for the matching coefficient. In this embodiment, Take 0.90, Take 1.15. When When the following relationship is satisfied, the equivalent selenium supply within a single pulse cycle falls within the supply range corresponding to the thickness of the platinum precursor layer: The selenium source turn-on time can be obtained from the calibration relationship between the equivalent selenium supply and the selenium source turn-on time within a single pulse cycle. satisfy: The duty cycle of the selenium source pulse is determined according to the following formula: In the above formula, The duty cycle of the selenium source pulse. This refers to the selenium source shutdown time. It can be controlled to be no greater than 0.20, so that the selenium-containing carrier gas enters intermittently, avoiding the selenium source supply process from approaching continuous selenization.

[0040] Finish The total supply matching coefficient after one pulse cycle is determined by the following formula: In the above formula, This refers to the degree of matching between the total equivalent selenium supply and the theoretical selenium supply per unit area. When the value falls between 0.90 and 1.15, the total equivalent selenium supply matches the thickness of the platinum precursor layer. When the levels are too low, unreacted regions are likely to exist in the nanoscale platinum precursor layer. When the level is too high, there is a risk of excessive selenium supply in local areas, which increases the probability of vertical stacking growth.

[0041] Taking a platinum precursor layer thickness of 0.8 nm as an example, 0.8 nm is equivalent to 8.0 × 10⁻⁶. -8 cm. Take It is 21.45 g / cm³ 3 , The content of platinum precursor layer per unit area is 195.08 g / mol, and the content of platinum precursor layer per unit area is: The theoretical selenium supply per unit area is: Pulse cycle count Take 40, Take 0.90, Take 1.15. The lower limit of the equivalent selenium supply within a single pulse cycle is: The upper limit of the equivalent selenium supply within a single pulse cycle is: Equivalent selenium supply rate obtained from standard plate calibration 4.4×10 -11 mol / (cm 2 When ·s), the selenium source activation time It should meet the following requirements: Calculated from the above inequalities The duration is from 9.00s to 11.50s. This embodiment selects... It lasts for 10 seconds. At this time: Selenium source shutdown time When the time is set to 50 seconds, the duty cycle of the selenium source pulse is: After 40 pulse cycles, the total supply matching coefficient is: The above calculations show that when the platinum precursor layer thickness is 0.8 nm, For 10s, For 50s, The selenium source pulse control parameter of 40 ensures that the equivalent selenium supply within a single pulse cycle falls within the supply range, and also matches the total equivalent selenium supply with the theoretical selenium supply per unit area.

[0042] Table 2 lists the equivalent selenium supply rates. 4.4×10 -11 mol / (cm 2The selenium source pulse control parameters at time ·s). Table 2 shows the platinum density during calculation. Take 21.45 g / cm 3 platinum molar mass Take 195.08 g / mol, Take 0.90, Take 1.15.

[0043] Table 2 Example of Selenium Source Pulse Control Parameter Calculation

[0044] The on-time range in Table 2 is calculated based on the values ​​of the selenium source on-time. The selected pulse parameters are listed in the order of "selenium source on-time, selenium source off-time, and selenium source pulse duty cycle". The four groups were calculated using the total supply matching coefficient formula. All fall within the range of 0.90 to 1.15. A 0.6 nm platinum precursor layer corresponds to a lower target PtSe2 thin film layer number, which was selected. It lasts for 8 seconds. The pulse duration is 52 s, indicating a low selenium source introduction rate within a single pulse cycle. A 1.2 nm platinum precursor layer corresponds to a higher target PtSe2 thin film layer number, which was selected. It lasts for 12 seconds. The duration is 60 seconds. The amount of selenium source introduced within a single pulse cycle increases, but the duty cycle remains below 0.20.

[0045] After the wafer substrate with the nanoscale platinum precursor layer is placed in the selenization reaction chamber, the selenium-containing carrier gas enters the selenization reaction chamber through a valve-controlled gas path. The entry time of the selenium-containing carrier gas corresponds to the selenium source turn-on time. The adjacent entry time of the selenium-containing carrier gas or the bypass switching time corresponds to the selenium source turn-off time. The selenium-containing carrier gas enters the selenization reaction chamber in a pulsed manner, so the surface of the nanoscale platinum precursor layer is not continuously subjected to a high supply of selenium source in the initial stage.

[0046] The pulsed selenization process begins with a pre-selenization treatment. During this pre-selenization stage, the selenium source pulse primarily acts on the side of the nanoscale platinum precursor layer closest to the selenium source, forming an initial Pt-Se reaction layer on that side. Subsequently, in the crystallization selenization stage, the selenium-containing carrier gas continues to enter the selenization reaction chamber according to the selenium source pulse control parameters, and the Pt-Se interface reaction front advances from the initial Pt-Se reaction layer into the interior of the nanoscale platinum precursor layer.

[0047] To describe the extent of the advance of the Pt-Se interface reaction front, this embodiment uses a supply advance ratio. Indicates the first Cumulative equivalent selenium supply level after the end of each pulse cycle: In the above formula, For the first The supply advance ratio after the end of each pulse cycle This represents the number of pulse cycles that have been completed. This refers to the equivalent selenium supply within a single pulse cycle. The theoretical selenium supply per unit area. It is used to characterize the ratio between the cumulative selenium source supply and the theoretical selenium supply, and does not directly represent the actual thickness of the PtSe2 film.

[0048] In the batches prepared with 3 to 4 channel layers, the platinum precursor layer thickness was 0.8 nm. 4.4×10 -10 mol / cm 2 , It is 1.76 × 10 -8 mol / cm 2 The supply propulsion ratio corresponding to a single pulse cycle is: After completing 10 pulse cycles: After completing 20 pulse cycles, The value is 0.500; after completing 30 pulse cycles, It is 0.750; after completing 40 pulse cycles, The value is 1.000. The selenium source supply gradually accumulates with each pulse cycle, and the reaction front at the Pt-Se interface advances towards the thickness direction over multiple pulse cycles.

[0049] Figure 3 A line graph showing the change in the supply propulsion ratio with the number of pulse cycles, provided for an embodiment of the present invention. Figure 3 In the diagram, the horizontal axis represents the number of pulse cycles that have been completed. The vertical axis represents the supply-driven ratio. The four markers on the broken line are (10, 0.250), (20, 0.500), (30, 0.750), and (40, 1.000), which are used to represent the change in the cumulative equivalent selenium supply as the number of pulse cycles increases in a batch of preparation with a platinum precursor layer thickness of 0.8 nm. Figure 3 The two horizontal dashed lines correspond to The range indicates the pre-selenization treatment range; the portion exceeding this range and continuing to rise to 1.000 indicates the crystallization selenization treatment range.

[0050] The pre-selenization stage can correspond to The value ranged from 0.20 to 0.35. In the batches preparing 3- to 4-layer channel regions, the pre-selenization treatment employed 10 pulse cycles. The value is 0.250. During the crystallization and selenization treatment stage, the number of pulse cycles is further increased, making... The concentration was gradually increased from 0.250 to 1.000. Pre-selenization and crystallization selenization treatments can be distinguished by the cumulative equivalent selenium supply, not solely by the reaction time.

[0051] Within a single pulse cycle, the equivalent selenium supply is limited by the selenium source on-time. Between adjacent pulse cycles, the selenium source off-time provides a gap for selenium diffusion in the thickness direction. The advance depth of the Pt-Se interface reaction front within a single pulse cycle is limited. After multiple pulse cycles, the Pt-Se interface reaction front gradually advances to near the interface between the nanoscale platinum precursor layer and the wafer substrate.

[0052] After pulse selenization, the layer number distribution of the formed PtSe2 film is detected. Raman spectroscopy surface scanning is used as an in-plane screening method, and atomic force microscopy or transmission electron microscopy is used to confirm local areas. When the PtSe2 film is continuously distributed within the film formation area of ​​the wafer substrate, and the layer number distribution meets the target PtSe2 film layer number, the PtSe2 film is identified as a wafer-level continuous few-layer PtSe2 film.

[0053] Figure 5 The Raman spectrum of a wafer-level continuous few-layer PtSe2 thin film provided in an embodiment of the present invention is shown. Figure 5 As shown, the horizontal axis represents the Raman displacement, with units of cm. -1 The vertical axis represents Raman intensity, measured in au; the Raman spectrum appears at 171.79 cm⁻¹. -1 The nearby Eg characteristic peak is located at 202.77 cm⁻¹. -1 Nearby A 1g Characteristic peaks, the peak position difference between the two is approximately 31 cm. -1 Eg characteristic peaks and A 1g Characteristic peaks were used to characterize the in-plane and out-of-plane vibration modes of the PtSe2 film, respectively. The calibration relationship between the number of target PtSe2 film layers and the thickness of the platinum precursor layer was also considered. Figure 5 The Raman spectra shown are used to help confirm that the PtSe2 film obtained by pulse selenization is in the few-layer range and that the number of film layers corresponds to the target PtSe2 film layer number of 3 to 4 layers.

[0054] Crystal orientation distribution detection can be performed using polarized Raman spectroscopy, low-energy electron diffraction, or selected area electron diffraction. For wafer-level samples, regions meeting the layer number distribution requirements can be identified first through Raman plane scanning, and then selected area electron diffraction can be performed on samples from these regions for confirmation. Regions where the layer number distribution meets the target PtSe2 film layer number and the crystal orientation distribution meets the orientation consistency requirements are identified as the preset device region. Wafer-level continuous few-layer PtSe2 films within the preset device region have single-crystal orientation or quasi-single-crystal orientation. Single-crystal orientation or quasi-single-crystal orientation is used to describe the main orientation state within the preset device region, and it is not required that the entire wafer-level continuous few-layer PtSe2 film be a complete single-crystal structure.

[0055] The channel region location is determined within the predefined device area. The channel region is located within a region where the layer number distribution meets the target PtSe2 thin film layer number and the crystal orientation distribution meets the orientation consistency requirements. After determining the channel region location, electrodes are formed on both sides of the channel region location, spaced apart from each other. The electrodes are electrically connected to a wafer-level continuous few-layer PtSe2 thin film. The wafer-level continuous few-layer PtSe2 thin film located between the electrodes forms the channel region.

[0056] Figure 4 This is a schematic diagram of a photodetector structure provided in an embodiment of the present invention. Figure 4 As shown, a wafer-level continuous few-layer PtSe2 thin film 2 is formed on the upper surface of the wafer substrate 1. Two electrodes 3 are disposed above the wafer-level continuous few-layer PtSe2 thin film 2 at intervals. The wafer-level continuous few-layer PtSe2 thin film 2 between the two electrodes 3 forms a channel region 4. Incident light 5 irradiates the channel region 4 to show the photodetector structure composed of the wafer substrate 1, the wafer-level continuous few-layer PtSe2 thin film 2, the electrodes 3 and the channel region 4.

[0057] Electrodes can be formed using photolithography patterning and metal deposition. The electrode material can be selected based on the contact characteristics of the wafer-level continuous few-layer PtSe2 thin film. After electrode formation, the channel region is exposed to the area to be detected by illumination. When illumination is applied to the channel region, the wafer-level continuous few-layer PtSe2 thin film generates photogenerated carriers. The electrodes collect these photogenerated carriers and generate a photoelectric response signal. The channel region is located within a predetermined device region, and the number of layers and orientation state of the channel region correspond to the number of layers of the target PtSe2 thin film, minimizing the fundamental differences in the photodetector channel on the same wafer.

[0058] In this embodiment, the thickness of the platinum precursor layer is first determined based on the target number of PtSe2 thin film layers. Then, the theoretical selenium supply per unit area is calculated based on the platinum precursor layer thickness, and the selenium source turn-on time, selenium source turn-off time, and pulse cycle number are determined accordingly. The equivalent selenium supply within a single pulse cycle is limited to the supply range. The Pt-Se interface reaction front advances in stages along the thickness direction with each pulse cycle, making it difficult for the nanoscale platinum precursor layer to undergo excessively rapid selenization in local areas. The resulting wafer-level continuous few-layer PtSe2 thin film has a relatively consistent number of layers and orientation state within the preset device region. After the electrode is formed, the channel region of the photodetector can fall within the region where the layer distribution and crystal orientation distribution meet the requirements, thereby reducing the response deviation caused by differences in the channel film between different devices on the same wafer.

[0059] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0060] Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this invention. Furthermore, those skilled in the art will recognize that, based on the ideas of this invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this invention.

Claims

1. A method for fabricating wafer-level single-crystal few-layer PtSe2 thin films and photodetectors based on interface diffusion-restricted pulsed selenization, characterized in that, include: A nanoscale platinum precursor layer is formed on a wafer substrate, and the thickness of the nanoscale platinum precursor layer is determined according to the target number of PtSe2 thin film layers. The selenium source pulse control parameters are determined based on the thickness of the platinum precursor layer. The selenium source pulse control parameters include the selenium source turn-on time, the selenium source turn-off time, the selenium source pulse duty cycle, and the number of pulse cycles. The selenium source pulse duty cycle is determined by the selenium source turn-on time and the selenium source turn-off time. The wafer substrate on which the nanoscale platinum precursor layer is formed is placed in the selenization reaction chamber. The nanoscale platinum precursor layer is pulsed selenized according to the selenium source pulse control parameters, so that the equivalent selenium supply in a single pulse cycle falls into the supply range corresponding to the thickness of the platinum precursor layer, and the Pt-Se interface reaction front advances along the thickness direction of the nanoscale platinum precursor layer in a diffusion-restricted state. The nanoscale platinum precursor layer is transformed into a wafer-level continuous few-layer PtSe2 thin film, which has a single crystal orientation or quasi-single crystal orientation in a preset device region. An electrode electrically connected to the wafer-level continuous few-layer PtSe2 thin film is formed in the preset device region to obtain a photodetector with the wafer-level continuous few-layer PtSe2 thin film as the channel region.

2. The method for fabricating wafer-level single-crystal few-layer PtSe2 thin films and photodetectors based on interface diffusion-restricted pulsed selenization as described in claim 1, characterized in that, Forming a nanoscale platinum precursor layer on a wafer substrate includes: A platinum material layer is formed in the film-forming region of the wafer substrate; The thickness distribution of the platinum material layer in the film-forming region is controlled according to the thickness of the platinum precursor layer. The platinum material layer whose thickness distribution satisfies the thickness of the platinum precursor layer is used as the nanoscale platinum precursor layer.

3. The method for fabricating wafer-level single-crystal few-layer PtSe2 thin films and photodetectors based on interface diffusion-restricted pulsed selenization as described in claim 1, characterized in that, Determining the platinum precursor layer thickness of the nanoscale platinum precursor layer based on the target number of PtSe2 thin film layers includes: Establish the correspondence between the number of target PtSe2 thin film layers and the thickness of the platinum precursor layer; The platinum precursor layer thickness corresponding to the target number of PtSe2 thin film layers is selected according to the corresponding relationship; The selected platinum precursor layer thickness is used to determine the selenium source pulse control parameters.

4. The method for fabricating wafer-level single-crystal few-layer PtSe2 thin films and photodetectors based on interface diffusion-restricted pulsed selenization as described in claim 1, characterized in that, The selenium source pulse control parameters are determined based on the thickness of the platinum precursor layer, including: The supply range corresponding to the thickness of the platinum precursor layer is determined based on the thickness of the platinum precursor layer. The selenium source start-up time and selenium source shutdown time are determined according to the supply range; The selenium source pulse duty cycle is determined based on the selenium source turn-on time and the selenium source turn-off time. The number of pulse cycles is determined based on the thickness of the platinum precursor layer and the supply range.

5. The method for fabricating wafer-level single-crystal few-layer PtSe2 thin films and photodetectors based on interface diffusion-restricted pulsed selenization as described in claim 1, characterized in that, The duty cycle of the selenium source pulse satisfies: ； Wherein, D is the duty cycle of the selenium source pulse. The selenium source activation time. The selenium source shutdown time.

6. The method for fabricating wafer-level single-crystal few-layer PtSe2 thin films and photodetectors based on interface diffusion-restricted pulsed selenization as described in claim 1, characterized in that, The nanoscale platinum precursor layer is subjected to pulse selenization treatment according to the selenium source pulse control parameters, including: The nanoscale platinum precursor layer is pre-selenized according to the selenium source pulse control parameters, so that an initial Pt-Se reaction layer is formed on the side of the nanoscale platinum precursor layer close to the selenium source. According to the selenium source pulse control parameters, the nanoscale platinum precursor layer on which the initial Pt-Se reaction layer is formed is subjected to crystallization and selenization treatment, so that the Pt-Se interface reaction front advances from the initial Pt-Se reaction layer into the interior of the nanoscale platinum precursor layer.

7. The method for fabricating wafer-level single-crystal few-layer PtSe2 thin films and photodetectors based on interface diffusion-restricted pulsed selenization as described in claim 1, characterized in that, Ensuring that the equivalent selenium supply within a single pulse cycle falls within the supply range corresponding to the thickness of the platinum precursor layer includes: The single pulse cycle is formed by the time of one selenium source turn-on and the time of an adjacent selenium source turn-off. Within the single pulse cycle, the amount of selenium source introduced is controlled by the selenium source turn-on time, and the selenium source introduction interval is controlled by the selenium source turn-off time. Adjust the duty cycle of the selenium source pulse so that the equivalent selenium supply falls within the supply range.

8. The method for fabricating wafer-level single-crystal few-layer PtSe2 thin films and photodetectors based on interface diffusion-restricted pulsed selenization as described in claim 1, characterized in that, Promoting the Pt-Se interfacial reaction front along the thickness direction of the nanoscale platinum precursor layer in a diffusion-restricted state includes: Within the single pulse cycle, the advance depth of the Pt-Se interface reaction front is less than the remaining thickness of the nanoscale platinum precursor layer; Within multiple pulse cycles, the reaction front of the Pt-Se interface is advanced sequentially along the thickness direction of the nanoscale platinum precursor layer. Before the conversion of the nanoscale platinum precursor layer is completed, the Pt-Se interface reaction front is restricted to penetrate the nanoscale platinum precursor layer in one go.

9. The method for fabricating wafer-level single-crystal few-layer PtSe2 thin films and photodetectors based on interface diffusion-restricted pulsed selenization as described in claim 1, characterized in that, The wafer-level continuous few-layer PtSe2 thin film has a single-crystal orientation or quasi-single-crystal orientation within a predetermined device region, including: Layer number distribution and crystal orientation distribution are detected in the device forming region of the wafer-level continuous few-layer PtSe2 thin film; The region whose layer number distribution meets the target PtSe2 thin film layer number and whose crystal orientation distribution meets the orientation consistency requirement is defined as the preset device region; The wafer-level continuous few-layer PtSe2 thin film within the preset device region is configured to have the single-crystal orientation or the quasi-single-crystal orientation.

10. The method for fabricating wafer-level single-crystal few-layer PtSe2 thin films and photodetectors based on interface diffusion-restricted pulsed selenization as described in claim 1, characterized in that, An electrode electrically connected to the wafer-level continuous few-layer PtSe2 thin film is formed in the preset device region, including: Determine the location of the channel region within the preset device area; The electrodes are formed on both sides of the location in the channel region, spaced apart from each other; The wafer-level continuous few-layer PtSe2 thin film located between the electrodes forms the channel region.

Images