Wide bandgap semiconductor photoelectric homojunction junction field effect transistor, method of manufacturing and application thereof

Abstract

The application discloses a wide-bandgap semiconductor photoelectric homojunction field effect transistor, a manufacturing method thereof and application. The transistor comprises a wide-bandgap semiconductor layer capable of generating photo-generated carriers under light irradiation, a conductive channel formed in the semiconductor layer, a source, a drain and a gate. The gate comprises a p-type semiconductor material layer arranged on a first region of the surface of the wide-bandgap semiconductor layer, which is in contact with the wide-bandgap semiconductor layer to form a heterojunction or a p-n junction, and can deplete the electrons in the conductive channel under the first region. Meanwhile, a light receiving window is formed on the transistor, which can allow light to pass through and irradiate on the surface and / or inside of the wide-bandgap semiconductor layer. The transistor utilizes the p-type semiconductor material layer and the wide-bandgap semiconductor channel to form a heterojunction gate or a p-n junction gate control structure, which can improve the gate control ability, reduce the off-state leakage current, serve as an extraction channel for photo-generated holes, promote the export of residual holes in the off process, and realize low conduction loss and fast turn-off.

Description

Technical Field

[0001] This invention relates to a junction field-effect transistor, specifically to a wide-bandgap semiconductor optoelectronic co-controlled junction field-effect transistor (JFET), its fabrication method, and its applications, belonging to the field of semiconductor technology. Background Technology

[0002] Wide bandgap semiconductor materials possess advantages such as large bandgap width, high critical breakdown field strength, high electron saturation drift velocity, and good thermal stability, making them valuable for applications in high-voltage, high-frequency, and high-power electronic devices. Among them, group III nitride semiconductors such as gallium nitride (GaN) combine wide bandgap, high breakdown field strength, and direct bandgap characteristics, making them suitable not only for high-power power electronic devices but also for achieving light absorption and photoresponse functions. Therefore, optoelectronic power transistors based on wide bandgap semiconductors are expected to play a crucial role in high-frequency, high-power power supplies, optically triggered switches, strong-weak current isolation, and electromagnetic interference-resistant drives.

[0003] Traditional power transistors typically employ electronic control, controlling the channel carrier concentration or depletion region width via gate voltage to achieve device switching. Electronic control devices are mature, possess strong gate control capabilities, and exhibit fast turn-off response, making them suitable for high-frequency switching applications. However, this electronic control approach usually requires complex gate drive and signal transmission systems. In high-voltage, high-frequency, and strong electromagnetic interference environments, parasitic capacitance, parasitic inductance, and electromagnetic coupling in the drive circuit can easily affect switching stability and increase system design complexity and switching losses. Especially in applications involving strong-weak current isolation, high-voltage floating ground drives, or complex power modules, traditional electronic control methods often require additional isolation drives, level shifting, and protection circuits, further increasing system complexity.

[0004] Unlike electrically controlled devices, optically controlled power devices regulate their conduction state by generating photogenerated carriers or altering the internal potential distribution of the device through incident light. Optically controlled devices eliminate the need for complex electrical signal transmission paths, offer strong immunity to electromagnetic interference, and reduce electrical coupling between the driver and power terminals. Furthermore, their simple driver structure and low parasitic capacitance help reduce conduction losses and improve transmission efficiency. Therefore, optically controlled power devices are advantageous in scenarios requiring electrical isolation, electromagnetic interference immunity, and optical triggering. However, single optically controlled devices still exhibit persistent photoconductivity. After the light is removed, the remaining photogenerated carriers in the channel are difficult to recombine or be extracted in a timely manner, easily leading to increased leakage current and current tailing, resulting in prolonged turn-off time and reduced turn-off frequency, making it difficult to meet the requirements of high-frequency, high-power applications.

[0005] To balance the turn-off performance of electronically controlled devices with the advantages of optically controlled devices, such as simple driving, electromagnetic interference resistance, and low conduction loss, a photoelectric co-control approach can be used to regulate the devices. Photoelectric co-control refers to the use of light to generate photogenerated carriers when the device is turned on, thereby reducing on-resistance and increasing output current; when the device is turned off, applying a gate voltage, especially a negative gate voltage, promotes the extraction or recombination of photogenerated carriers, thus shortening the turn-off time and solving the problems of current tailing and persistent photoconductivity. This type of device is expected to simultaneously achieve low conduction loss, fast turn-off, high output power, and electromagnetic interference resistance, meeting the needs of future high-frequency and high-power applications.

[0006] Existing optoelectronic co-controlled devices fall into two categories: lateral optoelectronic co-controlled transistors and longitudinal optoelectronic co-controlled transistors. Lateral optoelectronic co-controlled devices are typically based on GaN HEMT or p-GaN gate HEMT structures, utilizing the two-dimensional electron gas at the AlGaN / GaN heterojunction interface as the conductive channel. Under illumination, photogenerated carriers are generated in the channel or buffer layer, increasing the output current. However, due to the high electron concentration of the two-dimensional electron gas itself, the modulation ratio of photogenerated carriers to the total channel current is limited, resulting in low optical gain and limited output current increase. Furthermore, the high electric field of lateral devices is mainly concentrated near the surface or gate-drain region, making them susceptible to surface states, interface states, and passivation layer reliability issues, posing certain reliability challenges under high voltage and high power operation. Longitudinal optoelectronic co-controlled devices typically use low-doped GaN or similar wide bandgap semiconductors as the longitudinal drift region or channel region. Because of the low intrinsic carrier concentration in the low-doped channel, the carriers generated by illumination can significantly improve the channel conductivity, thus resulting in higher optical gain and a larger output current increase. Simultaneously, the electric field of the longitudinal device is mainly distributed within the material bulk, leading to better high-voltage reliability. However, existing longitudinal optoelectronic co-control devices generally lack effective transport and extraction channels for photogenerated holes. After illumination removal, residual holes are difficult to extract in a timely manner, easily leading to slower turn-off and current tailing, limiting the device's switching frequency. Especially in Schottky gate structures, hole transport is easily blocked by potential barriers, further affecting the device's rapid turn-off. Summary of the Invention

[0007] The main objective of this invention is to provide a wide bandgap semiconductor optoelectronic co-controlled junction field-effect transistor, its fabrication method, and its application, thereby overcoming the shortcomings of the prior art.

[0008] To solve the above technical problems, the technical solution of the present invention is as follows: According to a first aspect of the present invention, a wide bandgap semiconductor opto-junction field-effect transistor is provided, comprising a wide bandgap semiconductor layer, a conductive channel formed in the wide bandgap semiconductor layer, and a source, a drain, and a gate connected to the wide bandgap semiconductor layer; and photogenerated carriers can be generated in the wide bandgap semiconductor layer under illumination with light of a selected wavelength. The gate includes a p-type semiconductor material layer, which is disposed on a first region on the surface of the wide bandgap semiconductor layer and forms a heterojunction or pn junction with the wide bandgap semiconductor layer, and is capable of depleting electrons in the conductive channel located below the first region. Furthermore, a light-receiving window is formed on the field-effect transistor, which allows light of the selected wavelength to pass through and illuminate the surface and / or interior of the wide bandgap semiconductor layer.

[0009] According to a second aspect of the present invention, a method for fabricating the wide-bandgap semiconductor opto-junction field-effect transistor is provided, comprising: A wide bandgap semiconductor layer is provided, wherein a conductive channel is formed in the wide bandgap semiconductor layer, and photogenerated carriers can be generated in the wide bandgap semiconductor layer under light irradiation of a selected wavelength; A p-type semiconductor material layer is disposed on a first region on the surface of the wide bandgap semiconductor layer to form a gate, and the p-type semiconductor material layer is made to contact and cooperate with the wide bandgap semiconductor layer to form a heterojunction or pn junction, thereby depleting the electrons in the conductive channel located below the first region. Fabricate source and drain electrodes, and connect the source and drain electrodes to the wide bandgap semiconductor layer; Additionally, a light-receiving window is provided on the field-effect transistor, the light-receiving window allowing light of the selected wavelength to pass through and illuminate the surface and / or interior of the wide bandgap semiconductor layer.

[0010] According to a third aspect of the present invention, a method of using the wide-bandgap semiconductor opto-junction field-effect transistor is provided, comprising: A first set voltage is applied to the gate, and light of a selected wavelength is irradiated through the light-receiving window to illuminate the surface and / or interior of the wide bandgap semiconductor layer, thereby turning on the field-effect transistor; Alternatively, a second set voltage is applied to the gate, and at least a portion of the photogenerated carriers in the wide bandgap semiconductor layer are removed using the gate as a extraction channel, thereby turning off the field-effect transistor; Wherein, the first set voltage is greater than the second set voltage.

[0011] Compared with the prior art, the present invention has at least the following beneficial effects: (1) The wide bandgap semiconductor opto-junction field-effect transistor of the present invention combines the advantages of both optical and electrical control devices, and can achieve low conduction loss and fast turn-off. In particular, by using a p-type semiconductor material layer to construct the gate and forming a heterojunction between the p-type semiconductor and the wide bandgap semiconductor, when the device is turned on, photogenerated carriers (including photogenerated holes and photogenerated electrons) can be generated by illumination, which can improve the channel conductivity, reduce the on-resistance and increase the output current. When the device is turned off, the p-type semiconductor material layer can provide an effective transport and extraction channel for photogenerated holes. The built-in electric field of the aforementioned heterojunction or pn junction can be used to promote the transport of photogenerated holes to the p-type semiconductor material. By controlling the gate voltage, especially by applying a negative gate voltage, the channel depletion can be enhanced and the photogenerated holes can be led out through the gate, reducing the residual holes in the channel, thereby suppressing the continuous photoconductivity effect, reducing the current tail, shortening the turn-off time and increasing the device switching frequency.

[0012] (2) Preferably, the wide bandgap semiconductor opto-junction field-effect transistor of the present invention adopts a fin channel structure, which can further enhance the gate's depletion control capability over the channel. The gate, containing a p-type semiconductor material layer, can be depleted from the sidewalls and / or bottom of the fin channel. Compared with existing planar structure devices, this effectively enhances the lateral depletion effect, improves gate control capability, reduces off-state leakage current, and achieves comprehensive optimization of pinch-off characteristics, on-resistance, and off-state leakage current.

[0013] (3) This invention is applicable to a variety of material systems, device structures, and light incidence methods, and its application is flexible. The wide bandgap semiconductor can be selected from, but is not limited to, materials such as GaN, AlGaN, AlN, SiC, β-Ga2O3, and diamond, and is especially suitable for ultra-wide bandgap semiconductors such as gallium oxide, which are difficult to dopant in the p-type. The device structure can be quasi-vertical, fully vertical, lateral, or multi-fin parallel JFET. The light-receiving window can be set on the top, side, or back of the device, or it can be coupled into the device through a transparent electrode or a packaging window. Compared with existing lateral optoelectronic co-control devices, the device of this invention can achieve higher optical gain and better high-voltage reliability. In particular, when this invention is applied to quasi-vertical or fully vertical Fin-JFETs, the low-doped channel or drift region is conducive to enhancing the modulation of the channel conductance by photogenerated carriers, while the electric field in the vertical structure is mainly distributed in the bulk of the material, which is conducive to improving high-voltage reliability.

[0014] (4) The present invention can form a p-type semiconductor material layer by means of low-temperature deposition, magnetron sputtering, secondary epitaxy, selective epitaxy, ion implantation, diffusion or selective doping, depending on different material systems and device structures, and the process route is flexible. In particular, when using p-type oxide semiconductor materials, it can avoid the complex process of traditional p-type epitaxial growth, high-energy ion implantation or high-temperature activation, and improve the process compatibility of three-dimensional fin structure; at the same time, the work function, hole concentration, light absorption characteristics and bandgap matching relationship can be adjusted by material selection and sputtering, annealing, epitaxy or doping processes, thereby optimizing the built-in electric field, depletion region width, hole transport capability and device photoelectric response of heterojunction or pn junction.

[0015] (5) Furthermore, the present invention can also enhance the gate function through a multilayer p-type oxide stacked structure. Compared with a single p-type oxide layer, the multilayer structure can simultaneously adjust the work function, hole concentration, light absorption / transmission characteristics and interface bandgap matching without significantly increasing the thickness of a single film, thereby taking into account channel depletion control, hole extraction, electric field modulation and optical coupling efficiency. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of an epitaxial wafer in one embodiment of the present invention; Figure 2 This is a schematic diagram of the photolithographically defined fin channel region in one embodiment of the present invention; Figure 3 This is a schematic diagram of the structure after etching to form fin-shaped channels in one embodiment of the present invention; Figure 4 This is a schematic diagram of a structure formed by etching multiple fin-shaped channels in one embodiment of the present invention; Figure 5 This is a top view schematic diagram defining the p-type oxide gate formation region and the light incident window region in one embodiment of the present invention; Figure 6 This is a schematic diagram of the three-dimensional structure after a p-type oxide gate is patterned in one embodiment of the present invention; Figure 7 This is one of the cross-sectional schematic diagrams of a p-type oxide gate after patterning in one embodiment of the present invention; Figure 8 This is a second schematic cross-sectional view of a p-type oxide gate after patterning in one embodiment of the present invention; Figure 9 This is a schematic diagram of the three-dimensional structure of a Fin-JFET after depositing source and gate metals in one embodiment of the present invention. Figure 10 This is one of the schematic cross-sectional views of a fully vertically controlled Fin-JFET after depositing source, drain and gate metals in one embodiment of the present invention. Figure 11 This is a second schematic cross-sectional view of a fully vertically controlled Fin-JFET after depositing source, drain, and gate metals in one embodiment of the present invention. Figure 12 This is a schematic diagram of the structure of a fully vertically controlled Fin-JFET after depositing a passivation layer and forming a light incident window in one embodiment of the present invention; Figure 13 This is one of the cross-sectional structural schematic diagrams of a quasi-vertical optoelectronic co-controlled Fin-JFET in one embodiment of the present invention; Figure 14 This is a second schematic cross-sectional view of a quasi-vertical co-controlled Fin-JFET in one embodiment of the present invention; Figure 15 This is a schematic diagram of the quasi-vertical photoelectric co-controlled Fin-JFET structure after depositing a passivation layer and forming a light incident window in one embodiment of the present invention; Figure 16 This is a schematic diagram of the structure of a lateral photoelectric co-controlled Fin-JFET in one embodiment of the present invention; Figure 17 This is a top view schematic diagram of a lateral photoelectric co-controlled Fin-JFET in one embodiment of the present invention; Figure 18 This is a schematic diagram of the structure of a lateral photoelectric co-controlled Fin-JFET after depositing a passivation layer and forming a light incident window in one embodiment of the present invention; Figure 19 This is a schematic diagram of the energy band and carrier transport of a fully vertically integrated optoelectronic Fin-JFET in the illumination-on state according to an embodiment of the present invention. Figure 20 This is a schematic diagram of the energy band and hole extraction of a fully vertically integrated optoelectronic Fin-JFET in an electrically controlled off state according to an embodiment of the present invention. Explanation of reference numerals in the attached figures: 101 is a low-doped drift region or channel layer, 102 is a high-doped layer, 103 is a substrate, 104 is a photoresist or hard mask, 105 is a p-type semiconductor material layer or a p-type semiconductor gate, 106 is a source metal, 107 is a drain metal, 108 is a gate metal, 109 is a buffer layer, 110 is incident light, 111 is photogenerated electrons, 112 is photogenerated holes, and 113 is a passivation layer. Detailed Implementation

[0018] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0019] Some embodiments of the present invention provide a wide bandgap semiconductor opto-junction field-effect transistor, including a wide bandgap semiconductor layer, a conductive channel formed in the wide bandgap semiconductor layer, and a source, drain, and gate connected to the wide bandgap semiconductor layer; and photogenerated carriers can be generated in the wide bandgap semiconductor layer under illumination of light of a selected wavelength. Furthermore, the gate includes a p-type semiconductor material layer, which is disposed on a first region on the surface of the wide bandgap semiconductor layer and forms a heterojunction or pn junction with the wide bandgap semiconductor layer, and is capable of depleting electrons in the conductive channel located below the first region; Furthermore, a light-receiving window is formed on the field-effect transistor, which allows light of the selected wavelength to pass through and illuminate the surface and / or interior of the wide bandgap semiconductor layer.

[0020] Furthermore, the field-effect transistor can adopt a single-fin, multi-fin parallel, quasi-vertical, fully vertical, or lateral structure.

[0021] Furthermore, the p-type semiconductor material layer can be disposed on one sidewall, two sidewalls, bottom, top, or a combination of multiple surfaces of the fin channel to achieve channel depletion control, photogenerated hole extraction, and photoelectric synergistic control.

[0022] For example, one or more fin channels are formed in the wide bandgap semiconductor layer, and the first region includes a local region of the sidewall of the fin channel and / or a local region of the surface of the semiconductor layer on at least one side of the fin channel. By forming a p-type semiconductor material layer in a partial region of the sidewall and / or bottom of the fin channel, a p-type semiconductor / wide bandgap semiconductor heterojunction gate control structure is constructed, which simultaneously possesses channel depletion control, illumination-enhanced conduction, and hole extraction shutdown functions, enabling synergistic optimization of light-controlled on-off and electrical-controlled off-off.

[0023] For example, a plurality of fin-shaped channels are formed in parallel in the wide bandgap semiconductor layer.

[0024] For example, the field-effect transistor includes a lateral field-effect transistor, a fully vertical Fin-JFET, or a quasi-vertical Fin-JFET.

[0025] In one embodiment, the p-type semiconductor material layer is made of an oxide semiconductor material, which includes, but is not limited to, NiO, CuO, Co3O4, SnO, ZnO or other p-type oxides.

[0026] In one embodiment, the material of the p-type semiconductor material layer includes a wide bandgap semiconductor material, which includes GaN, AlGaN, SiC, or other p-type semiconductor materials, and is not limited thereto.

[0027] In some cases, p-type semiconductor material layers can be formed through secondary epitaxy, selected epitaxy, ion implantation, diffusion, selected doping, and other methods.

[0028] In some cases, p-type semiconductor material layers can be single-layer, double-layer, multi-layer stacked, or gradient composition structures to adjust the work function, hole concentration, band matching relationship, and hole extraction efficiency.

[0029] Furthermore, when the p-type semiconductor material layer adopts a multilayer p-type oxide stack structure, the multilayer structure may include p-NiO / p-CuO, p-NiO / p-Cu2O, p-NiO / p-Co3O4, p-CuO / p-NiO, or other p-type oxide stacks, or a combination of a transparent p-type oxide layer, a hole transport enhancement layer, and an electric field modulation layer. Compared to a single-layer p-type oxide layer, the multilayer structure can respectively undertake functions such as light transmission, hole transport, interface barrier modulation, and electric field buffering, thereby improving the degree of freedom in structural design and enhancing the overall performance of the device.

[0030] Preferably, the p-type semiconductor material layer includes a first p-type semiconductor material layer and a second p-type semiconductor material layer sequentially stacked along a direction away from the surface of the wide bandgap semiconductor layer. The bandgap width of the first p-type semiconductor material layer is higher than that of the wide bandgap semiconductor layer, and the bandgap width of the second p-type semiconductor material layer is lower than that of the wide bandgap semiconductor layer. The first p-type semiconductor material layer can serve as a high bandgap interface layer near the channel to maintain a high interface barrier and suppress interface leakage in the off-state. The second p-type semiconductor material layer can serve as a narrow bandgap hole transport layer away from the channel to reduce the equivalent hole transport resistance on the gate side and promote the outflow of photogenerated holes through the gate.

[0031] Preferably, both the first p-type semiconductor material layer and the second p-type semiconductor material layer are made of p-type oxide, which is not only easier to manufacture, but also allows for more flexible adjustment of functional parameters.

[0032] For example, if the wide bandgap semiconductor layer is an n-GaN layer (with a bandgap of about 3.4 eV), then the first p-type semiconductor material layer can be a p-type NiO layer with a bandgap of about 3.6–4.0 eV; the second p-type semiconductor material layer can be a p-type CuO or p-type Cu2O layer with a bandgap of about 1.2–2.2 eV.

[0033] In one embodiment, the material of the wide bandgap semiconductor layer is selected from materials capable of forming fin channels and forming an effective heterojunction or pn junction gate control structure with a p-type semiconductor, thereby realizing channel depletion control, optical control conduction enhancement, and hole extraction assisted turn-off. For example, it can be one or more combinations of wide bandgap / ultra-wide bandgap semiconductor materials such as GaN, AlGaN, AlN, SiC, Ga2O3, and diamond, and is not limited thereto.

[0034] In one embodiment, the light of the selected wavelength includes one or more combinations of ultraviolet light, visible light, or infrared light. For example, it can be a broadband light composed of a combination of ultraviolet light, visible light, infrared light, etc., and preferably light that can be absorbed by a wide bandgap semiconductor channel and generate effective photoelectric modulation.

[0035] In one embodiment, one or more light-receiving windows are provided on the top, bottom, or sidewall of the field-effect transistor. That is, light can enter the field-effect transistor from the top, side, or back, or it can be coupled into the field-effect transistor through an optical waveguide or a package window, such as an optical fiber, waveguide, microlens, LED, laser, package window, or transparent gate.

[0036] For example, the surface of the wide bandgap semiconductor layer has a first region and a second region that do not overlap with each other; the light-receiving window is formed in the second region.

[0037] In one embodiment, the gate further includes a gate metal disposed on a p-type semiconductor material layer. Exemplarily, the gate metal may be an opaque or semi-transparent metal, a transparent conductive oxide, or a combination thereof, such as Ni / Au, Pt / Au, Pd / Au, ITO, AZO, graphene, or a thin-layer metal / transparent conductive layer composite structure, and is not limited thereto.

[0038] Furthermore, the gate can be transparent or semi-transparent.

[0039] In one embodiment, the field-effect transistor further includes a substrate on which the wide bandgap semiconductor layer is disposed. Exemplary examples include, but are not limited to, sapphire substrates, silicon carbide substrates, silicon substrates, gallium nitride substrates, etc.

[0040] In some cases, the wide bandgap semiconductor layer may be a highly doped semiconductor layer and a low-doped drift region or channel layer formed sequentially on the substrate.

[0041] Some embodiments of the present invention also provide a method for fabricating the wide-bandgap semiconductor opto-junction field-effect transistor, comprising: A wide bandgap semiconductor layer is provided, wherein a conductive channel is formed in the wide bandgap semiconductor layer, and photogenerated carriers can be generated in the wide bandgap semiconductor layer under light irradiation of a selected wavelength; A p-type semiconductor material layer is disposed on a first region on the surface of the wide bandgap semiconductor layer to form a gate, and the p-type semiconductor material layer is made to contact and cooperate with the wide bandgap semiconductor layer to form a heterojunction or pn junction, thereby depleting the electrons in the conductive channel located below the first region. Fabricate source and drain electrodes, and connect the source and drain electrodes to the wide bandgap semiconductor layer; Additionally, a light-receiving window is provided on the field-effect transistor, the light-receiving window allowing light of the selected wavelength to pass through and illuminate the surface and / or interior of the wide bandgap semiconductor layer.

[0042] In one embodiment, the method includes: processing one or more fin channels in the wide bandgap semiconductor layer, and depositing the p-type semiconductor material layer on a local area of ​​the sidewall of the fin channel and / or a local area of ​​the surface of the semiconductor layer on at least one side of the fin channel.

[0043] Furthermore, the method may include: fabricating a plurality of parallel fin channels in the wide bandgap semiconductor layer.

[0044] In one embodiment, the method includes: disposing the source at the top of the fin channel, disposing the drain on the surface of a semiconductor layer on at least one side of the fin channel, and disposing the gate between the source and the drain, thereby forming a quasi-vertical Fin-JFET structure.

[0045] In one embodiment, the method includes: processing one or more fin channels on a first surface of the wide bandgap semiconductor layer, and placing the source electrode at the top of the fin channel, while placing the drain electrode on a second surface of the wide bandgap semiconductor layer, wherein the first surface and the second surface are disposed opposite to each other, thereby forming a fully vertical Fin-JFET structure.

[0046] In one embodiment, the method includes: forming a gate, a drain, and a source on the same side surface of the wide bandgap semiconductor layer, with the gate positioned between the source and the drain, thereby forming a lateral JFET structure.

[0047] For example, the method may specifically include: A first region and a second region that do not overlap with each other are defined on the surface of the wide bandgap semiconductor layer; A p-type semiconductor material layer is disposed in the first region, and a light-receiving window is disposed in the second region.

[0048] In one embodiment, the method includes: patterning a p-type semiconductor material layer using processes such as sputtering, secondary epitaxy, selected area epitaxy, or selected area doping. Specifically, for p-type oxide semiconductor materials, magnetron sputtering, reactive sputtering, radio frequency sputtering, DC sputtering, pulsed laser deposition, atomic layer deposition, chemical vapor deposition, electron beam evaporation, thermal evaporation, or other thin film deposition processes can be used; for p-type wide bandgap semiconductor materials, secondary epitaxy, selected area epitaxy, ion implantation, diffusion, or selected area doping can be used. In this invention, the selection can be based on the requirements for device structure and performance, combined with the three-dimensional coverage capability, deposition or epitaxial temperature, thin film quality, doping controllability, and process compatibility of the aforementioned processes.

[0049] In a more specific embodiment, a method for fabricating a co-controlled Fin-JFET using magnetron sputtered p-type oxide as the gate is provided, which includes the following steps: S1. A semiconductor epitaxial wafer is provided, comprising a substrate 103, a highly doped semiconductor layer 102 on the substrate, and a low-doped drift region or channel layer 101 on the highly doped semiconductor layer, such as... Figure 1 As shown. The semiconductor epitaxial wafer is then subjected to relevant cleaning, surface treatment, and necessary interface repair. The materials of the low-doped drift region or channel layer 101 and the high-doped semiconductor layer 102 can be selected from GaN, AlGaN, AlN, SiC, β-Ga2O3, diamond, or other wide-bandgap or ultra-wide-bandgap semiconductor materials.

[0050] S2. A patterned photoresist or hard mask 104 is formed using photolithography to define fin-shaped channels in the low-doped drift region or channel layer 101, such as... Figure 2 As shown.

[0051] S3. Etch the low-doped drift region or channel layer 101 using ICP, RIE, or other dry etching processes to form one or more fin-shaped channels, such as... Figure 3 or Figure 4 As shown. The sidewalls of the fin-shaped channel can be vertical sidewalls or inclined sidewalls with a certain angle (>0° and <90°, preferably ≥45°).

[0052] S4. After forming the fin channel, the sidewalls of the fin channel can be subjected to wet etching, low-damage etching, plasma treatment, thermal annealing, chemical cleaning, or surface passivation to reduce etching damage, decrease sidewall interface states, and improve the interface quality of the p-type semiconductor / wide bandgap semiconductor heterojunction. Subsequently, a patterned photoresist 104 is formed using photolithography to define the deposition area of ​​the p-type semiconductor material layer, such as... Figure 5 As shown. It should be noted that, Figure 5This is a top view showing the coverage of the patterned photoresist 104 in the top, sidewall, and bottom regions of the fin channel, where the areas not subsequently covered by the p-type semiconductor can serve as light incident windows.

[0053] S5. A p-type semiconductor material is deposited across the entire surface of the fin channel using magnetron sputtering, and the previously patterned photoresist is stripped away, resulting in a p-type semiconductor material layer 105 deposited on a portion of the fin channel sidewalls and the surface of the semiconductor layers on both sides of the fin channel (referred to as the bottom). Figure 6 As shown. p-type semiconductor materials can be p-type oxides such as p-type NiO, p-type CuO, p-type Co3O4, and p-type SnO, or they can be p-type semiconductors formed by secondary epitaxy p-GaN, selected area epitaxy p-type semiconductors, ion implantation, or selected area doping. Their thickness, composition, and carrier concentration can be controlled by process parameters such as deposition, epitaxy, doping, and annealing.

[0054] Preferably, the p-type semiconductor material layer deposited in this step can be a multilayer p-type oxide stack. For example, a first p-type oxide layer can be deposited near the fin channel interface to form a stable heterojunction interface and enhance channel depletion; then a second p-type oxide layer can be deposited to improve hole transport capability, adjust work function, or improve optical transmittance. By adjusting the material, thickness, oxygen partial pressure, and annealing conditions of each layer, the multilayer structure can achieve stronger gate depletion capability, lower gate equivalent resistance, and better photogenerated hole extraction efficiency compared to the single-layer structure.

[0055] It should be noted that, Figure 6 Only the distribution of the p-type semiconductor material layer 105 on the right side of the fin channel is shown; the distribution on the left side of the fin channel is symmetrical. Along the length of the fin channel, at different cross-sectional locations, the areas on the sidewalls and bottom of the fin channel covered by p-type oxide are the gate control regions, such as... Figure 7 As shown. The areas on the sidewalls and part of the bottom of the finned channel not covered by the p-type semiconductor material layer 105 can serve as light incident windows, such as... Figure 8 As shown.

[0056] S6. Source metal 106 and drain metal 107 are deposited in the source and drain regions of the device formed in step S5, respectively, and ohmic contacts are formed through an annealing process. Then, gate metal 108 is deposited on the p-type semiconductor material layer 105 through evaporation, sputtering, or other metal deposition processes, so that the gate metal and the p-type semiconductor material form an electrical contact, such as... Figure 9 , Figure 10 and Figure 11 As shown. Preferably, an ohmic contact or a low-resistance contact is formed between the p-type oxide and the gate metal to facilitate the extraction of photogenerated holes through the p-type oxide gate.

[0057] S7. Finally, a passivation layer 113 is deposited on the device formed in step S6, and a light incident window is formed above the gate or in other selected areas on the device, such as... Figure 12 As shown.

[0058] Furthermore, the fabrication method may include conventional processes such as surface treatment, sidewall repair, ohmic contact, dielectric passivation, field plate deposition, transparent electrode deposition, light incident window opening, annealing, and encapsulation, which will not be elaborated here.

[0059] This fabrication method involves depositing a p-type semiconductor material layer on a portion of the sidewalls and / or bottom of a fin channel made of a wide-bandgap semiconductor material, forming a heterojunction or pn junction gate control structure with the fin channel. This structure enhances the lateral depletion effect of the fin channel, improves gate control capability, and reduces off-state leakage current. It also suppresses the electric field congestion effect during reverse bias, reduces local peak electric field, and thus improves the breakdown characteristics of the device. Furthermore, it serves as a transport and extraction channel for photogenerated holes, promoting the extraction of residual holes during turn-off, thereby achieving low conduction loss and fast turn-off.

[0060] Some embodiments of the present invention also provide a method of using the wide-bandgap semiconductor opto-junction field-effect transistor (hereinafter referred to as the device), including: A first set voltage is applied to the gate, and light of a selected wavelength is irradiated through the light-receiving window to illuminate the surface and / or interior of the wide bandgap semiconductor layer, thereby turning on the device; Alternatively, a second set voltage is applied to the gate, and at least a portion of the photogenerated carriers in the wide bandgap semiconductor layer are removed using the gate as a extraction channel, thereby turning off the device. Wherein, the first set voltage is greater than the second set voltage.

[0061] In some cases, the first set voltage is ≥0, the second set voltage is ≤0, and preferably <0.

[0062] Specifically, when the device is turned on, the incident light generates photogenerated carriers, which increases the channel conductivity, reduces the on-resistance, and increases the output current. When the device is turned off, the built-in electric field of the heterojunction or pn junction and the applied gate bias voltage together promote the transport of photogenerated holes to the p-type semiconductor gate and out through the gate metal, thereby suppressing the continuous photoconductivity effect, shortening the turn-off time, and increasing the switching frequency.

[0063] Furthermore, taking a fully vertical junction field-effect transistor with a fin channel as an example, the electrically controlled depletion of the fin channel can be achieved using a heterojunction or pn junction formed by a p-type semiconductor material layer and a wide bandgap semiconductor layer. The width of the depletion region can be adjusted by the built-in electric field and the applied gate voltage, allowing the fin channel to be in an on, partially on, or pinch-off state, thereby reducing off-state leakage current, adjusting pinch-off characteristics, and improving device turn-off performance. Illumination can also control the device's on-state. (See also...) Figure 19 Under illumination, incident light of a selected wavelength can act on a p-type semiconductor material layer, a fin channel, or the interface between the two, generating photogenerated carriers (including photogenerated electrons and holes), thereby increasing channel conductivity, reducing on-resistance, and boosting output current. Furthermore, the gate containing the p-type semiconductor material layer can be used as a transport and extraction channel for photogenerated holes. When illumination is removed or the device is turned off, the built-in electric field of the heterojunction or pn junction and the applied gate bias promote the transport of photogenerated holes to the p-type semiconductor material layer and their extraction through the gate metal, thereby reducing residual holes in the channel, suppressing persistent photoconductivity, reducing current tailing, and improving turn-off speed and switching frequency. For an example, please refer to [link to example]. Figure 20 At gate bias V G <0, drain bias voltage V D When the value is greater than 0, the photogenerated holes in the channel can be rapidly extracted and exported through the p-type semiconductor material layer and the gate metal.

[0064] The technical solutions of this application are further described in detail below with reference to several specific embodiments.

[0065] Example 1 This example provides a GaN-based fully vertically controlled Fin-JFET, the structure of which can be found in [reference needed]. Figure 12 The fabrication method of this Fin-JFET includes the following steps: A highly doped n-type GaN layer 102 and a lightly doped n-type GaN drift region or channel layer 101 are sequentially epitaxially grown on a conductive GaN substrate 103 to form a GaN-based epitaxial wafer. The highly doped n-type GaN layer 102 has a thickness of approximately 1 μm and an electron concentration of approximately 1 × 10⁻⁶. 18 cm -3 This is used to reduce series resistance and form good ohmic contacts; the thickness of the lightly doped n-type GaN layer 101 is approximately 5 μm, and the electron concentration is approximately 1 × 10⁻⁶. 16 cm -3The fins are used to bear the main blocking voltage and form fin channels. Before wafer fabrication, the epitaxial wafer is first cleaned, and then fin channels are formed on the front side of the epitaxial wafer through photolithography and etching processes. The width of the fin channel is about 1 μm, the height is about 2 μm, and the length is about 50 μm; in the multi-fin parallel structure, the spacing between adjacent fin channels is about 1.5 μm. Then, wet processing is used to repair the sidewalls of the fin channels to reduce etching damage and interface states. Subsequently, a patterned photoresist 104 is formed by photolithography to define the source region of the fin channel and the light incident windows of the sidewalls and bottom of the fin channel. Then, a p-type NiO layer is deposited as the p-type semiconductor material layer 105 by magnetron sputtering, and patterning is achieved by a lift-off process. The thickness of the p-type semiconductor material layer 105 is about 100 nm. Finally, source metal 106, drain metal 107, and gate metal 108 are deposited to form a fully vertical current transport path. The source metal 106 and drain metal 107 are Ti / Al / Ni / Au metal stacks with thicknesses of approximately 30 nm / 100 nm / 50 nm / 100 nm, respectively, and are formed into ohmic contacts through annealing; the gate metal 108 is a Ni / Au metal stack with thicknesses of approximately 30 nm / 100 nm, respectively, and is used to form electrical contacts with the p-type semiconductor material layer 105.

[0066] Comparative Example 1: The structure and fabrication method of the GaN-based fully vertical Fin-JFET provided in this comparative example are basically the same as those in Example 1, except that: no p-type NiO layer is deposited as the p-type semiconductor material layer 105.

[0067] Compared to Comparative Example 1, the p-type NiO layer introduced in Example 1 can form a p-type semiconductor / GaN heterojunction gate control structure with the n-type GaN fin channel, thereby enhancing the lateral depletion capability of the fin channel, reducing off-state leakage current, and providing transport and extraction channels for holes. In the illumination-on state, Example 1 can improve channel conductivity, reduce on-resistance, and increase output current through photogenerated carriers; in the off state, the p-type NiO layer can promote photogenerated hole extraction under the influence of the built-in electric field of the heterojunction or pn junction and the applied gate voltage, thereby suppressing the continuous photoconductivity effect, reducing current tailing, and shortening the turn-off time.

[0068] Under the same test conditions, Example 1 exhibits lower off-state leakage current, faster turn-off speed, and weaker current tail compared to Comparative Example 1. Based on the one-dimensional depletion approximation and the first-order carrier extraction model, under the same epitaxial structure, the same fin channel size, a drain bias of 100 V, and a turn-off gate voltage... 5 V, and 365 nm, 10 mW / cm 2Under the condition of illumination followed by removal of illumination, the off-state leakage current of Example 1 can be reduced by more than 90% compared to Comparative Example 1, the current tail amplitude after illumination removal can be reduced by more than 60%, and the turn-off time can be shortened by more than 50%. This is because the built-in electric field formed by the p-type NiO / GaN heterojunction can enhance the lateral depletion of the fin channel, reducing the equivalent conductive cross-sectional area in the off-state; simultaneously, the p-type NiO layer provides a gate extraction channel for photogenerated holes, thus reducing the effective clearance time constant of residual photogenerated holes.

[0069] The above-mentioned quantitative values ​​are theoretical estimates based on device structure, channel doping concentration, depletion width and carrier extraction path. They can be used as the expected performance improvement of this embodiment relative to Comparative Example 1, and do not limit the actual performance parameters of the present invention. The actual values ​​can be adjusted with changes in p-type NiO layer thickness, fin channel size, light intensity and gate bias conditions.

[0070] Example 2 This example provides a GaN-based vertical optoelectronic co-controlled Fin-JFET, the structure of which can be found in [reference]. Figure 15 The fabrication method of this Fin-JFET includes the following steps: A highly doped n-type GaN layer 102 and a lightly doped n-type GaN drift region or channel layer 101 are sequentially epitaxially grown on a SiC substrate 103 to form a GaN reference vertical epitaxial wafer. The highly doped n-type GaN layer 102 has a thickness of approximately 1 μm and an electron concentration of approximately 1 × 10⁻⁶. 18 cm -3 It is used to reduce contact resistance and serve as a current spreading layer; the thickness of the lightly doped n-type GaN drift region 101 is approximately 10 μm, and the electron concentration is approximately 1 × 10⁻⁶. 16 cm -3 The fins are used to bear the main blocking voltage and form fin channels. Before the wafer fabrication process begins, the epitaxial wafer is first cleaned; then, fin channels are formed on the front side of the epitaxial wafer through photolithography and etching processes. The width of the fin channel is approximately 0.5 μm, the height is approximately 3 μm, and the length is approximately 30 μm. In the multi-fin parallel structure, the spacing between adjacent fin channels is approximately 2 μm. Next, the drain region is further etched down to the highly doped n-type GaN layer 102 through photolithography and dry etching to form a quasi-vertical current transport path. Subsequently, a low-damage atomic layer etching process is used to repair the sidewalls of the fin channels to reduce etching damage and sidewall interface states.

[0071] Subsequently, a patterned photoresist 104 is formed using photolithography to define the source region of the fin channel and the light incident windows located on the sidewalls and bottom of the fin channel. Then, a p-type NiO layer is deposited as the p-type semiconductor material layer 105 using magnetron sputtering, and the p-type NiO is patterned using a lift-off process. The thickness of the p-type semiconductor material layer 105 is approximately 50 nm.

[0072] Then, source metal 106, drain metal 107, and gate metal 108 are deposited sequentially to form a device structure as shown in the figure. Figure 13 and Figure 14 As shown in the diagram, the source metal 106 and drain metal 107 are Ti / Al / Ni / Au metal stacks with thicknesses of approximately 25 nm / 100 nm / 50 nm / 100 nm, respectively, and are formed into ohmic contacts through rapid thermal annealing. The gate metal 108 is a Ni / Au metal stack with thicknesses of approximately 30 nm / 150 nm, used to form an electrical contact with the p-type semiconductor material layer 105.

[0073] Finally, a passivation layer 113 is deposited on the device, and a light incident window is formed above the gate or in other selected areas on the device, such as... Figure 15 As shown.

[0074] In this embodiment, the substrate 103 can also be replaced with a sapphire substrate or a Si substrate, etc.

[0075] Comparative Example 2: The structure and fabrication method of the GaN-based vertical optoelectronic co-controlled Fin-JFET provided in this comparative example are basically the same as those in Example 2, except that a p-type NiO layer is not formed on the sidewalls and bottom of the fin channel, i.e., no p-type semiconductor material layer 105 is provided. Based on the one-dimensional depletion approximation and the first-order carrier extraction model, under the same epitaxial structure, the same fin channel size, a drain bias of 100 V, and a turn-off gate voltage... 5 V, and 365 nm, 10 mW / cm 2 Under the condition of illumination followed by removal of illumination, the off-state leakage current of Example 2 can be reduced by more than 90% compared to Comparative Example 2, the current tail amplitude after illumination removal can be reduced by more than 60%, and the turn-off time can be shortened by more than 50%. This is because the p-type NiO layer enhances the lateral depletion of the quasi-vertical fin channel and shortens the transport path of residual photogenerated holes to the gate.

[0076] The above-mentioned quantitative values ​​are theoretical estimates based on the device structure and working mechanism, and can be used as the expected performance improvement of this embodiment relative to Comparative Example 2; the actual values ​​can be adjusted with changes in light intensity, gate bias, passivation layer window size and p-type NiO layer thickness.

[0077] Example 3 This example provides a SiC-based optoelectronic co-controlled Fin-JFET, the structure of which can be found in [reference needed]. Figure 12 The fabrication method of this Fin-JFET includes the following steps: A highly doped n-type SiC layer 102 and a lightly doped n-type SiC drift region or channel layer 101 are sequentially formed on a conductive n-type 4H-SiC substrate 103 to form a SiC-based epitaxial wafer. The thickness of the 4H-SiC substrate 103 is approximately 350 μm; the thickness of the highly doped n-type SiC layer 102 can be 1 μm, with an electron concentration of approximately 1 × 10⁻⁶. 18 cm -3 It is used to reduce contact resistance and form a current spreading layer; the thickness of the low-doped n-type SiC drift region or channel layer 101 is about 10 μm, and the electron concentration is about 1×10⁻⁶. 16 cm -3 It is used to bear the main blocking voltage and form a finned channel.

[0078] Subsequently, SiC fin channels are formed in the low-doped n-type SiC drift region or channel layer 101 using photolithography and etching processes. The fin channels have a width of approximately 2 μm, a height of approximately 5 μm, and a length of approximately 100 μm. In the multi-fin parallel structure, the spacing between adjacent fin channels is approximately 10 μm.

[0079] After forming the fin channel, the sidewalls of the fin channel are oxidized to reduce etching damage and sidewall interface states. Then, a patterned photoresist 104 is formed using photolithography to define the source region of the fin channel and the light incident windows located on the sidewalls and bottom of the fin channel. Next, a p-type NiO layer is deposited as the p-type semiconductor material layer 105 using magnetron sputtering, and the p-type NiO is patterned using a lift-off process. The thickness of the p-type semiconductor material layer 105 is approximately 200 nm.

[0080] Subsequently, source metal 106, drain metal 107, and gate metal 108 are deposited to form an all-vertical current transport path. Among them, source metal 106 and drain metal 107 adopt Ni / Au metal stack with thicknesses of approximately 100 nm and 300 nm, respectively, and form n-type SiC ohmic contacts through high-temperature annealing; gate metal 108 adopts Ti / Au metal stack with thicknesses of approximately 50 nm and 150 nm, respectively, and is used to form electrical contacts with p-type semiconductor material layer 105.

[0081] Comparative Example 3 This comparative example provides a SiC-based optoelectronic co-control Fin-JFET, whose structure and fabrication method are basically the same as those of Example 3, except that: instead of depositing a p-type NiO layer as a p-type semiconductor material layer 105, a p-type gate region 105 is formed on the sidewall and bottom of the fin channel by ion implantation and high-temperature activation.

[0082] Compared to Comparative Example 3, Example 3 uses magnetron sputtering of a p-type NiO layer to form a heterojunction gate, which avoids lattice damage to the SiC fin channel sidewalls caused by high-energy ion implantation and reduces the risk of interface degradation caused by the high-temperature activation process. Simultaneously, the p-type NiO layer can form a p-type semiconductor / SiC heterojunction gate control structure with the n-type SiC fin channel, thereby achieving channel depletion control and providing transport and extraction channels for holes.

[0083] Under the same test conditions, Example 3 is expected to exhibit lower sidewall interface state density, lower off-state leakage current, weaker current tail, and faster turn-off speed compared to Comparative Example 3. Theoretical estimations were made based on the same SiC epitaxial structure and the same fin channel size, with a drain bias of 100 V and a turn-off gate voltage... 5 V, and 365 nm, 10 mW / cm 2 Under the condition of illumination followed by removal of illumination, Example 3, compared to Comparative Example 3, shows a reduction of over 50% in sidewall interface state density, over 80% in off-state leakage current, over 50% in current tail amplitude after illumination removal, and over 40% in turn-off time. This is because magnetron sputtering of p-type NiO avoids direct damage to the SiC fin sidewalls caused by high-energy ion implantation, while retaining the heterojunction's lateral depletion and photogenerated hole extraction functions.

[0084] Example 4 This example provides a gallium oxide-based vertically controlled photoelectric Fin-JFET, the structure of which can be found in [reference needed]. Figure 12 The fabrication method of this Fin-JFET includes the following steps: A highly doped n-type β-Ga2O3 layer 102 and a lightly doped n-type β-Ga2O3 drift region (or channel layer) 101 are sequentially formed on a conductive n-type β-Ga2O3 substrate 103 to form a β-Ga2O3-based epitaxial wafer. The thickness of the β-Ga2O3 substrate 103 is approximately 500 μm; the thickness of the highly doped n-type β-Ga2O3 layer 102 is approximately 1 μm, and the electron concentration is approximately 1 × 10⁻⁶. 18 cm -3 It is used to reduce contact resistance and form a current spreading layer; the thickness of the low-doped n-type β-Ga2O3 drift region (or channel layer) 101 is approximately 12 μm, and the electron concentration is approximately 1 × 10⁻⁶. 16 cm -3 It is used to bear the main blocking voltage and form a finned channel.

[0085] Subsequently, fin-shaped channels are formed in the low-doped n-type β-Ga2O3 drift region or channel layer 101 using photolithography and etching processes. The width of the fin-shaped channel is approximately 0.1 μm, the height is approximately 0.5 μm, and the length is approximately 5 μm; in the multi-fin parallel structure, the spacing between adjacent fin-shaped channels is approximately 0.2 μm. After forming the fin-shaped channels, the sidewalls of the fin-shaped channels are subjected to wet etching to reduce etching damage and sidewall interface states.

[0086] Subsequently, a patterned photoresist 104 is formed using photolithography to define the source region of the fin channel and the light incident windows located on the sidewalls and bottom of the fin channel. Then, a p-type NiO layer is deposited as the p-type semiconductor material layer 105 using magnetron sputtering, and the p-type NiO is patterned using a lift-off process. The thickness of the p-type semiconductor material layer 105 is approximately 50 nm.

[0087] Subsequently, source metal 106, drain metal 107, and gate metal 108 are deposited to form a fully vertical current transport path. The source metal 106 and drain metal 107 are Ti / Al / Ni / Au metal stacks with thicknesses of approximately 50 nm / 150 nm / 80 nm / 200 nm, respectively, and are annealed to form ohmic contacts. The gate metal 108 is a Ti / Au metal stack with thicknesses of approximately 50 nm / 80 nm, used to form electrical contacts with the p-type semiconductor material layer 105.

[0088] Forming stable and effective p-type doping in β-Ga2O3 material is quite difficult. In this embodiment, an externally formed p-type oxide is used as the heterojunction gate, which enables depletion control of the fin channel. Compared with p-type doping schemes such as ion implantation, diffusion, or selected area doping, this structure reduces process complexity and thermal budget, minimizes fin channel sidewall damage and interface state introduction, thereby reducing off-state leakage current and improving gate control stability. Simultaneously, the p-type oxide gate can also serve as a transport and extraction channel for photogenerated holes, suppressing persistent photoconductivity and current tailing, and improving device turn-off speed and dynamic response characteristics. In this embodiment's Fin-JFET, the low-doped drift region bears the main blocking voltage, and the electric field is mainly distributed within the material, which is beneficial for improving device breakdown voltage and high-voltage reliability. When the Fin-JFET of this embodiment is turned on, the current flows from the front source through the fin channel and the longitudinal drift region to the back drain.

[0089] In this embodiment, the thickness of the β-Ga2O3 substrate can be adjusted within the range of 100–700 μm.

[0090] Example 5 This example provides a gallium oxide-based lateral photoelectric control JFET, the structure of which can be found in [reference needed]. Figures 16-18 The fabrication method of this JFET includes the following steps: A high-resistivity β-Ga2O3 layer 109 and a lightly doped n-type β-Ga2O3 channel layer 101 are formed on a β-Ga2O3 substrate 103. A patterned photoresist 104 is formed using photolithography to define the gate region and the light incident window of the channel. Then, a p-type NiO layer is deposited as the p-type semiconductor material layer 105 using magnetron sputtering, and the p-type NiO is patterned using a lift-off process. Subsequently, source metal 106, drain metal 107, and gate metal 108 are deposited to form a lateral current transport path. The thickness of the β-Ga2O3 substrate 103 is approximately 300 μm; the thickness of the high-resistivity β-Ga2O3 layer 109 is approximately 5 μm; and the thickness of the lightly doped n-type β-Ga2O3 channel layer 101 is approximately 15 μm, with an electron concentration of approximately 1 × 10⁻⁶. 16 cm -3 The p-type semiconductor material layer 105 has a thickness of approximately 200 nm and a comb-like structure. The source metal 106, drain metal 107, and gate metal 108 are made of essentially the same material and have the same thickness as in Example 4.

[0091] The JFET in this embodiment has a lateral structure, which facilitates the formation of a light incident window and a patterned gate on the device surface, enabling coordinated control of light-controlled turn-on and electrically controlled turn-off. Especially for β-Ga2O3, a material difficult to dope with p-type, using an externally formed p-type oxide as a heterojunction gate allows for channel depletion control and hole extraction while avoiding direct p-type doping. Compared to p-type doping methods such as ion implantation, diffusion, or selected area doping, the external p-type oxide heterojunction gate reduces the process thermal budget, avoids lattice damage to the β-Ga2O3 channel and interface caused by high-energy implantation, and reduces leakage current and carrier trapping effects caused by defect states. Therefore, this embodiment is expected to exhibit lower off-state leakage current, more stable gate control characteristics, weaker sustained photoconductivity, and faster turn-off speed. Simultaneously, the p-type oxide / β-Ga2O3 heterojunction can also adjust the electric field distribution at the gate edge and channel surface, reducing local peak electric fields, thereby improving device breakdown voltage and high-voltage reliability.

[0092] Comparative Example 5 This comparative example provides a β-Ga2O3-based lateral photoelectric co-control JFET, whose structure and fabrication method are basically the same as those of Example 5. The difference is that: this comparative example does not use an externally formed p-type oxide as a heterojunction gate, but instead uses ion implantation, diffusion or selective doping to form a p-type gate region 105 in the β-Ga2O3 channel region 101.

[0093] Compared to Comparative Example 5, this embodiment uses an external p-type oxide as the heterojunction gate, which avoids problems such as difficulties in p-type doping in β-Ga2O3, low acceptor activation efficiency, and high-energy injection damage. This structure not only enables channel depletion control but also provides transport and extraction channels for holes, thereby reducing persistent photoconductivity and current tailing. Theoretical estimations were performed based on the same channel thickness, gate length, and illumination conditions, with a drain bias of 50 V and a turn-off gate voltage... 5 V, and 365nm, 10 mW / cm 2 Under the condition of illumination followed by removal of illumination, Example 5, compared to Comparative Example 5, shows a reduction of over 90% in off-state leakage current, a reduction of over 30% in threshold or pinch-off voltage drift, a reduction of over 60% in current tail amplitude after illumination removal, and a reduction of over 50% in turn-off time. The aforementioned performance improvements can be adjusted based on the type and thickness of the p-type oxide material, work function, channel doping concentration, channel length, illumination intensity, and gate bias conditions.

[0094] Example 6 This example provides a multi-fin parallel-connected optoelectronic co-controlled Fin-JFET, whose structure is similar to that of Example 1, except that the Fin-JFET has five parallel-distributed fin channels, and the multiple fin channels are connected in parallel. Each fin channel has a width of 1 μm, a height of 2 μm, and a length of 50 μm. The spacing between adjacent fin channels is 1.5 μm, and the p-type semiconductor material layer 105 is a 100 nm thick p-type NiO layer. The fabrication method of this Fin-JFET is also similar to that of Example 1, except that five parallel-distributed fin channels are formed in the low-doped n-type GaN layer 101 through photolithography and etching processes, such as... Figure 4 As shown. Subsequently, a p-type semiconductor material layer 105 is deposited and patterned on the sidewalls and / or bottom of each fin channel, so that multiple fin channels are controlled by the same gate or multiple gates.

[0095] In this embodiment, a five-fin parallel structure is used to increase the effective channel width, reduce the device's on-resistance, and improve the output current capability. Based on theoretical estimations using the same single-fin size, the effective channel width of the five-fin parallel structure is approximately five times greater than that of a single-fin structure. Considering factors such as contact resistance and uneven current distribution at the edge fins, the device's on-state current can be increased by more than three times, and the on-resistance can be reduced by more than 60%. Simultaneously, each fin channel can be laterally depleted by the p-type semiconductor gate 105, which helps to maintain low off-state leakage current and a faster turn-off speed while improving current capability.

[0096] Example 7 This example provides a GaN-based optoelectronic co-control Fin-JFET, whose structure is basically the same as that of Example 1, except that the p-type semiconductor material layer 105 is a p-GaN layer 105 formed by selected area epitaxy or secondary epitaxy. The thickness of the p-GaN layer 105 is 100 nm, and the Mg doping concentration is 5 × 10⁻⁶. 19 cm -3 The effective hole concentration at room temperature is 1×10 17 cm -3 .

[0097] The fabrication method of this Fin-JFET is similar to that of Example 1, except that after forming the fin channel and completing the sidewall repair, a p-GaN layer 105 is formed in a portion of the sidewall and / or bottom of the fin channel as a p-type semiconductor material layer 105 by selective epitaxy or secondary epitaxy.

[0098] In this embodiment, the p-GaN105, which is selectively epitaxial or epitaxially layered, can form a homogeneous pn junction gate control structure with the n-type GaN fin channel, exhibiting strong depletion control capability and good bandgap matching. Based on theoretical estimation using the same fin channel size and turn-off bias as in Embodiment 1, this embodiment, compared to the control device without a p-type semiconductor gate, can reduce the off-state leakage current by more than 90% and shorten the turn-off time by more than 40%. When illumination is removed or the device is turned off, the p-GaN gate105 can serve as a transport and extraction channel for photogenerated holes, thereby reducing the continuous photoconductivity effect and improving the turn-off speed.

[0099] In contrast, using p-type oxides such as p-NiO105 as heterojunction gates offers advantages such as lower processing temperature, lower cost, and simpler fabrication process. It also reduces the impact of the high-temperature secondary epitaxial process on the sidewalls and interfaces of the fin channel and facilitates the formation of patterned gate control regions on the sidewalls and bottom of complex three-dimensional fin structures. The thickness, work function, hole concentration, and resistivity of p-NiO can be adjusted through sputtering and annealing processes, thereby controlling the channel depletion level, photogenerated hole extraction efficiency, and local electric field distribution. For optoelectronic devices, the p-NiO105 gate can also serve as a fast transport and extraction channel for photogenerated holes, helping to suppress persistent photoconductivity and current tailing, and improving turn-off speed and dynamic response characteristics. Therefore, p-GaN gates are more advantageous for obtaining high-quality homogeneous pn junctions and stable depletion control; while p-NiO gates are more advantageous for achieving low-temperature three-dimensional coverage, adjustable work function, flexible electric field modulation, and fast photogenerated hole extraction, especially suitable for complex fin structures and wide / ultra-wide bandgap semiconductor material systems where p-type doping is difficult.

[0100] Example 8 This example provides a GaN-based optoelectronic co-control Fin-JFET, whose structure and fabrication method are basically the same as those in Example 1, except that a p-type CuO layer is used as the p-type semiconductor material layer 105 instead of the p-type NiO layer. This p-type CuO layer can be formed by magnetron sputtering, reactive sputtering, or radio frequency sputtering processes.

[0101] The p-type CuO105 used in this embodiment possesses p-type conductivity and a high work function, enabling it to form heterojunction gate structures with wide-bandgap semiconductors such as GaN, SiC, and β-Ga2O3. By adjusting the sputtering power, oxygen partial pressure, deposition temperature, and annealing conditions of CuO, its hole concentration and work function can be controlled, thereby optimizing channel depletion, photogenerated hole extraction, and device photoelectric response. Compared to p-type NiO, p-type CuO exhibits differences in work function, carrier concentration, resistivity, band structure, and optical absorption characteristics; therefore, the heterojunction barrier height, depletion region width, and hole transport capability formed by it can also differ. Based on theoretical estimations using the same fin channel size and the same illumination conditions, in some embodiments, the p-type CuO layer 105 can reduce the equivalent resistance of photogenerated hole extraction by more than 30% compared to the p-type NiO layer 105, reduce the current tail amplitude after illumination removal by more than 20%, and shorten the turn-off time by more than 20%. The actual improvement can be adjusted according to changes in the resistivity, work function, and interface quality of the CuO thin film.

[0102] Example 9 This example provides a GaN-based co-controlled Fin-JFET with a multilayer p-type oxide gate. Its structure and basic fabrication method are similar to those of Example 1, except that the p-type semiconductor material layer 105 adopts a multilayer p-type oxide stacked structure. Specifically, a p-type NiO layer with a thickness of approximately 30 nm (as part of the p-type semiconductor material layer 105) is disposed near the n-type GaN fin channel, and a p-type CuO or p-type Cu2O layer with a thickness of approximately 70 nm (as part of the p-type semiconductor material layer 105) is disposed above this p-type NiO layer. Under the same test conditions, based on the one-dimensional depletion approximation and the first-order carrier extraction model, and with the same epitaxial structure, the same fin channel size, a drain bias of 100 V, and a turn-off gate voltage... 5 V, and 365 nm, 10 mW / cm 2 Under conditions of illumination followed by removal of illumination, compared to the device in Example 1, the device in Example 9 exhibits a reduction of over 20% in off-state leakage current, a reduction of over 30% in current tail amplitude after illumination removal, and a reduction of over 30% in turn-off time. The above quantitative values ​​are theoretical estimates based on the high bandgap layer at the interface and the low-resistance hole transport layer in the multilayer p-type oxide stacked structure. They are used to illustrate the expected improvement trend of this embodiment compared to a single-layer p-type NiO gate structure and do not limit the actual performance parameters of the present invention.

[0103] It should be noted that the dimensions of the multiple structural layers in the above embodiments can also be adjusted according to the device's breakdown voltage, on-resistance, gate control capability, and light incident window area. Specifically, the thickness of the low-doped n-type GaN layer in Embodiment 1 or the low-doped n-type GaN drift region (or channel layer) 101 in Embodiment 2 can be 2–20 μm. The width of the fin channel can be 0.1–2 μm, the height can be 0.2–5 μm, and the length can be 1–100 μm. In the multi-fin parallel structure, the spacing between adjacent fin channels can be 0.2–10 μm. After forming the fin channel, the sidewalls of the fin channel can be oxidized, wet-etched, annealed, plasma-treated, or surface-passivated to reduce etching damage and sidewall interface states. The thickness of the p-type semiconductor material layer 105 can be 5–500 nm, preferably 50–200 nm, and its thickness can be adjusted according to the channel depletion capability, hole extraction efficiency, and process coverage. The source and drain metals can also be Ni / Au metal stacks (thicknesses of 10–100 nm / 50–300 nm, respectively), Ti / Al / Ni / Au, Ti / Al / Ti / Au or Ni / Ti / Al / Au metal stacks (thicknesses of 10–50 nm / 50–300 nm / 20–100 nm / 50–300 nm, respectively).

[0104] Based on the above embodiments of the present invention, it can be seen that the gate structure of the optoelectronic co-controlled power transistor provided by the present invention has a strong channel depletion control capability. At the same time, the transistor has low conduction loss, high optical gain, high breakdown voltage and good high voltage reliability, and has a fast turn-off capability after the light is removed. Therefore, it can well meet the needs of high frequency and high power applications. In addition, its fabrication process should be simple and flexible, and its application prospects are broad.

[0105] In addition to the above embodiments, the present invention may have other implementation methods; all technical solutions formed by equivalent substitution or equivalent transformation fall within the protection scope claimed by the present invention.

Claims

1. A wide bandgap semiconductor opto-junction field-effect transistor, comprising a wide bandgap semiconductor layer, a conductive channel formed in the wide bandgap semiconductor layer, and a source, drain, and gate connected to the wide bandgap semiconductor layer; and capable of generating photogenerated carriers in the wide bandgap semiconductor layer under illumination with light of a selected wavelength; Its features are: The gate includes a p-type semiconductor material layer, which is disposed on a first region on the surface of the wide bandgap semiconductor layer and forms a heterojunction or pn junction with the wide bandgap semiconductor layer, and is capable of depleting electrons in the conductive channel located below the first region. Furthermore, a light-receiving window is formed on the field-effect transistor, which allows light of the selected wavelength to pass through and illuminate the surface and / or interior of the wide bandgap semiconductor layer.

2. The wide bandgap semiconductor optoelectronic co-controlled junction field-effect transistor according to claim 1, characterized in that: The wide bandgap semiconductor layer has one or more fin channels formed therein, and the first region includes a local region of the sidewall of the fin channel and / or a local region of the semiconductor layer surface on at least one side of the fin channel.

3. The wide bandgap semiconductor optoelectronic co-controlled junction field-effect transistor according to claim 2, characterized in that: Multiple fin-shaped channels are formed in parallel in the wide bandgap semiconductor layer; And / or, the field-effect transistor includes a lateral field-effect transistor, a fully vertical Fin-JFET, or a quasi-vertical Fin-JFET.

4. The wide bandgap semiconductor optoelectronic co-controlled junction field-effect transistor according to claim 1, characterized in that: The p-type semiconductor material layer has a multilayer stacked structure.

5. The wide bandgap semiconductor optoelectronic co-controlled junction field-effect transistor according to claim 4, characterized in that: The p-type semiconductor material layer includes a first p-type semiconductor material layer and a second p-type semiconductor material layer stacked sequentially along a direction away from the surface of the wide bandgap semiconductor layer. The bandgap width of the first p-type semiconductor material layer is higher than the bandgap width of the wide bandgap semiconductor layer, and the bandgap width of the second p-type semiconductor material layer is lower than the bandgap width of the wide bandgap semiconductor layer.

6. The wide bandgap semiconductor optoelectronic co-controlled junction field-effect transistor according to any one of claims 1, 4, and 5, characterized in that: The p-type semiconductor material layer is made of a wide bandgap semiconductor material, which includes GaN, AlGaN, or SiC.

7. The wide bandgap semiconductor optoelectronic co-controlled junction field-effect transistor according to any one of claims 1, 4, and 5, characterized in that: The p-type semiconductor material layer is made of oxide semiconductor material, which includes NiO, CuO, Co3O4, SnO or ZnO.

8. The wide bandgap semiconductor optoelectronic co-controlled junction field-effect transistor according to claim 1, characterized in that: The wide bandgap semiconductor layer is made of one or more of the following materials: GaN, AlGaN, AlN, SiC, Ga2O3, and diamond. And / or, the selected wavelength of light includes one or more combinations of ultraviolet light, visible light, or infrared light; And / or, one or more light-receiving windows are provided on the top surface, bottom surface or sidewall of the field-effect transistor; And / or, the gate further includes gate metal disposed on a p-type semiconductor material layer; And / or, the gate is transparent or translucent; And / or, the field-effect transistor further includes a substrate, on which the wide bandgap semiconductor layer is disposed.

9. The wide bandgap semiconductor optoelectronic co-controlled junction field-effect transistor according to claim 8, characterized in that: The surface of the wide bandgap semiconductor layer has a first region and a second region that do not overlap with each other; the light-receiving window is formed in the second region.

10. A method for manufacturing a wide-bandgap semiconductor optoelectronic co-controlled junction field-effect transistor according to any one of claims 1-9, characterized in that, include: A wide bandgap semiconductor layer is provided, wherein a conductive channel is formed in the wide bandgap semiconductor layer, and photogenerated carriers can be generated in the wide bandgap semiconductor layer under light irradiation of a selected wavelength; A p-type semiconductor material layer is disposed on a first region on the surface of the wide bandgap semiconductor layer to form a gate, and the p-type semiconductor material layer is made to contact and cooperate with the wide bandgap semiconductor layer to form a heterojunction or pn junction, thereby depleting the electrons in the conductive channel located below the first region. Fabricate source and drain electrodes, and connect the source and drain electrodes to the wide bandgap semiconductor layer; Additionally, a light-receiving window is provided on the field-effect transistor, the light-receiving window allowing light of the selected wavelength to pass through and illuminate the surface and / or interior of the wide bandgap semiconductor layer.

11. The manufacturing method according to claim 10, characterized in that, include: One or more fin channels are fabricated in the wide bandgap semiconductor layer, and the p-type semiconductor material layer is deposited on a local area of ​​the sidewall of the fin channel and / or a local area of ​​the surface of the semiconductor layer on at least one side of the fin channel.

12. The manufacturing method according to claim 11, characterized in that, include: Multiple fin-shaped channels arranged in parallel are fabricated in the wide bandgap semiconductor layer; And / or, the source is disposed at the top of the fin channel, and the drain is disposed on the surface of the semiconductor layer on at least one side of the fin channel, and the gate is disposed between the source and the drain; or, one or more fin channels are processed on the first surface of the wide bandgap semiconductor layer, and the source is disposed at the top of the fin channel, while the drain is disposed on the second surface of the wide bandgap semiconductor layer, wherein the first surface and the second surface are disposed opposite to each other.

13. The manufacturing method according to claim 10, characterized in that, Specifically, it includes: A first region and a second region that do not overlap with each other are defined on the surface of the wide bandgap semiconductor layer; A p-type semiconductor material layer is disposed in the first region, and a light-receiving window is disposed in the second region.

14. A method of using the wide bandgap semiconductor optoelectronic co-controlled junction field-effect transistor according to any one of claims 1-9, characterized in that, include: A first set voltage is applied to the gate, and light of a selected wavelength is irradiated through the light-receiving window to illuminate the surface and / or interior of the wide bandgap semiconductor layer, thereby turning on the field-effect transistor; Alternatively, a second set voltage is applied to the gate, and at least a portion of the photogenerated carriers in the wide bandgap semiconductor layer are removed using the gate as a extraction channel, thereby turning off the field-effect transistor; Wherein, the first set voltage is greater than the second set voltage.

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