Image sensor device and method of formation

Abstract

An isolation structure in a pixel sensor array of an image sensor device is fabricated to include a first liner layer having a negative charge that passivates a dangling bond in a substrate layer of the image sensor that is formed during etching of the substrate layer to form a trench in which a section of the isolation structure is formed. A second liner layer having a neutral charge can be deposited on the first liner layer to protect the electronegativity of the first liner layer from being offset by a material of a fill layer subsequently deposited in the trench of the isolation structure. The neutral charge causes the second liner layer to act as a barrier between the first liner layer and the fill layer, which prevents a positive charge of the material of the fill layer from offsetting a negative charge of the material of the first liner layer.

Description

Technical Field

[0001] This invention relates to an image sensor device and a method for forming it. Background Technology

[0002] Complementary metal-oxide-semiconductor (CMOS) image sensors utilize photosensitive CMOS circuitry to convert light energy (e.g., photons) into electrical energy. The photosensitive CMOS circuitry may include a photodiode formed in a silicon substrate. When the photodiode is exposed to light, a charge (called photocurrent) is induced in it. The photodiode may be coupled to a switching transistor, which samples the charge in the photodiode. Color can be determined by placing a filter over the photosensitive CMOS circuitry. Summary of the Invention

[0003] Some embodiments described herein provide methods for forming an image sensor device. The methods for forming an image sensor device include doping a semiconductor layer of a semiconductor device to form a photodiode of a pixel sensor within the semiconductor layer. The methods include etching the semiconductor layer to form a trench in the semiconductor layer such that the trench surrounds the photodiode in a top view of the semiconductor device. The methods include depositing a conformal liner material in the trench to form a conformal liner on the sidewalls and bottom surface of the trench. The methods include depositing an anti-reflective coating film material above a surface of the semiconductor layer such that a portion of the anti-reflective coating film extends into the trench along the top portion of the sidewalls of the trench, wherein the conformal liner material and the anti-reflective coating film material are the same material, and wherein the conformal liner material and the anti-reflective coating film material are deposited using different deposition techniques. The methods include depositing a dielectric filling layer material on the conformal liner in the trench and above the anti-reflective coating film, wherein the conformal liner and the dielectric filling layer in the trench correspond to a DTI structure laterally surrounding the photodiode in a top view of the semiconductor device.

[0004] Some embodiments described herein provide methods for forming an image sensor device. The method of forming an image sensor device includes doping a semiconductor layer of a semiconductor device to form a photodiode of a pixel sensor within the semiconductor layer. The method includes etching the semiconductor layer to form a trench in the semiconductor layer such that the trench surrounds the photodiode in a top view of the semiconductor device. The method includes depositing a material of a first conformal liner in the trench to form a first conformal liner on the sidewalls and bottom surface of the trench. The method includes depositing a material of a second conformal liner in the trench to form a second conformal liner on the first conformal liner, wherein the materials of the first conformal liner and the second conformal liner are different dielectric materials. The method includes depositing a material of an antireflective coating film above a surface of the semiconductor layer such that a portion of the antireflective coating film extends into the trench along the top portion of the sidewalls of the trench, wherein the materials of the second conformal liner and the antireflective coating film are deposited using different deposition techniques, wherein the material of the second conformal liner has a neutral charge, and wherein the material of the antireflective coating film has a positive charge. The method includes depositing a material of a dielectric filling layer on a second conformal liner in a trench, wherein the first conformal liner, the second conformal liner, and the dielectric filling layer in the trench correspond to a DTI structure laterally surrounding a photodiode in a top view of a semiconductor device.

[0005] Some embodiments described herein provide an image sensor device. The image sensor device includes a sensor device. The image sensor device includes a processing device bonded to the sensor device such that the sensor device and the processing device are stacked within the image sensor device. A first side of the sensor device is bonded to the processing device. The sensor device includes a plurality of photodiodes and an isolation structure in a semiconductor layer of the sensor device. The isolation structure includes a plurality of interconnected segments in the semiconductor layer, the plurality of interconnected segments extending laterally around the plurality of photodiodes. In a top view of the isolation structure, the isolation structure includes rounded corners at the intersections of the plurality of interconnected segments. The plurality of interconnected segments of the isolation structure include a dielectric filling layer. The plurality of interconnected segments of the isolation structure include a first substrate between the semiconductor layer and the dielectric filling layer, wherein the material of the first substrate has a negative flat-band voltage. The plurality of interconnected segments of the isolation structure include a second substrate between the first substrate and the dielectric filling layer. The material of the second substrate has a positive flat-band voltage, and the sensor device includes an anti-reflective coating film on top of the dielectric filling layer and between the second substrate. The material of the anti-reflective coating film has a negative flat-band voltage. Attached Figure Description

[0006] The various aspects of this disclosure are best understood when read in conjunction with the following detailed description and accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 This is a schematic diagram of an example of a pixel sensor described in this article.

[0008] Figures 2A to 2C This is a schematic diagram of an example of an image sensor device described in this article.

[0009] Figure 3 This is a schematic diagram of an example of hydrogen concentration in the sensor device described in this article.

[0010] Figures 4A to 4E This is a schematic diagram of an example embodiment of the forming processing device (or part thereof) described herein.

[0011] Figures 5A to 5F This is a schematic diagram illustrating an example implementation of a sensor device (or part thereof) as described herein.

[0012] Figure 6A and Figure 6B This is a schematic diagram illustrating an example implementation of an image sensor device (or part thereof) as described herein.

[0013] Figures 7A to 7H This is a schematic diagram of an example implementation of a pixel sensor array (or a portion thereof) forming a sensor die as described herein.

[0014] Figure 8 This is a schematic diagram illustrating an example implementation of a pixel sensor in a sensor device that may be included in the image sensor device described herein.

[0015] Figures 9A to 9D This is a schematic diagram of an example implementation of a pixel sensor array (or a portion thereof) forming a sensor die as described herein.

[0016] Figure 10 This is a schematic diagram illustrating an example implementation of a pixel sensor in a sensor device that may be included in the image sensor device described herein.

[0017] Figure 11 This is a schematic diagram illustrating an example implementation of a pixel sensor in a sensor device that may be included in the image sensor device described herein.

[0018] Figure 12 This is a flowchart of an example process associated with the formation of a semiconductor device described herein.

[0019] Figure 13 This is a flowchart of an example process associated with the formation of a semiconductor device described herein. Detailed Implementation

[0020] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component symbols are used in the drawings and description to denote the same or similar parts.

[0021] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature on or above a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0022] Additionally, for ease of explanation, this document may use spatially relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one component or feature shown in the figure and another component or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figure. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein will be interpreted accordingly.

[0023] Optical crosstalk can occur between adjacent pixel regions in a pixel sensor array. Optical crosstalk is a performance issue of pixel sensor arrays, caused by incident light passing through the pixel sensor at a non-orthogonal angle and being at least partially absorbed by the photodiodes of adjacent pixel sensors. Optical crosstalk in the pixel sensor array of an image sensor device can degrade the spatial resolution of the image sensor, reduce the overall sensitivity of the image sensor device, cause color mixing between pixel sensors, increase dark current levels, reduce optical responsivity, reduce white pixel performance, and / or cause image noise after color correction.

[0024] In some cases, the pixel sensor array of an image sensor device may include an isolation structure (e.g., a deep trench isolation (DTI) structure). The isolation structure includes multiple interconnect segments that form an isolation grid laterally surrounding the pixel sensors in the pixel sensor array. The isolation structure increases the confinement of incident light to individual pixel sensors, thereby reducing optical crosstalk between pixel sensors.

[0025] The process of forming the isolation structure includes etching the substrate of the image sensor device to form multiple interconnected trenches, which resemble the shape and layout of the isolation structure segments. Various substrates and / or layers may be deposited in the trenches to form the isolation structure. Etching the substrate to form the trenches may cause damage to the substrate in the form of dangling bonds (e.g., silicon (Si) dangling bonds). These dangling bonds in the substrate can act as charge trapping sites, which can lead to the accumulation of residual charge in the photodiodes of the pixel sensors in a pixel sensor array. The accumulation of residual charge can reduce the optical sensitivity of the pixel sensor because it increases the signal threshold of the pixel sensor, thereby reducing the difference between the lowest and highest signal readings of the pixel sensor.

[0026] In some embodiments described herein, the isolation structure in the pixel sensor array of an image sensor device is fabricated to include a first liner that passivates dangling bonds in the substrate layer of the image sensor, such dangling bonds being formed during etching of the substrate layer to form trenches in which the isolation structure segments are formed. The first liner may have a negative charge to passivate the dangling bonds in the substrate layer, which reduces the likelihood and / or amount of charge accumulation around the isolation structure. This increases the sensitivity of the pixel sensor in the pixel sensor array, which may increase the responsiveness of the pixel sensor (which may increase low-light performance) and / or increase the dynamic range of the pixel sensor, among other examples.

[0027] As further described herein, a second liner may be deposited on the first liner to protect the electronegativity of the first liner from being offset by a filler material subsequently deposited in the trenches of the isolation structure. The filler material may have a positive charge, which may further offset the passivation provided by the negative charge of the first liner. The second liner may be deposited using a deposition technique such as atomic layer deposition (ALD), resulting in a neutral charge on the second liner. This neutral charge causes the second liner to act as a barrier layer between the first liner and the filler layer, preventing the positive charge of the filler material from offsetting the negative charge of the first liner material.

[0028] Figure 1This is a schematic diagram of an example of the pixel sensor 100 described herein. The pixel sensor 100 may include a front-side pixel sensor (e.g., a pixel sensor configured to receive photons from the front side of a sensor die), a rear-side pixel sensor (e.g., a pixel sensor configured to receive photons from the back side of a sensor die), and / or another type of pixel sensor. The pixel sensor 100 may be electrically connected to a supply voltage (V). dd 102 and electrical grounding 104.

[0029] Pixel sensor 100 includes a sensing region 106 configured to sense and / or accumulate incident light (e.g., light directed toward pixel sensor 100). Pixel sensor 100 also includes a control circuitry region 108. The control circuitry region 108 is electrically connected to the sensing region 106 and configured to receive a photocurrent 110 generated by the sensing region 106. Furthermore, the control circuitry region 108 is configured to transmit the photocurrent 110 from the sensing region 106 to downstream circuitry such as an amplifier or an analog-to-digital (AD) converter, among other examples.

[0030] Sensing region 106 includes a photodiode 112. The photodiode 112 absorbs and accumulates photons of incident light and generates a photocurrent 110 based on the absorbed photons. The magnitude of the photocurrent 110 is based on the amount of light collected in the photodiode 112. Therefore, the accumulation of photons in the photodiode 112 produces a charge accumulation representing the intensity or brightness of the incident light (e.g., a larger amount of charge corresponds to a larger intensity or brightness, while a smaller amount of charge corresponds to a lower intensity or brightness).

[0031] Photodiode 112 is electrically connected to the source of transfer gate 114 in control circuit region 108. Transfer gate 114 is configured to control the transmission of photocurrent 110 from photodiode 112. Photocurrent 110 is provided from the source of transfer gate 114 to the drain of transfer gate 114 based on selectively switching the gate of transfer gate 114. The gate of transfer gate 114 can be controlled by transmitting a transfer voltage (V... tx A transfer voltage 116 is applied to the transmission gate 114 to selectively switch the current. In some embodiments, the application of the transfer voltage 116 to the transmission gate 114 causes a conductive channel to be formed between the source and drain of the transmission gate 114, which allows the photocurrent 110 to travel along the conductive channel from the source to the drain. In some embodiments, the removal of the transfer voltage 116 from the transmission gate 114 (or the absence of the transfer voltage 116) causes the conductive channel to be removed, preventing the photocurrent 110 from flowing from the source to the drain.

[0032] The control circuit region 108 further includes a reset gate 118. The reset gate 118 is electrically connected to the supply voltage 102. The reset gate 118 can be powered by a reset voltage (V). rst 120 is controlled. The transfer gate 114 and the reset gate 118 are electrically coupled to the floating diffusion node 122. The reset voltage 120 can be applied to the reset gate 118 to pull the drain of the transfer gate 114 to a high voltage (e.g., to the supply voltage 102) to "reset" the floating diffusion node 122 (e.g., by draining any residual charge in the floating diffusion node 122) before the transfer gate 114 is activated to transfer the photocurrent 110 from the photodiode 112 to the floating diffusion node 122.

[0033] Photocurrent 110 can be used to apply floating diffusion voltage (V) fd A source follower gate 124 is applied to the control circuit region 108. This allows the photocurrent 110 to be observed without removing or discharging the photocurrent 110 from the floating diffusion node 122. The reset gate 118 can alternatively be used to remove or discharge the photocurrent 110 from the floating diffusion node 122.

[0034] The source follower gate 124 serves as a high-impedance amplifier for the pixel sensor 100. The source follower gate 124 provides voltage-to-current conversion for the floating diffused voltage. The output of the source follower gate 124 is electrically connected to the row select gate 126, which is configured to control the flow of photocurrent 110 to external circuitry. The row select gate 126 selectively applies a selection voltage (V0). di )128 is applied to the gate of row selection gate 126 for control. This allows photocurrent 110 to flow to the output 130 of pixel sensor 100.

[0035] As indicated above, provide Figure 1 As an example. Other examples may be related to... Figure 1 The descriptions are different.

[0036] Figures 2A to 2C This is a schematic diagram of example 200 of the image sensor device described herein. (As shown...) Figure 2AAs shown, an image sensor device can be formed by bonding a processing wafer 202 and a sensor wafer 204. For example, a bonding tool can be used to perform bonding operations to bond the processing wafer 202 and the sensor wafer 204 using metal-to-metal bonding, dielectric-to-dielectric bonding, and / or other bonding techniques. In the bonding operation, a processing device 206 on the processing wafer 202 is bonded to an associated sensor device 208 on the sensor wafer 204 to form an image sensor device 210. The image sensor device 210 is then diced and packaged. Other process steps can be performed to form the image sensor device 210.

[0037] Each image sensor device 210 includes a processing device 206 and a sensor device 208. The processing device 206 and the sensor device 208 may be stacked or vertically arranged in the image sensor device 210. Thus, the image sensor device 210 may be a three-dimensional (3D) complementary metal-oxide-semiconductor (CMOS) image sensor (3DCIS) device. The sensor device 208 may be a sensor die or semiconductor die fabricated on a sensor wafer 204 to include a pixel sensor array comprising a plurality of pixel sensors 100 or portions thereof. In particular, the pixel sensor array of the sensor device 208 includes at least a sensing region 106 of the pixel sensor 100 (and therefore a photodiode 112). Thus, the sensor device 208 is primarily configured to sense photons of incident light and convert the photons into a photocurrent 110.

[0038] Processing device 206 may be a processing die (e.g., an application-specific integrated circuit (ASIC) die, a system-on-a-chip (SOC) die) or other semiconductor die fabricated on processing wafer 202, to include circuitry configured to measure, manipulate, and / or otherwise utilize photocurrent 110. Furthermore, processing device 206 includes at least a subset of transistors in the control circuitry region 108 of pixel sensor 100. For example, processing device 206 may include row select gate 126 of pixel sensor 100, source follower gate 124 of pixel sensor, and / or combinations thereof. This provides increased area for photodiode 112 on sensor device 208, allowing the size of photodiode 112 to be increased to increase the sensitivity and / or overall performance of the pixel sensor's photosensitivity, and / or allowing the size of pixel sensor 100 to be reduced while maintaining the same size for photodiode 112.

[0039] like Figure 2AAs further shown, the processing device 206 may include a device layer 212 and an internal connection layer 214. Device layer 212 may include devices of the processing device 206 (e.g., transistors), and internal connection layer 214 may include internal connections enabling signals and / or power to be provided to and / or from the devices in device layer 212. The sensor device 208 may also include a device layer 216 and an internal connection layer 218. Device layer 216 may include portions of the pixel sensor 100, including a photodiode 112, a transmission gate 114, and a floating diffusion node 122, among other examples. Internal connection layer 218 may include internal connections enabling signals and / or power to and / or from device layer 216.

[0040] Processing device 206 and sensor device 208 may be bonded at bonding interface 220, which may be included between interconnect layers 214 and 218, and / or may be included in portions of interconnect layers 214 and / or 218. Bonding interface 220 may include bonding pads, bonding vias, bonding dielectric layers, and / or other bonding structures.

[0041] Figure 2B This is a top view of an example pixel sensor array 222 included on sensor device 208. Pixel sensor array 222 may be included on sensor device 208 of image sensor device 210. Figure 2B As shown, the pixel sensor array 222 may include a plurality of pixel sensors 100 (or portions thereof). For example, the pixel sensor array 222 may include photodiodes 112 of the pixel sensors 100. Figure 2B As further shown, the pixel sensor 100 can be configured as a grid. In some embodiments, the pixel sensor 100 is square (e.g., Figure 2B (As shown in the example). In some embodiments, the pixel sensor 100 includes other shapes, such as rectangular, circular, octagonal, rhomboid, and / or other shapes.

[0042] In some embodiments, the size of pixel sensor 100 (e.g., the width or diameter of pixel sensor 100) is approximately 1 micrometer. In some embodiments, the size of pixel sensor 100 (e.g., the width or diameter of pixel sensor 100) is less than approximately 1 micrometer. For example, the width of one or more pixel sensors 100 may include a range from approximately 0.6 micrometers to approximately 0.7 micrometers. In these examples, pixel sensor 100 may be referred to as sub-micron pixel sensors. Sub-micron pixel sensors can reduce the pixel sensor pitch (e.g., the distance between adjacent pixel sensors) in pixel sensor array 222, which can increase the pixel sensor density in pixel sensor array 222 (which can increase the efficiency of pixel sensor array 222). However, other values ​​in the size range of pixel sensor 100 are within the scope of this disclosure.

[0043] Each pixel sensor 100 may be configured to sense a specific wavelength range of incident light associated with a specific color component of the incident light. For example, pixel sensor 100 may be configured to sense a wavelength range associated with the red component of the incident light, and thus may be referred to as a red pixel sensor. As another example, pixel sensor 100 may be configured to sense a wavelength range associated with the blue component of the incident light, and thus may be referred to as a blue pixel sensor. As another example, pixel sensor 100 may be configured to sense a wavelength range associated with the green component of the incident light, and thus may be referred to as a green pixel sensor. In some embodiments, multiple pixel sensors 100 are configured to sense a wavelength range associated with the near-infrared (NIR) component of the incident light, and thus may be referred to as NIR pixel sensors. NIR pixel sensors may be included in pixel sensor array 222 to improve the low-light performance of image sensor device 210 and / or enable image sensor device 210 to achieve night vision functionality.

[0044] like Figure 2B Further, it is shown that the pixel sensor 100 can be electrically and optically isolated via an isolation structure 224 included in the pixel sensor array 222. The isolation structure 224 may include multiple interconnected and intersecting segments that extend into the substrate of the sensor device 208 and laterally surround the photodiode 112 of the pixel sensor 100. The segments of the isolation structure 224 can be formed by etching the substrate to form multiple trenches filled with one or more types of materials, such as dielectric materials, metallic materials, and / or other types of materials. The trenches may be formed around the periphery of the pixel sensor 100, such that the isolation structure 224 forms an isolation grid surrounding the photodiode 112 of the pixel sensor 100, as shown below. Figure 2BAs shown in the diagram. The isolation structure 224 may include a deep trench isolation (DTI) structure or another type of structure that extends into the substrate layer at least partially along the depth of the photodiode 112.

[0045] like Figure 2B The top-down view further shows that the isolation structure 224 may have rounded corners 226 at the intersections of two or more segments of the isolation structure 224. The corners 226 may be rounded due to etch loading at the intersections of trenches formed in the semiconductor layer. Etch loading may occur because the etch dose flowing into the intersections is greater than the etch dose along the trench segments, resulting in a higher etch rate at the intersections than in the trench segments.

[0046] Figure 2C A cross-sectional view of the image sensor device 210 is shown. Figure 2C As shown, the processing device 206 and the sensor device 208 can be joined at the joining interface 220, such that the processing device 206 and the sensor device 208 are stacked or vertically arranged in the image sensor device 210 along the z-direction. Figure 2C The image sensor device 210 further illustrates that it includes, for example, a pixel sensor array 222 (e.g., including pixel sensor 100), a black level correction (BLC) region 228 adjacent (e.g., horizontally adjacent) to the pixel sensor array 222, a bonding pad region 230 adjacent (e.g., horizontally adjacent) to the black level correction region 228, and a sealing ring region 232 adjacent (e.g., horizontally adjacent) to the bonding pad region 230. In a top view of the image sensor device 210, the black level correction region 228, the bonding pad region 230, and / or the sealing ring region 232 may laterally surround the pixel sensor array 222 and may be referred to as the periphery of the pixel sensor array 222.

[0047] like Figure 2C The image sensor device 210 further shows that it includes multiple layers, such as device layer 212 and interconnect layer 214 of processing device 206, and device layer 216 and interconnect layer 218 of sensor device 208. Device layer 212 of processing device 206 includes a semiconductor layer 234 and a dielectric layer 236 above semiconductor layer 234. Semiconductor layer 234 may correspond to a portion of the substrate forming processing device 206 and may include silicon (Si) (e.g., a silicon substrate), silicon-containing materials, III-V compound semiconductor materials such as gallium arsenide (GaAs), or other types of semiconductor materials. Dielectric layer 236 may include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N yExamples include silicon oxynitride (SiON), tetraethyl orthosilicate oxide, silicon phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), silicon fluoride glass (FSG), and / or carbon-doped silicon oxide.

[0048] Integrated circuit device 238 may be contained in and / or on semiconductor layer 234 of device layer 212 of processing device 206. Integrated circuit device 238 may include one or more ASIC devices, one or more SOC devices, one or more transistors and / or one or more other components configured to measure the magnitude of photocurrent 110 generated by pixel sensor 100 to determine the light intensity of incident light and / or generate images and / or video (e.g., digital images, digital video).

[0049] The interconnect layer 214 of the processing device 206 may include a dielectric layer 240, a bonding layer 242, a plurality of interconnect structures 244 in the dielectric layer 240, and a plurality of bonding structures 246 in the bonding layer 242. The dielectric layer 240 may include one or more interlayer dielectric (ILD) layers, one or more intermetallic dielectric (IMD) layers, and / or one or more etch stop layers (ESL), etc. The dielectric layer 240 and the bonding layer 242 may each include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Examples include silicon oxynitride (SiON), tetraethyl orthosilicate oxide, silicon phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), silicon fluoride glass (FSG), and / or carbon-doped silicon oxide.

[0050] Interconnect structures 244 may each include conductive lines, trenches, vias, internal connections, metallization layers, and / or other types of conductive structures, for example, electrically connecting integrated circuit device 238 to one or more other regions of processing device 206 and / or one or more regions of sensor device 208. Bond structures 246 may each include bonding pads, bonding vias, and / or other types of bonding structures. Interconnect structures 244 and bonding structures 246 may each include one or more conductive materials, such as conductive metals, conductive metal alloys, conductive ceramics, tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au).

[0051] The device layer 216 of the sensor device 208 includes a semiconductor layer 248 and a dielectric layer 250 beneath the semiconductor layer 248. The semiconductor layer 248 may correspond to at least a portion of the substrate (or substrate layer) forming the sensor device 208 and may include silicon (Si) (e.g., a silicon substrate), a silicon layer or another type of semiconductor layer, a silicon-containing material, a III-V compound semiconductor material such as gallium arsenide (GaAs), and / or another type of semiconductor material. In some embodiments, the semiconductor layer 248 is a layer forming a silicon-on-insulator (SOI) substrate of the sensor device 208.

[0052] The dielectric layer 250 may include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Examples include silicon oxynitride (SiON), tetraethyl orthosilicate oxide, silicon phosphosilicate glass (PSG), borosilicate phosphosilicate glass (BPSG), silicon fluoride glass (FSG), and / or carbon-doped silicon oxide.

[0053] The photodiode 112 of the pixel sensor 100 is included in the semiconductor layer 248 of the sensor device 208. Each photodiode 112 may include one or more doped regions of the semiconductor layer 248. The semiconductor layer 248 may be doped with multiple types of ions to form a pn junction or PIN junction corresponding to the photodiode 112 (e.g., a junction between a p-type portion, an intrinsic (or undoped) type portion, and an n-type portion). For example, the semiconductor layer 248 may be doped with n-type dopant to form a first portion (e.g., an n-type portion) of the photodiode 112 and p-type dopant to form a second portion (e.g., a p-type portion) of the photodiode 112. The photodiode 112 may be configured to absorb photons of incident light. The absorption of photons causes the photodiode 112 to accumulate charge (photocurrent 110) due to the photoelectric effect. Here, photons bombard the photodiode 112, which causes electron emission from the photodiode 112. Electron emission leads to the formation of electron-hole pairs, where electrons migrate toward the cathode of the photodiode 112 and holes migrate toward the anode, generating the photocurrent 110.

[0054] Photodiode 112 can be electrically and / or optically isolated from each other through one or more isolation structures in semiconductor layer 248. Shallow trench isolation (STI) structure 252 can extend into semiconductor layer 248 from the bottom side (referred to as the front side of semiconductor layer 248). Shallow trench structure 252 may include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Examples include silicon oxynitride (SiON) and / or silicon oxynitride (SiON).

[0055] The isolation structure 224 extends from the top side of the semiconductor layer 248 (referred to as the back side of the semiconductor layer 248) into the semiconductor layer 248, situated above the shallow trench structure 252. The combination of the shallow trench structure 252 and the isolation structure 224 laterally surrounds the pixel sensor 100 (e.g., ...) in the semiconductor layer 248. Figure 2B (As shown) and provides electrical and / or optical isolation for the pixel sensor 100 in the semiconductor layer 248. Because the isolation structure 224 extends from the back side of the semiconductor layer 248 into the semiconductor layer 248, the isolation structure 224 may be referred to as a back-side deep trench isolation (BDTI) structure. Alternatively, the isolation structure 224 may be formed from the front side of the semiconductor layer 248, such that the isolation structure 224 extends from the front side into the semiconductor layer 248. In these embodiments, the isolation structure 224 may be referred to as a front-side deep trench isolation (FDTI) structure.

[0056] The isolation structure 224 may include elongated segments extending into the semiconductor layer 248. Each segment of the isolation structure 224 may include a filler layer 254 and one or more liner layers located between the filler layer 254 and the semiconductor layer 248. For example, a liner layer 256 may be included between the filler layer 254 and the semiconductor layer 248, while another liner layer 258 may be included between the liner layer 256 and the semiconductor layer 248. In some embodiments, another liner layer is included between the liner layer 258 and the semiconductor layer 248. The filler layer 254, liner layer 256, and / or liner layer 258 may also extend (e.g., continuously) across the back side of the semiconductor layer 248 between segments of the isolation structure 224.

[0057] The filling layer 254 of the isolation structure 224 may include silicon oxide (SiO2). x For example, SiO2), phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicon glass (FSG), another low-k dielectric material with a dielectric constant of about 3.9 or less, and / or another dielectric material. The filler layer 254 may be deposited as a bulk dielectric layer filling the trenches forming the isolation structure 224.

[0058] Substrates 256 and 258 may each comprise conformal layers deposited conformally on the sidewalls and bottom surface of the trench forming the isolation structure 224. Substrates 256 and 258 may each comprise a high-k dielectric material with a dielectric constant greater than about 3.9. Substrate 256 may comprise one or more high-k dielectric materials, such as tantalum oxide (Ta2O3). x O y Zirconium oxide (ZrO) x For example, ZrO2), molybdenum oxide (MoO2) x For example, MoO3), titanium dioxide (TiO2), etc. xExamples include TiO2, barium titanate (BaTiO3), niobium pentoxide (Nb2O5), and / or iron oxide (Fe3O4). The liner 258 may include one or more highly dielectric materials, such as alumina (Al2O3). x O y ) and / or silicon nitride (Si x N y Examples such as ).

[0059] In some embodiments, liners 256 and 258 comprise different dielectric materials. For example, liner 256 may comprise tantalum oxide (Ta2O3). x O y For example, Ta2O5) material, while the liner 258 may include alumina (Al) x O y Materials such as Al2O3. In these embodiments, the dielectric constant of the material of the liner 256 (e.g., tantalum oxide: dielectric constant of about 25 to about 50) may be greater than the dielectric constant of the material of the liner 258 (e.g., alumina: dielectric constant of about 4 to about 10).

[0060] In some embodiments, liner 256 and / or liner 258 serve as an antireflective coating for the isolation structure 224. Therefore, liner 256 and / or liner 258 comprise a material having a refractive index closer to that of the semiconductor layer 248 than the refractive index of the material of the filler layer 254. For example, the material of the filler layer 254 may include silicon dioxide (SiO2: refractive index of about 1.45 for visible light wavelengths), the material of the semiconductor layer 248 may include silicon (Si: refractive index of about 3.7 to about 6 for visible light wavelengths), the material of the liner 256 may include tantalum pentoxide (Ta2O5: refractive index of about 2.13 to about 2.25 for visible light wavelengths), and the material of the liner 258 may include aluminum oxide (Al2O3: refractive index of about 1.76 to about 1.79 for visible light wavelengths). The material of the liner 256 may typically have a refractive index greater than or about equal to 2.0 to obtain suitable antireflective properties. However, other combinations of materials are within the scope of this disclosure.

[0061] The material of liner 258 can have a positive flat band voltage (V). fbA positive voltage causes the material of the substrate 258 to have a negative charge. This negative charge passivates the material of the semiconductor layer 248 surrounding the isolation structure 224 (which may have positive charges resulting from dangling bonds formed by etching the semiconductor layer 248 to create trenches in which the isolation structure 224 is formed). Specifically, the negative charge of the substrate 258 induces positive charges at the interface between the substrate 258 and the semiconductor layer 248 surrounding the isolation structure 224 (e.g., due to dipole interactions). The positive charges passivate charge trapping sites in the material of the semiconductor layer 248 by preventing free electrons from propagating into the semiconductor layer 248 (and into the photodiode 112 of the pixel sensor 100).

[0062] The material of liner 256 may have a neutral or positive flat voltage (V) fb This results in the material of the liner 256 having a neutral or slightly negative charge. This allows the liner 256 to act as a buffer layer between the liner 258 and the filler layer 254 (the filler layer 254 may also have a positive charge due to the use of plasma-enhanced deposition techniques, such as plasma-enhanced atomic layer deposition (PEALD)), to protect the negative charge of the liner 258 material from being canceled out by the positive charge of the filler layer 254 material. The material of the liner 256 can be deposited using chemical-based deposition techniques (e.g., relative to physical bombardment-based techniques such as sputtering) such as atomic layer deposition, such that positive charge does not transfer to the material of the liner 256 during deposition. The buffer layer provided between the liner 258 and the filler layer 254 results in the isolation structure 224 having an overall positive flat-band voltage in the range of about 20 volts to about 35 volts. However, other values ​​and ranges of the flat-band voltage of the isolation structure 224 are within the scope of this disclosure.

[0063] In example 200 of the image sensor device 210, an isolation structure 224 may be included in the back side of the semiconductor layer 248. On the front side of the semiconductor layer 248, a transmission gate 114 of the pixel sensor 100 is included, and a dielectric layer 250 is included over the transmission gate 114. The transmission gate 114 is electrically connected to the interconnect layer 218, which allows an input (e.g., a gate voltage) to be provided to the transmission gate 114 to control the flow of photocurrent 110 from the photodiode 112 to the floating diffusion node 122 of the pixel sensor 100.

[0064] Interconnect layer 218 may include dielectric layer 260, bonding layer 262, multiple interconnect structures 264 in dielectric layer 260, and multiple bonding structures 266 in bonding layer 262. Dielectric layer 260 may include one or more ILD layers, one or more IMD layers, and / or one or more ESLs, and other examples. Dielectric layer 260 and bonding layer 262 may each include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x N y Silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), and / or carbon-doped silicon oxide, and other examples.

[0065] Interconnect structures 264 may each include conductive lines, trenches, vias, internal connections, metallization layers, and / or other types of conductive structures that electrically connect the transmission gate 114 to one or more other regions of the sensor device 208 and / or to one or more regions of the processing device 206, and other examples. Bond structures 266 may each include bonding pads, bonding vias, and / or other types of bonding structures. Interconnect structures 264 and bonding structures 266 may each include one or more conductive materials, such as conductive metals, conductive metal alloys, conductive ceramics, tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), and / or gold (Au), and other examples of conductive materials.

[0066] At the bonding interface 220, bonding layers 242 and 262 may be bonded together (e.g., in a dielectric-to-dielectric bonding), and bonding structures 246 and 266 may be bonded together (e.g., in a metal-to-metal bonding). In some embodiments, a slight offset may occur between bonding structures 246 and 266, such that the edges of bonding structures 246 and 266 are offset relative to each other. Signal and / or power can be transmitted through bonding structures 246 and 266 between processing device 206 and sensor device 208.

[0067] An antireflective coating (ARC) film 268 may be included over a segment of the isolation structure 224, above the top side (e.g., the back side) of the semiconductor layer 248. In some embodiments, the antireflective coating film 268 is formed prior to the formation of the filler layer 254 of the isolation structure 224, and the ends of the antireflective coating film 268 extend into portions of the segment of the isolation structure 224. In some embodiments, the antireflective coating film 268 is formed after the formation of the filler layer 254, and the antireflective coating film 268 extends to cover the filler layer 254. Substrates 256 and 258 may be located between the semiconductor layer 248 and the antireflective coating film 268.

[0068] The material of the antireflective coating film 268 may include one or more highly dielectric materials, such as tantalum oxide (Ta2O3). x O y Zirconium oxide (ZrO) x For example, ZrO2), molybdenum oxide (MoO2), etc. x For example, MoO3), titanium dioxide (TiO2), etc. x Materials such as TiO2, barium titanate (BaTiO3), niobium pentoxide (Nb2O5), and / or iron oxide (Fe3O4), and others. The material of the antireflective coating film 268 may have a refractive index greater than or approximately equal to 2.0. However, in other embodiments, the material of the antireflective coating film 268 may have another refractive index.

[0069] In some embodiments, the antireflective coating film 268 and the liner 256 may comprise the same material, such as tantalum oxide. In these embodiments, an interface may not be visible between the antireflective coating film 268 and the liner 256, and the antireflective coating film 268 may correspond to the top of the liner 256, extending along the top of the sidewall of a segment of the isolation structure 224. Furthermore, in these embodiments, the material of the antireflective coating film 268 may have a positive charge (e.g., Ta₂O) due to oxygen vacancies in the material of the antireflective coating film 268. 5-z These oxygen vacancies may be generated by physical vapor deposition (PVD) or sputtering deposition techniques used to deposit the material of the antireflective coating film 268. Some contamination of the target material of the antireflective coating film 268 may occur during the PVD process, resulting in negative flat-band voltage and positive charge in the material of the antireflective coating film 268. Contamination of the target material cathode may be caused by the formation of compounds on the surface of the target material cathode. Alternatively, the material of the antireflective coating film 268 and the material of the substrate 256 may be different materials. In these embodiments, the interface between the antireflective coating film 268 and the substrate 256 may be visible in the image sensor device 210 (e.g., in an electron microscope, such as a transmission electron microscope (TEM) image).

[0070] The mesh structure 270 may be included above the anti-reflective coating film 268. Segments of the mesh structure 270 may be located above corresponding segments of the isolation structure 224 and may be formed around the periphery of the photodiode 112 of the pixel sensor 100. Therefore, the mesh structure 270 may have an overall top-view shape and layout similar to the isolation structure 224. Openings in the mesh structure 270 are included above the photodiode 112 to allow incident light to pass through the mesh structure 270 and reach the photodiode 112.

[0071] In some embodiments, the mesh structure 270 is formed of a metallic material, such as gold (Au), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), titanium (Ti), ruthenium (Ru), metal alloys (e.g., aluminum-copper (AlCu)), and / or combinations thereof, and other examples. In some embodiments, the mesh structure 270 is formed of a dielectric material, such as silicon oxide (SiO2). x ) and / or silicon nitride (SiN) x (and other examples.) In some embodiments, the mesh structure 270 is a multi-layer structure, including one or more dielectric layers and one or more metal layers stacked and arranged vertically.

[0072] A color filter region 272 of the pixel sensor 100 may be included within an opening in the grid structure 270. The color filter region 272 may be included above a photodiode 112 of the pixel sensor 100. Each color filter region 272 may be configured to filter incident light to allow a specific wavelength of incident light to pass through to the photodiode 112. For example, the color filter region 272 may filter incident light to allow red light to pass through the color filter region 272 to the associated photodiode 112. As another example, the color filter region 272 may filter incident light to allow green light to pass through the color filter region 272 to the associated photodiode 112. As another example, the color filter region 272 may filter incident light to allow blue light to pass through the color filter region 272 to the associated photodiode 112. In some embodiments, the color filter region 272 may be indiscriminate or unfiltered, which may define a white pixel sensor. Undifferentiated or unfiltered color filter region 272 may include a material that allows light of all wavelengths to pass through to the associated photodiode 112 (e.g., to determine overall brightness to increase the photosensitivity of the image sensor). In some embodiments, color filter region 272 may be an NIR bandpass color filter region 272, which may define an NIR pixel sensor. NIR bandpass color filter region 272 may include a material that allows incident light in the NIR wavelength range to pass through to the associated photodiode 112 while blocking visible light from passing through.

[0073] Microlens 274 may be included above and / or on color filter region 272. Microlens 274 may include a corresponding microlens for each of the pixel sensors 100. Microlenses may be formed to focus incident light toward the photodiode 112 of the associated pixel sensor 100.

[0074] like Figure 2CThe diagram further shows that a metal layer 276 may be included above the semiconductor layer 248 in the black level correction region 228 of the semiconductor layer 248. The metal layer 276 may serve as a light-shielding layer to prevent incident light from entering a portion of the semiconductor layer 248 in the black level correction region 228. Therefore, a portion of the semiconductor layer 248 in the black level correction region 228 is a sensing area that remains "dark," allowing dark current measurement to be performed within the black level correction region 228. Dark current measurement can be performed to measure the amount of charge (dark current) generated in the semiconductor layer 248 from sources other than incident light (e.g., heat energy from the semiconductor layer 248), making the dark current measurement usable for black level correction (or black level calibration) of the pixel sensor array 222.

[0075] like Figure 2C The image further shows that the bonding pad region 230 may include multiple dielectric layers 278, 280, 282, and 284, which electrically isolate the bonding pad structure 286. The bonding pad structure 286 is electrically and / or physically coupled to one or more of the interconnect structures 264 in the interconnect layer 218 of the sensor device 208. A bonding pad opening 288 is included above the bonding pad structure 286 to allow external electrical connections to be formed to the bonding pad structure 286.

[0076] The multiple dielectric layers 278, 280, 282, and 284 may each include one or more dielectric materials, such as silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), tetraethyl orthosilicate oxide, phosphosilicate glass (PSG), borosilicate glass (BPSG), fluorinated silicate glass (FSG), and / or carbon-doped silicon oxide. The bonding pad structure 286 may include metallic materials, such as gold (Au), copper (Cu), silver (Ag), cobalt (Co), tungsten (W), titanium (Ti), ruthenium (Ru), metal alloys (e.g., aluminum-copper (AlCu)), and / or combinations thereof.

[0077] The sealing ring region 232 includes multiple stacked interconnect structures 244 in the interconnect layer 214 and multiple stacked interconnect structures 264 in the interconnect layer 218 to seal the structure and layers of the image sensor device 210 to prevent moisture and other contaminants from entering, and to provide structural rigidity for the image sensor device 210.

[0078] As pointed out above, Figures 2A to 2C Provided as an example. Other examples are available with reference to [link / details]. Figures 2A to 2C The descriptions are different.

[0079] Figure 3 This is a diagram of an example embodiment 300 of the isolation structure 224 segment in the sensor device 208 described herein. (See diagram below.) Figure 3As shown, segments of the isolation structure 224 may include elongated structures extending primarily along the z-direction within the semiconductor layer 248 of the sensor device 208. The isolation structure 224 may have tapered sidewalls (e.g., Figure 3 As shown in the example below), it may have substantially vertical sidewalls. In some embodiments, the bottom of the isolation structure 224 may be substantially flat (e.g., as shown in the example below). Figure 3 (As shown in the example), or it can be circular.

[0080] like Figure 3 Detailed view 302 further shows that the sidewall of the isolation structure 224 near the bottom of the isolation structure 224 includes a laterally arranged filler layer 254, a liner 256, and a liner 258. The filler layer 254 may be made of a positively charged material, while the liner 258 may be made of a negatively charged material. The liner 256 may be made of a substantially neutrally charged material, providing a barrier between the positively charged material of the filler layer 254 and the negatively charged material of the liner 258, and preventing electrons in the liner 258 material from binding with holes in the filler layer 254 material.

[0081] like Figure 3 Detailed view 302 further shows that the liner 258 may have a thickness (in a direction generally perpendicular to the sidewall of the isolation structure 224) Figure 3 The dimension is indicated as D1. The liner 256 may have a thickness in a direction generally perpendicular to the sidewall of the isolation structure 224 (in Figure 3 The dimension is indicated as D2. In some embodiments, the thicknesses of the liner 256 and 258 are approximately equal. In some embodiments, the thickness of the liner 256 is greater than the thickness of the liner 258 (e.g., D2 > D1).

[0082] The thickness (dimension D1) of the liner 258 may range from about 70 angstroms to about 150 angstroms to provide effective passivation of dangling bonds in the semiconductor layer 248 surrounding the isolation structure 224. However, other values ​​and ranges are within the scope of this disclosure.

[0083] The thickness (dimension D2) of the liner 256 can range from about 100 angstroms to about 200 angstroms to provide effective buffering between the liner 258 and the antireflective coating film 268 and / or between the liner 258 and the filler layer 254. At thicknesses greater than about 200 angstroms, the ALD technique used to deposit the liner 256 material may significantly reduce the manufacturing throughput of the sensor device 208 with only a minimal to no increase in the effectiveness of isolating the negative charge of the liner 258 from the positive charge of the antireflective coating film 268 and / or the filler layer 254. However, other values ​​and ranges are within the scope of this disclosure.

[0084] like Figure 3Detailed view 304 further shows that the sidewalls of the isolation structure 224 near the bottom of the isolation structure 224 include a laterally arranged filler layer 254, a liner 256, a liner 258, and an anti-reflective coating film 268. The anti-reflective coating film 268 may also have a positive charge due to the deposition technique (e.g., PVD or sputtering) used to deposit the material of the anti-reflective coating film 268. PVD or sputtering techniques can be used to deposit the material of the anti-reflective coating film 268 because such physical deposition techniques provide relatively low step coverage to minimize the amount of anti-reflective coating film 268 material deposited into the trenches forming the segments of the isolation structure 224.

[0085] like Figure 3 Detailed view 304 further shows that the anti-reflective coating film 268 may have a thickness (in) in a direction generally perpendicular to the sidewall of the isolation structure 224. Figure 3 The thickness of the antireflective coating film 268 can vary from the bottom of the portion of the antireflective coating film 268 on the sidewall of the isolation structure 224 (corresponding to the end of the antireflective coating film 268 extending along the sidewall of the isolation structure 224) to the top of the portion of the antireflective coating film 268 on the sidewall of the isolation structure 224 (corresponding to the portion of the antireflective coating film 268 at the top of the sidewall of the isolation structure 224). At the top of the sidewall of the isolation structure 224, the thickness of the antireflective coating film 268 can be greater than the thickness of the liner 256 (e.g., D3 > D2), and can be greater than about 200 angstroms. However, other values ​​and ranges for the thickness of the antireflective coating film 268 are within the scope of this disclosure.

[0086] As mentioned above, Figure 3 This is provided as an example. Other examples may be related to... Figure 3 The descriptions are different.

[0087] Figures 4A to 4E This is a diagram illustrating an exemplary embodiment 400 of the forming processing device 206 (or a portion thereof) described herein. In some embodiments, combined with Figures 4A to 4E The one or more semiconductor processing operations may be performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, electroplating tools, ion implantation tools, and / or wafer / die transfer tools.

[0088] like Figure 4A As shown, a semiconductor layer 234 is provided as the device layer 212 of the processing device 206. The semiconductor layer 234 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer. In some embodiments, the semiconductor layer 234 is provided as a layer of an SOI wafer. In some embodiments, the semiconductor layer 234 is provided as another type of semiconductor workpiece.

[0089] like Figure 4B As shown, one or more integrated circuit devices 238 may be formed in and / or on semiconductor layer 234. One or more semiconductor process tools may be used to form one or more portions of integrated circuit device 238. For example, deposition tools may be used to perform various deposition operations to deposit layers of integrated circuit device 238, and / or deposit photoresist layers for etching semiconductor layer 234 and / or portions of the deposited layers. As another example, exposure tools may be used to expose photoresist layers to form patterns in the photoresist layers. As another example, developing tools may be used to develop patterns in the photoresist layers. As another example, etching tools may be used to etch semiconductor layer 234 and / or portions of the deposited layers to form integrated circuit device 238. As another example, planarization tools may be used to planarize portions of integrated circuit device 238. As another example, electroplating tools may be used to deposit metal structures and / or layers of integrated circuit device 238.

[0090] like Figure 4B As further shown, the dielectric layer 236 may be deposited on and / or on the semiconductor layer 234 and the integrated circuit device 238. Deposition tools may be used to deposit the dielectric layer 236 using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, or other types of deposition techniques. In some embodiments, planarization tools may be used to planarize the dielectric layer 236 after deposition.

[0091] like Figure 4C As shown, a first portion of the interconnect layer 214 of the processing device 206 is formed over the device layer 212. To form the first portion of the interconnect layer 214, deposition tools can be used to deposit a dielectric layer 240 (which may comprise one or more ILD layers, one or more IMD layers, one or more ESL layers, and / or one or more dielectric layers of another type) using PVD, ALD, CVD, oxidation, or other deposition techniques. In some embodiments, planarization tools can be used to planarize the dielectric layer 240 after deposition.

[0092] Deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor processing tools may be used to perform various operations to form an interconnect structure 244 in the dielectric layer 240 of the first portion of the interconnect layer 214. The deposition tools and / or electroplating tools may be used to deposit the interconnect structure 244 using PVD, ALD, CVD, electroplating, and / or other deposition techniques. In some embodiments, a planarization tool may be used to planarize the interconnect structure 244 after deposition.

[0093] In some embodiments, a first portion of interconnect layer 214 is constructed in the z-direction with a plurality of via layers (V layers) and metallization layers (M layers). For example, a first portion of dielectric layer 240 may be formed, a groove may be formed in the first portion of dielectric layer 240, and a first interconnect structure 244 (e.g., V0 via layer, M0 metallization layer) may be formed in the groove. A second portion of dielectric layer 240 may be formed, a groove may be formed in the second portion of dielectric layer 240, and a second interconnect structure 244 (e.g., V1 via layer, M1 metallization layer) may be formed in the groove. The remaining via layers and / or metallization layers of the first portion of interconnect layer 214 may be formed in a similar manner.

[0094] like Figure 4D and Figure 4E As shown, a second portion of interconnect layer 214 may be formed, and the second portion of interconnect layer 214 may include bonding layer 242 and bonding structure 246. Figure 4D As shown, the bonding layer 242 may be formed above and / or on the dielectric layer 240, and above and / or on the topmost interconnect structure 244. Deposition tools may be used to deposit the bonding layer 242 using PVD, ALD, CVD, oxidation, or other deposition techniques. In some embodiments, planarization tools may be used to planarize the bonding layer 242 after deposition.

[0095] like Figure 4E As shown, the bonding structure 246 can be formed in the bonding layer 242. For example, deposition tools, exposure tools, and developing tools can be used to form a patterned mask layer on the bonding layer 242. Etching tools can be used to etch the bonding layer 242 (e.g., using wet etching techniques, dry etching techniques) to form grooves in the bonding layer 242. Deposition tools and / or electroplating tools can be used to deposit the bonding structure 246 in the grooves using CVD, PVD, ALD, electroplating, and / or other deposition techniques. In some embodiments, a planarization tool can perform a planarization operation to planarize the bonding structure 246 after deposition.

[0096] Alternatively, a metal layer may be deposited over the dielectric layer 240 and may be patterned and etched to define the bonding structure 246. Subsequently, a bonding layer 242 may be deposited around and over the bonding structure 246, and the bonding layer 242 may be planarized to expose the bonding structure 246.

[0097] As mentioned above, providing Figures 4A to 4E As an example. Other examples may be related to... Figures 4A to 4E The descriptions are different.

[0098] Figures 5A to 5FThis is a schematic diagram of an exemplary embodiment 500 for forming a sensor device 208 (or a portion thereof) as described herein. In particular, exemplary embodiment 500 may include an exemplary front-end process flow for the sensor device 208. In some embodiments, with... Figures 5A to 5F The one or more semiconductor processing operations described herein may be performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, electroplating tools, ion implantation tools, and / or wafer / die transfer tools.

[0099] like Figure 5A As shown, a semiconductor layer 248 is provided as the device layer 216 of the sensor device 208. In some embodiments, the semiconductor layer 248 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer. In some embodiments, the semiconductor layer 248 is provided as a layer of an SOI wafer. In some embodiments, the semiconductor layer 248 is provided in the form of another type of semiconductor workpiece.

[0100] like Figure 5B As shown, the photodiode 112 of the pixel sensor array 222 of the sensor device 208 and the floating diffusion node 122 of the pixel sensor 100 can be formed in the semiconductor layer 248 from the front side of the semiconductor layer 248. In some embodiments, an ion implantation tool can be used to implant ions into the semiconductor layer 248 to form a PN junction between a p-doped region and an n-doped region of the semiconductor layer 248, or to form a PIN junction between a p-doped region, an n-doped region, and an intrinsic (e.g., undoped) semiconductor region for the photodiode 112. In some embodiments, an ion implantation tool can be used to implant n-type dopant and / or p-type dopant into the semiconductor layer 248 to form the floating diffusion node 122.

[0101] like Figure 5B As further shown, the shallow trench structure 252 may be formed in the semiconductor layer 248 (e.g., from the front side of the semiconductor layer 248) such that the shallow trench structure 252 is located between the photodiodes 112. In some embodiments, the shallow trench structure 252 is formed after the photodiodes 112 are formed. In some embodiments, the shallow trench structure 252 is formed before the photodiodes 112 are formed.

[0102] Deposition tools, exposure tools, and development tools can be used to form a patterned mask layer on semiconductor layer 248. Etching tools can be used to etch into semiconductor layer 248 from the front side (e.g., using wet etching techniques, dry etching techniques) to form trenches on the front side of semiconductor layer 248. Deposition tools can be used to deposit shallow trench structures 252 in the trenches using CVD, PVD, ALD, oxidation, and / or other deposition techniques. In some embodiments, planarization tools can perform a planarization operation after the shallow trench structure 252 is deposited to planarize the shallow trench structure 252.

[0103] like Figure 5C As shown, the transfer gate 114 of the pixel sensor 100 may be formed above and / or on the front surface of the semiconductor layer 248. Forming the transfer gate 114 may include, for example, depositing a gate dielectric layer on the front surface of the semiconductor layer 248, depositing a gate electrode on the gate dielectric layer, and / or forming sidewall spacers on the sidewalls of the gate electrode.

[0104] like Figure 5C As further shown, the dielectric layer 250 may be formed above and / or on the front side of the semiconductor layer 248. In some embodiments, the dielectric layer 250 is deposited above and / or on the transfer gate 114. In some embodiments, a dummy gate structure is formed to replace the transfer gate 114, and the dielectric layer 250 is deposited around and / or above the dummy gate. The dummy gate is then replaced by the transfer gate 114 by forming the transfer gate 114 in a recess in the dielectric layer 250 formed by removing the dummy gate.

[0105] The deposition tools can be used to deposit the dielectric layer 250 using CVD, PVD, ALD, electroplating, and / or other deposition techniques. In some embodiments, the planarization tools can perform a planarization operation after the dielectric layer 250 is deposited to planarize the dielectric layer 250.

[0106] like Figure 5D As shown, a first portion of the interconnect layer 218 of the sensor device 208 is formed over the device layer 216. To form the first portion of the interconnect layer 218, deposition tools can be used to deposit a dielectric layer 260 (which may include one or more ILD layers, one or more IMD layers, one or more ESL layers, and / or one or more dielectric layers of another type) using PVD, ALD, CVD, oxidation, or other deposition techniques. In some embodiments, planarization tools can be used to planarize the dielectric layer 260 after deposition.

[0107] Deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor process tools may be used to perform various operations to form interconnect structures 264 in a first portion of interconnect layer 218. Deposition tools and / or electroplating tools may be used to deposit interconnect structures 264 using PVD, ALD, CVD, electroplating, and / or other deposition techniques. In some embodiments, planarization tools may be used to planarize interconnect structures 264 after deposition.

[0108] In some embodiments, a first portion of interconnect layer 218 is constructed in the z-direction with a plurality of via layers (V layers) and metallization layers (M layers). For example, a first portion of dielectric layer 260 may be formed, and a groove may be formed in the first portion of dielectric layer 260, where a first interconnect structure 264 (e.g., a V0 via layer and an M0 metallization layer) may be formed. A second portion of dielectric layer 260 may be formed, and a groove may be formed in the second portion of dielectric layer 260, where a second interconnect structure 264 (e.g., a V1 via layer and an M1 metallization layer) may be formed. The remaining via layers and / or metallization layers of the first portion of interconnect layer 218 may be formed in a similar manner.

[0109] like Figure 5E and Figure 5F As shown, a second portion of interconnect layer 218 may be formed, and the second portion of interconnect layer 218 may include bonding layer 262 and bonding structure 266. As... Figure 5E As shown, the bonding layer 262 may be formed above and / or on the dielectric layer 260, and above and / or on the topmost interconnect structure 264. Deposition tools may be used to deposit the bonding layer 262 using PVD, ALD, CVD, oxidation, or other deposition techniques. In some embodiments, planarization tools may be used to planarize the bonding layer 262 after deposition.

[0110] like Figure 5F As shown, the bonding structure 266 can be formed in the bonding layer 262. For example, deposition tools, exposure tools, and developing tools can be used to form a patterned mask layer on the bonding layer 262. Etching tools can be used to etch the bonding layer 262 (e.g., using wet etching techniques, dry etching techniques) to form grooves in the bonding layer 262. Deposition tools and / or electroplating tools can be used to deposit the bonding structure 266 in the grooves using CVD, PVD, ALD, electroplating, and / or other deposition techniques. In some embodiments, a planarization tool can perform a planarization operation to planarize the bonding structure 266 after deposition.

[0111] As mentioned above, providing Figures 5A to 5F As an example. Other examples may be related to... Figures 5A to 5FThe descriptions are different.

[0112] Figure 6A and Figure 6B This is a schematic diagram of an example embodiment 600 of forming an image sensor device 210 (or a portion thereof) as described herein. In some embodiments, with Figure 6A and Figure 6B The one or more semiconductor processing operations described in the link can be performed using one or more semiconductor process tools, such as bonding tools and / or wafer / die transfer tools.

[0113] like Figure 6A and Figure 6B As shown, a bonding operation is performed to bond the processing device 206 and the sensor device 208 to form an image sensor device 210. The processing device 206 and the sensor device 208 may be bonded at a bonding interface 220, which may include bonding layers 242 and 262 (bonding layers of the processing device 206 and the sensor device 208, respectively), and bonding structures 246 and 266 (bonding structures of the processing device 206 and the sensor device 208, respectively). A bonding tool may be used to form a dielectric-to-dielectric bond between bonding layers 242 and 262 at the bonding interface 220, and a metal-to-metal bond between bonding structures 246 and 266 at the bonding interface 220.

[0114] like Figure 6B As shown, after bonding, the processing device 206 and the sensor device 208 are stacked or vertically configured in the z-direction within the image sensor device 210. The interconnect layer 214 of the processing device 206 and the interconnect layer 218 of the sensor device 208 face each other in the image sensor device 210, while the device layer 212 of the processing device 206 and the device layer 216 of the sensor device 208 are opposite to each other.

[0115] The bonding operation of the processing device 206 and the sensor device 208 can be performed at the wafer level, meaning that multiple processing devices 206 formed on the processing wafer 202 can be bonded to corresponding multiple sensor devices 208 on the sensor wafer 204 to form multiple image sensor devices 210. The wafer stack of the bonded processing wafer 202 and sensor wafer 204 can then be diced to separate the image sensor devices 210.

[0116] As mentioned above, providing Figure 6A and Figure 6B As an example. Other examples may be related to... Figure 6A and Figure 6B The descriptions are different.

[0117] Figures 7A to 7H This is a schematic diagram of an exemplary embodiment 700 of the formation of a pixel sensor array 222 (or a portion thereof) of the sensor device 208 described herein. In particular, the exemplary embodiment 700 may include an example of performing a back-side processing on the back side of the semiconductor layer 248 of the sensor device 208 to form a back-side pixel sensor array 222 for the sensor device 208. In some embodiments, with... Figures 7A to 7H The one or more semiconductor processing operations described in the link can be performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, electroplating tools, ion implantation tools, and / or wafer / die transfer tools.

[0118] like Figure 7A As shown, with Figures 7A to 7H The semiconductor processing operations described in the link can be processed on the front side of the sensor device 208 (in Figures 5A to 5F (As illustrated and described in the figure) Joining sensor device 208 and processing device 206 to form image sensor device 210 (in Figure 6A and Figure 6B (As illustrated and described in the figure) is then performed. The image sensor device 210 can be flipped and bonded to a carrier substrate (not shown) to allow back-side processing of the sensor device 208 to be performed.

[0119] like Figure 7B and Figure 7C As shown, trench 702 can be formed in the back side of semiconductor layer 248. Therefore, trench 702 can extend from the back surface of semiconductor layer 248 into semiconductor layer 248. Figure 7B As shown, trench 702 can be formed above shallow trench structure 252. Trench 702 can be formed such that... Figure 7C In the top view of the back side of the sensor device 208 shown, the trenches 702 intersect to form a shape similar to... Figure 2B The isolated structure of the icon is a grid of 224.

[0120] In some embodiments, a pattern in the photoresist layer is used to etch the semiconductor layer 248 to form the trench 702. In these embodiments, a deposition tool can be used to form the photoresist layer on the back side of the semiconductor layer 248. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch into the back side of the semiconductor layer 248 based on the pattern to form the trench 702. In some embodiments, the etching operation includes plasma etching, wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique).

[0121] In some embodiments, the etching operation includes a deep reactive ion etching process. For example, a first etching operation may be performed to etch semiconductor layer 248 to form trench 702 to a first depth in semiconductor layer 248. A protective layer may be formed on the sidewalls of trench 702. A portion of the protective layer on the bottom of trench 702 may be removed, and a second operation may be performed to etch semiconductor layer 248 to increase the depth of trench 702 to a second depth in semiconductor layer 248. The protective layer protects the sidewalls of trench 702 from etching and thus prevents, minimizes, and / or otherwise reduces lateral expansion of trench 702. These operations may be performed in multiple cycles to form trench 702 having a high aspect ratio between the depth of trench 702 and the lateral width of trench 702.

[0122] like Figure 7D As shown, the material of the liner 258 of the isolation structure 224 can be conformally deposited on the sidewalls and bottom surface of the trench 702. Deposition tools can be used to deposit the material of the liner 258 using conformal deposition techniques (such as CVD and / or ALD). However, other deposition techniques can be used to deposit the material of the liner 258.

[0123] In some embodiments, the material of the liner 258 is also deposited on the back surface of the semiconductor layer 248. In these embodiments, the liner 258 may extend through the back surface of the semiconductor layer 248 between the trenches 702.

[0124] In some embodiments, a hydrogen (H2) treatment operation is performed during and / or after the material deposition of the substrate 258. The hydrogen treatment operation may include providing a flow of hydrogen into the trench 702 to treat the substrate 258 to improve the alumina-silicon (AlO-Si) bonding at the interface between the semiconductor layer 248 and the substrate 258, which increases the smoothness and uniformity of the interface between the semiconductor layer 248 and the substrate 258.

[0125] like Figure 7E As shown, the material of the liner 256 of the isolation structure 224 can be conformally deposited on the sidewalls and bottom surface of the trench 702. Specifically, the material of the liner 256 can be deposited on the liner 258 within the trench 702. Deposition tools can be used to deposit the material of the liner 256 using conformal deposition techniques (e.g., ALD). The use of ALD results in the material of the liner 256 having a neutral charge, which acts as a buffer against the negative charge of the material of the liner 258. In some embodiments, other chemical deposition techniques (e.g., CVD) can be used to deposit the material of the liner 256.

[0126] In some embodiments, the material of the liner 256 is also deposited on the back surface of the semiconductor layer 248. In these embodiments, the liner 256 may extend through the back surface of the semiconductor layer 248 between the trenches 702.

[0127] like Figure 7F As shown, an antireflective coating film 268 may be formed on the back side of semiconductor layer 248. The antireflective coating film 268 may be deposited on substrate 256. An end of the antireflective coating film 268 may extend into a portion of trench 702. Deposition tools may be used to deposit the material of the antireflective coating film 268 using a deposition technique with a high deposition rate (e.g., PVD), which may result in a low step coverage of the material of the antireflective coating film 268. This reduces and / or minimizes the amount of material deposited into trench 702. Using PVD to deposit the material of the antireflective coating film 268 results in the material of the antireflective coating film 268 having a positive charge, while the material of substrate 256 (e.g., having a neutral charge) minimizes and / or prevents the positive charge of the material of the antireflective coating film 268 from offsetting the negative charge of the material of substrate 256. However, the material of the antireflective coating film 268 may be deposited using another deposition technique.

[0128] like Figure 7G As shown, trench 702 can be filled with the material of filler layer 254 of isolation structure 224. Deposition tools can be used to deposit the material of filler layer 254 on liner 256 in the trench using CVD, PVD, ALD, and / or other suitable deposition techniques. In some embodiments, plasma-enhanced deposition techniques (e.g., PEALD) are used to deposit the material of filler layer 254, resulting in the material of filler layer 254 having a positive charge. The material of liner 256 (e.g., having a neutral charge) minimizes and / or prevents the positive charge of the material of filler layer 254 from offsetting the negative charge of the material of liner 258. Filler layer 254 can be planarized (e.g., using a planarization tool) to provide a substantially flat surface on which subsequent layers and / or structures are formed.

[0129] like Figure 7H As shown, a mesh structure 270 may be formed above and / or on the filler layer 254. Deposition tools may be used to deposit one or more layers of material on the filler layer 254 using CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. The one or more layers may be patterned and etched using photolithography to form the mesh structure 270. Color filter regions 272 may be formed in the openings of the mesh structure 270, and microlenses 274 may be formed on the color filter regions 272.

[0130] As shown above, Figures 7A to 7H This is provided as an example. Other examples may differ from those provided. Figures 7A to 7H The content described.

[0131] Figure 8 This is a schematic diagram of an example embodiment 800 of pixel sensor 100, which may be included in the pixel sensor array 222 of sensor device 208 of image sensor device 210 described herein. Figure 8 The example embodiment 800 of the pixel sensor 100 shown includes... Figures 2A to 2C The pixel sensor 100 shown has a similar configuration and combination. However, in example embodiment 800, the isolation structure 224 surrounding the pixel sensor 100 includes one or more voids 802 in the filling layer 254.

[0132] A void 802 may be included in the filling layer 254 to increase the reflectivity of the isolation structure 224. Specifically, the void 802 may be filled with air (having a refractive index of approximately 1.0), which has the lowest refractive index of all materials and is closest to that of a vacuum. The low refractive index of air relative to the material of the filling layer 254 reduces the critical angle for total internal reflection of incident light 804 at the boundary between the filling layer 254 and the void 802. Incident light 804 traveling at an angle equal to or greater than the critical angle toward the boundary between the material of the filling layer 254 and the void 802 is very likely to undergo total internal reflection at the material-void boundary. Therefore, the lower critical angle increases the likelihood of total internal reflection of incident light within the isolation structure 224, which would cause the incident light to be reflected from the material-void boundary and absorbed by the photodiode 112 of the pixel sensor 100. Thus, the void 802 can increase the quantum efficiency (QE) of the pixel sensor 100.

[0133] As shown above, Figure 8 This is provided as an example. Other examples may differ from those provided. Figure 8 The content described.

[0134] Figures 9A to 9D This is a schematic diagram of an exemplary embodiment 900 of the formation of the pixel sensor array 222 (or a portion thereof) of the sensor device 208 described herein. In particular, the exemplary embodiment 900 may include an example of performing a back-side processing on the back side of the semiconductor layer 248 of the sensor device 208 to form a back-side pixel sensor array 222 for the sensor device 208. In some embodiments, in conjunction with... Figures 9A to 9D The one or more semiconductor processing operations may be performed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, electroplating tools, ion implantation tools, annealing tools, plasma tools, corona charging tools, and / or wafer / die transfer tools.

[0135] like Figures 9A to 9D As shown, the example embodiment 900 that forms the pixel sensor array 222 is similar to combining Figures 7A to 7H Example embodiment 700 shown and described. For example, trench 702 for a segment of isolation structure 224 may be formed in semiconductor layer 248, substrate 256 may be conformally deposited on the sidewalls and bottom surface of trench 702, high hydrogen concentration material of substrate 256 may be processed to make the material of substrate 256 negatively charged, antireflective coating film 268 may be formed above the back surface of semiconductor layer 248, trench 702 may be filled with material of filling layer 254 of isolation structure 224, and mesh structure 270, color filter region 272 and microlens may be formed above filling layer 254.

[0136] However, in example embodiment 900, voids 802 are formed during the deposition of material in filler layer 254. To form voids 802, a deposition technique with low step coverage (e.g., PVD) can be used to deposit material in filler layer 254. The low step coverage of the deposition technique causes material in filler layer 254 to accumulate at the top of trench 702 faster than the trench 702 can be completely filled with material in filler layer 254. In other words, the low step coverage of the deposition technique causes material in filler layer 254 to coalesce at the top of trench 702 and close trench 702 before it is completely filled with material in filler layer 254, resulting in incomplete filling of trench 702. In some embodiments, a single continuous void 802 extends through filler layer 254 of isolation structure 224. In some embodiments, multiple discontinuous voids 802 are dispersed within filler layer 254 of isolation structure 224.

[0137] As shown above, Figures 9A to 9D This is provided as an example. Other examples may differ from those provided. Figures 9A to 9D The content described.

[0138] Figure 10 This is a schematic diagram of an example embodiment 1000 of a pixel sensor 100 that may be included in the pixel sensor array 222 of the sensor device 208 of the image sensor device 210 described herein. Figure 10 An example embodiment 1000 of the pixel sensor 100 shown includes a... Figures 2A to 2CThe pixel sensor 100 shown has a similar configuration and combination. However, in the example embodiment 1000, the liner 256 and antireflective coating film 268 of the isolation structure 224 are combined to form a single layer having a greater thickness on top of the isolation structure 224 than on the bottom. The liner 256 and antireflective coating film 268 may be formed of the same material (e.g., tantalum oxide) deposited using different deposition techniques (e.g., ALD for the liner 256 and PVD for the antireflective coating film 268), and the materials may be combined to form a single continuous layer without a visible interface. The antireflective coating film 268 may correspond to a protrusion in the continuous layer on top of the isolation structure 224, resulting in necking in the fill layer 254 on top of the isolation structure 224.

[0139] As shown above, Figure 10 This is provided as an example. Other examples may differ from those provided. Figure 10 The content described.

[0140] Figure 11 This is a schematic diagram of an example embodiment 1100 of a pixel sensor 100 that may be included in the pixel sensor array 222 of the sensor device 208 of the image sensor device 210 described herein. Figure 11 Example implementation 1100 of the pixel sensor 100 shown includes with Figures 2A to 2C The pixel sensor 100 shown has a similar configuration and combination. However, in example embodiment 1100, the liner 256 of the isolation structure 224 includes a multilayer film stack.

[0141] The multilayer film stack of the liner 256 may include a first liner 256a and a second liner 256b. In some embodiments, the multilayer film stack of the liner 256 includes an additional layer. The first liner 256a and the second liner 256b may include different materials selected to adjust the refractive index of the liner 256, to adjust the dielectric constant of the liner 256, and / or to adjust other parameters of the liner 256. The materials of the first liner 256a and the second liner 256b may each include a high dielectric material having a refractive index greater than or about equal to 2.0, such as tantalum oxide (Ta2O3). x O y Zirconium oxide (ZrO) x For example, ZrO2), molybdenum oxide (MoO2) x Examples include MoO3, titanium oxide (TiOx, such as TiO2), barium titanate (BaTiO3), niobium pentoxide (Nb2O5), and / or iron oxide (Fe3O4). The liner 258 may include one or more highly dielectric materials, such as aluminum oxide (Al2O3). x O y ) and / or silicon nitride (Si xN y Examples include the first liner 256a and the second liner 256b. The materials of the first liner 256a and the second liner 256b may each be deposited using ALD technology and / or another suitable technology to achieve substantially neutral charge of the materials of the first liner 256a and the second liner 256b.

[0142] As shown above, Figure 11 This is provided as an example. Other examples may differ from those provided. Figure 11 The content described.

[0143] Figure 12 This is a flowchart of an example process 1200 associated with forming the semiconductor device described herein. In some embodiments, Figure 12 One or more process blocks are executed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, bonding tools, wafer / die transfer tools, and / or other types of semiconductor process tools.

[0144] like Figure 12 As shown, process 1200 may include a semiconductor layer of a doped semiconductor device to form a photodiode (block 1210) of a pixel sensor within the semiconductor layer. For example, one or more semiconductor process tools may be used to dope a semiconductor layer (e.g., semiconductor layer 248) of a semiconductor device (e.g., sensor device 208, image sensor device 210) to form a photodiode (e.g., photodiode 112) of a pixel sensor (e.g., pixel sensor 100) within the semiconductor layer, as described herein.

[0145] like Figure 12 As further shown, process 1200 may include etching a semiconductor layer to form a trench in the semiconductor layer such that the trench surrounds the photodiode in a top view of the semiconductor device (block 1220). For example, one or more semiconductor process tools may be used to etch the semiconductor layer to form a trench (e.g., trench 702) in the semiconductor layer such that the trench surrounds the photodiode in a top view of the semiconductor device, as described herein.

[0146] like Figure 12 As further shown, process 1200 may include depositing material for a conformal liner in a trench to form a conformal liner on the sidewalls and bottom surface of the trench (block 1230). For example, one or more semiconductor process tools may be used to deposit material for a conformal liner (e.g., liner 256, first liner 256a, second liner 256b) in a trench to form a conformal liner on the sidewalls and bottom surface of the trench, as described herein.

[0147] like Figure 12As further shown, process 1200 may include depositing a material for an antireflective coating film above the surface of a semiconductor layer, such that a portion of the antireflective coating film extends into the trench along the top portion of the sidewall of the trench (block 1240). For example, one or more semiconductor process tools may be used to deposit a material for an antireflective coating film (e.g., antireflective coating film 268) above the surface of a semiconductor layer, such that a portion of the antireflective coating film extends into the trench along the top portion of the sidewall of the trench, as described herein. In some embodiments, the material of the conformal liner and the material of the antireflective coating film are the same material. In some embodiments, the material of the conformal liner and the material of the antireflective coating film are deposited using different deposition techniques.

[0148] like Figure 12 As further shown, process 1200 may include material for depositing a dielectric fill layer on a conformal liner and over an antireflective coating film in the trench (block 1250). For example, one or more semiconductor process tools may be used to deposit material for a dielectric fill layer (e.g., fill layer 254) on a conformal liner and over an antireflective coating film in the trench, as described herein. In some embodiments, the conformal liner and dielectric fill layer in the trench correspond to a DTI structure (e.g., isolation structure 224) laterally surrounding a photodiode in a top view of the semiconductor device.

[0149] Process 1200 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or described elsewhere herein.

[0150] In the first embodiment, the material for depositing the conformal liner includes the material for depositing the conformal liner using ALD technology, and the material for depositing the antireflective coating film includes the material for depositing the antireflective coating film using PVD technology.

[0151] In the second embodiment, either alone or in combination with the first embodiment, the ALD technology causes the material of the conformal liner to have a neutral charge, and the PVD technology causes the material of the antireflective coating film to have a positive charge.

[0152] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, the thickness of the conformal liner on the trench sidewall includes the range of about 100 angstroms to about 200 angstroms.

[0153] In the fourth embodiment, either alone or in combination with one or more of the first to third embodiments, the material of the conformal liner and the material of the antireflective coating film are both tantalum oxide (Ta). x O y ).

[0154] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the material for depositing the conformal liner includes the material for depositing the conformal liner at a first deposition rate, and the material for depositing the antireflective coating film includes the material for depositing the antireflective coating film at a second deposition rate greater than the first deposition rate.

[0155] In the sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, the material for depositing the conformal liner includes the material for depositing the conformal liner in the first deposition operation, and the material for depositing the antireflective coating film includes the material for depositing the antireflective coating film in a second deposition operation following the first deposition operation.

[0156] although Figure 12 An example block of process 1200 is shown, but in some embodiments, process 1200 includes... Figure 12 The blocks shown can be compared to more blocks, fewer blocks, different blocks, or blocks with different arrangements. Additionally or alternatively, two or more blocks of process 1200 can be executed in parallel.

[0157] Figure 13 This is a flowchart of an exemplary process 1300 associated with forming the semiconductor device described herein. In some embodiments, Figure 13 One or more process blocks are executed using one or more semiconductor process tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, bonding tools, wafer / die transfer tools, and / or other types of semiconductor process tools.

[0158] like Figure 13 As shown, process 1300 may include a semiconductor layer of a doped semiconductor device to form a photodiode (block 1310) of a pixel sensor within the semiconductor layer. For example, one or more semiconductor process tools may be used to dope a semiconductor layer (e.g., semiconductor layer 248) of a semiconductor device (e.g., sensor device 208) to form a photodiode (e.g., photodiode 112) of a pixel sensor (e.g., pixel sensor 100) within the semiconductor layer, as described herein.

[0159] like Figure 13 As further shown, process 1300 may include etching a semiconductor layer to form a trench in the semiconductor layer such that the trench surrounds the photodiode in a top view of the semiconductor device (block 1320). For example, one or more semiconductor process tools may be used to etch the semiconductor layer to form a trench (e.g., trench 702) in the semiconductor layer such that the trench surrounds the photodiode in a top view of the semiconductor device, as described herein.

[0160] like Figure 13As further shown, process 1300 may include depositing material of a first conformal liner in a trench to form a first conformal liner on the sidewalls and bottom surface of the trench (block 1330). For example, one or more semiconductor process tools may be used to deposit material of a first conformal liner (e.g., liner 258) in a trench to form a first conformal liner on the sidewalls and bottom surface of the trench, as described herein.

[0161] like Figure 13 As further shown, process 1300 may include depositing a material of the second conformal liner in a trench to form the second conformal liner on the first conformal liner (block 1340). For example, one or more semiconductor process tools may be used to deposit a material of the second conformal liner (e.g., liner 256, first liner 256a, second liner 256b) in a trench to form the second conformal liner on the first conformal liner, as described herein. In some embodiments, the materials of the first conformal liner and the second conformal liner are different dielectric materials.

[0162] like Figure 13 As further shown, process 1300 may include depositing a material for an antireflective coating film above the surface of the semiconductor layer, such that a portion of the antireflective coating film extends into the trench along the top portion of the trench sidewall (block 1350). For example, one or more semiconductor process tools may be used to deposit a material for an antireflective coating film (e.g., antireflective coating film 268) above the surface of the semiconductor layer, such that a portion of the antireflective coating film extends into the trench along the top portion of the trench sidewall, as described herein. In some embodiments, the materials of the second conformal substrate and the antireflective coating film are deposited using different deposition techniques. In some embodiments, the material of the second conformal substrate has a neutral charge. In some embodiments, the material of the antireflective coating film has a positive charge.

[0163] like Figure 13 As further shown, process 1300 may include material for depositing a dielectric filling layer on a second conformal liner in the trench (block 1360). For example, one or more semiconductor process tools may be used to deposit material for a dielectric filling layer (e.g., filling layer 254) on the second conformal liner in the trench, as described herein. In some embodiments, the first conformal liner, the second conformal liner, and the dielectric filling layer in the trench correspond to a DTI structure (e.g., isolation structure 224) laterally surrounding the photodiode in a top view of the semiconductor device.

[0164] Process 1300 may include additional implementations, such as any single implementation or any combination of implementations described below and / or in conjunction with one or more other processes described elsewhere herein.

[0165] In a first embodiment, process 1300 includes bonding a semiconductor device to another semiconductor device to form a 3DCIS device (e.g., image sensor device 210) including the semiconductor device and the other semiconductor device.

[0166] In the second embodiment, either alone or in combination with the first embodiment, the materials of the second conformal liner and the antireflective coating film each have a dielectric constant that is approximately twice that of the material of the second conformal liner.

[0167] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, the material density of the second conformal liner is greater than the material density of the antireflective coating film.

[0168] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, the material for depositing the dielectric fill layer includes a material for depositing the dielectric fill layer at a deposition rate that results in the formation of voids (e.g., void 802) in the dielectric fill layer in the trench.

[0169] In the fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, the materials of the second conformal liner and the antireflective coating film each have a refractive index greater than about 2.0.

[0170] In the sixth embodiment, the material of the second conformal liner and the material of the antireflective coating film are different, either alone or in combination with one or more of the first to fifth embodiments.

[0171] In the seventh embodiment, the material of the second conformal liner and the material of the antireflective coating film are the same, either alone or in combination with one or more of the first to sixth embodiments.

[0172] Although Figure 13 The example block of process 1300 is shown, but in some embodiments, process 1300 includes... Figure 13 The blocks described herein are compared to additional blocks, fewer blocks, different blocks, or blocks with different arrangements. In addition, or alternatively, two or more blocks of process 1300 can be executed in parallel.

[0173] In this manner, the isolation structure in the pixel sensor array of an image sensor device is fabricated to include a first substrate that passivates dangling bonds in the substrate layer of the image sensor, such dangling bonds being formed during etching of the substrate layer to form trenches in which segments of the isolation structure are formed. The first substrate may have a negative charge to passivate the dangling bonds in the substrate layer, which reduces the likelihood and / or amount of charge accumulation around the isolation structure. This increases the sensitivity of the pixel sensor in the pixel sensor array, which may increase the responsiveness of the pixel sensor (which may increase low-light rotation performance) and / or increase the dynamic range of the pixel sensor, among other examples. A second substrate may be deposited on the first substrate to protect the electronegativity of the first substrate from being offset by the material of the filler layer subsequently deposited in the trenches of the isolation structure. The material of the filler layer may have a positive charge, which would otherwise potentially offset the passivation provided by the negative charge of the first substrate. The second substrate may be deposited using a deposition technique such as atomic layer deposition, which results in the second substrate having a neutral charge. The neutral charge causes the second liner to act as a barrier between the first liner and the filler layer, which prevents the positive charge of the filler material from offsetting the negative charge of the first liner material.

[0174] As described in more detail above, some embodiments described herein provide methods for forming an image sensor device. The method of forming an image sensor device includes doping a semiconductor layer of a semiconductor device to form a photodiode of a pixel sensor within the semiconductor layer. The method includes etching the semiconductor layer to form a trench in the semiconductor layer such that the trench surrounds the photodiode in a top view of the semiconductor device. The method includes depositing a conformal liner material in the trench to form a conformal liner on the sidewalls and bottom surface of the trench. The method includes depositing an anti-reflective coating film material above a surface of the semiconductor layer such that a portion of the anti-reflective coating film extends into the trench along the top portion of the sidewalls of the trench, wherein the conformal liner material and the anti-reflective coating film material are the same material, and wherein the conformal liner material and the anti-reflective coating film material are deposited using different deposition techniques. The method includes depositing a dielectric filling layer material on the conformal liner in the trench and above the anti-reflective coating film, wherein the conformal liner and the dielectric filling layer in the trench correspond to a DTI structure laterally surrounding the photodiode in a top view of the semiconductor device.

[0175] As described in more detail above, some embodiments described herein provide methods for forming an image sensor device. The method of forming an image sensor device includes doping a semiconductor layer of a semiconductor device to form a photodiode of a pixel sensor within the semiconductor layer. The method includes etching the semiconductor layer to form a trench in the semiconductor layer such that the trench surrounds the photodiode in a top view of the semiconductor device. The method includes depositing a material of a first conformal liner in the trench to form a first conformal liner on the sidewalls and bottom surface of the trench. The method includes depositing a material of a second conformal liner in the trench to form a second conformal liner on the first conformal liner, wherein the materials of the first conformal liner and the second conformal liner are different dielectric materials. The method includes depositing a material of an antireflective coating film above a surface of the semiconductor layer such that a portion of the antireflective coating film extends into the trench along the top portion of the sidewalls of the trench, wherein the materials of the second conformal liner and the antireflective coating film are deposited using different deposition techniques, wherein the material of the second conformal liner has a neutral charge, and wherein the material of the antireflective coating film has a positive charge. The method includes depositing a material of a dielectric filling layer on a second conformal liner in a trench, wherein the first conformal liner, the second conformal liner, and the dielectric filling layer in the trench correspond to a DTI structure laterally surrounding a photodiode in a top view of a semiconductor device.

[0176] As described in more detail above, some embodiments described herein provide an image sensor device. The image sensor device includes a sensor device. The image sensor device includes a processing device bonded to the sensor device such that the sensor device and the processing device are stacked within the image sensor device. A first side of the sensor device is bonded to the processing device. The sensor device includes a plurality of photodiodes and an isolation structure in a semiconductor layer of the sensor device. The isolation structure includes a plurality of interconnected segments in the semiconductor layer, the plurality of interconnected segments extending laterally around the plurality of photodiodes. In a top view of the isolation structure, the isolation structure includes rounded corners at the intersections of the plurality of interconnected segments. The plurality of interconnected segments of the isolation structure include a dielectric filling layer. The plurality of interconnected segments of the isolation structure include a first substrate between the semiconductor layer and the dielectric filling layer, wherein the material of the first substrate has a negative flat-band voltage. The plurality of interconnected segments of the isolation structure include a second substrate between the first substrate and the dielectric filling layer. The material of the second substrate has a positive flat-band voltage, and the sensor device includes an anti-reflective coating film on top of the dielectric filling layer and between the second substrate. The material of the anti-reflective coating film has a negative flat-band voltage.

[0177] The terms "approximately" and "substantially" can indicate that a given quantity varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and not limiting. It should be understood that the terms "approximately" and "substantially" can refer to a percentage of a given quantity according to this disclosure.

[0178] The features of several embodiments have been summarized above to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be used as a basis for designing or modifying other processes and structures to achieve the same purpose and / or attain the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming an image sensor device, characterized in that, include: A semiconductor layer doped with a semiconductor device to form a photodiode for a pixel sensor in the semiconductor layer; The semiconductor layer is etched to form trenches in the semiconductor layer such that the trenches surround the photodiode in a top view of the semiconductor device; The material of the conformal liner is deposited in the trench to form the conformal liner on the sidewalls and bottom surface of the trench. A material for depositing an anti-reflective coating film is deposited on the surface of the semiconductor layer such that a portion of the anti-reflective coating film extends into the trench along the top portion of the sidewall of the trench. The conformal liner and the antireflective coating film are made of the same material. The materials of the conformal liner and the antireflective coating film are deposited using different deposition techniques; as well as Material for depositing a dielectric filler layer on the conformal liner in the trench and above the antireflective coating film. The conformal liner and the dielectric filling layer in the trench correspond to a deep trench isolation structure that laterally surrounds the photodiode in the top view of the semiconductor device.

2. The method according to claim 1, characterized in that, The material used to deposit the conformal liner includes the material used to deposit the conformal liner using atomic layer deposition technology; and The material used to deposit the antireflective coating film includes the material used to deposit the antireflective coating film using physical vapor deposition technology.

3. The method according to claim 2, characterized in that, The atomic layer deposition technique described therein results in the conformal substrate material having a neutral charge; and The physical vapor deposition technique described therein results in the material of the antireflective coating film having a positive charge.

4. The method according to claim 1, characterized in that, The thickness of the conformal liner on the sidewall of the trench is in the range of 100 angstroms to 200 angstroms.

5. A method for forming an image sensor device, characterized in that, include: A semiconductor layer doped with a semiconductor device to form a photodiode for a pixel sensor in the semiconductor layer; The semiconductor layer is etched to form trenches in the semiconductor layer such that the trenches surround the photodiode in a top view of the semiconductor device; The material of the first conformal liner is deposited in the trench to form the first conformal liner on the sidewalls and bottom surface of the trench; Material for the second conformal liner is deposited in the trench to form the second conformal liner on the first conformal liner. The materials of the first conformal liner and the second conformal liner are different dielectric materials; A material for depositing an anti-reflective coating film is deposited on the surface of the semiconductor layer such that a portion of the anti-reflective coating film extends into the trench along the top portion of the sidewall of the trench. The material of the second conformal liner and the material of the anti-reflective coating film are deposited using different deposition techniques. The material of the second conformal liner has a neutral charge, and The material of the antireflective coating film has a positive charge; as well as The material for depositing a dielectric filling layer on the second conformal liner in the trench, The first conformal liner, the second conformal liner, and the dielectric filling layer in the trench correspond to a deep trench isolation structure laterally surrounding the photodiode in the top view of the semiconductor device.

6. The method according to claim 5, characterized in that, Including: The semiconductor device is coupled with another semiconductor device to form a three-dimensional complementary metal-oxide-semiconductor image sensor device comprising the semiconductor device and the other semiconductor device.

7. The method according to claim 5, characterized in that, The material of the second conformal liner and the material of the antireflective coating film each have a dielectric constant that is more than twice the dielectric constant of the material of the second conformal liner.

8. The method according to claim 5, characterized in that, The material density of the second conformal liner is greater than that of the antireflective coating film.

9. The method according to claim 5, characterized in that, The material used to deposit the dielectric filling layer includes: The material of the dielectric filling layer is deposited at a deposition rate that causes voids to form in the dielectric filling layer in the trench.

10. An image sensor device, characterized in that, include: Sensor devices; as well as A processing device is coupled to the sensor device such that the sensor device and the processing device are stacked within the image sensor device. The first side of the sensor device is coupled to the processing device, and The sensor device mentioned above includes: Multiple photodiodes in the semiconductor layer of the sensor device; An isolation structure includes a plurality of interconnected segments in the semiconductor layer, the plurality of interconnected segments extending laterally around the plurality of photodiodes. In the top view of the isolation structure, the isolation structure includes rounded corners at the intersections of the plurality of interconnected segments, and The plurality of interconnected segments of the isolation structure include: Dielectric filling layer; A first substrate is located between the semiconductor layer and the dielectric filling layer. The material of the first liner has a negative flat voltage; and The second liner is located between the first liner and the dielectric filling layer. The material of the second liner has a positive flat voltage; and An anti-reflective coating film is located on top of the dielectric filling layer and between the second liner. The material of the antireflective coating film has a negative flat band voltage.

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