An image sensor and a manufacturing method thereof

Abstract

An image sensor and a manufacturing method thereof, the method comprising: providing a substrate, the substrate having a first photodiode and a second photodiode formed therein; forming a plurality of top wide and middle narrow color isolation structures between adjacent photodiodes on a first surface of the substrate; depositing a first dielectric layer covering the color isolation structures; performing a photoresist-free blocking dry etching on the first dielectric layer to remove a lateral protrusion on a top portion thereof; depositing an optical blocking layer on the first dielectric layer; forming a patterned photoresist layer on the optical blocking layer, the patterned photoresist layer exposing at least a portion of the first photodiode and shielding at least a portion of the second photodiode; etching the optical blocking layer with the patterned photoresist layer as a mask to remove at least a portion of the optical blocking layer above the first photodiode. The present application can avoid forming optical blocking layer residues.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically to an image sensor and its manufacturing method. Background Technology

[0002] In image sensors, to improve dynamic range, photodiodes of different sizes are typically placed within the same pixel array. Larger photodiodes are used for low-intensity sensing, while smaller photodiodes are used for high-intensity sensing. Currently, color isolation is used to form a color-isolation structure between the large and small photodiodes to achieve optical isolation between pixels. A metal grid process is used to form an optical blocking layer above the smaller photodiode to prevent saturation under high-intensity light. However, during the etching process of the metal grid, the inwardly recessed sidewalls of the color isolation structure during etching cause the subsequently deposited dielectric layer to form outwardly protruding lateral protrusions on top of the color isolation structure. When an optical blocking layer is deposited on this morphology and photolithography is performed, residual optical blocking layers remain at the recessed areas. These residual optical blocking layers affect the overall performance of the image sensor. Summary of the Invention

[0003] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. The summary section of this invention is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0004] To address the existing problems, one embodiment of the present invention provides a method for manufacturing an image sensor, comprising: A substrate is provided, the substrate including a first surface and a second surface, wherein a plurality of photodiodes are formed in the substrate adjacent to the first surface, the plurality of photodiodes including at least one first photodiode and at least one second photodiode; On the first surface of the substrate, a plurality of color isolation structures, which are wide at the top and narrow in the middle, are formed between adjacent photodiodes; A first dielectric layer is deposited to cover the color isolation structure; Dry etching without photoresist obstruction is performed on the first dielectric layer to remove the lateral protrusions on the top of the first dielectric layer; An optical blocking layer is deposited on the first dielectric layer; A patterned photoresist layer is formed on the optical blocking layer, the patterned photoresist layer exposing at least a portion of the first photodiode and shielding at least a portion of the second photodiode; The optical blocking layer is etched using the patterned photoresist layer as a mask to remove at least a portion of the optical blocking layer located above the first photodiode.

[0005] In one embodiment, forming a plurality of color-blocking structures that are wide at the top and narrow in the middle between adjacent photodiodes includes: A second metal layer and a third metal layer are sequentially formed on the first surface of the substrate; The third metal layer and the second metal layer are etched sequentially to form the color isolation structure; The etching rate of the third metal layer is less than that of the second metal layer, so that the width of the third metal layer after etching is greater than that of the second metal layer.

[0006] In one embodiment, a first metal layer is further formed between the second metal layer and the substrate, and the etching rate of the first metal layer is less than the etching rate of the second metal layer, such that the width of the first metal layer is greater than the width of the second metal layer after etching.

[0007] In one embodiment, the materials of the first metal layer and the third metal layer include at least one of the following: titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, and tantalum oxide, and the material of the second metal layer includes aluminum.

[0008] In one embodiment, a second dielectric layer is further formed on the first surface of the substrate, the color isolation structure is formed on the second dielectric layer, and the first dielectric layer covers the second dielectric layer between adjacent color isolation structures.

[0009] In one embodiment, the deposition covers a first dielectric layer of the color isolation structure; the first dielectric layer is subjected to dry etching without photoresist obstruction to remove the lateral protrusions on the top of the first dielectric layer, including: After depositing the first dielectric layer using a deposition process, the first dielectric layer is etched using a dry etching process without photoresist obstruction. The deposition process includes at least one of the following: plasma-enhanced chemical vapor deposition, high aspect ratio chemical vapor deposition, high-density plasma chemical vapor deposition, and atomic layer deposition. The dry etching process includes inductively coupled plasma etching, capacitively coupled plasma etching, or atomic layer etching.

[0010] In one embodiment, the deposition covers a first dielectric layer of the color isolation structure; the first dielectric layer is subjected to dry etching without photoresist obstruction to remove the lateral protrusions on the top of the first dielectric layer; including: A high-density plasma chemical vapor deposition process is performed, wherein deposition and etching are carried out simultaneously in the high-density plasma chemical vapor deposition process; In the first stage, the deposition rate is greater than the etching rate to form the first dielectric layer; In the second stage, the etching rate is greater than the deposition rate to remove the lateral protrusions on top of the first dielectric layer.

[0011] In one embodiment, the deposition covers a first dielectric layer of the color isolation structure; the first dielectric layer is subjected to dry etching without photoresist obstruction to remove the lateral protrusions on the top of the first dielectric layer, including: After depositing the first dielectric layer using a deposition process, the first dielectric layer is dry-etched without photoresist obstruction using a high-density plasma chemical vapor deposition process. The deposition process includes at least one of the following: plasma-enhanced chemical vapor deposition, high aspect ratio chemical vapor deposition, and atomic layer deposition. During the high-density plasma chemical vapor deposition process, the etching rate is greater than the deposition rate to remove the lateral protrusions on the top of the first dielectric layer.

[0012] In one embodiment, after the dry etching process without photoresist obstruction, the width of the first dielectric layer gradually increases from top to bottom.

[0013] In one embodiment, the material of the optical blocking layer includes at least one of the following: titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, and tantalum oxide.

[0014] Another embodiment of the present invention provides an image sensor, comprising: A substrate, the substrate including a first surface and a second surface, wherein a plurality of photodiodes are formed in the substrate adjacent to the first surface, the plurality of photodiodes including at least one first photodiode and at least one second photodiode; Multiple color isolation structures, wide at the top and narrow in the middle, are formed on the first surface of the substrate and located between adjacent photodiodes; A first dielectric layer covering the color isolation structure, wherein the top width of the first dielectric layer is not greater than its bottom width; An optical blocking layer is formed on the first dielectric layer above the second photodiode.

[0015] According to the image sensor manufacturing method of the present invention, by removing the lateral protrusions on the top of the first dielectric layer before depositing the optical blocking layer, it is possible to avoid the formation of optical blocking layer residue due to the lateral protrusions blocking the etching. Attached Figure Description

[0016] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0017] In the attached image: Figures 1A-1D A cross-sectional view of an image sensor obtained by sequentially performing the steps of a manufacturing method for an image sensor in the related art is shown. Figure 1E A TEM (transmission electron microscope) image of the optical blocking layer remaining on the sidewall of the color-isolated structure is shown. Figure 2 A schematic flowchart illustrating a method for manufacturing an image sensor according to an embodiment of the present invention is shown; Figures 3A-3F A cross-sectional view of an image sensor obtained by sequentially performing the steps of a method for manufacturing an image sensor according to an embodiment of the present invention is shown. Detailed Implementation

[0018] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0019] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0020] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0021] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0023] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0024] In related technologies, firstly, such as Figure 1A As shown, a substrate 100 is provided, in which a larger first photodiode 101 and a smaller second photodiode 102 are formed, and a color isolation structure 103 is formed on the surface of the substrate 100; then as... Figure 1B As shown, a dielectric layer 104 and an optical blocking layer 105 are formed covering the color isolation structure 103; then as... Figure 1C As shown, a photoresist layer 106 is formed above the second photodiode 102, while simultaneously exposing the first photodiode 101; finally, as shown... Figure 1D As shown, the optical blocking layer 105 is etched using the photoresist layer 106 as a mask to remove the optical blocking layer 105 above the first photodiode 101, while retaining the optical blocking layer 105 above the second photodiode 102 to prevent the second photodiode 102 from saturating under high-intensity light irradiation, while ensuring that the first photodiode 101 receives sufficient light.

[0025] In the above process, because the top of the color isolation structure 103 is relatively wide, a lateral protrusion is formed on the top of the dielectric layer 104. This lateral protrusion blocks the etching of the optical blocking layer 105, resulting in a residue of the optical blocking layer 105 in the recess below the lateral protrusion. Figure 1E As shown. These residual optical blocking layers 105 can affect the overall performance of the image sensor.

[0026] To address the aforementioned problems, embodiments of the present invention provide an image sensor and a method for manufacturing the same. The following refers to... Figure 2 The manufacturing method of the image sensor according to embodiments of the present invention will be described in detail. For example... Figure 2 As shown, the manufacturing method mainly includes the following steps: In step S201, a substrate is provided, the substrate including a first surface and a second surface, and a plurality of photodiodes adjacent to the first surface are formed in the substrate, the plurality of photodiodes including at least one first photodiode and at least one second photodiode; In step S202, a plurality of color isolation structures, which are wide at the top and narrow in the middle, are formed on the first surface of the substrate between adjacent photodiodes; In step S203, a first dielectric layer covering the color isolation structure is deposited; In step S204, the first dielectric layer is subjected to dry etching without photoresist obstruction to remove the lateral protrusions on the top of the first dielectric layer; In step S205, an optical blocking layer is deposited on the first dielectric layer; In step S206, a patterned photoresist layer is formed on the optical blocking layer, the patterned photoresist layer exposing at least a portion of the first photodiode and shielding at least a portion of the second photodiode; In step S207, the optical blocking layer is etched using a patterned photoresist layer as a mask to remove at least a portion of the optical blocking layer located above the first photodiode.

[0027] The following reference Figures 3A-3F A method for manufacturing an image sensor according to an embodiment of the present invention will be described in detail.

[0028] First, such as Figure 3A As shown, a substrate 300 is provided. The substrate 300 includes a first surface and a second surface. In this embodiment, the first surface is the back surface of the substrate 300, and the second surface is the front surface of the substrate 300, thus forming a back-illuminated image sensor. In other embodiments, the first surface is the front surface of the substrate 300, and the second surface is the back surface of the substrate 300, thus forming a front-illuminated image sensor. The material of the substrate 300 can be single-crystal silicon, silicon-on-insulator, or other semiconductor materials. In a preferred embodiment, the substrate 300 is a p-type doped silicon substrate.

[0029] In the substrate 300, a plurality of photodiodes are formed near the first surface. The plurality of photodiodes includes at least one first photodiode 301 and at least one second photodiode 302. Exemplarily, the first photodiode 301 is larger than the second photodiode 302. The first photodiode 301 is used for low light intensity sensing and has a larger full-well capacity; the second photodiode 302 is used for high light intensity sensing and has a smaller full-well capacity. By using two photodiodes of different sizes, high dynamic range imaging can be achieved.

[0030] Photodiodes can be formed using an ion implantation process. For example, N-type doped ions (such as phosphorus or arsenic) are implanted onto the first surface of substrate 300 to form an N-type photodiode region, followed by high-temperature annealing to activate the doped ions and repair lattice damage.

[0031] Exemplarily, a deep trench isolation structure 303 is also formed between adjacent photodiodes. The deep trench isolation structure 303 extends from a first surface of the substrate 300 into the interior of the substrate 300 to prevent electrical and optical crosstalk between adjacent photodiodes. In other embodiments, the deep trench isolation structure 303 extends from a second surface of the substrate 300 into the interior of the substrate 300. Exemplarily, trenches can be formed in the substrate 300 by photolithography and etching processes, and then dielectric material can be filled into the trenches to form the deep trench isolation structure 303.

[0032] For example, a second dielectric layer 304 is also formed on the first surface of the substrate 300. The material of the second dielectric layer 304 may be silicon oxide, silicon nitride, or silicon oxynitride, etc., serving as an etch stop layer or a stress buffer layer.

[0033] Next, a plurality of color isolation structures 305 are formed on the first surface of the substrate 300, located between adjacent photodiodes. The color isolation structures 305 are formed above the deep trench isolation structure 303. In this embodiment of the invention, the color isolation structures 305 have a morphology that is wide at the top and narrow in the middle, a morphology caused by the difference in etching rates of different materials during the etching process. Specifically, the color isolation structures 305 can be as follows: Figure 3A The top and bottom are wide and the middle is narrow, or the top is wide and the bottom is narrow, as long as there is a depression in the middle, it is applicable to the embodiments of the present invention.

[0034] In this embodiment, the specific method for forming the color isolation structure 305 includes: First, a first metal layer 3051, a second metal layer 3052, and a third metal layer 3053 are sequentially formed on the first surface of the substrate 300. Exemplarily, the second metal layer 3052 is made of aluminum, and the first metal layer 3051 or the third metal layer 3053 is made of at least one of titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, and tantalum oxide. Next, the stacked layers are patterned using photolithography and etching processes to form a grid-like color isolation structure 305. The openings of the grid-like structure correspond one-to-one with the photodiodes below, and the grid-like structure is located above the area between adjacent photodiodes.

[0035] During the etching process, the etching rate of the third metal layer 3053 and the first metal layer 3051 is less than that of the second metal layer 3052. Therefore, after etching, the width of the third metal layer 3053 and the first metal layer 3051 is greater than that of the second metal layer 3052, forming a cross-sectional shape that is wide at the top and bottom and narrow in the middle.

[0036] In other embodiments, if the first metal layer 3051 is not formed below the second metal layer 3052, or if the etching rate of the first metal layer 3051 is not less than the etching rate of the second metal layer 3052, the color isolation structure 305 formed after etching will have a morphology that is wide at the top and narrow at the bottom.

[0037] Next, as Figure 3B As shown, a first dielectric layer 306 is deposited on the first surface of the substrate 300 and on the color isolation structure 305. The first dielectric layer 306 also covers a second dielectric layer 304 between adjacent color isolation structures 305. Exemplarily, the material of the first dielectric layer 306 is silicon oxide. The first dielectric layer 306 is deposited using a thickened deposition method, and its deposition thickness is greater than the dielectric layer thickness required below the optical blocking layer in conventional processes, in order to compensate for the amount of material to be removed in subsequent dry etching processes without photoresist blocking, ensuring that sufficient dielectric layer thickness is retained after etching and shaping.

[0038] Because the color isolation structure 305 has a widened top, the first dielectric layer 306 will form an outward lateral protrusion on the top of the color isolation structure 305 during the deposition process. If this lateral protrusion is retained in subsequent processes, it will block the etching ions and form an optical blocking layer residue below it.

[0039] Next, as Figure 3C As shown, the first dielectric layer 306 is subjected to dry etching without photoresist obstruction. This dry etching does not use a photoresist mask and uniformly etches the entire first dielectric layer 306.

[0040] During the etching process, the lateral protrusions on the top of the color isolation structure 305, due to their large surface area, are exposed to etching ions in multiple directions and are therefore preferentially removed. Furthermore, in the dry etching process without photoresist obstruction, for the trenches between the color isolation structures 305, ions continuously collide with the sidewalls after entering the trenches, gradually losing energy. Therefore, the top of the trench receives the highest plasma density and the strongest ion energy, gradually decreasing downwards, while the bottom of the trench receives the lowest plasma density and the weakest ion energy. This causes the etching rate to decrease with increasing trench depth. Therefore, as etching progresses, the first dielectric layer 306 eventually forms a trapezoidal morphology that is narrower at the top and wider at the bottom.

[0041] In one embodiment, a high-density plasma chemical vapor deposition (HDPCVD) process can be performed, integrating deposition and etching. Specifically, during the HDPCVD process, deposition and etching occur simultaneously: chemical vapor deposition is performed on one hand, and on the other hand, a radio frequency bias is applied to the wafer to attract high-energy ions to physically bombard the thin film (i.e., etching). This simultaneous physical bombardment can preferentially remove overhangs grown at the top corners of the holes, preventing premature sealing at the top, thereby ensuring that reactive gases can continuously enter the bottom of the holes, achieving bottom-up hole-free filling.

[0042] Generally, due to its high cost, HDPCVD technology is mainly used for filling trenches with high aspect ratios. The trenches between the color isolation structures 305 have a smaller aspect ratio, and plasma-enhanced chemical vapor deposition (PECVD) is primarily used. This embodiment uses HDPCVD to deposit the first dielectric layer 306 to integrate deposition and etching. Specifically, in the first stage, the deposition rate is greater than the etching rate to form the first dielectric layer 306; in the second stage, the process parameters are adjusted so that the etching rate is greater than the deposition rate to remove the lateral protrusions on the top of the first dielectric layer. This eliminates the need for additional etching steps, shortens the process time, and improves production efficiency.

[0043] In another embodiment, the deposition and etching of the first dielectric layer 306 can also be performed in steps, with the first dielectric layer 306 being formed by a deposition process and then etched and trimmed by an independent dry etching process.

[0044] Specifically, firstly, a first dielectric layer 306 is deposited on the second dielectric layer 304 and the color isolation structure 305 using plasma-enhanced chemical vapor deposition (PECVD), high aspect ratio chemical vapor deposition (HARPCVD), high-density plasma-enhanced chemical vapor deposition (HDCVD), or atomic layer deposition (ALD). Then, the wafer is transferred to a dry etching apparatus, where the first dielectric layer 306 is etched without photoresist obstruction to remove the lateral protrusions on its top. Plasma-enhanced chemical vapor deposition is less expensive than HDCVD and has a faster deposition rate; the independent dry etching process offers more flexible morphology control, allowing for independent optimization of the etching effect by adjusting etching parameters, without being constrained by the deposition process.

[0045] For example, dry etching processes include inductively coupled plasma etching, capacitively coupled plasma etching, or atomic layer etching.

[0046] In another embodiment, a first dielectric layer may be deposited first using a deposition process, and then the first dielectric layer may be dry etched without photoresist obstruction using an HDPCVD process; wherein, the deposition process includes PECVD, HARP, ALD or other deposition processes other than HDPCVD; then, the wafer is transferred to an HDPCVD device, and during the HDPCVD process, the etching rate is greater than the deposition rate to remove the lateral protrusions on the top of the first dielectric layer.

[0047] Next, as Figure 3D As shown, an optical blocking layer 307 is deposited on the first dielectric layer 306. The material of the optical blocking layer 307 includes at least one of titanium, titanium oxide, titanium nitride, tantalum, tantalum oxide, or tantalum nitride. The optical blocking layer 307 is used to attenuate light entering the second photodiode 302, preventing the second photodiode 302 from saturating under high-intensity light irradiation. Exemplarily, the optical blocking layer 307 can be formed using a physical vapor deposition (PVD) process.

[0048] Next, as Figure 3E As shown, a patterned photoresist layer 308 is formed on the optical blocking layer 307. The patterned photoresist layer 308 exposes at least a portion of the area above the first photodiode 301 while shielding at least a portion of the area above the second photodiode 302.

[0049] Specifically, the openings in the patterned photoresist layer 308 can have different sizes and locations. For example, in one embodiment, such as Figure 3E As shown, the opening exposes at least the entire first photodiode 301, and also exposes portions of the color isolation structure located on both sides of the first photodiode. In another embodiment, the opening exposes only the central region of the first photodiode 301. In one embodiment, the photoresist layer 308 shields the entire second photodiode 302. In another embodiment, the photoresist layer 308 shields the central region of the second photodiode 302.

[0050] Next, as Figure 3F As shown, using a patterned photoresist layer 308 as a mask, the optical blocking layer 307 is etched to remove at least a portion of the optical blocking layer 307 located above the first photodiode 301, while retaining at least a portion of the optical blocking layer 307 above the second photodiode 302.

[0051] Since the lateral protrusions on the top of the color isolation structure 305 have been removed in the previous dry etching without photoresist obstruction, when the optical barrier layer 307 is etched using the patterned photoresist layer 308 as a mask, the etching plasma can enter the bottom of the trench without obstruction in the vertical direction, and there will be no areas that cannot be etched due to the obstruction of the lateral protrusions. Therefore, the optical barrier layer 307 located above the first photodiode 301 can be completely removed without any residue.

[0052] After etching, the patterned photoresist layer 308 is removed. Following this, a color filter array and a microlens array can be formed, along with subsequent processes such as wafer dicing and packaging, to create the image sensor chip. These subsequent processes can employ standard processes known in the art and will not be elaborated upon here.

[0053] According to the image sensor manufacturing method of the present invention, by removing the lateral protrusions on the top of the first dielectric layer before depositing the optical blocking layer, it is possible to avoid the formation of optical blocking layer residues above the photodiode due to the lateral protrusions blocking the etching.

[0054] The present invention also provides an image sensor, which can be manufactured using the above-described process. For example... Figure 3F As shown, the image sensor of this embodiment includes: a substrate 300, the substrate 300 including a first surface and a second surface, and a plurality of photodiodes adjacent to the first surface formed in the substrate 300, the plurality of photodiodes including at least one first photodiode 301 and at least one second photodiode 302; On the first surface of the substrate 300, there are multiple color isolation structures 305 that are wide at the top and narrow in the middle, located between adjacent photodiodes; The first dielectric layer 306 covering the color isolation structure has a top width that is not greater than its bottom width. An optical blocking layer 307 is formed on the first dielectric layer 306 above the second photodiode 302.

[0055] In the image sensor of this embodiment, there is no residual optical blocking layer 307 above the first photodiode 301, so the light entering the first photodiode 301 will not be blocked.

[0056] Another embodiment of the present invention also provides an electronic device including the aforementioned image sensor, which is prepared according to the aforementioned method.

[0057] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, television, VCD player, DVD player, navigator, digital photo frame, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including circuitry. The electronic device in this embodiment of the invention, due to the use of the aforementioned image sensor, has better performance.

[0058] The present invention has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, those skilled in the art will understand that the present invention is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of the present invention, all of which fall within the scope of protection claimed by the present invention. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for manufacturing an image sensor, characterized in that, include: A substrate is provided, the substrate including a first surface and a second surface, wherein a plurality of photodiodes are formed in the substrate adjacent to the first surface, the plurality of photodiodes including at least one first photodiode and at least one second photodiode; On the first surface of the substrate, a plurality of color isolation structures, which are wide at the top and narrow in the middle, are formed between adjacent photodiodes; A first dielectric layer is deposited to cover the color isolation structure; Dry etching without photoresist obstruction is performed on the first dielectric layer to remove the lateral protrusions on the top of the first dielectric layer; An optical blocking layer is deposited on the first dielectric layer; A patterned photoresist layer is formed on the optical blocking layer, the patterned photoresist layer exposing at least a portion of the first photodiode and shielding at least a portion of the second photodiode; The optical blocking layer is etched using the patterned photoresist layer as a mask to remove at least a portion of the optical blocking layer located above the first photodiode.

2. The method according to claim 1, characterized in that, The formation of multiple color isolation structures, wider at the top and narrower in the middle, located between adjacent photodiodes, includes: A second metal layer and a third metal layer are sequentially formed on the first surface of the substrate; The third metal layer and the second metal layer are etched sequentially to form the color isolation structure; The etching rate of the third metal layer is less than that of the second metal layer, so that the width of the third metal layer after etching is greater than that of the second metal layer.

3. The method according to claim 2, characterized in that, A first metal layer is also formed between the second metal layer and the substrate. The etching rate of the first metal layer is less than that of the second metal layer, so that the width of the first metal layer is greater than that of the second metal layer after etching.

4. The method according to claim 3, characterized in that, The materials of the first metal layer and the third metal layer include at least one of the following: titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, and tantalum oxide; the material of the second metal layer includes aluminum.

5. The method according to claim 1, characterized in that, The deposition covers the first dielectric layer of the color isolation structure; Performing dry etching without photoresist blockage on the first dielectric layer to remove the lateral protrusions on the top of the first dielectric layer includes: After depositing the first dielectric layer using a deposition process, the first dielectric layer is etched using a dry etching process without photoresist obstruction. The deposition process includes at least one of the following: plasma-enhanced chemical vapor deposition, high aspect ratio chemical vapor deposition, high-density plasma chemical vapor deposition, and atomic layer deposition. The dry etching process includes inductively coupled plasma etching, capacitively coupled plasma etching, or atomic layer etching.

6. The method according to claim 1, characterized in that, The deposition covers the first dielectric layer of the color isolation structure; Dry etching without photoresist blockage is performed on the first dielectric layer to remove the lateral protrusions on the top of the first dielectric layer; including: A high-density plasma chemical vapor deposition process is performed, wherein deposition and etching are carried out simultaneously in the high-density plasma chemical vapor deposition process; In the first stage, the deposition rate is greater than the etching rate to form the first dielectric layer; In the second stage, the etching rate is greater than the deposition rate to remove the lateral protrusions on top of the first dielectric layer.

7. The method according to claim 1, characterized in that, The deposition covers the first dielectric layer of the color isolation structure; Performing dry etching without photoresist blockage on the first dielectric layer to remove the lateral protrusions on the top of the first dielectric layer includes: After depositing the first dielectric layer using a deposition process, the first dielectric layer is dry-etched without photoresist obstruction using a high-density plasma chemical vapor deposition process. The deposition process includes at least one of the following: plasma-enhanced chemical vapor deposition, high aspect ratio chemical vapor deposition, and atomic layer deposition. During the high-density plasma chemical vapor deposition process, the etching rate is greater than the deposition rate to remove the lateral protrusions on the top of the first dielectric layer.

8. The method according to claim 1, characterized in that, After the dry etching process without photoresist obstruction, the width of the first dielectric layer gradually increases from top to bottom.

9. The method according to claim 1, characterized in that, The material of the optical blocking layer includes at least one of the following: titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, and tantalum oxide.

10. An image sensor, characterized in that, include: A substrate, the substrate including a first surface and a second surface, wherein a plurality of photodiodes are formed in the substrate adjacent to the first surface, the plurality of photodiodes including at least one first photodiode and at least one second photodiode; Multiple color isolation structures, wide at the top and narrow in the middle, are formed on the first surface of the substrate and located between adjacent photodiodes; A first dielectric layer covering the color isolation structure, wherein the top width of the first dielectric layer is not greater than its bottom width; An optical blocking layer is formed on the first dielectric layer above the second photodiode.

Images