A front-illuminated image sensor and method of implementing the same

Abstract

The application discloses a front-illuminated image sensor and an implementation method thereof. The front-illuminated image sensor is optically and electrically isolated by an isolation structure formed in a deep trench in a semiconductor substrate. Further, the electrical isolation between at least some pixel transistors in a pixel cell is achieved by multiplexing the isolation structure, thereby reducing the area of the photodiode region of the pixel cell occupied by the pixel transistors. Further, a second doped region is formed below the first trench to form a potential barrier region between the photodiode region and the semiconductor substrate. The second doped region is in contact with a first doped region formed on the sidewall of the first trench. The formation of the first doped region helps to pin defects formed by deep trench etching, thereby optimizing the performance of the pixel. The first doped region is in communication with a third doped region arranged outside the pixel array region. The third doped region is connected to the ground through a contact hole, thereby achieving a meshed ground of the potential barrier region around the photodiode region. In addition, the distance between the top surface of the doped dielectric layer forming the isolation structure in the deep trench and the surface of the semiconductor substrate is designed to improve the performance of the transistor in the pixel cell.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more particularly to a front-illuminated image sensor and its implementation method. Background Technology

[0002] Image sensors utilize the photoelectric conversion function of photoelectric devices in a pixel array to convert the light image on the photosensitive surface into an electrical signal proportional to the light image. This signal is then processed and stored by peripheral circuits to record image information.

[0003] Electrical isolation of image sensor pixels prevents crosstalk between electrical signals by building electrical barriers between pixels. Good electrical isolation effectively reduces noise, improves the signal-to-noise ratio of the image, and makes the image clearer and cleaner. For example, in high-resolution image sensors, electrical isolation ensures the independence of the electrical signal of each pixel, avoids interference between electrical signals of adjacent pixels, and improves image quality. However, to achieve a fine electrical isolation structure, inversion implantation is usually used to build electrical barriers between pixels. For deeper pixels (infrared applications), the depth of ion implantation may be insufficient, resulting in poor isolation. For shallower pixels, high-energy ion implantation at deeper depths can diffuse far after thermal processing, sacrificing the full-well capacity of the pixel and effectively increasing the pixel area. However, with the advancement of semiconductor technology, advanced isolation techniques (such as deep trench isolation) can minimize the impact on pixel area while ensuring electrical isolation, balancing the relationship between performance and area. Optical isolation of image sensor pixels prevents light crosstalk between pixels and is achieved through physical barriers (such as metal light-shielding layers or dielectric barriers). Effective optical isolation ensures that each pixel accurately receives its corresponding light, improving color reproduction and contrast, and enhancing image quality. Especially in high-contrast scenes, optical isolation prevents light from strong pixels from interfering with adjacent weak pixels, making details in dark areas clearer. Optical isolation structures occupy space, increasing pixel area. To avoid affecting pixel integration and sensor resolution, the optical isolation design needs to be optimized to minimize its impact on pixel area while maintaining effective isolation. This can be achieved by using thinner light-blocking materials and optimizing the shape and layout of the isolation walls.

[0004] Generally, larger pixel areas can accommodate more sophisticated electrical and optical isolation structures, and can receive more light, improving photosensitivity and dynamic range while reducing noise. Larger pixels perform better in low-light environments and can output high-quality images. Conversely, smaller pixel areas limit the implementation space for electrical and optical isolation structures, increase the risk of crosstalk, and reduce performance. However, smaller pixels can increase pixel integration and achieve higher resolution, making them suitable for scenarios requiring high image detail, but the performance degradation issue needs to be overcome through advanced technologies (such as new isolation materials and process optimization).

[0005] However, front-illuminated image sensors have more stringent requirements for electrical and optical isolation. Compared to back-illuminated image sensors, the incident light in a front-illuminated image sensor needs to pass through a rear metal layer to reach the photosensitive area. Therefore, ensuring the performance of the incident light reaching the photosensitive area has always been a challenge for front-illuminated image sensors. Currently, deep trench isolation structures in front-illuminated image sensors are typically only used for electrical isolation between pixel units, and the isolation between transistors within a pixel unit is achieved through additional shallow trench isolation structures. These features undoubtedly severely compress the photosensitive area of ​​the front-illuminated image sensor, making the designed front-illuminated image sensor less competitive. Therefore, designing isolation structures with better matching and lower costs, as well as corresponding manufacturing processes to improve the competitiveness of front-illuminated image sensors, has become an urgent research topic in the industry. Summary of the Invention

[0006] Based on the problems described above, this invention discloses a front-illuminated image sensor and its implementation method. Optical and electrical isolation of the front-illuminated image sensor is achieved through an isolation structure formed in a deep trench in a semiconductor substrate. Furthermore, electrical isolation between at least some pixel transistors within a pixel unit is achieved by reusing this isolation structure, thereby reducing the area of ​​the photodiode region occupied by the pixel transistors in the pixel unit. Further, a second doped region is formed below the first trench to form a barrier region between the photodiode region and the semiconductor substrate. The second doped region contacts a first doped region formed on the sidewall of the first trench. The formation of the first doped region helps to pin defects formed by deep trench etching, optimizing pixel performance. The first doped region communicates with a third doped region disposed outside the pixel array region. The third doped region is connected to ground through contact holes, thereby achieving a mesh grounding of the barrier region around the photodiode region. Additionally, the distance between the top surface of the doped dielectric layer forming the isolation structure within the deep trench and the surface of the semiconductor substrate is designed to improve the performance of the transistors within the pixel unit.

[0007] In a first aspect, a method for implementing a front-illuminated image sensor is provided, characterized by comprising: Etching a semiconductor substrate forms a first trench and pixel units spaced apart by the first trench; An isolation structure is formed in the first trench, the isolation structure being used for optical and electrical isolation between the pixel units; The first trench is a deep trench with a depth greater than 2 μm.

[0008] Preferably, the first trench has at least a first insulating medium layer formed on its sidewall surface, and the step of forming the insulating structure in the first trench includes: A first doped region is formed on the sidewall of the first trench, and a second doped region is formed below it; A doped polycrystalline silicon layer is filled in the first trench; The doped polycrystalline silicon layer is in contact with the second doped region, and the doping types of the first and second doped regions are opposite to the doping type of the photodiode region.

[0009] Preferably, the formation of the first doped region includes the following steps: The first isolation dielectric layer is formed, and the first isolation dielectric layer is a doped dielectric layer; The doped atoms in the doped dielectric layer diffuse from the first trench to the semiconductor substrate, wherein the doped atoms in the doped dielectric layer diffuse from the sidewall of the first trench to the semiconductor substrate to a first depth to form the first doped region.

[0010] Preferably, before filling the doped polysilicon layer, the dielectric layer at the bottom of the first trench is removed so that the filled doped polysilicon layer can contact the second doped region.

[0011] Preferably, the formation of the second doped region includes the following steps: Ion implantation is performed at the location below the first trench; The second doped region is formed by laterally diffusing the implanted ions to a second depth.

[0012] Preferably, the second doped region forms a barrier region between the photodiode region and the semiconductor substrate.

[0013] Preferably, the first doped region is in contact with the second doped region.

[0014] Preferably, the first doped region and the second doped region are formed simultaneously or at different times.

[0015] Preferably, the first doped region, the second doped region, and the doped polysilicon layer are grounded.

[0016] Preferably, a third doped region is provided outside the pixel array region and communicates with the first doped region. The third doped region is connected to ground through a contact hole, and the doping type of the third doped region is the same as that of the first doped region.

[0017] Preferably, in the pixel array region, in the first trench of the pixel transistor adjacent to the pixel unit, the top surface of the doped dielectric layer is disposed at a distance greater than 0.1 μm from the surface of the semiconductor substrate.

[0018] Preferably, in the pixel array region, in the first trench of the pixel transistor adjacent to the pixel unit, the top surface of the doped dielectric layer is positioned at a distance greater than 0.2 μm from the surface of the semiconductor substrate to improve the performance of the pixel transistor.

[0019] Preferably, the pixel unit includes a pixel transistor, wherein electrical isolation between at least some of the pixel transistors is achieved by reusing the isolation structure to reduce the photodiode area that the pixel transistor needs to occupy.

[0020] Preferably, the electrical isolation between the pixel transistor and the photodiode region is achieved through inversion doping, or through the isolation structure, or through floating polysilicon pixel isolation.

[0021] Preferably, the pixel transistor includes one or more of a source follower transistor, a transfer transistor, a reset transistor, a select transistor, and a gain control transistor.

[0022] Preferably, the source follower transistor within the pixel unit spans the isolation structure.

[0023] Preferably, the source follows the gate, source, and drain of the transistor across the isolation structure.

[0024] Preferably, the formation of the first trench and / or the removal of the doped dielectric layer at the bottom of the first trench share a hard mask with the fabrication of the shallow trench, and the formation of the shallow trench and the back etching of the doped polycrystalline layer in the first trench are carried out using the same process.

[0025] Preferably, the dielectric layer filling the shallow trench is manufactured using the same process as the second insulating dielectric layer filling the top of the first trench.

[0026] Preferably, the diffusion process of the first doped region and / or the second doped region is the same as the diffusion process after the shallow trench is formed.

[0027] Preferably, the top opening of the first groove converges relative to the portion below the top.

[0028] Secondly, a front-illuminated image sensor is provided, which is formed using the implementation method of the front-illuminated image sensor described in any of the foregoing embodiments.

[0029] Compared with existing technologies, the technical solution of this invention has the following beneficial effects: Optical and electrical isolation of the front-illuminated image sensor is achieved through an isolation structure formed in a deep trench in a semiconductor substrate. Furthermore, electrical isolation between at least some pixel transistors within a pixel unit is achieved by reusing this isolation structure, thereby reducing the area of ​​the photodiode region occupied by the pixel transistors in the pixel unit. Further, a second doped region is formed below the first trench to form a barrier region between the photodiode region and the semiconductor substrate; the second doped region contacts the first doped region formed on the sidewall of the first trench. The formation of the first doped region helps to pin defects formed by deep trench etching, optimizing pixel performance; the first doped region communicates with a third doped region disposed outside the pixel array region, and the third doped region is connected to ground through contact holes, thereby achieving a mesh grounding of the barrier region around the photodiode region. In addition, the distance between the top surface of the doped dielectric layer forming the isolation structure in the deep trench and the surface of the semiconductor substrate is designed to improve the performance of the transistors within the pixel unit. Attached Figure Description

[0030] The accompanying drawings, which form part of this specification, are used to further understand the invention. The drawings illustrate embodiments of the invention and, together with the specification, serve to explain the principles of the invention.

[0031] Figures 1-1 to 1-8 The following is the implementation process flow of the front-illuminated image sensor according to the first embodiment of the present invention.

[0032] Figures 2-1 to 2-9 The following is the implementation process flow of the front-illuminated image sensor according to the second embodiment of the present invention.

[0033] Figure 3 This is a partial example of a front-illuminated image sensor according to the third embodiment of the present invention.

[0034] Figures 4-1 to 4-6 This is a partial example of a front-illuminated image sensor according to the fourth embodiment of the present invention.

[0035] Figure 5 This is an example of a partition in the front-illuminated image sensor of the present invention. Detailed Implementation

[0036] The following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0037] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the present invention.

[0038] In a first aspect, embodiments of the present invention provide a method for implementing a front-illuminated image sensor as follows: First Embodiment

[0039] To address the aforementioned problems, the first embodiment of the present invention provides a method for implementing a front-illuminated image sensor, such as... Figures 1-1 to 1-8 The diagram shown is a schematic representation of the process flow of the first embodiment of the present invention.

[0040] like Figure 1-1 As shown, the semiconductor substrate 100 is etched to form a first trench DTI1 and pixel units (not shown) spaced apart by the first trench DTI1. The formation of the first trench DTI1 can be achieved, for example, by etching the semiconductor substrate 100 according to the pattern of a designed hard mask HM, such as... Figure 1-1 An example is shown where a patterned hard mask HM is formed on a semiconductor substrate 100. An isolation structure is formed in the first trench DTI1, which serves as optical and electrical isolation between pixel units. The first trench DTI1 refers to a deep trench with a depth greater than 2 μm, and further, the depth of the first trench DTI1 can be greater than 3 μm. The cross-sectional shape of the first trench DTI1 is... Figure 1-1 The example illustrates a regular shape; however, more preferably, the top opening of the first groove DTI1 is relatively converging towards the portion below the top, that is, the cross-section can form a bottleneck-like structure, which can provide more space for the arrangement of subsequent structures of the present invention and is more conducive to area utilization.

[0041] like Figure 1-2 As shown, a first insulating dielectric layer 101 is formed in the first trench DTI1, wherein the first insulating dielectric layer 101 is formed on at least the sidewall surface of the first trench DTI1, with... Figure 1-2 The diagram illustrates the formation of a first isolation dielectric layer 101 covering the surface of the first trench DTI1. The first isolation dielectric layer 101 may be a doped dielectric layer, such as a boron-doped oxide.

[0042] like Figure 1-3 As shown, ion implantation is performed below the first trench DTI1 to form an ion implantation region 102.

[0043] like Figure 1-4 As shown, the first isolation dielectric layer 101 and other dielectric layers at the bottom of the first trench DTI1 are removed. Optionally, the depth of the first trench DTI1 can be extended further after removing the first isolation dielectric layer 101 at the bottom of the first trench DTI1, or the depth of the first trench DTI1 can be left unextended.

[0044] like Figure 1-5 As shown, the first trench DTI1 is filled with a doped polysilicon layer 103, which may be, for example, B-doped polysilicon.

[0045] like Figure 1-6 As shown, a portion of the first isolation dielectric layer 101 on the sidewall of the first trench DTI1 is removed. Preferably, in the pixel array region, the distance d between the top surface of the doped dielectric layer 101 disposed in the first trench DTI1 of the pixel transistor adjacent to the pixel unit and the top surface of the semiconductor substrate 100 is greater than 0.1 μm, and more preferably d is greater than 0.2 μm, in order to improve the performance of the pixel transistor.

[0046] like Figure 1-7 As shown, doped atoms in the doped dielectric layer 101 diffuse from the first trench DTI1 to the semiconductor substrate 100. The doped atoms diffuse from the sidewall of the first trench DTI1 to the semiconductor substrate to a first depth to form the first doped region 1011. The formation of the first doped region helps to pin defects formed by deep trench etching and optimize pixel performance. Lateral diffusion to the ion implantation region 102 to a second depth forms the second doped region 1021. The second doped region 1021 forms a barrier region between the photodiode region and the semiconductor substrate 100. The second depth of the ion implantation regions 102 below adjacent first trenches DTI1 can be designed. Preferably, the second depth of the lateral diffusion is sufficient to allow adjacent second doped regions 1021 to contact each other, or they may not contact each other, or may not be in complete contact, so that a plurality of second doped regions 1021 can form a mesh-like structure throughout the pixel array region. The photodiode region PD is the region formed by doping a region in the pixel unit of the semiconductor substrate 100, such as... Figure 1-7 An exemplary illustration shows a photodiode region (PD). In this first embodiment, the diffusion processes for forming the first doped region 1011 and the second doped region 1021 can be synchronized, meaning the first doped region 1011 and the second doped region 1021 are formed simultaneously. The first doped region 1011 is also in contact with the second doped region 1021, so that the second doped region 1021 and the first doped region 1011 throughout the entire pixel array region can participate in encapsulating the photodiode region (PD) of each pixel unit.

[0047] like Figure 1-8 As shown, the first trench DTI1 is filled with the second isolation medium layer 104 to flatten the first trench DTI1.

[0048] Additionally, the first doped region 1011, the second doped region 1021, and the doped polysilicon layer 103 are grounded. For example, a third doped region (not shown) connected to the first doped region 1011 can be provided outside the pixel array region. The third doped region is connected to ground through a contact hole, and the doping type of the third doped region is the same as that of the first doped region. The ground contact hole can be provided, for example, in the boundary region between the surrounding circuit region and the pixel array region, and the ground contact hole can be formed on the surface of the semiconductor substrate as a third doped region. This third doped region can reuse the corresponding doped type region of a logic region or a pixel unit. The corresponding logic region can, for example, include wells, source implants, drain implants, etc., of the corresponding doped type that form its transistor; the corresponding pixel unit can, for example, be a well, surface pinning layer, etc., of the corresponding doped type that forms its pixel transistor.

[0049] It should be noted that the first embodiment provided is as follows: Figures 1-1 to 1-8 The implementation method of the front-illuminated image sensor is only an example of the key process flow. In specific embodiments, the specific process steps included should not be limited to these processes.

[0050] In one specific embodiment, the steps of "having a first isolation dielectric layer 101 formed on at least the sidewall surface of the first trench DTI1, and forming the isolation structure in the first trench DTI1" include: forming a first doped region 1011 on the sidewall of the first trench DTI1 and forming a second doped region 1021 below it; filling the first trench DTI1 with a doped polysilicon layer 103; wherein the doped polysilicon layer 103 is in contact with the second doped region 1021, and the doping types of the first doped region 1011 and the second doped region 1021 are opposite to the doping type of the photodiode region" are all within the scope of this invention.

[0051] In one specific embodiment, any step that satisfies the following is within the scope of the present invention: forming a first isolation dielectric layer 101, wherein the first isolation dielectric layer 101 is a doped dielectric layer; causing doped atoms in the doped dielectric layer 101 to diffuse from the first trench DTI1 to the semiconductor substrate 100, wherein the doped atoms in the doped dielectric layer 101 diffuse from the sidewall of the first trench DTI1 to the semiconductor substrate to a first depth to form the first doped region 1011.

[0052] In one specific embodiment, any condition that satisfies the requirement of "removing the dielectric layer such as the doped dielectric layer 101 at the bottom of the first trench DTI1 before filling the doped polysilicon layer 103 so that the filled doped polysilicon layer 103 can contact the second doped region 1021" is within the scope of this invention.

[0053] In one specific embodiment, any step that satisfies the following steps is within the scope of the present invention: “the formation of the second doped region 1021 includes the following steps: ion implantation is performed on the position below the first trench DTI1 to form an ion implantation region 102; the ion implantation is laterally diffused to a second depth to form the second doped region 1021”. Second Embodiment

[0054] In the first embodiment, an example was described in which the first doped region 1011 and the second doped region 1021 could be formed simultaneously. In this second embodiment, an example will be described in which the first doped region 1011 and the second doped region 1021 are not formed simultaneously. Otherwise, the actual structure or process of this second embodiment can be referred to the first embodiment, and details will not be repeated here. Figures 2-1 to 2-9 This is a schematic diagram of the process flow of the second embodiment of the present invention.

[0055] like Figure 2-1 As shown, the semiconductor substrate 100 is etched to form a first trench DTI1 and pixel units (not shown) spaced apart by the first trench DTI1. The formation of the first trench DTI1 can be achieved, for example, by etching the semiconductor substrate 100 according to the pattern of a designed hard mask HM, such as... Figure 1-1 An example is shown where a patterned hard mask HM is formed on a semiconductor substrate 100. An isolation structure is formed in the first trench DTI1, which serves as optical and electrical isolation between pixel units. The first trench DTI1 refers to a deep trench with a depth greater than 2 μm, and further, the depth of the first trench DTI1 can be greater than 3 μm.

[0056] like Figure 2-2 As shown, a first insulating dielectric layer 101 is formed in the first trench DTI1, wherein the first insulating dielectric layer 101 is formed on at least the sidewall surface of the first trench DTI1, with... Figure 2-2 The diagram illustrates the formation of a first isolation dielectric layer 101 covering the surface of the first trench DTI1. The first isolation dielectric layer 101 is an undoped dielectric layer. Furthermore, an ion implantation region 102 is formed by ion implantation at a location below the first trench DTI1.

[0057] like Figure 2-3As shown, a second doped region 1021 is formed by lateral diffusion to a second depth in the ion implantation region 102. The second doped region 1021 forms a barrier region between the photodiode region and the semiconductor substrate 100. The second depth of the ion implantation regions 102 below adjacent first trenches DTI1 can be designed to allow the adjacent second doped regions 1021 to contact each other, or they may not contact each other, or they may not contact each other completely, so that a number of second doped regions 1021 can form a mesh-like structure in the entire pixel array region. The photodiode region PD is the region formed by doping a region in the pixel unit of the semiconductor substrate 100, such as... Figure 2-3 An example is shown of a photodiode region PD.

[0058] like Figure 2-4 The first isolation dielectric layer 101 is formed as a doped dielectric layer 101.

[0059] like Figure 2-5 The first isolation dielectric layer 101 and other dielectric layers at the bottom of the first trench DTI1 are removed. Optionally, the depth of the first trench DTI1 can be extended further after removing the first isolation dielectric layer 101 at the bottom of the first trench DTI1, or the depth of the first trench DTI1 can be left unextended.

[0060] like Figure 2-6 As shown, a doped polysilicon layer 103 is filled in the first trench DTI1.

[0061] like Figure 2-7 As shown, a portion of the first isolation dielectric layer 101 on the sidewall of the first trench DTI1 is removed. Preferably, in the pixel array region, the distance d between the top surface of the doped dielectric layer 101 disposed in the first trench DTI1 of the pixel transistor adjacent to the pixel unit and the top surface of the semiconductor substrate 100 is greater than 0.1 μm, and more preferably d is greater than 0.2 μm, in order to improve the performance of the pixel transistor.

[0062] like Figure 2-8As shown, doped atoms in the doped dielectric layer 101 diffuse from the first trench DTI1 to the semiconductor substrate 100. The doped atoms diffuse from the sidewall of the first trench DTI1 to the semiconductor substrate to a first depth to form the first doped region 1011. The formation of the first doped region 1011 helps to pin defects formed by deep trench etching and optimize pixel performance. In this second embodiment, the diffusion processes for forming the first doped region 1011 and the second doped region 1021 are asynchronous. The first doped region 1011 must still be in contact with the second doped region 1021, so that the second doped region 1021 and the first doped region 1011 in the entire pixel array area can participate in wrapping the photodiode region PD of each pixel unit.

[0063] like Figure 2-9 As shown, the first trench DTI1 is filled with the second isolation medium layer 104 to flatten the first trench DTI1.

[0064] Similar to the first embodiment, this embodiment also grounds the first doped region 1011, the second doped region 1021, and the doped polysilicon layer 103. For example, a third doped region (not shown) connected to the first doped region 1011 can be provided outside the pixel array region. The third doped region is connected to ground through a contact hole, and the doping type of the third doped region is the same as that of the first doped region. The ground contact hole can be provided, for example, in the boundary region between the surrounding circuit region and the pixel array region, and the ground contact hole can be formed on the surface of the semiconductor substrate in the third doped region. This third doped region can reuse the corresponding doped type region of the logic region or the pixel unit. The corresponding logic region can, for example, include the corresponding doped type well, source implant, drain implant, etc., which form the transistor; the corresponding pixel unit can, for example, be the corresponding doped type well, surface pinning layer, etc., which form the pixel transistor.

[0065] It should be noted that the second embodiment provided herein is as follows: Figures 2-1 to 2-9 The implementation method of the front-illuminated image sensor is only an example of the key process flow. In specific embodiments, the specific process steps included should not be limited to these processes. Third Embodiment

[0066] Based on the first and second embodiments and any optional embodiments therein, this embodiment further optimizes the isolation design of the pixel transistors within the pixel unit to further optimize the area limitation of the front-illuminated image sensor. The smaller area limitation can reduce the area occupied by the pixel transistors in the photodiode region (PD).

[0067] In the third embodiment of the present invention, the implementation method of a front-illuminated image sensor includes a pixel unit comprising a pixel transistor. Electrical isolation between at least some of the pixel transistors is achieved by multiplexing the isolation structure, thereby reducing the photodiode area occupied by the pixel transistor. For example... Figure 3 As shown, only four pixel units P (the specific number of pixel units P should not be limited to this) are illustrated by the isolation structure S. Each pixel unit P contains a photodiode region PD. Figure 3 The diagram also illustrates several pixel transistors of pixel unit P, which may include one or more of the following: source follower transistor, transfer transistor, reset transistor, selection transistor, and gain control transistor. (Appendix) Figure 3 The diagram illustrates the arrangement of elements such as the source follower transistor SF, transfer transistor Tx, and reset transistor RST at the edge of the pixel unit P and the isolation structure S, i.e., the actual pixel unit P'. As can be seen in the diagram, the arrangement of these pixel transistors compresses the area of ​​the photodiode region PD. Therefore, in this embodiment, electrical isolation between at least some of the pixel transistors is achieved by reusing the isolation structures mentioned in previous embodiments. For example, electrical isolation between the source follower transistor SF, transfer transistor Tx, and reset transistor RST is achieved through the isolation structure S. Electrical isolation between the pixel transistors and the photodiode region PD is achieved through inversion doping, reusing the isolation structure, or floating polysilicon pixel isolation. For example, electrical isolation between the source follower transistor SF, transfer transistor Tx, and reset transistor RST and their adjacent photodiode region PD can be achieved through inversion doping, reusing the isolation structure, or floating polysilicon pixel isolation. This isolation design avoids the need for additional shallow trench STI isolation to achieve electrical isolation, saving the area occupied by shallow trench STI isolation and avoiding the expensive manufacturing costs associated with fabricating shallow trench STI isolation in the pixel array area.

[0068] In particular, this embodiment also designs a source follower transistor SF within the pixel unit that spans the isolation structure S. Specifically, the gate, source, and drain of the source follower transistor SF can span the isolation structure S. Since the source follower transistor SF occupies a relatively large area of ​​the pixel transistor, the design of spanning the isolation structure S in this embodiment can further reduce the squeezing of the photodiode region PD by the pixel transistor, thereby increasing area utilization. Fourth embodiment

[0069] Embodiments of the present invention also integrate some processes in the manufacturing process to reduce manufacturing costs. This third embodiment is an implementation method of a front-illuminated image sensor based on the first, second, and third embodiments or any optional embodiments included therein. See the appendix below. Figures 4-1 to 4-6 and attached Figure 5 Please provide an explanation.

[0070] The inventors discovered that the manufacturing cost of this front-illuminated image sensor is significantly higher due to the processes and the use of hard masks. Therefore, in designing the front-illuminated image sensor of this invention, some process steps were integrated and some materials were cleverly reused. Specifically, the first trench DTI1 and / or the removal of, for example, the doped dielectric layer 101 at the bottom of the first trench DTI1 share a hard mask HM, and the fabrication of the shallow trench STI outside the pixel array region also shares this hard mask HM. Furthermore, the formation of the shallow trench STI is performed using the same process as the back etching of the doped polycrystalline layer 103 within the first trench DTI1. Further, the dielectric layer filling the shallow trench STI is processed using the same process as the second isolation dielectric layer 104 filling the top of the first trench DTI1. Even further, the diffusion process of the first doped region and / or the second doped region is the same process as the diffusion process after the formation of the shallow trench STI.

[0071] like Figure 5 As shown, this front-illuminated image sensor has a pixel array area and areas such as the boundary area and peripheral circuit area outside the pixel array area. In the previous embodiment, it was introduced that the electrical isolation of the pixel transistors of the pixel units in the pixel array area of ​​the present invention needs to avoid the use of shallow trench isolation. However, outside the pixel array area, this embodiment is designed so that the isolation material formed in the shallow trench STI can be used to isolate transistor devices outside the pixel array area without avoiding the use of shallow trench STI. That is, shallow trench isolation can be applied outside the pixel array area to achieve electrical isolation of transistor devices.

[0072] For example, such as Figure 4-1 , 4-2 As shown, the hard mask HM used to form the first trench DTI1 is retained. To form a shallow trench STI outside the pixel array area, as... Figure 4-3 As shown, a patterned photoresist AAPH is used to pattern the hard mask HM. Then, a shallow trench STI is formed outside the pixel array region using the patterned hard mask HM. Furthermore, the formation of the shallow trench STI is performed using the same process as the back etching of the doped polycrystalline layer 103 and / or the first isolation dielectric layer 101 within the first trench DTI1. Figure 4-5 As shown. The dielectric layer filling the shallow trench STI is fabricated using the same process as the second isolation dielectric layer 104 filling the top of the first trench DTI1, as shown. Figure 4-6 As shown.

[0073] Secondly, the present invention also provides a front-illuminated image sensor, which is formed by the implementation method of the front-illuminated image sensor described in any of the foregoing embodiments, and the specific details will not be repeated here.

[0074] The basic concepts have been described above. It is clear that the detailed disclosure above is merely illustrative and does not constitute a limitation of the present invention. Although not explicitly stated herein, various modifications, improvements, and corrections may be made to the present invention by those skilled in the art. Such modifications, improvements, and corrections are suggested in this invention and therefore remain within the spirit and scope of the exemplary embodiments of the present invention.

[0075] It should be understood that the embodiments described in this invention are merely illustrative of the principles of the invention. Other modifications may also fall within the scope of this invention. Therefore, alternative configurations of the embodiments of this invention are considered as examples and not limitations, and are regarded as consistent with the teachings of this invention. Accordingly, the embodiments of this invention are not limited to those explicitly described and illustrated herein.

Claims

1. A method for implementing a front-illuminated image sensor, characterized in that, include: Etching a semiconductor substrate forms a first trench and pixel units spaced apart by the first trench; An isolation structure is formed in the first trench, the isolation structure being used for optical and electrical isolation between the pixel units; The first trench is a deep trench with a depth greater than 2 μm.

2. The method for implementing the front-illuminated image sensor as described in claim 1, characterized in that, The step of forming the isolation structure in the first trench includes: (1) A first insulating medium layer is formed on at least the sidewall surface of the first trench. A first doped region is formed on the sidewall of the first trench, and a second doped region is formed below it; A doped polycrystalline silicon layer is filled in the first trench; The doped polycrystalline silicon layer is in contact with the second doped region, and the doping types of the first and second doped regions are opposite to the doping type of the photodiode region.

3. The method for implementing a front-illuminated image sensor as described in claim 2, characterized in that, The formation of the first doped region includes the following steps: The first isolation dielectric layer is formed, and the first isolation dielectric layer is a doped dielectric layer; The doped atoms in the doped dielectric layer diffuse from the first trench to the semiconductor substrate, wherein the doped atoms in the doped dielectric layer diffuse from the sidewall of the first trench to the semiconductor substrate to a first depth to form the first doped region.

4. The method for implementing a front-illuminated image sensor as described in claim 2 or 3, characterized in that, Before filling the doped polysilicon layer, the dielectric layer at the bottom of the first trench is removed so that the filled doped polysilicon layer can contact the second doped region.

5. The method for implementing a front-illuminated image sensor as described in claim 2, characterized in that, The formation of the second doped region includes the following steps: Ion implantation is performed at the location below the first trench; The second doped region is formed by laterally diffusing the implanted ions to a second depth.

6. The method for implementing the front-illuminated image sensor as described in claim 2, characterized in that, The second doped region forms a barrier region between the photodiode region and the semiconductor substrate.

7. The method for implementing a front-illuminated image sensor as described in claim 2, characterized in that, The first doped region is in contact with the second doped region.

8. The method for implementing the front-illuminated image sensor as described in claim 2, characterized in that, The first doped region and the second doped region may be formed simultaneously or at different times.

9. The method for implementing the front-illuminated image sensor as described in claim 2, characterized in that, The first doped region, the second doped region, and the doped polysilicon layer are grounded.

10. The method for implementing a front-illuminated image sensor as described in claim 9, characterized in that, A third doped region is provided outside the pixel array region and is connected to the first doped region. The third doped region is connected to ground through a contact hole, and the doping type of the third doped region is the same as that of the first doped region.

11. The method for implementing the front-illuminated image sensor as described in claim 3, characterized in that, In the pixel array region, in the first trench of the pixel transistor adjacent to the pixel unit, the top surface of the doped dielectric layer is positioned at a distance greater than 0.1 μm from the surface of the semiconductor substrate.

12. The method for implementing a front-illuminated image sensor as described in claim 11, characterized in that, In the pixel array region, in the first trench of the pixel transistor adjacent to the pixel unit, the top surface of the doped dielectric layer is positioned at a distance greater than 0.2 μm from the surface of the semiconductor substrate to improve the performance of the pixel transistor.

13. The method for implementing a front-illuminated image sensor as described in claim 1, characterized in that, The pixel unit includes a pixel transistor, wherein electrical isolation between at least some of the pixel transistors is achieved by reusing the isolation structure to reduce the photodiode area that the pixel transistor needs to occupy.

14. The method for implementing a front-illuminated image sensor as described in claim 13, characterized in that, The electrical isolation between the pixel transistor and the photodiode region is achieved through inversion doping, or through the isolation structure, or through floating polysilicon pixel isolation.

15. The method for implementing a front-illuminated image sensor as described in claim 14, characterized in that, The pixel transistor includes one or more of the following: source follower transistor, transfer transistor, reset transistor, selection transistor, and gain control transistor.

16. The method for implementing a front-illuminated image sensor as described in claim 15, characterized in that, The source follower transistor within the pixel unit spans the isolation structure.

17. The method for implementing a front-illuminated image sensor as described in claim 16, characterized in that, The source follows the gate, source, and drain of the transistor across the isolation structure.

18. The method for implementing a front-illuminated image sensor as described in claim 3, characterized in that, The formation of the first trench and / or the removal of the doped dielectric layer at the bottom of the first trench share a hard mask with the fabrication of the shallow trench, and the formation of the shallow trench and the back etching of the doped polycrystalline layer in the first trench are carried out using the same process.

19. The method for implementing a front-illuminated image sensor as described in claim 18, characterized in that, The dielectric layer filling the shallow trench is manufactured using the same process as the second insulating dielectric layer filling the top of the first trench.

20. The method for implementing a front-illuminated image sensor as described in claim 19, characterized in that, The diffusion process for the first doped region and / or the second doped region is the same as the diffusion process after the shallow trench is formed.

21. The method for implementing a front-illuminated image sensor as described in claim 1, characterized in that, The top opening of the first groove tapers towards the portion below the top.

22. A front-illuminated image sensor, characterized in that, It is formed using the implementation method of the front-illuminated image sensor as described in any one of claims 1 to 21.

Images