Solid-state imaging device

Abstract

The present application provides a kind of solid-state camera device, can inhibit the generation of noise.This embodiment of the present application has semiconductor chip, which includes semiconductor layer with first surface and second surface opposite to the first surface, the semiconductor layer includes: a plurality of photodiodes, disposed on the first surface of the semiconductor layer, along the first direction configuration;First trench column, disposed on the first surface of the semiconductor layer, and is arranged between the photodiode and the end of the semiconductor chip, includes at least one first trench, extends along the first direction;And second trench column, arranged between the first trench column and the end, includes at least one second trench, extends along the first direction.

Description

[0001] This application enjoys priority based on Japanese Patent Application No. 2025-048746 (filed on March 24, 2025). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] Embodiments of the present invention relate to solid-state imaging devices. Background Technology

[0003] In solid-state imaging devices, multiple photodiodes are arranged in one-dimensional or two-dimensional arrays. Each photodiode comprises a pn-junction diode formed within a semiconductor chip. The photodiode uses the photoelectric effect of the pn-junction diode to convert incident light into electric current.

[0004] When light enters a photodiode from outside the semiconductor chip or from an adjacent photodiode, noise is generated, degrading the initial characteristics or reliability of the solid-state camera. Summary of the Invention

[0005] Embodiments of the present invention provide a solid-state imaging device capable of suppressing noise generation.

[0006] The solid-state imaging device of this embodiment includes a semiconductor chip. The semiconductor chip includes a semiconductor layer having a first surface and a second surface facing the first surface. The semiconductor layer includes: a plurality of photodiodes disposed on the first surface of the semiconductor layer and arranged along a first direction; a first trench row disposed on the first surface of the semiconductor layer and disposed between the photodiodes and the end of the semiconductor chip, including at least one first trench and extending along the first direction; and a second trench row disposed between the first trench row and the end, including at least one second trench and extending along the first direction. Attached Figure Description

[0007] Figure 1 This is a schematic top view of the solid-state imaging device according to the first embodiment.

[0008] Figure 2 This is an enlarged schematic top view of the solid-state imaging device according to the first embodiment.

[0009] Figure 3 This is an enlarged schematic cross-sectional view of the solid-state imaging device according to the first embodiment.

[0010] Figure 4 This is a schematic top view of a comparative example solid-state imaging device.

[0011] Figure 5 This is an enlarged schematic top view of a comparative example solid-state imaging device.

[0012] Figure 6 This is an enlarged schematic cross-sectional view of a comparative example solid-state imaging device.

[0013] Figure 7 This is an explanatory diagram of a comparative example solid-state imaging device.

[0014] Figure 8 This is an explanatory diagram illustrating the function and effect of the solid-state imaging device according to the first embodiment.

[0015] Figure 9 This is an enlarged schematic top view of a first modified example of a solid-state imaging device according to the first embodiment.

[0016] Figure 10 This is an enlarged schematic top view of a solid-state imaging device of a second variation of the first embodiment.

[0017] Figure 11 This is an enlarged schematic cross-sectional view of a solid-state imaging device of the third variation of the first embodiment.

[0018] Figure 12 This is an enlarged schematic top view of the solid-state imaging device of the fourth variation of the first embodiment.

[0019] Figure 13 This is an enlarged schematic cross-sectional view of the solid-state imaging device of the fourth variation of the first embodiment.

[0020] Figure 14 This is a schematic top view of the solid-state camera device according to the second embodiment.

[0021] Figure 15 This is an enlarged schematic top view of the solid-state camera device according to the second embodiment.

[0022] Figure 16 This is an enlarged schematic cross-sectional view of the solid-state imaging device according to the second embodiment.

[0023] Figure 17 This is an enlarged schematic top view of a comparative example solid-state imaging device.

[0024] Figure 18 This is an enlarged schematic cross-sectional view of a comparative example solid-state imaging device.

[0025] Figure 19 This is an explanatory diagram of a comparative example solid-state imaging device.

[0026] Figure 20 This is an explanatory diagram illustrating the function and effect of the solid-state imaging device according to the second embodiment.

[0027] Explanation of reference numerals in the attached figures

[0028] 10 semiconductor layers

[0029] 10a p-type high-concentration region (third semiconductor region)

[0030] 10b p-type low-concentration region (first semiconductor region)

[0031] 10c n-type region (second semiconductor region)

[0032] 18 dielectric

[0033] 19 Holes

[0034] 20-element separation trench

[0035] 21 First trench

[0036] 22 Second trench

[0037] 23 Third trench

[0038] 24 Fourth trench

[0039] 25 Fifth Groove

[0040] 26 Sixth Trench

[0041] 100 Linear Image Sensor (Solid-State Imaging Device)

[0042] 101 Semiconductor Chip

[0043] 200 linear image sensor (solid-state imaging device)

[0044] 201 Semiconductor Chips

[0045] E1 First End (End)

[0046] F1 First Side

[0047] F2 Second Side

[0048] PD photodiode

[0049] TC1 First Trench Column

[0050] TC2 Second Trench Column

[0051] TC3 third trench column

[0052] TC4 Fourth Trench

[0053] TC5 fifth trench column

[0054] TC6 sixth trench train Detailed Implementation

[0055] In this specification, the same or similar parts are sometimes labeled with the same reference numerals, and repeated descriptions are omitted.

[0056] In this specification, to indicate the positional relationship of components, the upper direction of the attached drawings is sometimes described as "upper" and the lower direction as "lower". In this specification, the concepts of "upper" and "lower" do not necessarily refer to their relationship with the direction of gravity.

[0057] In this specification, when there is n + Type, n-type, n - In the case of the type expression, it means that the impurity concentration of type n is according to n + Type, n-type, n - The order of the type decreases. Furthermore, in the presence of p... + Type, p type, p - In the case of p-type description, it means that the concentration of p-type impurities is determined according to p... + Type, p type, p - The order of the types decreases.

[0058] In this specification, the distribution and absolute values ​​of impurity concentrations in the semiconductor regions can be determined, for example, using secondary ion mass spectrometry (SIMS). Furthermore, the relative magnitudes of impurity concentrations in two semiconductor regions can be determined, for example, using scanning capacitance microscopy (SCM).

[0059] Qualitative and quantitative analyses of the chemical composition of the components constituting the solid-state imaging device described in this specification can be performed, for example, by SIMS or energy dispersive X-ray spectroscopy (EDX). Furthermore, measurements of the thickness of the components constituting the solid-state imaging device, the distance between components, etc., can be performed, for example, by transmission electron microscopy (TEM). Additionally, the identification of the substances constituting the components of the solid-state imaging device can be performed, for example, by X-ray diffraction (XRD), electron beam diffraction (EBD), or X-ray photoelectron spectroscopy (XPS).

[0060] (First Implementation)

[0061] The solid-state imaging device of the first embodiment includes a semiconductor chip, which comprises a semiconductor layer having a first surface and a second surface opposite to the first surface. The semiconductor layer includes: a plurality of photodiodes disposed on the first surface of the semiconductor layer and arranged along a first direction; a first trench row disposed on the first surface of the semiconductor layer and disposed between the photodiodes and an end of the semiconductor chip, including at least one first trench and extending along the first direction; and a second trench row disposed between the first trench row and the end, including at least one second trench and extending along the first direction.

[0062] The following explanation will be based on the case where the first conductivity type is p-type and the second conductivity type is n-type.

[0063] Figure 1 This is a schematic top view of the solid-state imaging device according to the first embodiment. The solid-state imaging device of the first embodiment is a linear image sensor 100.

[0064] like Figure 1 As shown, the linear image sensor 100 includes a semiconductor chip 101. The semiconductor chip 101 includes a photodiode region 101a, a control circuit region 101b, and a photonic crystal region 101c.

[0065] The semiconductor chip 101 extends along a first direction. The direction perpendicular to the first direction is the second direction.

[0066] The semiconductor chip 101 has a first end E1, a second end E2, a third end E3, and a fourth end E4. The second end E2 is the end opposite to the first end E1, separated from the semiconductor chip 101. The fourth end E4 is the end opposite to the third end E3, separated from the semiconductor chip 101.

[0067] In photodiode region 101a, a plurality of photodiodes PD are arranged along a first direction. Furthermore, in photodiode region 101a, a plurality of photodiodes PD are arranged along a second direction.

[0068] The number of photodiodes (PDs) arranged along the first direction is, for example, more than 10 times and less than 1000 times the number of photodiodes (PDs) arranged along the second direction. Figure 1 The example shown illustrates a case where three photodiodes (PDs) are arranged along the second direction. The number of photodiodes (PDs) arranged along the first direction is, for example, between 30 and 3000.

[0069] A control circuit region 101b is disposed between the photodiode region 101a and the second end E2. In the photodiode region 101a, for example, an electronic circuit for controlling the operation of the linear image sensor 100 is formed. The electronic circuit includes, for example, transistors, capacitors, or resistors.

[0070] A photonic crystal region 101c is disposed between the photodiode region 101a and the first end E1. The photonic crystal region 101c is continuously disposed between the two ends of the photodiode region 101a in the first direction, along the photodiode region 101a extending in the first direction.

[0071] A photonic crystal is formed in photonic crystal region 101c. The photonic crystal is formed by a periodic structure of trenches disposed on the semiconductor chip. The photonic crystal region 101c has the function of suppressing light incident from the end of the semiconductor chip 101 from entering the photodiode region 101a.

[0072] In the second direction, the distance between the photodiode PD closest to the first end E1 and the first end E1 ( Figure 1 In the second direction, d1 is, for example, greater than 30 μm and less than 500 μm. The distance between the photodiode PD closest to the second end E2 and the second end E2 (…). Figure 1 d2 in the example is 1mm or more and 20mm or less.

[0073] Figure 2 This is an enlarged schematic top view of the solid-state imaging device according to the first embodiment. Figure 2 yes Figure 1 A top view of the region R1 enclosed by quadrilaterals. Figure 2 It is a diagram showing the layout pattern of the surface of the semiconductor layer 10 included in the semiconductor chip 101.

[0074] Figure 3 This is an enlarged schematic cross-sectional view of the solid-state imaging device according to the first embodiment. Figure 3 This is a cross-sectional view of semiconductor chip 101. Figure 3 yes Figure 2 AA' section.

[0075] Semiconductor chip 101 includes a semiconductor layer 10, an interlayer insulating layer 12, a metal layer 14, a component separation insulating layer 16, and a dielectric 18. Semiconductor layer 10 includes a p-type high-concentration region 10a (third semiconductor region), a p-type low-concentration region 10b (first semiconductor region), an n-type region 10c (second semiconductor region), a component separation trench 20, a first trench 21, a second trench 22, and a third trench 23, a first trench column TC1, a second trench column TC2, and a third trench column TC3.

[0076] The semiconductor layer 10 includes a first surface F1 and a second surface F2. Hereinafter, the first surface F1 will sometimes be referred to as the surface and the second surface F2 as the back surface.

[0077] Semiconductor layer 10 is, for example, silicon. Semiconductor layer 10 is, for example, a single-crystal silicon layer.

[0078] The p-type high-concentration region 10a is a silicon region containing p-type impurities.

[0079] The p-type low-concentration region 10b is disposed between the p-type high-concentration region 10a and the first surface F1. The p-type low-concentration region 10b is a silicon region containing p-type impurities. The p-type low-concentration region 10b is, for example, an epitaxial growth layer formed on the p-type high-concentration region 10a. The p-type impurity concentration in the p-type low-concentration region 10b is lower than the p-type impurity concentration in the p-type high-concentration region 10a.

[0080] The depth of the p-type low-concentration region 10b is, for example, greater than 5 μm and less than 20 μm.

[0081] Additionally, in this specification, "depth" refers to the distance from the first surface F1 toward the second surface F2, with the first surface F1 as the reference.

[0082] The n-type region 10c is disposed between the p-type low-concentration region 10b and the first surface F1. The n-type region 10c is in contact with the first surface F1. The n-type region 10c is a silicon region containing n-type impurities.

[0083] A photodiode (PD) consists of an n-type region 10c and a p-type low-concentration region 10b. The photodiode (PD) contains a pn junction formed by the n-type region 10c and the p-type low-concentration region 10b.

[0084] Component separation trench 20 is disposed on the first surface F1 of semiconductor layer 10. Component separation trench 20 is a trench disposed on semiconductor layer 10. Component separation trench 20 is a part of semiconductor layer 10.

[0085] Component separation trench 20 is disposed between two adjacent photodiodes PD. Component separation trench 20 is disposed between two adjacent n-type regions 10c.

[0086] The component separation trench 20 has the function of electrically separating two adjacent photodiodes PD.

[0087] The depth of the component separation trench 20 is shallower than the depth of the first trench 21, the second trench 22, and the third trench 23.

[0088] The depth of the component separation trench 20 is, for example, shallower than the depth of the n-type region 10c.

[0089] The interior of the component separation trench 20 is, for example, filled with a component separation insulating layer 16. The component separation insulating layer 16 is an insulator. The component separation insulating layer 16 is, for example, silicon oxide.

[0090] The first trench 21 is disposed on the first surface F1 of the semiconductor layer 10. The first trench 21 is a trench disposed on the semiconductor layer 10. The first trench 21 is a part of the semiconductor layer 10.

[0091] The depth of the first trench 21 is greater than the depth of the n-type region 10c. The depth of the first trench 21 is greater than the depth of the component separation trench 20.

[0092] The depth of the first trench 21 is, for example, deeper than the depth of the p-type low-concentration region 10b. The first trench 21 is, for example, connected to the p-type high-concentration region 10a.

[0093] The second trench 22 is disposed on the first surface F1 of the semiconductor layer 10. The second trench 22 is a trench disposed on the semiconductor layer 10. The second trench 22 is a part of the semiconductor layer 10.

[0094] The depth of the second trench 22 is greater than the depth of the n-type region 10c. The depth of the second trench 22 is greater than the depth of the component separation trench 20.

[0095] The depth of the second trench 22 is, for example, deeper than the depth of the p-type low-concentration region 10b. The second trench 22 is, for example, connected to the p-type high-concentration region 10a.

[0096] The third trench 23 is disposed on the first surface F1 of the semiconductor layer 10. The third trench 23 is a trench disposed on the semiconductor layer 10. The third trench 23 is a part of the semiconductor layer 10.

[0097] The depth of the third trench 23 is greater than the depth of the n-type region 10c. The depth of the third trench 23 is greater than the depth of the component separation trench 20.

[0098] The depth of the third trench 23 is, for example, deeper than the depth of the p-type low-concentration region 10b. The third trench 23 is, for example, connected to the p-type high-concentration region 10a.

[0099] The depth of the first trench 21, the depth of the second trench 22, and the depth of the third trench 23 are, for example, more than 3 μm and less than 10 μm.

[0100] The interiors of the first trench 21, the second trench 22, and the third trench 23 are, for example, embedded with a dielectric 18. The dielectric 18 is, for example, an oxide, a nitride, or an oxynitride. The dielectric 18 is, for example, silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

[0101] The first trench column TC1, the second trench column TC2, and the third trench column TC3 are disposed in the photonic crystal region 101c.

[0102] The first trench column TC1 is disposed between the photodiode PD and the first end E1. The first trench column TC1 extends along a first direction.

[0103] A plurality of first grooves 21 constitute a first groove row TC1. In the first groove row TC1, the plurality of first grooves 21 are repeatedly arranged in a first direction in a predetermined first pattern.

[0104] The second groove column TC2 is disposed between the first groove column TC1 and the first end E1. The second groove column TC2 extends along the first direction.

[0105] A plurality of second grooves 22 constitute a second groove column TC2. In the second groove column TC2, the plurality of second grooves 22 are repeatedly arranged in a first direction in a predetermined second pattern.

[0106] The third groove column TC3 is disposed between the second groove column TC2 and the first end E1. The third groove column TC3 extends along a first direction. The second groove column TC2 is disposed between the first groove column TC1 and the third groove column TC3.

[0107] Multiple third grooves 23 constitute a third groove row TC3. In the third groove row TC3, multiple third grooves 23 are repeatedly arranged in a predetermined third pattern in a first direction.

[0108] An interlayer insulating layer 12 is disposed on the semiconductor layer 10. The interlayer insulating layer 12 is an insulator. For example, the interlayer insulating layer 12 is silicon oxide.

[0109] A metal layer 14 is disposed within the interlayer insulating layer 12. The metal layer 14 is metal. The metal layer 14 may be, for example, an electrode or wiring used to transmit electrical signals obtained from a photodiode PD.

[0110] Alternatively, the semiconductor chip 101 may include a color filter or microlens (not shown) on top of the photodiode PD.

[0111] A photonic crystal is formed in region 101c. A photonic crystal is a structure in which two materials with different refractive indices are regularly arranged. A photonic crystal has the property of reflecting light within a specified wavelength range.

[0112] For example, suppose the peak wavelength of the reflected light is λ, the refractive index of material A is na, and the refractive index of material B is nb. When the dimensions of material A are da and the dimensions of material B are db, they exhibit properties as photonic crystals if the following equations are satisfied respectively. Furthermore, ma and mb in the equations are arbitrary natural numbers including 0.

[0113] da=maλ / 2na+λ / 4na

[0114] db=mbλ / 2nb+λ / 4nb

[0115] In the photonic crystal region 101c, semiconductor layers 10 with different refractive indices and dielectrics 18 embedded in the first trench 21, the second trench 22 and the third trench 23 are regularly arranged to form a photonic crystal.

[0116] like Figure 2 As shown, in the semiconductor chip 101 of the first embodiment, the first trench 21, the second trench 22, and the third trench 23 are regularly arranged in a pattern of equilateral triangles to form a photonic crystal. The photonic crystal of the semiconductor chip 101 of the first embodiment is a so-called two-dimensional photonic crystal in which two substances are regularly arranged in a two-dimensional manner.

[0117] The reflectivity of light with a wavelength of 1000 nm formed in the photonic crystal region 101c is, for example, above 80%.

[0118] The width of the first trench column TC1, the second trench column TC2, and the third trench column TC3 in the second direction perpendicular to the first direction ( Figure 2 The wx in the text is, for example, above 170nm and below 1000nm. Furthermore, the distances between the first trench column TC1 and the second trench column TC2, and between the second trench column TC2 and the third trench column TC3 (…). Figure 2 The dx in the image is, for example, above 60nm and below 1000nm.

[0119] Next, the function and effects of the linear image sensor 100 of the first embodiment will be explained.

[0120] Figure 4 This is a schematic top view of a comparative example solid-state imaging device. The comparative example solid-state imaging device is a linear image sensor 900.

[0121] like Figure 4 As shown, the linear image sensor 900 includes a semiconductor chip 901. The semiconductor chip 901 includes a photodiode region 101a and a control circuit region 101b. The linear image sensor 900 of the comparative example differs from the linear image sensor 100 of the first embodiment in that it does not include a photonic crystal region 101c.

[0122] Figure 5 This is an enlarged schematic top view of a comparative example solid-state imaging device. Figure 5 It is the same as the first embodiment. Figure 2 The corresponding diagram.

[0123] Figure 6 This is an enlarged schematic cross-sectional view of a comparative example solid-state imaging device. Figure 6 It is the same as the first embodiment. Figure 3 The corresponding diagram. Figure 6 yes Figure 5 AA' section.

[0124] Figure 7 This is an explanatory diagram of a comparative example solid-state imaging device. For example, assuming light ( Figure 7 The arrow in the image indicates that the light is incident from the outside of the first end E1 side of the semiconductor chip 901. Figure 7 Is with Figure 6 The corresponding diagram.

[0125] Some of the incident light is not completely absorbed by the semiconductor layer 10 and enters the photodiode PD. This intruding light generates a current in the photodiode PD based on the photoelectric effect. This generated current becomes noise. The noise generated by the intruding light from the outside degrades the initial characteristics and reliability of the linear image sensor 900.

[0126] Especially when the semiconductor layer 10 is silicon, long-wavelength light with low absorption in silicon is prone to generating noise. For example, infrared light with a wavelength around 1000 nm is prone to generating noise.

[0127] In a linear image sensor 900, for example, unlike a region image sensor where photodiodes are arranged in two dimensions, multiple photodiodes PDs are arranged in one direction. Therefore, a high proportion of the photodiodes PDs are affected by light incident from the ends of the semiconductor chip, particularly from the ends of the semiconductor chip near the photodiodes PDs. Consequently, the influence on the characteristics of light incident from the ends of the semiconductor chip, particularly from the ends of the semiconductor chip near the photodiodes PDs, is significant.

[0128] Figure 8 This is an explanatory diagram illustrating the function and effect of the solid-state imaging device according to the first embodiment. Figure 8 It is the same as the first embodiment. Figure 3 The corresponding diagram.

[0129] For example, suppose light ( Figure 8 The incident light (as indicated by the arrow in the image) enters from the outside of the first end E1 side of the semiconductor chip 101. The incident light is reflected by the photonic crystal formed in the photonic crystal region 101c. Therefore, the incident light is suppressed from entering the photodiode PD. Thus, a linear image sensor 100 that suppresses noise generation and improves initial characteristics and reliability can be realized.

[0130] Furthermore, since the photonic crystal formed in the photonic crystal region 101c is a two-dimensional photonic crystal, for example, the reflectivity can be improved even when the incident light has an angle with the normal direction of the first end E1.

[0131] From the viewpoint of suppressing incident light from entering the photodiode PD, it is preferable that the depth of the first trench 21, the depth of the second trench 22, and the depth of the third trench 23 are deeper than the depth of the n-type region 10c.

[0132] From the viewpoint of suppressing incident light from entering the photodiode PD, the depths of the first trench 21, the second trench 22, and the third trench 23 are preferably such that the depth of the n-type region 10c is deeper than the depth of the element separation trench 20.

[0133] From the viewpoint of suppressing incident light from entering the photodiode PD, it is preferable that the depth of the first trench 21, the depth of the second trench 22, and the depth of the third trench 23 are deeper than the depth of the p-type low-concentration region 10b.

[0134] From the viewpoint of suppressing incident light from entering the photodiode PD, it is preferable that the first trench 21, the second trench 22, and the third trench 23 are connected to the p-type high-concentration region 10a.

[0135] From the viewpoint of suppressing incident light from entering the photodiode PD, the depth of the first trench 21, the depth of the second trench 22, and the depth of the third trench 23 are preferably 3 μm or more, and more preferably 5 μm or more.

[0136] From the viewpoint of efficiently reflecting infrared light with a wavelength around 1000nm, the width of the first trench column TC1, the second trench column TC2, and the third trench column TC3 in the second direction perpendicular to the first direction ( Figure 2 The wavelength (wx) is preferably 170 nm or more and 1000 nm or less. Furthermore, from the viewpoint of efficiently reflecting infrared light with a wavelength around 1000 nm, the distance between the first trench column TC1 and the second trench column TC2, and between the second trench column TC2 and the third trench column TC3 (… Figure 2 The dx in the image is, for example, above 60nm and below 1000nm.

[0137] According to the first embodiment, a linear image sensor capable of suppressing noise generation can be realized.

[0138] (First variation)

[0139] The solid-state imaging device of the first variant of the first embodiment differs from the solid-state imaging device of the first embodiment in that the arrangement patterns of the first groove, the second groove, and the third groove are different.

[0140] Figure 9 This is an enlarged schematic top view of a first modified example of a solid-state imaging device according to the first embodiment. Figure 9 It is the same as the first embodiment. Figure 2 The corresponding diagram.

[0141] like Figure 9As shown, in the semiconductor chip of the first variation of the first embodiment, the first trench 21, the second trench 22, and the third trench 23 are regularly arranged in a square pattern to form a photonic crystal. The photonic crystal of the semiconductor chip of the first variation of the first embodiment is a so-called two-dimensional photonic crystal in which two substances are regularly arranged in a two-dimensional manner.

[0142] According to the first variation of the first embodiment, a linear image sensor that can suppress the generation of noise can be realized.

[0143] (Second variation)

[0144] The solid-state imaging device of the second variation of the first embodiment differs from the solid-state imaging device of the first embodiment in that the arrangement patterns of the first groove, the second groove, and the third groove are different.

[0145] Figure 10 This is an enlarged schematic top view of a solid-state imaging device of a second variation of the first embodiment. Figure 10 It is the same as the first embodiment. Figure 2 The corresponding diagram.

[0146] like Figure 10 As shown, in the semiconductor chip of the second variation of the first embodiment, the first trench 21, the second trench 22, and the third trench 23 are regularly arranged in a honeycomb structure pattern to form a photonic crystal. The photonic crystal of the semiconductor chip of the second variation of the first embodiment is a so-called two-dimensional photonic crystal in which two substances are regularly arranged in a two-dimensional manner.

[0147] According to the second variation of the first embodiment, a linear image sensor that can suppress the generation of noise can be realized.

[0148] (Third variation)

[0149] The solid-state imaging device of the third variation of the first embodiment differs from the solid-state imaging device of the first embodiment in that the interior of the first groove, the interior of the second groove, and the interior of the third groove have cavities.

[0150] Figure 11 This is an enlarged schematic cross-sectional view of a solid-state imaging device of the third variation of the first embodiment. Figure 11 It is the same as the first embodiment. Figure 3 The corresponding diagram.

[0151] like Figure 11As shown, in the semiconductor chip of the third variation of the first embodiment, the interiors of the first trench 21, the second trench 22, and the third trench 23 have cavities 19. For example, the upper portions of the first trench 21, the second trench 22, and the third trench 23 are embedded with dielectric 18.

[0152] Void 19 does not contain solid material. Void 19 may contain gas, for example.

[0153] According to the third variation of the first embodiment, a linear image sensor capable of suppressing noise generation can be realized.

[0154] (Fourth variation)

[0155] The solid-state imaging device of the fourth variation of the first embodiment differs from the solid-state imaging device of the first embodiment in that the first groove, the second groove, and the third groove have a straight shape extending along a first direction.

[0156] Figure 12 This is an enlarged schematic top view of the solid-state imaging device of the fourth variation of the first embodiment. Figure 12 It is the same as the first embodiment. Figure 2 The corresponding diagram.

[0157] Figure 13 This is an enlarged schematic cross-sectional view of the solid-state imaging device of the fourth variation of the first embodiment. Figure 13 It is the same as the first embodiment. Figure 3 The corresponding diagram. Figure 13 yes Figure 12 AA' section.

[0158] like Figure 12 As shown, in the semiconductor chip of the fourth variation of the first embodiment, the first trench 21, the second trench 22, and the third trench 23 have a straight shape extending along a first direction.

[0159] The first groove 21, which is straight in shape, constitutes the first groove column TC1. The second groove 22, which is straight in shape, constitutes the second groove column TC2. The third groove 23, which is straight in shape, constitutes the third groove column TC3.

[0160] In the semiconductor chip of the fourth variation of the first embodiment, the first trench 21, the second trench 22, and the third trench 23 are regularly arranged in a straight-line pattern to form a photonic crystal. The photonic crystal of the semiconductor chip of the fourth variation of the first embodiment is a so-called one-dimensional photonic crystal formed by regularly arranging two materials in a one-dimensional manner.

[0161] According to the fourth variation of the first embodiment, a linear image sensor capable of suppressing noise generation can be realized.

[0162] Based on the first embodiment and its variations, a solid-state camera device capable of suppressing noise generation can be realized.

[0163] (Second Implementation)

[0164] The solid-state imaging device of the second embodiment differs from that of the first embodiment in that it includes a semiconductor layer having a first surface and a second surface opposite to the first surface. The semiconductor layer includes: a plurality of photodiodes disposed on the first surface of the semiconductor layer; a first trench row disposed between two adjacent photodiodes, including at least one first trench and extending along a first direction; and a second trench row disposed between the first trench row and one of the two adjacent photodiodes, including at least one second trench and extending along the first direction. Hereinafter, descriptions that are repeated in the first embodiment will sometimes be omitted.

[0165] The following explanation will be based on the case where the first conductivity type is p-type and the second conductivity type is n-type.

[0166] Figure 14 This is a schematic top view of the solid-state imaging device according to the second embodiment. The solid-state imaging device of the second embodiment is a linear image sensor 200.

[0167] like Figure 14 As shown, in the linear image sensor 200, the semiconductor chip 201 includes a photodiode region 101a and a control circuit region 101b.

[0168] The semiconductor chip 201 extends in a first direction. The direction perpendicular to the first direction is the second direction.

[0169] In photodiode region 101a, a plurality of photodiodes PD are arranged along a first direction. Furthermore, in photodiode region 101a, a plurality of photodiodes PD are arranged along a second direction.

[0170] A photonic crystal is formed in the photodiode region 101a. The photonic crystal is formed by a periodic structure of trenches disposed on the semiconductor chip.

[0171] A control circuit region 101b is disposed between the photodiode region 101a and the end of the semiconductor chip 201 in a second direction. In the photodiode region 101a, for example, electronic circuitry for controlling the operation of the linear image sensor 200 is formed.

[0172] Figure 15 This is an enlarged schematic top view of the solid-state camera device according to the second embodiment. Figure 15 yes Figure 14 A top view of the region R2 enclosed by quadrilaterals. Figure 15 It is a diagram showing the layout pattern of the surface of the semiconductor layer 10 included in the semiconductor chip 201.

[0173] Figure 16 This is an enlarged schematic cross-sectional view of the solid-state imaging device according to the second embodiment. Figure 16 This is a cross-sectional view of semiconductor chip 201. Figure 16 yes Figure 15 AA' section.

[0174] Semiconductor chip 201 includes a semiconductor layer 10, an interlayer insulating layer 12, a metal layer 14, a component separation insulating layer 16, and a dielectric 18. Semiconductor layer 10 includes a p-type high-concentration region 10a (third semiconductor region), a p-type low-concentration region 10b (first semiconductor region), an n-type region 10c (second semiconductor region), a component separation trench 20, a first trench 21, a second trench 22, a third trench 23, a fourth trench 24, a fifth trench 25, a sixth trench 26, a first trench column TC1, a second trench column TC2, a third trench column TC3, a fourth trench column TC4, a fifth trench column TC5, and a sixth trench column TC6.

[0175] The first trench 21 is disposed on the first surface F1 of the semiconductor layer 10. The first trench 21 is a trench disposed on the semiconductor layer 10. The first trench 21 is a part of the semiconductor layer 10.

[0176] The first trench 21 is disposed between two adjacent photodiodes PD in the second direction.

[0177] The depth of the first trench 21 is greater than the depth of the n-type region 10c. The depth of the first trench 21 is greater than the depth of the component separation trench 20.

[0178] The depth of the first trench 21 is, for example, deeper than the depth of the p-type low-concentration region 10b. The first trench 21 is, for example, connected to the p-type high-concentration region 10a.

[0179] The second trench 22 is disposed on the first surface F1 of the semiconductor layer 10. The second trench 22 is a trench disposed on the semiconductor layer 10. The second trench 22 is a part of the semiconductor layer 10.

[0180] The second trench 22 is disposed between two adjacent photodiodes PD in the second direction.

[0181] The depth of the second trench 22 is greater than the depth of the n-type region 10c. The depth of the second trench 22 is greater than the depth of the component separation trench 20.

[0182] The depth of the second trench 22 is, for example, deeper than the depth of the p-type low-concentration region 10b. The second trench 22 is, for example, connected to the p-type high-concentration region 10a.

[0183] The third trench 23 is disposed on the first surface F1 of the semiconductor layer 10. The third trench 23 is a trench disposed on the semiconductor layer 10. The third trench 23 is a part of the semiconductor layer 10.

[0184] The third trench 23 is disposed between two adjacent photodiodes PD in the second direction.

[0185] The depth of the third trench 23 is greater than the depth of the n-type region 10c. The depth of the third trench 23 is greater than the depth of the component separation trench 20.

[0186] The depth of the third trench 23 is, for example, deeper than the depth of the p-type low-concentration region 10b. The third trench 23 is, for example, connected to the p-type high-concentration region 10a.

[0187] The depth of the first trench 21, the depth of the second trench 22, and the depth of the third trench 23 are, for example, more than 3 μm and less than 10 μm.

[0188] The interiors of the first trench 21, the second trench 22, and the third trench 23 are embedded with a dielectric 18. The dielectric 18 is, for example, an oxide, a nitride, or an oxynitride. The dielectric 18 is, for example, silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

[0189] The first trench column TC1, the second trench column TC2, and the third trench column TC3 are disposed in the photodiode region 101a.

[0190] The first trench array TC1 is disposed between two adjacent photodiodes PD in the second direction. The first trench array TC1 extends along the first direction.

[0191] A plurality of first grooves 21 constitute a first groove row TC1. In the first groove row TC1, the plurality of first grooves 21 are repeatedly arranged in a first direction in a predetermined first pattern.

[0192] The second trench column TC2 is disposed between the first trench column TC1 and one of the two adjacent photodiodes PD in the second direction. The second trench column TC2 extends along the first direction.

[0193] A plurality of second grooves 22 constitute a second groove column TC2. In the second groove column TC2, the plurality of second grooves 22 are repeatedly arranged in a first direction in a predetermined second pattern.

[0194] The third trench column TC3 is disposed between the second trench column TC2 and one of the two adjacent photodiodes PD in the second direction. The second trench column TC2 is disposed between the first trench column TC1 and the third trench column TC3. The third trench column TC3 extends along the first direction.

[0195] Multiple third grooves 23 constitute a third groove row TC3. In the third groove row TC3, multiple third grooves 23 are repeatedly arranged in a predetermined third pattern in a first direction.

[0196] The fourth trench 24 is disposed on the first surface F1 of the semiconductor layer 10. The fourth trench 24 is a trench disposed in the semiconductor layer 10. The fourth trench 24 is a part of the semiconductor layer 10.

[0197] The fourth trench 24 is disposed between two adjacent photodiodes PD in the first direction.

[0198] The depth of the fourth trench 24 is greater than the depth of the n-type region 10c. The depth of the fourth trench 24 is greater than the depth of the component separation trench 20.

[0199] The depth of the fourth trench 24 is, for example, deeper than the depth of the p-type low-concentration region 10b. The fourth trench 24 is, for example, connected to the p-type high-concentration region 10a.

[0200] The fifth trench 25 is disposed on the first surface F1 of the semiconductor layer 10. The fifth trench 25 is a trench disposed in the semiconductor layer 10. The fifth trench 25 is a part of the semiconductor layer 10.

[0201] The fifth trench 25 is disposed between two adjacent photodiodes PD in the first direction.

[0202] The depth of the fifth trench 25 is greater than the depth of the n-type region 10c. The depth of the fifth trench 25 is greater than the depth of the component separation trench 20.

[0203] The depth of the fifth trench 25 is, for example, deeper than the depth of the p-type low-concentration region 10b. The fifth trench 25 is, for example, connected to the p-type high-concentration region 10a.

[0204] The sixth trench 26 is disposed on the first surface F1 of the semiconductor layer 10. The sixth trench 26 is a trench disposed on the semiconductor layer 10. The sixth trench 26 is a part of the semiconductor layer 10.

[0205] The sixth trench 26 is disposed between two adjacent photodiodes PD in the first direction.

[0206] The depth of the sixth trench 26 is greater than the depth of the n-type region 10c. The depth of the sixth trench 26 is greater than the depth of the component separation trench 20.

[0207] The depth of the sixth trench 26 is, for example, deeper than the depth of the p-type low-concentration region 10b. The sixth trench 26 is, for example, connected to the p-type high-concentration region 10a.

[0208] The depth of the fourth trench 24, the depth of the fifth trench 25, and the depth of the sixth trench 26 are, for example, more than 3 μm and less than 10 μm.

[0209] The interiors of the fourth trench 24, the fifth trench 25, and the sixth trench 26 are embedded with a dielectric 18. The dielectric 18 is, for example, an oxide, a nitride, or an oxynitride. The dielectric 18 is, for example, silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

[0210] The fourth trench column TC4, the fifth trench column TC5, and the sixth trench column TC6 are disposed in the photodiode region 101a.

[0211] The fourth trench column TC4 is disposed between two adjacent photodiodes PD in the first direction. The fourth trench column TC4 extends along the second direction.

[0212] Multiple fourth grooves 24 constitute a fourth groove row TC4. In the fourth groove row TC4, multiple fourth grooves 24 are repeatedly arranged in a predetermined fourth pattern in a second direction.

[0213] The fifth trench column TC5 is disposed between the fourth trench column TC4 and one of the two adjacent photodiodes PD in the first direction. The fifth trench column TC5 extends along the second direction.

[0214] Multiple fifth grooves 25 constitute a fifth groove row TC5. In the fifth groove row TC5, multiple fifth grooves 25 are repeatedly arranged in a predetermined fifth pattern in a second direction.

[0215] The sixth trench column TC6 is disposed between the fifth trench column TC5 and one of the two adjacent photodiodes PD in the first direction. The fifth trench column TC5 is disposed between the fourth trench column TC4 and the sixth trench column TC6. The sixth trench column TC6 extends along the second direction.

[0216] Multiple sixth grooves 26 constitute a sixth groove row TC6. In the sixth groove row TC6, multiple sixth grooves 26 are repeatedly arranged in a predetermined sixth pattern in a second direction.

[0217] A photonic crystal is formed in region 101a of a photodiode. A photonic crystal is a structure in which two materials with different refractive indices are regularly arranged. A photonic crystal has the property of reflecting light within a specified wavelength range.

[0218] In the photodiode region 101a, between two adjacent photodiodes PD in the second direction, semiconductor layers 10 with different refractive indices and dielectrics 18 embedded in the first trench 21, the second trench 22 and the third trench 23 are regularly arranged to form a photonic crystal.

[0219] like Figure 15As shown, in the semiconductor chip 201 of the second embodiment, the first trench 21, the second trench 22, and the third trench 23 are regularly arranged in an equilateral triangle pattern to form a photonic crystal. The photonic crystal of the semiconductor chip 201 of the second embodiment is a so-called two-dimensional photonic crystal in which two substances are regularly arranged in a two-dimensional manner.

[0220] Alternatively, as in the first variation of the first embodiment, the first groove 21, the second groove 22, and the third groove 23 may be arranged regularly in a quadrilateral pattern. Furthermore, as in the second variation of the first embodiment, the first groove 21, the second groove 22, and the third groove 23 may be arranged regularly in a honeycomb pattern. Additionally, as in the fourth variation of the first embodiment, the first groove 21, the second groove 22, and the third groove 23 may have a straight line shape extending along a first direction.

[0221] The reflectivity of light with a wavelength of 1000 nm formed between two adjacent photodiodes (PDs) in the second direction is, for example, over 80%.

[0222] The width of the first trench column TC1, the second trench column TC2, and the third trench column TC3 in the second direction perpendicular to the first direction ( Figure 15 The wx in the text is, for example, above 170nm and below 1000nm. Furthermore, the distances between the first trench column TC1 and the second trench column TC2, and between the second trench column TC2 and the third trench column TC3 (…). Figure 15 The dx in the image is, for example, above 60nm and below 1000nm.

[0223] In addition, in the photodiode region 101a, between two adjacent photodiodes PD in the first direction, semiconductor layers 10 with different refractive indices and dielectrics 18 buried in the fourth trench 24, the fifth trench 25 and the sixth trench 26 are regularly arranged to form a photonic crystal.

[0224] like Figure 15 As shown, in the semiconductor chip 201 of the second embodiment, the fourth trench 24, the fifth trench 25, and the sixth trench 26 are regularly arranged in an equilateral triangle pattern to form a photonic crystal. The photonic crystal of the semiconductor chip 201 of the second embodiment is a so-called two-dimensional photonic crystal in which two substances are regularly arranged in a two-dimensional manner.

[0225] Alternatively, as in the first variation of the first embodiment, the fourth groove 24, the fifth groove 25, and the sixth groove 26 may be arranged regularly in a quadrilateral pattern. Furthermore, as in the second variation of the first embodiment, the fourth groove 24, the fifth groove 25, and the sixth groove 26 may be arranged regularly in a honeycomb pattern. Additionally, as in the fourth variation of the first embodiment, the fourth groove 24, the fifth groove 25, and the sixth groove 26 may have a straight line shape extending along a first direction.

[0226] The reflectivity of light with a wavelength of 1000 nm formed between two adjacent photodiodes (PDs) in the first direction is, for example, 80% or more.

[0227] The width of the fourth trench column TC4, the fifth trench column TC5, and the sixth trench column TC6 in the first direction is, for example, 170 nm or more and 1000 nm or less. Furthermore, the distance in the first direction between the fourth trench column TC4 and the fifth trench column TC5, and between the fifth trench column TC5 and the sixth trench column TC6, is, for example, 60 nm or more and 1000 nm or less.

[0228] Next, the function and effects of the linear image sensor 200 in the second embodiment will be explained.

[0229] Figure 17 This is an enlarged schematic top view of a comparative example solid-state imaging device. Figure 17 It is the same as the second embodiment. Figure 15 The corresponding diagram.

[0230] Figure 18 This is an enlarged schematic cross-sectional view of a comparative example solid-state imaging device. Figure 18 It is the same as the second embodiment. Figure 16 The corresponding diagram. Figure 18 yes Figure 17 AA' section.

[0231] like Figure 17 as well as Figure 18 As shown, the semiconductor chip 902 of the comparative example linear image sensor differs from the semiconductor chip 201 of the linear image sensor 200 of the second embodiment in that it does not include the first trench column TC1, the second trench column TC2, the third trench column TC3, the fourth trench column TC4, the fifth trench column TC5, and the sixth trench column TC6.

[0232] Figure 19 This is an explanatory diagram of a comparative example solid-state imaging device. Figure 19 Is with Figure 18 The corresponding diagram.

[0233] For example, suppose light ( Figure 19(The arrow in the image indicates that the light is incident on the photodiode PD of the semiconductor chip 902 from the adjacent photodiode PD in the second direction. The light incident from the adjacent photodiode PD is, for example, reflected light from the adjacent photodiode PD or light generated by secondary photons generated in the adjacent photodiode PD.)

[0234] Light entering from an adjacent photodiode (PD) generates a current in the PD based on the photoelectric effect. This generated current becomes noise. The noise generated by the light entering from the adjacent PD degrades the initial characteristics and reliability of the linear image sensor.

[0235] Especially when the semiconductor layer 10 is silicon, long-wavelength light with low absorption in silicon is prone to generating noise. For example, infrared light with a wavelength around 1000 nm is prone to generating noise.

[0236] Figure 20 This is an explanatory diagram illustrating the function and effect of the solid-state imaging device according to the second embodiment. Figure 20 It is the same as the second embodiment. Figure 16 The corresponding diagram.

[0237] For example, suppose light ( Figure 20 The incident light (as indicated by the arrow in the diagram) is incident from adjacent photodiodes (PDs) in the second direction. The incident light is reflected by a photonic crystal formed between the two adjacent photodiodes (PDs) in the second direction. Therefore, incident light intrusion into the photodiodes (PDs) is suppressed. Thus, a linear image sensor 200 that suppresses noise generation and improves initial characteristics and reliability can be realized.

[0238] Furthermore, assuming light is incident from adjacent photodiodes (PDs) in the first direction, the incident light is reflected by a photonic crystal formed between the two adjacent photodiodes (PDs) in the first direction. Therefore, the intrusion of incident light into the photodiodes (PDs) is suppressed. Thus, a linear image sensor 200 that suppresses noise generation and improves initial characteristics and reliability can be realized.

[0239] From the viewpoint of suppressing incident light from entering the photodiode PD, it is preferable that the depths of the first trench 21, the second trench 22, the third trench 23, the fourth trench 24, the fifth trench 25, and the sixth trench 26 are deeper than the depth of the n-type region 10c.

[0240] From the viewpoint of suppressing incident light intrusion into the photodiode PD, the depths of the first trench 21, the second trench 22, the third trench 23, the fourth trench 24, the fifth trench 25, and the sixth trench 26 are preferably deeper than the depth of the n-type region 10c.

[0241] From the viewpoint of suppressing incident light from entering the photodiode PD, it is preferable that the depths of the first trench 21, the second trench 22, the third trench 23, the fourth trench 24, the fifth trench 25, and the sixth trench 26 are deeper than the depth of the p-type low-concentration region 10b.

[0242] From the viewpoint of suppressing incident light from entering the photodiode PD, it is preferable that the first trench 21, the second trench 22, the third trench 23, the fourth trench 24, the fifth trench 25 and the sixth trench 26 are connected to the p-type high-concentration region 10a.

[0243] From the viewpoint of suppressing incident light from entering the photodiode PD, the depths of the first trench 21, the second trench 22, the third trench 23, the fourth trench 24, the fifth trench 25, and the sixth trench 26 are preferably 3 μm or more, and more preferably 5 μm or more.

[0244] From the viewpoint of efficiently reflecting infrared light with a wavelength around 1000nm, the width of the second direction of the first trench column TC1, the second trench column TC2, and the third trench column TC3 ( Figure 15 The wavelength (wx) is preferably 170 nm or more and 1000 nm or less. Furthermore, from the viewpoint of efficiently reflecting infrared light with a wavelength around 1000 nm, the distance between the first trench column TC1 and the second trench column TC2, and between the second trench column TC2 and the third trench column TC3 (… Figure 15 The dx in the first direction is preferably 60 nm or more and 1000 nm or less. 4. The width of the fifth trench column TC5 and the sixth trench column TC6 in the first direction is preferably 170 nm or more and 1000 nm or less. Furthermore, from the viewpoint of efficiently reflecting infrared light with a wavelength around 1000 nm, the distance between the fourth trench column TC4 and the fifth trench column TC5, and between the fifth trench column TC5 and the sixth trench column TC6, is preferably 60 nm or more and 1000 nm or less.

[0245] According to the second embodiment, a linear image sensor that can suppress the generation of noise can be realized.

[0246] In the first and second embodiments, the case where the first conductivity type is p-type and the second conductivity type is n-type is used as an example for explanation, but the first conductivity type can also be set to n-type and the second conductivity type to p-type.

[0247] In the first and second embodiments, a case with three trench rows is illustrated, but there may also be two or four or more trench rows. From the viewpoint of balancing noise reduction and reduction of semiconductor chip area increase, three or more trench rows and ten or fewer are preferred.

[0248] In the first and second embodiments, the case where the semiconductor layer 10 is silicon was described as an example, but the semiconductor layer 10 may also be a semiconductor other than silicon, such as silicon carbide (SiC).

[0249] In the second embodiment, the case where the linear image sensor 200 does not include the photonic crystal region 101c of the first embodiment is described as an example, but the linear image sensor 200 of the second embodiment can also be configured to include the photonic crystal region 101c.

[0250] In the first and second embodiments, a linear image sensor was used as an example of a solid-state imaging device, but the solid-state imaging device of the present invention is not limited to a linear image sensor. The solid-state imaging device of the present invention may also be other optical sensors using photodiodes, such as area image sensors.

[0251] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. For example, the constituent elements of one embodiment may be substituted or modified with the constituent elements of other embodiments. These embodiments and their variations are included in the scope and spirit of the invention, and are included in the scope of the invention as described in the claims and its equivalents.

Claims

1. A solid-state imaging device, wherein, The device includes a semiconductor chip comprising a semiconductor layer having a first surface and a second surface opposite to the first surface. The semiconductor layer comprises: Multiple photodiodes are disposed on the first surface of the semiconductor layer and arranged along a first direction; A first trench array is disposed on the first surface of the semiconductor layer and between the ends of the photodiode and the semiconductor chip, and includes at least one first trench extending along the first direction; as well as A second groove row is disposed between the first groove row and the end, and includes at least one second groove extending along the first direction.

2. The solid-state imaging device as claimed in claim 1, wherein, In the first trench row, a plurality of the first trenches are repeatedly arranged in the first direction in a predetermined first pattern. In the second trench column, a plurality of the second trenches are repeatedly configured in the first direction in a predetermined second pattern.

3. The solid-state imaging device as claimed in claim 1, wherein, The first trench and the second trench have a straight shape extending along the first direction.

4. The solid-state imaging device as claimed in claim 1, wherein, The semiconductor layer further includes a third trench column disposed between the second trench column and the end, and includes at least one third trench extending along the first direction.

5. The solid-state imaging device as claimed in claim 1, wherein, The semiconductor chip further includes a dielectric embedded in the first trench and the second trench.

6. The solid-state imaging device as claimed in claim 5, wherein, The dielectric is silicon oxide, aluminum oxide, silicon nitride, or silicon oxynitride.

7. The solid-state imaging device as claimed in claim 1, wherein, The interior of the first trench and the interior of the second trench have cavities.

8. The solid-state imaging device as claimed in claim 1, wherein, The semiconductor layer further includes an element separation trench disposed on the first surface of the semiconductor layer and between two adjacent photodiodes, with a depth shallower than the depth of the first trench and the second trench.

9. The solid-state imaging device as claimed in claim 1, wherein, The plurality of photodiodes are arranged along a second direction perpendicular to the first direction.

10. The solid-state imaging device as claimed in claim 9, wherein, The number of photodiodes arranged along the first direction is more than 10 times the number of photodiodes arranged along the second direction.

11. The solid-state imaging device as claimed in claim 1, wherein, The first trench column and the second trench column constitute a photonic crystal.

12. The solid-state imaging device as claimed in claim 11, wherein, The photonic crystal has a reflectivity of over 80% for light with a wavelength of 1000 nm.

13. The solid-state imaging device as claimed in claim 1, wherein, The width of the first trench column and the second trench column in the second direction perpendicular to the first direction is less than 1000 nm. The distance between the first trench column and the second trench column is less than 1000 nm.

14. The solid-state imaging device as claimed in claim 1, wherein, The semiconductor layer includes: a first semiconductor region of a first conductivity type; and a second semiconductor region of a second conductivity type, disposed between the first semiconductor region and the first surface, and in contact with the first surface. The photodiode is composed of the second semiconductor region and the first semiconductor region. The depths of the first trench and the second trench are greater than the depth of the first semiconductor region.

15. The solid-state imaging device as claimed in claim 14, wherein, The semiconductor layer further includes a third semiconductor region of a first conductivity type, which is disposed between the first semiconductor region and the second surface, and the impurity concentration of the first conductivity type is higher than that of the first semiconductor region. The first trench and the second trench are connected to the third semiconductor region.

16. The solid-state imaging device as claimed in claim 1, wherein, The semiconductor layer is silicon.

17. The solid-state imaging device as claimed in claim 1, wherein, The solid-state camera device is a linear image sensor.

18. A solid-state imaging device, wherein, It includes a semiconductor layer having a first surface and a second surface opposite to the first surface. The semiconductor layer comprises: Multiple photodiodes are disposed on the first surface of the semiconductor layer; A first trench array is disposed between two adjacent photodiodes and includes at least one first trench extending along a first direction; as well as The second trench array, disposed between the first trench array and one of the two adjacent photodiodes, includes at least one second trench extending along the first direction.

19. The solid-state imaging device as claimed in claim 18, wherein, In the first trench row, a plurality of the first trenches are repeatedly arranged in the first direction in a predetermined first pattern. In the second trench column, a plurality of the second trenches are repeatedly configured in the first direction in a predetermined second pattern.

20. The solid-state imaging device as claimed in claim 18, wherein, The first trench and the second trench have a straight shape extending along the first direction.

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