Flat panel detector, method of manufacturing the same, and x-ray imaging system

Abstract

A flat panel detector, a preparation method thereof and an X-ray imaging system. The flat panel detector comprises a plurality of sub-pixels, at least one of which comprises a transistor and a photosensitive device, the photosensitive device comprising at least a bottom electrode, a photoelectric conversion layer, a top electrode and a control electrode, the photoelectric conversion layer comprising at least a first surface away from a substrate side, a second surface close to the substrate side and a side surface between the first surface and the second surface, the bottom electrode overlapping the second surface, the top electrode overlapping the first surface, and the control electrode being connected with the top electrode; in at least one of the sub-pixels, a normal projection of the top electrode on the substrate is within a range of a normal projection of the first surface of the photoelectric conversion layer on the substrate, and a normal projection of the control electrode on the substrate contains a normal projection of the side surface of the photoelectric conversion layer on the substrate. The scheme effectively solves the problems such as residual image.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a flat panel detector and its fabrication method, and an X-ray imaging system. Background Technology

[0002] X-ray detection is widely used in modern medical imaging. The most advanced direct digital radiography (DR) uses a one-dimensional or two-dimensional X-ray detector, controlled by a computer with image processing capabilities, to directly convert X-ray information into digital image information. A key component in two-dimensional X-ray detection technology is the flat panel detector (FPD) for image acquisition.

[0003] Existing flat panel detectors suffer from problems such as image retention. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] The technical problem to be solved by this disclosure is to provide a flat panel detector and its preparation method, as well as an X-ray imaging system, which solves the problems of image retention in existing flat panel detectors.

[0006] This disclosure provides a flat panel detector including a plurality of sub-pixels. At least one sub-pixel includes a transistor and a photosensitive device. In a direction perpendicular to the plane of the flat panel detector, the photosensitive device includes at least a bottom electrode disposed on a substrate, a photoelectric conversion layer disposed on the side of the bottom electrode away from the substrate, a top electrode disposed on the side of the photoelectric conversion layer away from the substrate, and a control electrode disposed on the side of the top electrode away from the substrate. The photoelectric conversion layer includes at least a first surface away from the substrate, a second surface close to the substrate, and a side surface located between the first surface and the second surface. The bottom electrode overlaps with the second surface, the top electrode overlaps with the first surface, and the control electrode is connected to the top electrode. In at least one sub-pixel, the orthographic projection of the top electrode on the substrate is within the range of the orthographic projection of the first surface of the photoelectric conversion layer on the substrate, and the orthographic projection of the control electrode on the substrate includes the orthographic projection of the side surface of the photoelectric conversion layer on the substrate.

[0007] In an exemplary embodiment, the first surface includes at least a first region and a second region, wherein the orthographic projection of the first region on the substrate at least partially overlaps with the orthographic projection of the top electrode on the substrate, the orthographic projection of the second region on the substrate does not overlap with the orthographic projection of the top electrode on the substrate, and the orthographic projection of the control electrode on the substrate includes the orthographic projection of the second region on the substrate.

[0008] In an exemplary embodiment, the orthographic projection of the control electrode on the substrate at least partially overlaps with the orthographic projection of the top electrode on the substrate.

[0009] In an exemplary embodiment, the flat panel detector further includes a third insulating layer disposed on the side of the top electrode away from the substrate, and the control electrode disposed on the side of the third insulating layer away from the substrate. A second via is disposed on the third insulating layer, and the control electrode is connected to the top electrode through the second via. The area of ​​the second via is smaller than the area of ​​the top electrode, and the orthographic projection of the second via on the substrate is within the range of the orthographic projection of the top electrode on the substrate.

[0010] In an exemplary embodiment, the flat panel detector further includes a fourth insulating layer and a fifth insulating layer, the fourth insulating layer being disposed on the side of the control electrode away from the substrate, and the fifth insulating layer being disposed on the side of the fourth insulating layer away from the substrate; the photosensitive device further includes a bias electrode, the bias electrode being disposed on the side of the fifth insulating layer away from the substrate, and a third via being disposed on the fourth and fifth insulating layers, the bias electrode being connected to the control electrode through the third via; wherein, the orthographic projection of the third via on the substrate at least partially overlaps with the orthographic projection of the top electrode on the substrate.

[0011] In an exemplary embodiment, the flat panel detector further includes a fourth insulating layer and a fifth insulating layer. The fourth insulating layer is disposed on the side of the control electrode away from the substrate, and the fifth insulating layer is disposed on the side of the fourth insulating layer away from the substrate. The photosensitive device further includes a connecting block and a bias electrode. The connecting block and the control electrode are an integral structure interconnected. The bias electrode is disposed on the side of the fifth insulating layer away from the substrate. The bias electrode includes a first sub-electrode and a second sub-electrode. A fourth via and a fifth via are disposed on the fourth insulating layer and the fifth insulating layer, respectively. The first sub-electrode is connected to the connecting block through the fourth via, and the second sub-electrode is connected to the control electrode through the fifth via.

[0012] In an exemplary embodiment, the orthographic projection of the fourth via on the substrate does not overlap with the orthographic projection of the photoelectric conversion layer on the substrate, the orthographic projection of the fifth via on the substrate at least partially overlaps with the orthographic projection of the top electrode on the substrate, the orthographic projection of the first sub-electrode on the substrate does not overlap with the orthographic projection of the photoelectric conversion layer on the substrate, and the orthographic projection of the second sub-electrode on the substrate at least partially overlaps with the orthographic projection of the photoelectric conversion layer on the substrate.

[0013] In an exemplary embodiment, the flat panel detector further includes a bias line, which includes at least a first bias sub-line and a second bias sub-line. The first bias sub-line is connected to the first sub-electrode, and the second bias sub-line is connected to the second sub-electrode. The first sub-electrode is disposed on the side of the photoelectric conversion layer away from the second sub-electrode, and the second sub-electrode is disposed at the edge of the photoelectric conversion layer away from the first sub-electrode. The first bias sub-line is disposed on the side of the first sub-electrode away from the second sub-electrode, and the second bias sub-line is disposed on the side of the second sub-electrode away from the first sub-electrode.

[0014] In an exemplary embodiment, the flat panel detector further includes a third insulating layer disposed on the side of the top electrode away from the substrate, and the control electrode disposed on the side of the third insulating layer away from the substrate; the photosensitive device further includes a bias electrode disposed on the side of the control electrode away from the substrate, and the control electrode is connected to the top electrode through the bias electrode.

[0015] In an exemplary embodiment, the control electrode includes a main body and an overlapping portion. The main body is ring-shaped, and the overlapping portion is block-shaped. The overlapping portion is disposed inside the ring of the main body. A first end of the overlapping portion is connected to the main body, and a second end of the overlapping portion is connected to the bias electrode. The orthographic projection of the main body on the substrate includes at least the orthographic projection of the side surface of the photoelectric conversion layer on the substrate.

[0016] In an exemplary embodiment, the flat panel detector further includes a fourth insulating layer and a fifth insulating layer. The fourth insulating layer is disposed on the side of the control electrode away from the substrate, and the fifth insulating layer is disposed on the side of the fourth insulating layer away from the substrate. The bias electrode is disposed on the side of the fifth insulating layer away from the substrate. The third, fourth, and fifth insulating layers are provided with a sixth via, and the bias electrode is connected to both the control electrode and the top electrode through the sixth via.

[0017] In an exemplary embodiment, the sixth via includes a first portion and a second portion, the first portion exposing a portion of the surface of the top electrode and the second portion exposing a portion of the surface of the overlap portion, so that the bias electrode is connected to both the control electrode and the top electrode through the sixth via.

[0018] In an exemplary embodiment, the sixth via includes a first portion and a second portion, the first portion exposing a portion of the surface of the top electrode, and the second portion exposing the end surface of the overlap portion away from the main body portion, so that the bias electrode is connected to both the control electrode and the top electrode through the sixth via.

[0019] This disclosure also provides an X-ray imaging system including the aforementioned flat panel detector.

[0020] This disclosure also provides a method for fabricating a flat panel detector, the flat panel detector comprising a plurality of sub-pixels, at least one sub-pixel comprising a transistor and a photosensitive device; the fabrication method comprising: A bottom electrode is formed on the substrate; A photoelectric conversion layer is formed on the side of the bottom electrode away from the substrate; the photoelectric conversion layer includes at least a first surface away from the substrate, a second surface close to the substrate, and a side surface located between the first surface and the second surface, the second surface overlapping the bottom electrode; A top electrode is formed on the side of the photoelectric conversion layer away from the substrate. The top electrode overlaps with the first surface, and the orthographic projection of the top electrode on the substrate is within the range of the orthographic projection of the first surface on the substrate. A control electrode is formed on the side of the top electrode away from the substrate. The control electrode is connected to the top electrode, and the orthographic projection of the control electrode on the substrate includes the orthographic projection of the side surface of the photoelectric conversion layer on the substrate.

[0021] This exemplary embodiment discloses a flat panel detector and its fabrication method, as well as an X-ray imaging system. By setting control electrodes, the orthogonal projection of the control electrodes on the substrate can include the orthogonal projection of the side surface of the photoelectric conversion layer on the substrate, which effectively improves the electric field intensity of the side surface of the photoelectric conversion layer, so that the photocharge generated in the photoelectric conversion layer can be completely read out, reducing the residual photocharge in the photoelectric conversion layer, and effectively solving the problems of image retention in existing flat panel detectors.

[0022] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0023] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0024] Figure 1 This is a schematic diagram of a flat panel detector; Figure 2A This is a schematic diagram of the structure of a flat panel detector, which is an exemplary embodiment of the present disclosure. Figure 2B for Figure 2A Schematic diagram of the cross-sectional structure along the AA direction; Figure 3A for Figure 2A The diagram shown illustrates the flat panel detector after the first conductive layer pattern has been formed. Figure 3B for Figure 3A Schematic diagram of the cross-sectional structure along the AA direction; Figure 4A for Figure 2A The diagram shown is a schematic diagram of the flat panel detector after the first semiconductor layer pattern has been formed. Figure 4B for Figure 4A Schematic diagram of the cross-sectional structure along the AA direction; Figure 5A for Figure 2A The diagram shown illustrates the second conductive layer pattern formed on the flat panel detector in the embodiment shown. Figure 5B for Figure 5A Schematic diagram of the cross-sectional structure along the AA direction; Figure 6A for Figure 2A The diagram shown is a schematic diagram of the flat panel detector after the second insulating layer pattern has been formed. Figure 6B for Figure 6A Schematic diagram of the cross-sectional structure along the AA direction; Figure 7A for Figure 2A The diagram shown illustrates the formation of the third conductive layer pattern in the flat panel detector of the embodiment shown. Figure 7B for Figure 7A Schematic diagram of the cross-sectional structure along the AA direction; Figure 8A for Figure 2A A schematic diagram of the flat panel detector after the formation of the second semiconductor layer pattern in the illustrated embodiment; Figure 8B for Figure 8A Schematic diagram of the cross-sectional structure along the AA direction; Figure 9A for Figure 2A The schematic diagram shown is a flat panel detector after the fourth conductive layer pattern has been formed in the embodiment shown. Figure 9B for Figure 9A Schematic diagram of the cross-sectional structure along the AA direction; Figure 10A for Figure 2A The diagram shown illustrates the formation of the third insulating layer pattern in the flat panel detector of the embodiment shown. Figure 10B for Figure 10A Schematic diagram of the cross-sectional structure along the AA direction; Figure 11A for Figure 2A The schematic diagram shown is a flat panel detector after the fifth conductive layer pattern has been formed in the embodiment shown. Figure 11B for Figure 11A Schematic diagram of the cross-sectional structure along the AA direction; Figure 12A for Figure 2A The schematic diagram shown is a schematic diagram of the flat panel detector after the formation of the fourth and fifth insulating layer patterns; Figure 12B for Figure 12A Schematic diagram of the cross-sectional structure along the AA direction; Figure 13A for Figure 2A A schematic diagram of the flat panel detector in the illustrated embodiment after the formation of the sixth conductive layer pattern; Figure 13B for Figure 13A Schematic diagram of the cross-sectional structure along the AA direction; Figure 14A This is a schematic diagram of the structure of another flat panel detector as an exemplary embodiment of the present disclosure; Figure 14B for Figure 14A Schematic diagram of the cross-sectional structure along the BB direction; Figure 15A for Figure 14A The schematic diagram shown is a flat panel detector after the fifth conductive layer pattern has been formed in the embodiment shown. Figure 15B for Figure 15A Schematic diagram of the cross-sectional structure along the BB direction; Figure 16A for Figure 14A The diagram shown is a schematic diagram of the flat panel detector after the formation of the fourth and fifth insulating layer patterns. Figure 16B for Figure 16A Schematic diagram of the cross-sectional structure along the BB direction; Figure 17A for Figure 14A The diagram shown is a schematic diagram of the flat panel detector after the formation of the sixth conductive layer pattern in the embodiment shown. Figure 17B for Figure 17A Schematic diagram of the cross-sectional structure along the BB direction; Figure 18A This is a schematic diagram of the structure of another flat panel detector, which is an exemplary embodiment of the present disclosure. Figure 18B for Figure 18A Schematic diagram of the cross-sectional structure along the CC direction; Figure 19A for Figure 18A The schematic diagram shown is a flat panel detector after the fifth conductive layer pattern has been formed in the embodiment shown. Figure 19B for Figure 19A Schematic diagram of the cross-sectional structure along the CC direction; Figure 20A for Figure 18A The schematic diagram shown is a schematic diagram of the flat panel detector after the formation of the fourth and fifth insulating layer patterns; Figure 20B for Figure 20A Schematic diagram of the cross-sectional structure along the CC direction; Figure 21A for Figure 18A A schematic diagram of the flat panel detector in the illustrated embodiment after the formation of the sixth conductive layer pattern; Figure 21B for Figure 21A Schematic diagram of the cross-sectional structure along the CC direction; Figure 22A This is a schematic diagram of the structure of another flat panel detector, which is an exemplary embodiment of the present disclosure. Figure 22B for Figure 22A A schematic diagram of the cross-sectional structure along the CC direction.

[0025] Explanation of reference numerals in the attached figures: Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0027] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0028] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0029] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0030] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0031] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the area through which current primarily flows.

[0032] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0033] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0034] In this specification, "parallel" refers to two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" refers to two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0035] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0036] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances, and may include chamfers, curved edges, and other variations. The term "approximately" in this disclosure means that the limits are not strictly defined, and the values ​​are within the allowable range of process and measurement errors.

[0037] Figure 1 This is a schematic diagram of a flat panel detector. Figure 1 As shown, the flat panel detector includes multiple scan signal lines 1, multiple data signal lines 2, and multiple sub-pixels forming multiple pixel rows and multiple pixel columns. At least one sub-pixel may include a transistor 3 and a photosensitive device 4, with the photosensitive device 4 connected to the transistor 3. The scan signal lines 1 are configured to provide scan signals to the corresponding transistors 3. In response to the scan signals, the transistors 3 are turned on, thereby sending the sensing signals from the photosensitive device 4 to the data signal lines 2. The data signal lines 2 output the sensing signals to an external data processing circuit.

[0038] This disclosure provides a flat panel detector including a plurality of sub-pixels. At least one sub-pixel includes a transistor and a photosensitive device. In a direction perpendicular to the plane of the flat panel detector, the photosensitive device includes at least a bottom electrode disposed on a substrate, a photoelectric conversion layer disposed on the side of the bottom electrode away from the substrate, a top electrode disposed on the side of the photoelectric conversion layer away from the substrate, and a control electrode disposed on the side of the top electrode away from the substrate. The photoelectric conversion layer includes at least a first surface away from the substrate, a second surface close to the substrate, and a side surface located between the first surface and the second surface. The bottom electrode overlaps with the second surface, the top electrode overlaps with the first surface, and the control electrode is connected to the top electrode. In at least one sub-pixel, the orthographic projection of the top electrode on the substrate is within the range of the orthographic projection of the first surface of the photoelectric conversion layer on the substrate, and the orthographic projection of the control electrode on the substrate includes the orthographic projection of the side surface of the photoelectric conversion layer on the substrate.

[0039] In an exemplary embodiment, the first surface includes at least a first region and a second region, wherein the orthographic projection of the first region on the substrate at least partially overlaps with the orthographic projection of the top electrode on the substrate, the orthographic projection of the second region on the substrate does not overlap with the orthographic projection of the top electrode on the substrate, and the orthographic projection of the control electrode on the substrate includes the orthographic projection of the second region on the substrate.

[0040] In an exemplary embodiment, the orthographic projection of the control electrode on the substrate at least partially overlaps with the orthographic projection of the top electrode on the substrate.

[0041] The following examples illustrate the flat panel detector of this disclosure.

[0042] Figure 2A This is a schematic diagram of the structure of a flat panel detector, which is an exemplary embodiment of the present disclosure. Figure 2B for Figure 2A A sectional view along the AA direction. (e.g.) Figure 2A and Figure 2BAs shown, in a plane parallel to the flat panel detector, the flat panel detector may include at least a scan signal line 1 extending along a first direction X, a data signal line 2 extending along a second direction Y, and transistors and photosensitive devices disposed in the area defined by the scan signal line 1 and the data signal line 2, wherein the first direction X and the second direction Y intersect. In a direction perpendicular to the plane of the flat panel detector, the flat panel detector may include at least a substrate 10, a first conductive layer disposed on the substrate 10, a first insulating layer 11 disposed on the side of the first conductive layer away from the substrate 10, a first semiconductor layer disposed on the side of the first insulating layer 11 away from the substrate 10, a second conductive layer disposed on the side of the first semiconductor layer away from the substrate 10, a second insulating layer 12 disposed on the side of the second conductive layer away from the substrate 10, a third conductive layer disposed on the side of the second insulating layer 12 away from the substrate 10, a second semiconductor layer disposed on the side of the third conductive layer away from the substrate 10, a fourth conductive layer disposed on the side of the second semiconductor layer away from the substrate 10, a third insulating layer 13 disposed on the side of the fourth conductive layer away from the substrate 10, a fifth conductive layer disposed on the side of the third insulating layer 13 away from the substrate 10, a fourth insulating layer 14 disposed on the side of the fifth conductive layer away from the substrate 10, a fifth insulating layer 15 disposed on the side of the fourth insulating layer 14 away from the substrate 10, a sixth conductive layer disposed on the side of the fifth insulating layer 15 away from the substrate 10, and a sixth insulating layer 16 disposed on the side of the sixth conductive layer away from the substrate 10.

[0043] In an exemplary embodiment, the first direction X can be the pixel row direction, the second direction Y can be the pixel column direction, and the first direction X and the second direction Y can be perpendicular to each other.

[0044] In an exemplary embodiment, in at least one sub-pixel, the first conductive layer may include at least a scan signal line 1 and a gate electrode 21, the first semiconductor layer may include at least an active portion 22, the second conductive layer may include at least a data signal line 2, a first electrode 23 and a second electrode 24, the third conductive layer may include at least a bottom electrode 31, the second semiconductor layer may include at least a photoelectric conversion layer 32, the fourth conductive layer may include at least a top electrode 33, the fifth conductive layer may include at least a control electrode 41, and the sixth conductive layer may include at least a bias line 5 and a bias electrode 51, with the bias electrode 51 connected to the bias line 5.

[0045] In an exemplary embodiment, the gate electrode 21 can be connected to the scan signal line 1, the first end of the first electrode 23 can be connected to the active part 22, the second end of the first electrode 23 can be connected to the data signal line 2, the first end of the second electrode 24 can be connected to the active part 22, and the second end of the second electrode 24 can be connected to the bottom electrode 31. The gate electrode 21, the active part 22, the first electrode 23, and the second electrode 24 constitute a transistor.

[0046] In an exemplary embodiment, in at least one sub-pixel, the photoelectric conversion layer 32 may include at least a first surface away from the substrate 10, a second surface close to the substrate 10, and a side surface located between the first surface and the second surface. The bottom electrode 31 may overlap with the second surface, the top electrode 33 may overlap with the first surface, and the control electrode 41 may be connected to the top electrode 33.

[0047] In an exemplary embodiment, the orthographic projection of the top electrode 33 on the substrate may be within the range of the orthographic projection of the first surface of the photoelectric conversion layer 32 on the substrate, and the orthographic projection of the control electrode 41 on the substrate may at least include the orthographic projection of the side surface of the photoelectric conversion layer 32 on the substrate.

[0048] In some possible implementations, the orthogonal projection of the control electrode 41 onto the substrate may include at least the orthogonal projection of the photoelectric conversion layer 32 onto the substrate.

[0049] In an exemplary embodiment, a second via may be provided on the third insulating layer 13. The orthogonal projection of the second via on the substrate may be located within the range of the orthogonal projection of the top electrode 33 on the substrate. The control electrode 41 may be connected to the top electrode 33 through the second via.

[0050] In an exemplary embodiment, a third via may be provided on the fourth insulating layer 14 and the fifth insulating layer 15. The orthographic projection of the third via on the substrate at least partially overlaps with the orthographic projection of the top electrode 31 on the substrate. The bias electrode 51 can be connected to the control electrode 41 through the third via.

[0051] In an exemplary embodiment, the bottom electrode 31, the photoelectric conversion layer 32, the top electrode 33, the control electrode 41, and the bias electrode 51 can constitute a photosensitive device.

[0052] The following is an illustrative example of the fabrication process of a flat panel detector. The "patterning process" described in this disclosure, for metallic, inorganic, or transparent conductive materials, includes processes such as depositing a film, coating the film with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as coating the organic material, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of A includes the orthographic projection of B" or "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0053] In an exemplary embodiment, the fabrication process of the flat panel detector in this embodiment may include the following operations.

[0054] (101) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: depositing a first conductive thin film on a substrate 10, and patterning the first conductive thin film using a patterning process to form a first conductive layer pattern disposed on the substrate 10, such as... Figure 3A and Figure 3B As shown, Figure 3B for Figure 3A Sectional view along the AA direction.

[0055] In an exemplary embodiment, the first conductive layer pattern of each sub-pixel in the flat panel detector may include at least a scan signal line 1 and a gate electrode 21.

[0056] In an exemplary embodiment, the shape of the scan signal line 1 can be a straight line or a broken line extending along the first direction X, and can be continuously set in a pixel row.

[0057] In an exemplary embodiment, the gate electrode 21 may be block-shaped (such as rectangular), and may be disposed on the side opposite to the second direction Y of the scan signal line 1, and connected to the scan signal line 1.

[0058] In an exemplary embodiment, in at least one sub-pixel, the scan signal line 1 and the gate electrode 21 can be an integral structure that is interconnected.

[0059] In an exemplary embodiment, the material of the first conductive layer can be a metallic material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy of the above metals, such as aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), or molybdenum-titanium alloy (MoTi). It can be a single-layer structure or a multi-layer composite structure, such as MoNb / Cu, MoTi / Cu, MoNb / Cu / MoTi, etc. In an exemplary embodiment, the first conductive layer can be referred to as a gate metal layer.

[0060] (102) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a first insulating layer and a first semiconductor thin film on a substrate on which the aforementioned pattern is formed; patterning the first semiconductor thin film using a patterning process to form a first insulating layer 11 covering the first conductive layer pattern; and a first semiconductor layer pattern disposed on the first insulating layer 11, such as... Figure 4A and Figure 4B As shown, Figure 4B for Figure 4A Sectional view along the AA direction.

[0061] In an exemplary embodiment, the first semiconductor layer pattern of each sub-pixel in the flat panel detector may include at least an active portion 22.

[0062] In an exemplary embodiment, the active portion 22 may be block-shaped (such as rectangular), and may be disposed on the side opposite to the second direction Y of the scanning signal line 1. The orthogonal projection of the active portion 22 on the substrate and the orthogonal projection of the gate electrode 21 on the substrate at least partially overlap.

[0063] In an exemplary embodiment, the active part 21 may be made of an oxide, which may be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper oxysulfide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN).

[0064] In an exemplary embodiment, the material of the first insulating layer 11 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer. The first insulating layer may be referred to as a gate insulating layer.

[0065] (103) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: depositing a second conductive film on a substrate on which the aforementioned pattern is formed, and patterning the second conductive film using a patterning process to form a second conductive layer pattern disposed on the first semiconductor layer and the first insulating layer, such as... Figure 5A and Figure 5B As shown, Figure 5B for Figure 5A Sectional view along the AA direction.

[0066] In an exemplary embodiment, the second conductive layer pattern of each sub-pixel in the flat panel detector may include at least a data signal line 2, a first electrode 23, and a second electrode 24.

[0067] In an exemplary embodiment, the shape of the data signal line 2 can be a straight line or a broken line extending along the second direction Y, and can be continuously set in a pixel column.

[0068] In an exemplary embodiment, the first electrode 23 may be shaped like a broken line and may be disposed on the side of the data signal line 2 close to the active part 22. The orthographic projection of the first end of the first electrode 23 on the substrate at least partially overlaps with the orthographic projection of the active part 22 on the substrate and is in contact with the active part 22. The second end of the first electrode 23 may be connected to the data signal line 2.

[0069] In an exemplary embodiment, in at least one sub-pixel, the data signal line 2 and the first electrode 23 can be an integral structure that is interconnected.

[0070] In an exemplary embodiment, the second electrode 24 may be zigzag-shaped and may be disposed on the side of the first electrode 23 away from the data signal line 2. The orthographic projection of the first end of the second electrode 24 on the substrate at least partially overlaps with the orthographic projection of the active portion 22 on the substrate and is in contact with the active portion 22. The second end of the second electrode 24 may extend in a direction away from the data signal line 2. The second electrode 24 is configured to be connected to the subsequently formed bottom electrode.

[0071] In an exemplary embodiment, the active portion 22 between the first electrode 23 and the second electrode 24 forms the channel region of the transistor, and the gate electrode 21, the active portion 22, the first electrode 23 and the second electrode 24 constitute the transistor.

[0072] In an exemplary embodiment, the first electrode 23 may be referred to as the source electrode and the second electrode 24 may be referred to as the drain electrode, or the first electrode 23 may be referred to as the drain electrode and the second electrode 24 may be referred to as the source electrode. This disclosure does not limit the specific electrode.

[0073] In an exemplary embodiment, the material of the second conductive layer can be any one or more of the following metallic materials: silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). It can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. In an exemplary embodiment, the second conductive layer can be referred to as the source / drain metal layer.

[0074] (104) Forming a second insulating layer pattern. In an exemplary embodiment, forming a second insulating layer pattern may include: depositing a second insulating film on a substrate on which the aforementioned pattern is formed, and patterning the second insulating film using a patterning process to form a second insulating layer 12 pattern covering the second conductive layer. The second insulating layer 12 has a plurality of vias, such as... Figure 6A and Figure 6B As shown, Figure 6B for Figure 6A Sectional view along the AA direction.

[0075] In an exemplary embodiment, the plurality of vias for each sub-pixel in the flat panel detector may include at least a first via K1.

[0076] In an exemplary embodiment, the orthographic projection of the first via K1 on the substrate may be within the range of the orthographic projection of the second electrode 24 on the substrate. The second insulating layer 12 inside the first via K1 is removed, exposing a portion of the surface of the second electrode 24. The first via K1 is configured to allow the subsequent formation of a bottom electrode to be connected to the second electrode 24 through the via.

[0077] In an exemplary embodiment, the material of the second insulating layer 12 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer.

[0078] (105) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: depositing a third conductive film on a substrate on which the aforementioned pattern is formed, and patterning the third conductive film using a patterning process to form a third conductive layer pattern disposed on the second insulating layer 12, such as... Figure 7A and Figure 7B As shown, Figure 7B for Figure 7A Sectional view along the AA direction.

[0079] In an exemplary embodiment, the third conductive layer pattern of each sub-pixel in the flat panel detector may include at least a bottom electrode 31.

[0080] In an exemplary embodiment, the bottom electrode 31 may be block-shaped (e.g., rectangular) and may be disposed within the area defined by the scan signal line 1 and the data signal line 2, and a first notch may be provided at the corner near the transistor, the first notch being configured to avoid the transistor.

[0081] In an exemplary embodiment, the orthographic projection of the bottom electrode 31 on the substrate and the orthographic projection of the second electrode 24 on the substrate at least partially overlap, and the bottom electrode 31 can be connected to the second electrode 24 through the first via K1.

[0082] In an exemplary embodiment, the bottom electrode 31 can be made of a single-layer transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or it can be made of a multi-layer composite structure, such as a metal stack like Mo / Al / Mo or Ti / Al / Ti.

[0083] (106) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: depositing a second semiconductor thin film on a substrate on which the aforementioned pattern is formed, and patterning the second semiconductor thin film using a patterning process to form a second semiconductor layer pattern disposed on a third conductive layer, such as... Figure 8A and Figure 8B As shown, Figure 8B for Figure 8A Sectional view along the AA direction.

[0084] In an exemplary embodiment, the second semiconductor layer pattern of each sub-pixel in the flat panel detector may include at least a photoelectric conversion layer 32.

[0085] In an exemplary embodiment, the photoelectric conversion layer 32 can be block-shaped (such as rectangular) and can be disposed in the area defined by the scan signal line 1 and the data signal line 2. Two second notches are provided near the corner of the transistor. One second notch is configured to avoid the transistor, and the other second notch is configured to avoid the first via K1.

[0086] In an exemplary embodiment, the photoelectric conversion layer 32 is directly connected to the bottom electrode 31.

[0087] In an exemplary embodiment, the area of ​​the photoelectric conversion layer 32 in a plane parallel to the substrate can be smaller than the area of ​​the bottom electrode 31, and the orthogonal projection of the photoelectric conversion layer 32 on the substrate can be within the range of the orthogonal projection of the bottom electrode 31 on the substrate.

[0088] In an exemplary embodiment, the cross-sectional shape of the photoelectric conversion layer 32 in the direction perpendicular to the substrate can be trapezoidal. The photoelectric conversion layer 32 may include a first surface 32-1 away from the substrate, a second surface 32-2 close to the substrate, and a side surface 32-3 located between the first surface 32-1 and the second surface 32-2, wherein the second surface 32-2 directly overlaps with the bottom electrode 31.

[0089] In an exemplary embodiment, the side surface 32-3 and the second surface 32-2 may have a first included angle θ1, which may be 75° to 85°.

[0090] In an exemplary embodiment, the material of the second semiconductor layer may be amorphous silicon.

[0091] (107) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a fourth conductive layer pattern may include: depositing a fourth conductive thin film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive thin film using a patterning process to form a fourth conductive layer pattern disposed on the second semiconductor layer, such as... Figure 9A and Figure 9B As shown, Figure 9B for Figure 9A Sectional view along the AA direction.

[0092] In an exemplary embodiment, the fourth conductive layer pattern of each sub-pixel in the flat panel detector may include at least a top electrode 33.

[0093] In an exemplary embodiment, the top electrode 33 can be block-shaped (such as rectangular) and can be set in the area defined by the scan signal line 1 and the data signal line 2. Two third notches are provided near the corner of the transistor. One third notch is configured to avoid the transistor, and the other third notch is configured to avoid the first via K1.

[0094] In an exemplary embodiment, the shape of the top electrode 33 may be substantially similar to the shape of the photoelectric conversion layer 32.

[0095] In an exemplary embodiment, the top electrode 33 is directly connected to the first surface 32-1 of the photoelectric conversion layer 32.

[0096] In an exemplary embodiment, in a plane parallel to the substrate, the area of ​​the top electrode 33 can be smaller than the area of ​​the first surface 32-1 of the photoelectric conversion layer 32, and the orthographic projection of the top electrode 33 onto the substrate can be within the range of the orthographic projection of the first surface 32-1 of the photoelectric conversion layer 32 onto the substrate, so that the orthographic projection of the top electrode 33 onto the substrate and the orthographic projection of the side surface 32-3 of the photoelectric conversion layer 32 onto the substrate do not overlap. Through this design, this disclosure avoids metal residue on the side surface of the photoelectric conversion layer 32 during the fabrication of the top electrode 33, thus avoiding problems such as uneven bright-state images and reduced dynamic range caused by excessive leakage current in the photodiode.

[0097] In an exemplary embodiment, the first surface 32-1 of the photoelectric conversion layer 32 may include at least a first region A1 and a second region A2. The orthographic projection of the first region A1 on the substrate and the orthographic projection of the top electrode 33 on the substrate may at least partially overlap, while the orthographic projection of the second region A2 on the substrate and the orthographic projection of the top electrode 33 on the substrate may not overlap.

[0098] In an exemplary embodiment, the top electrode 33 may be made of a single-layer transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO); or a multi-layer composite structure, such as Ag / ITO, Ag / IZO, or ITO / Ag / ITO.

[0099] (108) Forming a third insulating layer pattern. In an exemplary embodiment, forming a third insulating layer pattern may include: depositing a third insulating film on a substrate on which the aforementioned pattern is formed, patterning the third insulating film using a patterning process to form a third insulating layer 13 covering the aforementioned pattern, wherein the third insulating layer 13 is provided with a plurality of vias, such as... Figure 10A and Figure 10B As shown, Figure 10B for Figure 10A Sectional view along the AA direction.

[0100] In an exemplary embodiment, the plurality of vias in each sub-pixel of the flat panel detector may include at least a second via K2.

[0101] In an exemplary embodiment, the orthographic projection of the second via K2 onto the substrate may be within the range of the orthographic projection of the top electrode 33 onto the substrate. The third insulating layer 13 within the second via K2 is removed, exposing a portion of the surface of the top electrode 33. The second via K2 is configured to allow a subsequent forming control electrode to be connected to the top electrode 33 through the via.

[0102] In an exemplary embodiment, the shape of the second via K2 may be substantially similar to the shape of the top electrode 33.

[0103] In an exemplary embodiment, in a plane parallel to the substrate, the area of ​​the second via K2 can be smaller than the area of ​​the top electrode 33. The third insulating layer 13 surrounding the second via K2 encloses the edge of the top electrode 33, the second region of the first surface 32-1 in the photoelectric conversion layer 32, and the side surface 32-3 of the photoelectric conversion layer 32. This design ensures that the photoelectric conversion layer 32 can be completely covered by the top electrode 33 and the third insulating layer 13, thereby preventing the photoelectric conversion layer from being etched during the etching of the insulating layer vias, thus avoiding any impact on the characteristics of the photoelectric conversion layer.

[0104] In an exemplary embodiment, the material of the third insulating layer 13 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer.

[0105] (109) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer pattern disposed on the third insulating layer 13, such as... Figure 11A and Figure 11B As shown, Figure 11B for Figure 11A Sectional view along the AA direction.

[0106] In an exemplary embodiment, the fifth conductive layer pattern of each sub-pixel in the flat panel detector may include at least a control electrode 41.

[0107] In an exemplary embodiment, the control electrode 41 can be block-shaped (e.g., rectangular) and can be disposed within the area defined by the scan signal line 1 and the data signal line 2. Two fourth notches are provided near the corner of the transistor; one fourth notch is configured to avoid the transistor, and the other fourth notch is configured to avoid the first via K1. The control electrode 41 can be connected to the top electrode 33 through the second via K2.

[0108] In an exemplary embodiment, the shape of the control electrode 41 may be substantially similar to the shape of the photoelectric conversion layer 32.

[0109] In an exemplary embodiment, the area of ​​the control electrode 41 may be smaller than the area of ​​the bottom electrode 31 in a plane parallel to the substrate, and the orthogonal projection of the control electrode 41 on the substrate may be within the range of the orthogonal projection of the bottom electrode 31 on the substrate.

[0110] In an exemplary embodiment, the area of ​​the control electrode 41 in a plane parallel to the substrate can be larger than the area of ​​the photoelectric conversion layer 32 and the top electrode 33, and the orthogonal projection of the control electrode 41 on the substrate can include the orthogonal projections of the photoelectric conversion layer 32 and the top electrode 33 on the substrate.

[0111] In an exemplary embodiment, the orthographic projection of the control electrode 41 onto the substrate may include the orthographic projection of the side surface of the photoelectric conversion layer 32 onto the substrate.

[0112] In an exemplary embodiment, the orthographic projection of the control electrode 41 onto the substrate may include the orthographic projection of the second region A2 of the first surface 32-1 in the photoelectric conversion layer 32 onto the substrate.

[0113] In an exemplary embodiment, the orthogonal projection of the control electrode 41 onto the substrate may include the orthogonal projection of the photoelectric conversion layer 32 onto the substrate.

[0114] In an exemplary embodiment, since a third insulating layer is provided between the control electrode 41 and the side surface of the photoelectric conversion layer 32, the control electrode 41 does not directly contact the side surface of the photoelectric conversion layer 32.

[0115] In an exemplary embodiment, the material of the control electrode 41 may be a single-layer transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO); or a multi-layer composite structure, such as Ag / ITO, Ag / IZO, or ITO / Ag / ITO.

[0116] (110) Forming patterns for the fourth and fifth insulating layers. In an exemplary embodiment, forming the fourth and fifth insulating layers may include: sequentially coating a fourth insulating film and depositing a fifth insulating film on a substrate on which the aforementioned patterns are formed; patterning the fourth and fifth insulating films using a patterning process to form a pattern for the fourth insulating layer 14 covering the fifth conductive layer and a pattern for the fifth insulating layer 15 disposed on the fourth insulating layer 14; the fourth insulating layer 14 and the fifth insulating layer 15 are provided with a plurality of vias, such as... Figure 12A and Figure 12B As shown, Figure 12B for Figure 12A Sectional view along the AA direction.

[0117] In an exemplary embodiment, the plurality of vias for each sub-pixel in the flat panel detector may include at least a third via K3.

[0118] In an exemplary embodiment, the orthographic projection of the third via K3 on the substrate may be within the range of the orthographic projection of the control electrode 41 on the substrate. The fourth insulating layer 14 and the fifth insulating layer 15 in the third via K3 are removed, exposing part of the surface of the control electrode 41. The third via K3 is configured to allow a subsequently formed bias electrode to be connected to the control electrode 41 through the via.

[0119] In an exemplary embodiment, the orthographic projection of the third via K3 on the substrate at least partially overlaps with the orthographic projection of the top electrode 31 on the substrate.

[0120] In an exemplary embodiment, the orthogonal projection of the third via K3 on the substrate can be located within the range of the orthogonal projections of the bottom electrode 31, the photoelectric conversion layer 32, and the top electrode 33 on the substrate.

[0121] In an exemplary embodiment, the material of the fourth insulating layer 14 may be an organic material, such as polyimide, acrylic or polyethylene terephthalate, and the fourth insulating layer may be referred to as a planarization layer.

[0122] In an exemplary embodiment, the material of the fifth insulating layer 15 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or a composite layer. The fifth insulating layer 15 may be referred to as a passivation layer.

[0123] (111) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming a sixth conductive layer pattern may include: depositing a sixth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the sixth conductive film using a patterning process to form a sixth conductive layer pattern disposed on the fifth insulating layer 15, such as... Figure 13A and 13B As shown, Figure 13B for Figure 13A Sectional view along the AA direction.

[0124] In an exemplary embodiment, the sixth conductive layer pattern of each sub-pixel in the flat panel detector may include at least a bias line 5 and a bias electrode 51.

[0125] In an exemplary embodiment, the shape of the bias line 5 can be a straight line or a broken line extending along the second direction Y, and can be continuously set in a pixel column.

[0126] In an exemplary embodiment, the bias electrode 51 can be block-shaped (such as rectangular), and can be disposed on the side of the bias line 5 away from the data signal line 2 and connected to the bias line 5. The bias electrode 51 can be connected to the control electrode 41 through the third via K3.

[0127] In an exemplary embodiment, in at least one sub-pixel, the bias line 5 and the bias electrode 51 can be an integral structure that is interconnected.

[0128] In an exemplary embodiment, at least one sub-pixel may further include an occlusion block 52. The occlusion block 52 may be block-shaped (e.g., rectangular), and may be disposed on the side of the bias line 5 near the data signal line 2 and connected to the bias line 5.

[0129] In an exemplary embodiment, the orthographic projection of the shielding block 52 onto the substrate may include the orthographic projection of the channel region of the transistor onto the substrate, thereby effectively preventing excessive leakage current caused by light irradiating the transistor.

[0130] In an exemplary embodiment, the orthographic projection of the shielding block 52 onto the substrate may include the orthographic projections of the gate electrode 21 and the active portion 22 onto the substrate.

[0131] In an exemplary embodiment, in at least one sub-pixel, the bias line 5, the bias electrode 51, and the blocking block 52 can be an integral structure that is interconnected.

[0132] In an exemplary embodiment, the material of the sixth conductive layer can be any one or more of the following metallic materials: silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals: aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), or molybdenum-titanium alloy (MoTi). It can be a single-layer structure or a multi-layer composite structure, such as MoNb / Cu, MoTi / Cu, MoNb / Cu / MoTi, etc.

[0133] (112) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming a sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed to form a sixth insulating layer 16 covering the sixth conductive layer, such as... Figure 2A and 2B As shown.

[0134] Existing flat panel detectors suffer from problems such as image retention. The inventors of this application have discovered that this problem is primarily caused by a weak electric field in the edge region of the photoelectric conversion layer. To avoid excessive leakage current due to metal residue on the side surface of the photoelectric conversion layer during top electrode formation, existing flat panel detectors design the top electrode to be smaller than the photoelectric conversion layer. Because the top electrode cannot completely cover the photoelectric conversion layer, the electric field in the edge region of the photoelectric conversion layer is weak, causing the photocharge generated in this region to be incompletely read out during reading, thus resulting in image retention.

[0135] An exemplary embodiment of this disclosure provides a flat panel detector. By setting a control electrode connected to the top electrode, the orthogonal projection of the control electrode on the substrate can include the orthogonal projection of the side surface and edge region of the photoelectric conversion layer on the substrate. This effectively improves the electric field intensity of the side surface and edge region of the photoelectric conversion layer, so that the photocharge generated in the photoelectric conversion layer can be completely read out, reducing the residual photocharge in the photoelectric conversion layer, and effectively solving the problems of image retention in existing flat panel detectors.

[0136] Figure 14A This is a schematic diagram of the structure of another flat panel detector, which is an exemplary embodiment of this disclosure. Figure 14B for Figure 14A A sectional view along the BB direction. (e.g.) Figure 14A and Figure 14B As shown, the main structure of the flat panel detector in this embodiment is similar to... Figure 2A and Figure 2B The embodiments shown can be substantially the same, except that the bias line in this embodiment includes a first bias sub-line and a second bias sub-line, and the bias electrode includes a first sub-electrode and a second sub-electrode.

[0137] In an exemplary embodiment, the fifth conductive layer may include at least a control electrode 41 and a connecting block 42, and the control electrode 41 and the connecting block 42 may be an integral structure that is interconnected.

[0138] In an exemplary embodiment, the sixth conductive layer may include at least a bias line and a bias electrode. The bias line may include at least a first bias sub-line 5-1 and a second bias sub-line 5-2. The bias electrode may include at least a first sub-electrode 51-1 and a second sub-electrode 51-2. The first sub-electrode 51-1 is connected to the first bias sub-line 5-1, and the second sub-electrode 51-2 is connected to the second bias sub-line 5-2.

[0139] In an exemplary embodiment, the first sub-electrode 51-1 can be connected to the connecting block 42 through the fourth via, and the second sub-electrode 51-2 can be connected to the control electrode 41 through the fifth via.

[0140] In an exemplary embodiment, the orthographic projection of the first sub-electrode 51-1 on the substrate does not overlap with the orthographic projection of the photoelectric conversion layer 32 on the substrate, and the orthographic projection of the second sub-electrode 51-2 on the substrate at least partially overlaps with the orthographic projection of the photoelectric conversion layer 32 on the substrate. The first sub-electrode 51-1 may be disposed on the side of the photoelectric conversion layer 32 away from the second sub-electrode 51-2, and the second sub-electrode 51-2 may be disposed at the edge position of the side of the photoelectric conversion layer 32 away from the first sub-electrode 51-1.

[0141] In an exemplary embodiment, the first bias sub-line 5-1 may be disposed on the side of the first sub-electrode 51-1 away from the second sub-electrode 51-2, and the second bias sub-line 5-2 may be disposed on the side of the second sub-electrode 51-2 away from the first sub-electrode 51-1.

[0142] In an exemplary embodiment, a fourth via and a fifth via may be provided on the fourth insulating layer 14 and the fifth insulating layer 15. The orthographic projection of the fourth via K4 on the substrate does not overlap with the orthographic projection of the photoelectric conversion layer 32 on the substrate. The orthographic projection of the fifth via K5 on the substrate at least partially overlaps with the orthographic projection of the top electrode 31 on the substrate. The first sub-electrode 51-1 of the bias electrode 51 can be connected to the connecting block 42 through the fourth via, and the second sub-electrode 51-2 of the bias electrode 51 can be connected to the control electrode 41 through the fifth via.

[0143] In an exemplary embodiment, the fabrication process of the flat panel detector in this embodiment may include the following operations.

[0144] (201)-(208) sequentially form a first conductive layer, a first insulating layer, a first semiconductor layer, a second conductive layer, a second insulating layer, a third conductive layer, a second semiconductor layer, a fourth conductive layer, and a third insulating layer. The formation process and the resulting structure are similar to those described above. Figure 2A and Figure 2B The embodiments shown can be substantially the same.

[0145] (209) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming a fifth conductive layer pattern may include: depositing a fifth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process, and forming a fifth conductive layer pattern disposed on the third insulating layer 13, such as... Figure 15A and Figure 15B As shown, Figure 15B for Figure 15A Sectional view along the BB direction.

[0146] In an exemplary embodiment, the fifth conductive layer pattern of each sub-pixel in the flat panel detector may include at least a control electrode 41 and a connection block 42.

[0147] In an exemplary embodiment, the structure and material of the control electrode 41 are similar to those of the control electrode 41. Figure 2A and Figure 2B The embodiments shown can be substantially the same, and will not be described in detail here.

[0148] In an exemplary embodiment, the connecting block 42 can be block-shaped (such as rectangular), and can be disposed at the fourth notch near the first through hole K1 of the control electrode 41 and connected to the control electrode 41.

[0149] In an exemplary embodiment, the orthographic projection of the connecting block 42 on the substrate and the orthographic projection of the photoelectric conversion layer 32 on the substrate may not overlap, and the orthographic projection of the connecting block 42 on the substrate may include the orthographic projection of the first via K1 on the substrate.

[0150] In an exemplary embodiment, the control electrode 41 and the connecting block 42 can be an integral structure that is interconnected.

[0151] (210) Forming patterns for the fourth and fifth insulating layers. In an exemplary embodiment, forming the fourth and fifth insulating layers may include: sequentially coating a fourth insulating film and depositing a fifth insulating film on a substrate on which the aforementioned patterns are formed; patterning the fourth and fifth insulating films using a patterning process to form a pattern for the fourth insulating layer 14 covering the fifth conductive layer and a pattern for the fifth insulating layer 15 disposed on the fourth insulating layer 14; the fourth insulating layer 14 and the fifth insulating layer 15 are provided with a plurality of vias, such as... Figure 16A and Figure 16B As shown, Figure 16B for Figure 16A Sectional view along the BB direction.

[0152] In an exemplary embodiment, the plurality of vias may include at least a fourth via K4 and a fifth via K5.

[0153] In an exemplary embodiment, the orthographic projection of the fourth via K4 on the substrate may be within the range of the orthographic projection of the connecting block 42 on the substrate. The fifth insulating layer 15 and the fourth insulating layer 14 within the fourth via K4 are removed, exposing a portion of the surface of the connecting block 42. The fourth via K4 is configured to allow the subsequent formation of the first sub-electrode to be connected to the connecting block 42 through the via.

[0154] In an exemplary embodiment, the orthographic projection of the fourth via K4 on the substrate does not overlap with the orthographic projection of the photoelectric conversion layer 32 on the substrate.

[0155] In an exemplary embodiment, the orthographic projection of the fourth via K4 onto the substrate at least partially overlaps with the orthographic projection of the first via K1 onto the substrate. In some possible embodiments, the orthographic projection of the fourth via K4 onto the substrate may include the orthographic projection of the first via K1 onto the substrate.

[0156] In an exemplary embodiment, the orthographic projection of the fifth via K5 on the substrate is within the range of the orthographic projection of the control electrode 41 on the substrate. The fifth insulating layer 15 and the fourth insulating layer 14 within the fifth via K5 are removed, exposing a portion of the surface of the control electrode 41. The fifth via K5 is configured to allow the subsequent formation of a second sub-electrode to be connected to the control electrode 41 through the via.

[0157] In an exemplary embodiment, in the first direction X, the fourth via K4 and the fifth via K5 can be substantially the same distance from the data signal line 2, that is, the fourth via K4 and the fifth via K5 can be on a straight line extending along the second direction Y. In the second direction Y, the fifth via K5 can be located at the edge position of the top electrode 31 on the side away from the fourth via K4, and the orthographic projection of the fifth via K5 on the substrate at least partially overlaps with the orthographic projection of the top electrode 31 on the substrate.

[0158] (211) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming a sixth conductive layer pattern may include: depositing a sixth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the sixth conductive film using a patterning process to form a sixth conductive layer pattern disposed on the fifth insulating layer 15, such as... Figure 17A and Figure 17B As shown, Figure 17B for Figure 17A Sectional view along the BB direction.

[0159] In an exemplary embodiment, the sixth conductive layer pattern of each sub-pixel in the flat panel detector may include at least a bias line and a bias electrode. The bias line may include at least a first bias sub-line 5-1 and a second bias sub-line 5-2, and the bias electrode may include at least a first sub-electrode 51-1 and a second sub-electrode 51-2 that are isolated from each other.

[0160] In an exemplary embodiment, the first sub-electrode 51-1 can be block-shaped (e.g., rectangular). In the second direction Y, the first sub-electrode 51-1 can be disposed on the side of the photoelectric conversion layer 32 near the scan signal line. In the first direction X, the first sub-electrode 51-1 can be disposed on the side of the first bias sub-line 5-1 away from the data signal line 2, and the first sub-electrode 51-1 is connected to the first bias sub-line 5-1. The first sub-electrode 51-1 can be connected to the connecting block 42 through the fourth via K4.

[0161] In an exemplary embodiment, the orthographic projection of the first sub-electrode 51-1 on the substrate does not overlap with the orthographic projection of the photoelectric conversion layer 32 on the substrate.

[0162] In an exemplary embodiment, in at least one sub-pixel, the first bias sub-line 5-1 and the first sub-electrode 51-1 can be an integral structure that is interconnected.

[0163] In an exemplary embodiment, the second sub-electrode 51-2 can be block-shaped (e.g., rectangular). In the second direction Y, the second sub-electrode 51-2 can be disposed on the side of the sub-pixel away from the scan signal line. In the first direction X, the second sub-electrode 51-2 can be disposed on the side of the second bias sub-line 5-2 away from the data signal line 2, and the second sub-electrode 51-2 is connected to the second bias sub-line 5-2. The second sub-electrode 51-2 can be connected to the control electrode 41 through the fifth via K5.

[0164] In an exemplary embodiment, the orthographic projection of the second sub-electrode 51-2 onto the substrate at least partially overlaps with the orthographic projection of the photoelectric conversion layer 32 onto the substrate. In some possible embodiments, the orthographic projection of the second sub-electrode 51-2 onto the substrate may be located within the range of the orthographic projection of the photoelectric conversion layer 32 onto the substrate.

[0165] In an exemplary embodiment, in at least one sub-pixel, the second bias sub-line 5-2 and the second sub-electrode 51-2 can be an integral structure that is interconnected.

[0166] In an exemplary embodiment, the shape of the first bias sub-line 5-1 can be a straight line or a broken line extending along the second direction Y. It can be disposed on the side of the photoelectric conversion layer 32 near the scanning signal line 1. The first end of the first bias sub-line 5-1 is connected to the first sub-electrode 51-1, and the second end of the first bias sub-line 5-1 extends in the direction of the next pixel row and is configured to be connected to the second bias sub-line 5-2 of the next pixel row.

[0167] In an exemplary embodiment, the shape of the second bias sub-line 5-2 can be a straight line or a broken line extending along the second direction Y. It can be located on the side of the sub-pixel away from the scanning signal line 1. The first end of the second bias sub-line 5-2 is connected to the second sub-electrode 51-2, and the second end of the second bias sub-line 5-2 extends in the direction of the previous pixel row and is configured to be connected to the first bias sub-line 5-1 of the previous pixel row.

[0168] In an exemplary embodiment, the first sub-electrode 51-1 can be disposed on the side of the photoelectric conversion layer 32 away from the second sub-electrode 51-2, and the second sub-electrode 51-2 can be disposed at the edge of the photoelectric conversion layer 32 away from the first sub-electrode 51-1. The first bias sub-line 5-1 can be disposed on the side of the first sub-electrode 51-1 away from the second sub-electrode 51-2, and the second bias sub-line 5-2 can be disposed on the side of the second sub-electrode 51-2 away from the first sub-electrode 51-1. It can be seen that the first bias sub-line 5-1 and the first sub-electrode 51-1 are disconnected from the second bias sub-line 5-2 and the second sub-electrode 51-2 above the photoelectric conversion layer 32, thus reducing the shading of the photoelectric conversion layer by the bias lines.

[0169] In an exemplary embodiment, since the first bias sub-line 5-1 is connected to the first sub-electrode 51-1, the first sub-electrode 51-1 is connected to the connecting block 42, the second bias sub-line 5-2 is connected to the second sub-electrode 51-2, the second sub-electrode 51-2 is connected to the control electrode 41, and the control electrode 41 and the connecting block 42 are an integral structure that is interconnected, the connection between the first bias sub-line 5-1 and the second bias sub-line 5-2 is realized.

[0170] In an exemplary embodiment, at least one sub-pixel may further include an occlusion block 52, the structure of which is similar to... Figure 2A and Figure 2B The embodiments shown can be substantially the same, and will not be described in detail here.

[0171] (212) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming a sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed to form a sixth insulating layer 16 covering the sixth conductive layer, such as... Figure 14A and Figure 14B As shown.

[0172] The display substrate provided in this embodiment has Figure 2A and Figure 2B The illustrated embodiment achieves the same technical effect. Furthermore, this embodiment of the present disclosure, by setting two bias electrodes—a first sub-electrode and a second sub-electrode—splits the bias line into a first bias sub-line and a second bias sub-line, thereby reducing the obstruction of the photoelectric conversion layer by the bias line and thus improving the photoelectric conversion efficiency and signal-to-noise ratio.

[0173] Figure 18A This is a schematic diagram of the structure of another flat panel detector, which is an exemplary embodiment of the present disclosure. Figure 18B for Figure 18A A sectional view along the CC direction. (e.g.) Figure 18A and Figure 18B As shown, the main structure of the flat panel detector in this embodiment is similar to... Figure 2A and Figure 2B The embodiments shown can be substantially the same, except that the control electrode in this embodiment is ring-shaped.

[0174] In an exemplary embodiment, the fifth conductive layer may include at least a control electrode 41. The control electrode 41 may include a main body portion 41-1 and an overlapping portion 41-2. The main body portion 41-1 may be ring-shaped, and the overlapping portion 41-2 may be block-shaped. The overlapping portion 41-2 may be disposed inside the ring of the main body portion 41-1. One end of the overlapping portion 41-2 may be connected to the main body portion 41-1, and the other end of the overlapping portion 41-2 may be connected to the bias electrode 51.

[0175] In an exemplary embodiment, the orthographic projection of the main body 41-1 onto the substrate may include at least the orthographic projection of the side surface of the photoelectric conversion layer 32 onto the substrate.

[0176] In an exemplary embodiment, a sixth via may be provided on the third insulating layer 13, the fourth insulating layer 14 and the fifth insulating layer 15. The sixth via may include a first part and a second part. The first part exposes a portion of the surface of the top electrode 33, and the second part exposes a portion of the surface of the overlap portion 41-2 of the control electrode 41. The bias electrode 51 can be connected to both the control electrode 51 and the top electrode 33 through the sixth via.

[0177] In an exemplary embodiment, the fabrication process of the flat panel detector in this embodiment may include the following operations.

[0178] (301)-(307) sequentially form a first conductive layer, a first insulating layer, a first semiconductor layer, a second conductive layer, a second insulating layer, a third conductive layer, a second semiconductor layer, and a fourth conductive layer. The formation process and the resulting structure are similar to those described above. Figure 2A and Figure 2B The embodiments shown can be substantially the same.

[0179] (308) Forming a pattern for the third insulating layer and the fifth conductive layer. In an exemplary embodiment, forming the pattern for the third insulating layer and the fifth conductive layer may include: sequentially depositing a third insulating film and a fifth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process to form a third insulating layer 13 covering the aforementioned pattern, and a fifth conductive layer pattern disposed on the third insulating layer 13, such as... Figure 19A and Figure 19B As shown, Figure 19B for Figure 19A A cross-sectional view along the CC direction.

[0180] In an exemplary embodiment, the fifth conductive layer pattern of each sub-pixel in the flat panel detector may include at least a control electrode 41.

[0181] In an exemplary embodiment, the orthographic projection of the control electrode 41 on the substrate may include at least the orthographic projection of the second region A2 in the side surface 32-3 and the first surface 32-1 of the photoelectric conversion layer 32 on the substrate, and the orthographic projection of the control electrode 41 on the substrate at least partially overlaps with the orthographic projection of the top electrode 33 on the substrate.

[0182] In an exemplary embodiment, the control electrode 41 may include a main body portion 41-1 and an overlapping portion 41-2. The main body portion 41-1 may be annular (such as a rectangular ring) in shape and may be disposed within the area defined by the scan signal line 1 and the data signal line 2. Two fourth notches are provided near the corner of the transistor, one fourth notch being configured to avoid the transistor and the other fourth notch being configured to avoid the first via K1.

[0183] In an exemplary embodiment, the ring-shaped main body 41-1 may include an inner edge 41-1-1 and an outer edge 41-1-2, the outline shapes of which may be substantially similar.

[0184] In an exemplary embodiment, the area enclosed by the inner edge 41-1-1 can be smaller than the area of ​​the top electrode 33, and the orthographic projection of the inner edge 41-1-1 on the substrate can be within the range of the orthographic projection of the top electrode 33 on the substrate, so that the annular main body 41-1 can cover the edge of the top electrode 33.

[0185] In an exemplary embodiment, the area enclosed by the outer edge 41-1-2 can be larger than the area of ​​the photoelectric conversion layer 32. The orthographic projection of the area enclosed by the outer edge 41-1-2 onto the substrate can include the orthographic projection of the photoelectric conversion layer 32 onto the substrate, such that the annular main body 41-1 can at least include the side surface 32-3 of the photoelectric conversion layer 32 and the second region A2 in the first surface 32-1.

[0186] In an exemplary embodiment, the orthographic projection of the main body 41-1 on the substrate may include at least the orthographic projection of the side surface 32-3 of the photoelectric conversion layer 32 and the second region A2 in the first surface 32-1 on the substrate, and the orthographic projection of the main body 41-1 on the substrate at least partially overlaps with the orthographic projection of the top electrode 33 on the substrate.

[0187] In an exemplary embodiment, the overlapping portion 41-2 can be block-shaped (such as rectangular). The overlapping portion 41-2 can be disposed on the side of the inner edge 41-1-1 of the main body portion 41-1 away from the outer edge 41-1-2. The first end of the overlapping portion 41-2 can be connected to the inner edge 41-1-1 of the main body portion 41-1, and the second end of the overlapping portion 41-2 extends in a direction away from the outer edge 41-1-2 and is configured to be connected to the bias electrode formed subsequently.

[0188] In an exemplary embodiment, the orthographic projection of the overlapping portion 41-2 on the substrate may be within the range of the orthographic projection of the top electrode 33 on the substrate.

[0189] (309) Forming patterns for the fourth and fifth insulating layers. In an exemplary embodiment, forming the fourth and fifth insulating layers may include: sequentially coating a fourth insulating film and depositing a fifth insulating film on a substrate on which the aforementioned patterns are formed; patterning the fourth and fifth insulating films using a patterning process to form a pattern for the fourth insulating layer 14 covering the fifth conductive layer and a pattern for the fifth insulating layer 15 disposed on the fourth insulating layer 14; and having multiple vias disposed on the third insulating layer 13, the fourth insulating layer 14, and the fifth insulating layer 15, such as... Figure 20A and Figure 20B As shown, Figure 20B for Figure 20A A cross-sectional view along the CC direction.

[0190] In an exemplary embodiment, the plurality of vias for each sub-pixel in the flat panel detector may include at least a sixth via K6.

[0191] In an exemplary embodiment, the orthographic projection of the sixth via K6 onto the substrate at least partially overlaps with the orthographic projection of the overlap portion 41-2 of the top electrode 33 and the control electrode 41 onto the substrate. The sixth via K6 may include a first portion K61 and a second portion K62. The fifth insulating layer 15, the fourth insulating layer 14, and the third insulating layer 13 in the first portion K61 are removed, exposing a portion of the surface of the top electrode 33. The fifth insulating layer 15 and the fourth insulating layer 14 in the second portion K62 are removed, exposing a portion of the surface of the overlap portion 41-2 of the control electrode 41. The sixth via K6 is configured to allow a subsequent bias electrode to be connected to the overlap portion 41-2 of the top electrode 33 and the control electrode 41 simultaneously through the via.

[0192] (310) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming a sixth conductive layer pattern may include: depositing a sixth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the sixth conductive film using a patterning process to form a sixth conductive layer pattern disposed on the fifth insulating layer 15, such as... Figure 21A and Figure 21B As shown, Figure 21B for Figure 21A A cross-sectional view along the CC direction.

[0193] In an exemplary embodiment, the sixth conductive layer pattern of each sub-pixel in the flat panel detector may include at least a bias line 5 and a bias electrode 51.

[0194] In an exemplary embodiment, the main structure of the bias line 5 and the bias electrode 51 is similar to... Figure 2A and Figure 2BThe embodiments shown can be substantially the same, except that the bias electrode 51 is connected to the top electrode 33 through the first part K61 of the sixth through hole K6 on the one hand, and to the overlapping part 41-2 through the second part K62 of the sixth through hole K6 on the other hand. Thus, the bias electrode 51 is connected to both the top electrode 33 and the control electrode 41 at the same time, that is, the control electrode 41 can be connected to the top electrode 33 through the bias electrode 51.

[0195] (311) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming a sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate on which the aforementioned pattern is formed to form a sixth insulating layer 16 covering the sixth conductive layer, such as... Figure 18A and Figure 18B As shown.

[0196] The display substrate provided in this embodiment has Figure 2A and Figure 2B The illustrated embodiment achieves the same technical effects. Furthermore, by arranging the control electrode in a ring shape, this disclosure reduces the shading of the photoelectric conversion layer by the control electrode, thereby improving photoelectric conversion efficiency and signal-to-noise ratio.

[0197] Figure 22A and Figure 22B This is a schematic diagram illustrating another embodiment of the present disclosure where the bias electrode is simultaneously connected to both the top electrode and the control electrode. Figure 22B for Figure 22A A sectional view along the CC direction. (e.g.) Figure 22A and Figure 22B As shown, the sixth via K6 can expose part of the surface of the top electrode 33 on one hand, and the end surface of the overlapping part away from the main body on the other hand. The bias electrode 51 can be connected to the top electrode on one hand and the end surface of the overlapping part on the other hand, thus realizing that the bias electrode is simultaneously connected to the overlapping part of the top electrode and the control electrode.

[0198] This disclosure also provides an X-ray imaging system that may include the aforementioned flat panel detector.

[0199] This disclosure also provides a method for fabricating a flat panel detector. In an exemplary embodiment, the flat panel detector includes a plurality of sub-pixels, at least one sub-pixel including a transistor and a photosensitive device; the fabrication method may include: S1. Form a bottom electrode on the substrate; S2. A photoelectric conversion layer is formed on the side of the bottom electrode away from the substrate; the photoelectric conversion layer includes at least a first surface away from the substrate, a second surface close to the substrate, and a side surface located between the first surface and the second surface, the second surface overlapping the bottom electrode; S3. A top electrode is formed on the side of the photoelectric conversion layer away from the substrate. The top electrode overlaps with the first surface, and the orthographic projection of the top electrode on the substrate is within the range of the orthographic projection of the first surface on the substrate. S4. A control electrode is formed on the side of the top electrode away from the substrate. The control electrode is connected to the top electrode. The orthographic projection of the control electrode on the substrate includes the orthographic projection of the side surface of the photoelectric conversion layer on the substrate.

[0200] This disclosure provides a method for fabricating a flat panel detector. By setting a control electrode, the orthogonal projection of the control electrode on the substrate can include the orthogonal projection of the side surface of the photoelectric conversion layer on the substrate, which effectively improves the electric field intensity of the side surface of the photoelectric conversion layer, so that the photocharge generated in the photoelectric conversion layer can be completely read out, reducing the residual photocharge in the photoelectric conversion layer, and effectively solving the problems of image retention in existing flat panel detectors.

[0201] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A flat panel detector, characterized in that, The device includes multiple sub-pixels, at least one of which includes a transistor and a photosensitive device. In a direction perpendicular to the plane of the flat panel detector, the photosensitive device includes at least a bottom electrode disposed on a substrate, a photoelectric conversion layer disposed on the side of the bottom electrode away from the substrate, a top electrode disposed on the side of the photoelectric conversion layer away from the substrate, and a control electrode disposed on the side of the top electrode away from the substrate. The photoelectric conversion layer includes at least a first surface away from the substrate, a second surface close to the substrate, and a side surface located between the first surface and the second surface. The bottom electrode overlaps with the second surface, the top electrode overlaps with the first surface, and the control electrode is connected to the top electrode. In at least one sub-pixel, the orthogonal projection of the top electrode on the substrate is located within the range of the orthogonal projection of the first surface of the photoelectric conversion layer on the substrate, and the orthogonal projection of the control electrode on the substrate includes the orthogonal projection of the side surface of the photoelectric conversion layer on the substrate.

2. The flat panel detector according to claim 1, characterized in that, The first surface includes at least a first region and a second region, wherein the orthographic projection of the first region on the substrate at least partially overlaps with the orthographic projection of the top electrode on the substrate, and the orthographic projection of the second region on the substrate does not overlap with the orthographic projection of the top electrode on the substrate, and the orthographic projection of the control electrode on the substrate includes the orthographic projection of the second region on the substrate.

3. The flat panel detector according to claim 1, characterized in that, The orthographic projection of the control electrode on the substrate at least partially overlaps with the orthographic projection of the top electrode on the substrate.

4. The flat panel detector according to any one of claims 1-3, characterized in that, The flat panel detector further includes a third insulating layer, which is disposed on the side of the top electrode away from the substrate. The control electrode is disposed on the side of the third insulating layer away from the substrate. A second via is disposed on the third insulating layer, and the control electrode is connected to the top electrode through the second via. The area of ​​the second via is smaller than the area of ​​the top electrode, and the orthographic projection of the second via on the substrate is within the range of the orthographic projection of the top electrode on the substrate.

5. The flat panel detector according to claim 4, characterized in that, The flat panel detector further includes a fourth insulating layer and a fifth insulating layer. The fourth insulating layer is disposed on the side of the control electrode away from the substrate, and the fifth insulating layer is disposed on the side of the fourth insulating layer away from the substrate. The photosensitive device further includes a bias electrode, which is disposed on the side of the fifth insulating layer away from the substrate. A third via is provided on the fourth and fifth insulating layers, and the bias electrode is connected to the control electrode through the third via. The orthographic projection of the third via on the substrate at least partially overlaps with the orthographic projection of the top electrode on the substrate.

6. The flat panel detector according to claim 4, characterized in that, The flat panel detector further includes a fourth insulating layer and a fifth insulating layer. The fourth insulating layer is disposed on the side of the control electrode away from the substrate, and the fifth insulating layer is disposed on the side of the fourth insulating layer away from the substrate. The photosensitive device further includes a connecting block and a bias electrode. The connecting block and the control electrode are an integral structure connected to each other. The bias electrode is disposed on the side of the fifth insulating layer away from the substrate. The bias electrode includes a first sub-electrode and a second sub-electrode. A fourth via and a fifth via are disposed on the fourth insulating layer and the fifth insulating layer, respectively. The first sub-electrode is connected to the connecting block through the fourth via, and the second sub-electrode is connected to the control electrode through the fifth via.

7. The flat panel detector according to claim 6, characterized in that, The orthographic projection of the fourth via on the substrate does not overlap with the orthographic projection of the photoelectric conversion layer on the substrate. The orthographic projection of the fifth via on the substrate at least partially overlaps with the orthographic projection of the top electrode on the substrate. The orthographic projection of the first sub-electrode on the substrate does not overlap with the orthographic projection of the photoelectric conversion layer on the substrate. The orthographic projection of the second sub-electrode on the substrate at least partially overlaps with the orthographic projection of the photoelectric conversion layer on the substrate.

8. The flat panel detector according to claim 7, characterized in that, The flat panel detector further includes bias lines, which include at least a first bias sub-line and a second bias sub-line. The first bias sub-line is connected to the first sub-electrode, and the second bias sub-line is connected to the second sub-electrode. The first sub-electrode is disposed on the side of the photoelectric conversion layer away from the second sub-electrode, and the second sub-electrode is disposed at the edge of the photoelectric conversion layer away from the first sub-electrode. The first bias sub-line is disposed on the side of the first sub-electrode away from the second sub-electrode, and the second bias sub-line is disposed on the side of the second sub-electrode away from the first sub-electrode.

9. The flat panel detector according to any one of claims 1-3, characterized in that, The flat panel detector further includes a third insulating layer disposed on the side of the top electrode away from the substrate, and the control electrode disposed on the side of the third insulating layer away from the substrate; the photosensitive device further includes a bias electrode disposed on the side of the control electrode away from the substrate, and the control electrode is connected to the top electrode through the bias electrode.

10. The flat panel detector according to claim 9, characterized in that, The control electrode includes a main body and an overlapping portion. The main body is ring-shaped, and the overlapping portion is block-shaped. The overlapping portion is disposed inside the ring of the main body. A first end of the overlapping portion is connected to the main body, and a second end of the overlapping portion is connected to the bias electrode. The orthographic projection of the main body on the substrate includes at least the orthographic projection of the side surface of the photoelectric conversion layer on the substrate.

11. The flat panel detector according to claim 10, characterized in that, The flat panel detector further includes a fourth insulating layer and a fifth insulating layer. The fourth insulating layer is disposed on the side of the control electrode away from the substrate, and the fifth insulating layer is disposed on the side of the fourth insulating layer away from the substrate. The bias electrode is disposed on the side of the fifth insulating layer away from the substrate. The third, fourth, and fifth insulating layers are provided with a sixth via. The bias electrode is connected to both the control electrode and the top electrode through the sixth via.

12. The flat panel detector according to claim 11, characterized in that, The sixth via includes a first part and a second part. The first part exposes a portion of the surface of the top electrode, and the second part exposes a portion of the surface of the overlap portion, so that the bias electrode is connected to both the control electrode and the top electrode through the sixth via.

13. The flat panel detector according to claim 11, characterized in that, The sixth via includes a first part and a second part. The first part exposes a portion of the surface of the top electrode, and the second part exposes the end surface of the overlapping portion away from the main body, so that the bias electrode is connected to both the control electrode and the top electrode through the sixth via.

14. An X-ray imaging system, characterized in that, Including the flat panel detector as described in any one of claims 1 to 13.

15. A method for fabricating a flat panel detector, characterized in that, The flat panel detector includes multiple sub-pixels, at least one sub-pixel including a transistor and a photosensitive device; the fabrication method includes: A bottom electrode is formed on the substrate; A photoelectric conversion layer is formed on the side of the bottom electrode away from the substrate; the photoelectric conversion layer includes at least a first surface away from the substrate, a second surface close to the substrate, and a side surface located between the first surface and the second surface, the second surface overlapping the bottom electrode; A top electrode is formed on the side of the photoelectric conversion layer away from the substrate. The top electrode overlaps with the first surface, and the orthographic projection of the top electrode on the substrate is within the range of the orthographic projection of the first surface on the substrate. A control electrode is formed on the side of the top electrode away from the substrate. The control electrode is connected to the top electrode, and the orthographic projection of the control electrode on the substrate includes the orthographic projection of the side surface of the photoelectric conversion layer on the substrate.

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