A p-type passivated contact structure and method of fabrication

Abstract

The application provides a p-type passivation contact structure and a preparation method. The preparation method comprises the following steps: preparing a pre-carbon injection structure on a silicon substrate surface; performing first high-temperature annealing to form a carbon diffusion layer on the silicon substrate surface; etching and removing the pre-carbon injection structure; and preparing a TOPCon structure on the silicon substrate surface with the carbon diffusion layer. Through the pre-carbon injection process, carbon atoms are injected into the silicon substrate surface to form a carbon diffusion layer, which can inhibit the generation and migration of silicon interstitial atoms in the high-temperature process, thereby improving the passivation quality of the p-type passivation contact structure.

Description

Technical Field

[0001] This invention relates to the field of crystalline silicon solar cell technology, and more specifically, to a p-type passivated contact structure and its fabrication method. Background Technology

[0002] With the rapid development of the photovoltaic industry, the conversion efficiency of crystalline silicon solar cells is continuously improving. Among them, tunneling silicon oxide passivated contact (TOPCon) technology has become an important technical route for improving the efficiency of crystalline silicon solar cells due to its excellent passivation performance and selective carrier transport capability. Currently, solar cells based on the n-type TOPCon structure have achieved large-scale industrial application and have achieved high conversion efficiencies.

[0003] TOPCon structures typically consist of an ultrathin silicon oxide layer and a doped polycrystalline silicon layer. The silicon oxide layer provides excellent interface passivation, while the doped polycrystalline silicon layer provides selective carrier transport channels. n-type TOPCon structures have demonstrated superior passivation performance and electrical characteristics, but the efficiency of current back-side n-type TOPCon-based cells is gradually approaching its mass production limit. Analysis shows that recombination losses in the front contact region are one of the main reasons limiting further efficiency improvements.

[0004] To further improve the efficiency of TOPCon cells, researchers have begun exploring the possibility of replacing the boron emitter of traditional TOPCon cells with a p-type TOPCon structure. For example, patent document CN112259614A discloses a stacked thin-film passivation contact structure, which involves depositing a silicon carbide thin film on the surface of a silicon oxide layer, followed by a doped amorphous silicon thin film layer, and then forming a tunneling silicon oxide passivation contact structure through high-temperature crystallization. Patent document CN117936597A discloses a functional polycrystalline silicon tunneling silicon oxide passivation contact structure, which introduces carbon, nitrogen, and other doping atoms into polycrystalline silicon to achieve both bulk and surface passivation of the silicon wafer, thereby obtaining a TOPCon structure with high passivation performance.

[0005] However, despite considerable research efforts on p-type TOPCon structures, their passivation performance remains unsatisfactory. This is primarily because the fabrication process of TOPCon involves high-temperature procedures such as thermal oxidation, high-temperature diffusion, and high-temperature annealing. During these processes, the silicon substrate readily generates a large number of silicon interstitial atoms, which can form recombination centers with boron, ultimately negatively impacting passivation quality. Currently, there are no effective methods to suppress the influence of silicon interstitial atoms on the passivation performance of p-type TOPCon structures. Summary of the Invention

[0006] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is how to effectively suppress the generation and migration of silicon interstitial atoms during the preparation of p-type TOPCon structures.

[0007] To solve the above technical problems, the present invention provides a method for preparing a p-type passivated contact structure, comprising the following steps: S1. A pre-carbon-injected structure is prepared on the surface of a silicon substrate, the pre-carbon-injected structure comprising a first interface silicon oxide layer and a carbon-containing silicon dielectric layer sequentially disposed on the silicon substrate; S2. Perform the first high-temperature annealing to form a carbon diffusion layer on the surface of the silicon substrate; S3. Etch away the pre-filled carbon structure; S4. A TOPCon structure is prepared on the surface of the silicon substrate having the carbon diffusion layer.

[0008] This invention uses a pre-carbon implantation process to inject carbon atoms into the surface of a silicon substrate to form a carbon diffusion layer. This process can suppress the generation and migration of silicon interstitial atoms during high-temperature processes, thereby improving the passivation quality of p-type passivation contact structures.

[0009] Furthermore, the depth of the carbon diffusion layer is greater than 50 nm, and the surface carbon concentration of the carbon diffusion layer is greater than 1 × 10⁻⁶. 20 cm -3 The carbon concentration at a depth of 50 nm is greater than 1 × 10⁻⁶. 17 cm -3 The pre-carbon implantation process enables deep carbon pinning, with carbon atoms penetrating deep into the interstitial spaces of the silicon lattice. This effectively suppresses the generation and migration of interstitial atoms in silicon, and the high concentration of carbon covers defect sites, reducing the density of recombination centers.

[0010] Furthermore, the thickness of the first interface silicon oxide layer is 1.4~2.5 nm, and the thickness of the carbon-containing silicon dielectric layer is 5~50 nm. The first interface silicon oxide layer is used to protect the silicon substrate during pre-carburization and subsequent etching processes, limiting its thickness to balance surface protection and carburization effects. The carbon-containing silicon dielectric layer is used to provide a carbon source, limiting its thickness to ensure sufficient carbon atoms diffuse to the silicon substrate during high-temperature annealing, while also considering etching efficiency.

[0011] Furthermore, after the first high-temperature annealing, the carbon concentration in the first interface silicon oxide layer is greater than 1×10⁻⁶. 20 cm -3 The carbon concentration in the carbon-containing silicon dielectric layer gradually increases along the direction away from the first interface silicon oxide layer, and the carbon concentration of the carbon-containing silicon dielectric layer near the surface of the first interface silicon oxide layer is greater than 1×10⁻⁶. 20 cm -3 The carbon concentration of the carbon-containing silicon dielectric layer at a distance greater than 5 × 10⁻⁶ from the surface of the silicon oxide layer at the first interface is also greater than 5 × 10⁻⁶.21 cm -3 After high-temperature annealing, carbon is implanted into the silicon substrate. The first interface silicon oxide layer has a high concentration of carbon implantation, which can suppress the generation of interstitial atoms at the interface. The carbon concentration in the carbon-containing silicon dielectric layer is distributed in a gradient, ensuring that carbon continues to diffuse into the silicon substrate during high-temperature annealing.

[0012] Furthermore, step S3 specifically includes the following steps: S31. Use an alkaline solution to etch away the carbon-silicon dielectric layer; S32. Use hydrofluoric acid to etch away the silicon oxide layer at the first interface.

[0013] This step employs a step-by-step etching process to ensure that the silicon substrate is protected from etch damage by alkaline solutions.

[0014] Furthermore, step S4 specifically includes the following steps: S41. A second interface silicon oxide layer is prepared on the surface of the silicon substrate having the carbon diffusion layer by an oxidation method; S42. An intrinsic amorphous silicon layer is prepared on the second interface silicon oxide layer by PECVD. S43. A boron-doped amorphous silicon layer is prepared on the intrinsic amorphous silicon layer by PECVD. S44. Perform a second high-temperature annealing to allow boron to diffuse into the silicon substrate, transforming the intrinsic amorphous silicon layer into a first boron-doped polycrystalline silicon layer, and the boron-doped amorphous silicon layer into a second boron-doped polycrystalline silicon layer.

[0015] By employing a stepwise deposition of intrinsic amorphous silicon layers and boron-doped amorphous silicon layers, combined with a high-temperature annealing process, boron diffusion control is achieved, thereby reducing contact resistivity.

[0016] Furthermore, the thickness of the second interface silicon oxide layer is 1.4~2.5 nm, the thickness of the intrinsic amorphous silicon layer is 10~30 nm, and the thickness of the boron-doped amorphous silicon layer is greater than 10 nm. Limiting the thickness of the second interface silicon oxide layer balances passivation and carrier transport; limiting the thickness of the boron-doped amorphous silicon layer ensures a sufficient boron diffusion source.

[0017] Furthermore, after the second high-temperature annealing, the boron concentration on the surface of the silicon substrate is greater than 1×10⁻⁶. 19 cm -3 The carbon concentration in the second interface silicon oxide layer is greater than 1×10⁻⁶. 19 cm -3 The boron concentration in the first boron-doped polycrystalline silicon layer gradually increases along the direction away from the second interface silicon oxide layer, and the boron concentration of the first boron-doped polycrystalline silicon layer near the surface of the second interface silicon oxide layer is greater than 1×10⁻⁶. 19 cm -3 The activation concentration of boron is greater than 5 × 10⁻⁶.18 cm -3 The boron concentration in the second boron-doped polycrystalline silicon layer is greater than 5 × 10⁻⁶. 20 cm -3 The activation concentration of boron is greater than 5 × 10⁻⁶. 19 cm -3 The second interface silicon oxide layer contains a high concentration of carbon, which can suppress the bonding of boron with interstitial atoms and improve passivation stability; the resulting polycrystalline silicon layer can be carbon-free, thus maintaining a high contact resistivity.

[0018] Furthermore, the preparation method also includes the following steps: S5. Prepare a hydrogen-rich dielectric layer on the TOPCon structure and perform sintering, photoimplantation, or dark annealing.

[0019] This step involves hydrogen passivation to further reduce the recombination current density.

[0020] This invention also provides a passivated contact structure, prepared by the above-described method. The passivated contact structure of this invention exhibits excellent performance, with an optimal minority carrier lifetime (τ). eff The latency reaches 3.8~4.4ms, and the implied open-circuit voltage (iVoc) is increased to 740~743mV, which is an industry-leading level.

[0021] In summary, the present invention has the following advantages over the prior art: (1) The present invention forms a carbon diffusion layer on the surface of a silicon substrate through a pre-carbon implantation process, which effectively reduces the silicon self-interstitial concentration, suppresses defect states, and significantly improves the passivation quality of the p-type TOPCon structure.

[0022] (2) The present invention adopts a silicon substrate pre-carbon injection process, and the polycrystalline silicon layer of the p-type TOPCon structure can be carbon-free, and the contact resistivity is significantly lower than that of the existing carbon boron co-doping technology, breaking through the technical bottleneck that it is difficult to achieve both high concentration doping and low resistivity.

[0023] (3) The pre-carbon infusion technology of the present invention reduces the damage to the silicon oxide interface of the p-type TOPCon structure and avoids the destruction of silicon oxide by high concentration of carbon boron co-diffusion during high-temperature annealing, thereby ensuring the quality of interface passivation.

[0024] (4) The preparation process of the present invention is fully compatible with existing production lines. The plasma-enhanced chemical vapor deposition (PECVD) technology can be used to prepare each layer sequentially in the same reaction chamber. PECVD has a fast deposition rate, high wafer load, large production capacity, small winding size, good process compatibility, and high battery yield, and has a very good industrial application prospect. Attached Figure Description

[0025] Figure 1A schematic flowchart illustrating the preparation method of the passivated contact structure in a specific embodiment of the present invention.

[0026] Figure 2 A schematic diagram of the pre-injected carbon structure in a specific embodiment of the present invention.

[0027] Figure 3 This is a schematic diagram of the passivated contact structure prepared according to a specific embodiment of the present invention.

[0028] Figure 4 This is an elemental distribution diagram of the pre-injected carbon structure in Embodiment 1 of the present invention.

[0029] Figure 5 This is a distribution diagram of boron activation concentration in the passivated sheets prepared in Example 1 and Comparative Example 1 of the present invention.

[0030] Explanation of reference numerals in the attached figures: 1-Silicon substrate, 2-First interface silicon oxide layer, 3-Carbon-containing silicon dielectric layer, 4-Carbon diffusion region, 5-Second interface silicon oxide layer, 6-Intrinsic amorphous silicon layer, 7-Boron-doped amorphous silicon layer, 8-First boron-doped polycrystalline silicon layer, 9-Second boron-doped polycrystalline silicon layer, 10-Carbon-boron diffusion region, 11-Hydrogen-rich dielectric layer. Detailed Implementation

[0031] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the following embodiments are only used to illustrate the implementation methods and typical parameters of the present invention, and are not intended to limit the parameter range described in the present invention. Reasonable variations derived therefrom are still within the protection scope of the claims of the present invention.

[0032] It should be noted that the endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of the various ranges, the endpoint values ​​of the various ranges and individual point values, and individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein.

[0033] A specific embodiment of the present invention provides a method for preparing a passivated contact structure, combined with Figure 1 As shown, it includes the following steps: (1) Prepare a clean silicon substrate 1, and prepare a first interface silicon oxide layer 2 on the surface of the silicon substrate 1. In specific embodiments, the preparation method can be thermal oxidation, plasma-assisted oxidation, ozone oxidation, wet oxidation, etc. The thickness of the first interface silicon oxide layer 2 is 1.4~2.5nm, preferably 1.6~1.8nm.

[0034] (2) A carbon-silicon dielectric layer 3 is deposited on the first interface silicon oxide layer 2 using chemical vapor deposition (CVD). In a specific embodiment, the thickness of the carbon-silicon dielectric layer 3 is 5~50 nm, and the carbon concentration is greater than 5×10⁻⁶. 21 cm -3 .

[0035] (3) A first high-temperature annealing is performed to allow carbon atoms in the carbon-silicon dielectric layer 3 to diffuse into the silicon substrate 1, forming a carbon diffusion layer on the surface of the silicon substrate 1. In a specific embodiment, the temperature of the first high-temperature annealing is 700~1100℃.

[0036] After the first high-temperature annealing, the pre-injected carbon structure is as follows: Figure 2 As shown, the carbon diffusion layer formed on the surface of silicon substrate 1 has a depth greater than 50 nm and a surface carbon concentration greater than 1 × 10⁻⁶. 20 cm -3 The carbon concentration at a depth of 50 nm is still greater than 1 × 10⁻⁶. 17 cm -3 The carbon concentration in the first interface silicon oxide layer 2 is greater than 1×10⁻⁶. 20 cm -3 The carbon concentration in the carbon-silicon dielectric layer 3 is greater than 1×10⁻⁶ near the surface of the first interface silicon oxide layer 2. 20 cm -3 The carbon concentration gradually increases along the direction away from the first interface silicon oxide layer 2, and the carbon concentration on the surface of the silicon oxide layer 2 away from the first interface is greater than 5 × 10⁻⁶. 21 cm -3 .

[0037] (4) Use an alkaline solution to etch and remove the carbon-silicon dielectric layer 3.

[0038] (5) Use hydrofluoric acid etching to remove the first interface silicon oxide layer 2.

[0039] (6) The silicon substrate 1 is subjected to RCA cleaning, and a second interface silicon oxide layer 5 is prepared on the surface of the silicon substrate 1 with a carbon diffusion layer by oxidation. In specific embodiments, the preparation method can be thermal oxidation, plasma-assisted oxidation, ozone oxidation, wet oxidation, etc. The thickness of the second interface silicon oxide layer 5 is 1.4~2.5nm, preferably 1.6~1.8nm.

[0040] (7) The intrinsic amorphous silicon layer 6 is prepared by PECVD. In a specific embodiment, the thickness of the intrinsic amorphous silicon layer 6 is 10~30nm.

[0041] (8) A boron-doped amorphous silicon layer 7 is prepared on the intrinsic amorphous silicon layer 6 using PECVD. In a specific embodiment, the thickness of the boron-doped amorphous silicon layer 7 is greater than 10 nm, and the total boron concentration exceeds 5 × 10⁻⁶. 20 cm -3 .

[0042] (9) A second high-temperature annealing is performed, which allows boron to diffuse into the silicon substrate 1 and boron atoms to enter the carbon diffusion region 4, forming a carbon-boron diffusion region 10. The intrinsic amorphous silicon layer 6 is transformed into the first boron-doped polycrystalline silicon layer 8, and the boron-doped amorphous silicon layer 7 is transformed into the second boron-doped polycrystalline silicon layer 9, thus obtaining the TOPCon structure. In a specific embodiment, the temperature of the second high-temperature annealing is 800~1100℃.

[0043] (10) A hydrogen-rich dielectric layer 11 is prepared on the second boron-doped polycrystalline silicon layer 9. In specific embodiments, the commonly used material for the hydrogen-rich dielectric layer 11 is alumina, silicon nitride, or a combination thereof.

[0044] (11) Perform sintering, light implantation or dark annealing to achieve hydrogen passivation treatment.

[0045] The passivated contact structure prepared by the above method is as follows: Figure 3 As shown, the boron concentration on the surface of the carbon-boron diffusion region 10 is greater than 1 × 10⁻⁶. 19 cm -3 Carbon concentration greater than 1×10 20 cm -3 The carbon concentration in the second interface silicon oxide layer 5 is greater than 1×10⁵. 19 cm -3 Hydrogen concentration greater than 1×10 20 cm -3 In the first boron-doped polycrystalline silicon layer 8, the boron concentration is greater than 1 × 10⁻⁶ on the surface near the second interface silicon oxide layer 5. 19 cm -3 The activation concentration of boron is greater than 5 × 10⁻⁶. 18 cm -3 The boron concentration gradually increases along the direction away from the second interface silicon oxide layer 5. The boron concentration in the second boron-doped polycrystalline silicon layer 9 is greater than 5 × 10⁻⁶. 20 cm -3 The activation concentration of boron is greater than 5 × 10⁻⁶. 19 cm -3 .

[0046] The technical solution of this invention forms a carbon diffusion layer on the surface of a silicon substrate through a pre-carbon implantation process, which effectively suppresses the generation and migration of silicon interstitial atoms, solves the problems of the prior art, and improves the passivation performance of the p-type TOPCon structure.

[0047] The technical solution and effects of the present invention are described below through specific embodiments. In the following embodiments and comparative examples, the carbon concentration of the carbon-silicon dielectric layer is 1×10⁻⁶. 22 cm -3 The boron concentration in the boron-doped amorphous silicon layer is 1×10⁻⁶. 21 cm -3 .

[0048] Example 1 The following steps were taken to fabricate a double-sided p-type TOPCon passivation wafer: An n-type double-sided planar single-crystal silicon substrate was prepared and subjected to RCA cleaning. A first interface silicon oxide layer with a thickness of approximately 1.6 nm was grown on both sides of the n-type silicon substrate using thermal oxidation. A carbon-containing silicon dielectric layer with a thickness of approximately 10 nm was deposited using PECVD. After deposition, the substrate was annealed at 900℃ for 30 min using a tube furnace to implant carbon atoms into the silicon substrate. The carbon and oxygen doping concentration distribution in the pre-implanted carbon structure was measured using SIMS, and the results are shown below. Figure 4 As shown, the above process effectively implants carbon atoms into the silicon substrate. The carbon-containing silicon dielectric layer is etched away with an alkaline solution, and the first interface silicon oxide layer is etched away with hydrofluoric acid. The silicon substrate undergoes RCA cleaning, and a second interface silicon oxide layer with a thickness of approximately 1.6 nm is grown on both sides of the silicon substrate using thermal oxidation. Subsequently, an intrinsic amorphous silicon layer with a thickness of approximately 15 nm is deposited using PECVD, followed by a carbon-doped boron amorphous silicon layer of approximately 15 nm. After deposition, a tube furnace is used for high-temperature annealing at 900°C for 30 min to complete the crystallization of amorphous silicon and the diffusion activation of boron. After annealing, the oxide layer on the polycrystalline silicon surface is etched away with hydrofluoric acid, followed by ALD deposition of an aluminum oxide layer, annealed at 490°C for 30 min in a nitrogen atmosphere. Then, a silicon nitride layer is deposited using PECVD. Next, a nitrogen and hydrogen mixture is used for annealing at 400°C for 60 min, and finally, photoimplantation is performed.

[0049] Example 2 The following steps were taken to prepare a double-sided p-type TOPCon passivation wafer: An n-type double-sided planar single-crystal silicon substrate was prepared and subjected to RCA cleaning. A first interface silicon oxide layer with a thickness of approximately 1.8 nm was grown on both sides of the n-type crystalline silicon substrate using ozonation. A carbon-containing silicon dielectric layer with a thickness of approximately 10 nm was deposited using PECVD. After deposition, the substrate was annealed at 880 °C for 30 min using a tube furnace to implant carbon atoms into the silicon substrate. After annealing and diffusion, the carbon-containing silicon dielectric layer was etched away with an alkaline solution, and the first interface silicon oxide layer was etched away with hydrofluoric acid. The silicon substrate was then subjected to RCA cleaning, and a second interface silicon oxide layer with a thickness of approximately 1.6 nm was grown on both sides of the silicon substrate using ozonation. Subsequently, an intrinsic amorphous silicon layer with a thickness of approximately 20 nm was deposited using PECVD, followed by a carbon-doped boron-containing amorphous silicon layer with a thickness of approximately 25 nm. After deposition, the substrate was annealed at 900 °C for 30 min using a tube furnace to complete the crystallization of the amorphous silicon and the diffusion activation of boron. After annealing, the oxide layer on the polycrystalline silicon surface was etched away using hydrofluoric acid, followed by ALD deposition of an aluminum oxide layer, and annealing at 490°C for 30 min under a nitrogen atmosphere. Then, a silicon nitride layer was deposited using PECVD. Next, it was annealed at 400°C for 60 min using a nitrogen and hydrogen mixture, and finally photoimplanted.

[0050] Example 3 The following steps were taken to prepare a double-sided p-type TOPCon passivation wafer: An n-type double-sided planar single-crystal silicon substrate was prepared and subjected to RCA cleaning. A first interface silicon oxide layer with a thickness of approximately 1.7 nm was grown on both sides of the n-type crystalline silicon substrate using plasma oxidation. A carbon-containing silicon dielectric layer with a thickness of approximately 20 nm was deposited using PECVD. After deposition, the substrate was annealed at 900℃ for 30 min using a tube furnace to implant carbon atoms into the silicon substrate. After annealing and diffusion, the carbon-containing silicon dielectric layer was etched away with an alkaline solution, and the first interface silicon oxide layer was etched away with hydrofluoric acid. The silicon substrate was then subjected to RCA cleaning, and a second interface silicon oxide layer with a thickness of approximately 1.7 nm was grown on both sides of the silicon substrate using plasma oxidation. Subsequently, an intrinsic amorphous silicon layer with a thickness of approximately 20 nm was deposited using PECVD, followed by a carbon-doped boron-containing amorphous silicon layer of approximately 15 nm. After deposition, the substrate was annealed at 900℃ for 30 min using a tube furnace to complete the crystallization of the amorphous silicon and the diffusion activation of boron. After annealing, the oxide layer on the polycrystalline silicon surface was etched away using hydrofluoric acid, followed by ALD deposition of an aluminum oxide layer, and annealing at 490°C for 30 min under a nitrogen atmosphere. Then, a silicon nitride layer was deposited using PECVD. Next, it was annealed at 400°C for 60 min using a nitrogen and hydrogen mixture, and finally photoimplanted.

[0051] Example 4 The following steps were taken to prepare a double-sided p-type TOPCon passivation wafer: An n-type double-sided planar single-crystal silicon substrate was prepared and subjected to RCA cleaning. A first interface silicon oxide layer with a thickness of approximately 1.6 nm was grown on both sides of the n-type crystalline silicon substrate using thermal oxidation. A carbon-containing silicon dielectric layer with a thickness of approximately 10 nm was deposited using PECVD. After deposition, the substrate was annealed at 900℃ for 30 min using a tube furnace to implant carbon atoms into the silicon substrate. After annealing and diffusion, the carbon-containing silicon dielectric layer was etched away with an alkaline solution, and the first interface silicon oxide layer was etched away with hydrofluoric acid. The silicon substrate was then subjected to RCA cleaning, and a second interface silicon oxide layer with a thickness of approximately 1.6 nm was grown on both sides of the silicon substrate using thermal oxidation. Subsequently, an intrinsic amorphous silicon layer with a thickness of approximately 15 nm was deposited using PECVD, followed by a boron-doped amorphous silicon layer with a thickness of approximately 15 nm. After deposition, the substrate was annealed at 900℃ for 30 min using a tube furnace to complete the crystallization of the amorphous silicon and the diffusion activation of boron. After annealing, the oxide layer on the polycrystalline silicon surface was etched away using hydrofluoric acid, followed by ALD deposition of an aluminum oxide layer, and annealing at 490°C for 30 min under a nitrogen atmosphere. Then, a silicon nitride layer was deposited using PECVD. Next, it was annealed at 400°C for 60 min using a nitrogen and hydrogen mixture, and finally photoimplanted.

[0052] Example 5 The following steps were taken to prepare a double-sided p-type TOPCon passivation wafer: An n-type double-sided planar single-crystal silicon substrate was prepared and subjected to RCA cleaning. A first interface silicon oxide layer with a thickness of approximately 2 nm was grown on both sides of the n-type crystalline silicon substrate using ozonation. A carbon-containing silicon dielectric layer with a thickness of approximately 25 nm was deposited using PECVD. After deposition, the substrate was annealed at 900℃ for 30 min in a tube furnace to implant carbon atoms into the silicon substrate. After annealing and diffusion, the carbon-containing silicon dielectric layer was etched away with an alkaline solution, and the first interface silicon oxide layer was etched away with hydrofluoric acid. The silicon substrate was then subjected to RCA cleaning, and a second interface silicon oxide layer with a thickness of approximately 2 nm was grown on both sides of the silicon substrate using ozonation. Subsequently, an intrinsic amorphous silicon layer with a thickness of approximately 20 nm was deposited using PECVD, followed by a boron-doped amorphous silicon layer with a thickness of approximately 30 nm without carbon. After deposition, the substrate was annealed at 900℃ for 30 min in a tube furnace to complete the crystallization of the amorphous silicon and the diffusion activation of boron. After annealing, the oxide layer on the polycrystalline silicon surface was etched away using hydrofluoric acid, followed by ALD deposition of an aluminum oxide layer, and annealing at 490°C for 30 min under a nitrogen atmosphere. Then, a silicon nitride layer was deposited using PECVD. Next, it was annealed at 400°C for 60 min using a nitrogen and hydrogen mixture, and finally photoimplanted.

[0053] Example 6 The following steps were taken to prepare a double-sided p-type TOPCon passivation wafer: An n-type double-sided planar single-crystal silicon substrate was prepared and subjected to RCA cleaning. A first interface silicon oxide layer with a thickness of approximately 1.7 nm was grown on both sides of the n-type crystalline silicon substrate using plasma oxidation. A carbon-containing silicon dielectric layer with a thickness of approximately 10 nm was deposited using PECVD. After deposition, the substrate was annealed at 900℃ for 30 min using a tube furnace to implant carbon atoms into the silicon substrate. After annealing and diffusion, the carbon-containing silicon dielectric layer was etched away with an alkaline solution, and the first interface silicon oxide layer was etched away with hydrofluoric acid. The silicon substrate was then subjected to RCA cleaning, and a second interface silicon oxide layer with a thickness of approximately 1.7 nm was grown on both sides of the silicon substrate using plasma oxidation. Subsequently, an intrinsic amorphous silicon layer with a thickness of approximately 15 nm was deposited using PECVD, followed by a boron-doped amorphous silicon layer with a thickness of approximately 15 nm. After deposition, the substrate was annealed at 900℃ for 30 min using a tube furnace to complete the crystallization of the amorphous silicon and the diffusion activation of boron. After annealing, the oxide layer on the polycrystalline silicon surface was etched away using hydrofluoric acid, followed by ALD deposition of an aluminum oxide layer, and annealing at 490°C for 30 min under a nitrogen atmosphere. Then, a silicon nitride layer was deposited using PECVD. Next, it was annealed at 400°C for 60 min using a nitrogen and hydrogen mixture, and finally photoimplanted.

[0054] Comparative Example 1 The following steps were taken to prepare a double-sided p-type TOPCon passivation wafer: An n-type double-sided planar single-crystal silicon substrate was prepared and subjected to RCA cleaning. A first interface silicon oxide layer with a thickness of approximately 1.6 nm was grown on both sides of the n-type crystalline silicon substrate using thermal oxidation. A carbon-free silicon dielectric layer with a thickness of approximately 10 nm was deposited using PECVD. After deposition, the substrate was annealed at 900℃ for 30 min using a tube furnace to implant carbon atoms into the silicon substrate. After annealing and diffusion, the carbon-containing silicon dielectric layer was etched away with an alkaline solution, and the first interface silicon oxide layer was etched away with hydrofluoric acid. The silicon substrate was then subjected to RCA cleaning, and a second interface silicon oxide layer with a thickness of approximately 1.6 nm was grown on both sides of the silicon substrate using thermal oxidation. Subsequently, an intrinsic amorphous silicon layer with a thickness of approximately 15 nm was deposited using PECVD, followed by a boron-doped amorphous silicon layer with a thickness of approximately 15 nm. After deposition, the substrate was annealed at 900℃ for 30 min using a tube furnace to complete the crystallization of the amorphous silicon and the diffusion activation of boron. After annealing, the oxide layer on the polycrystalline silicon surface was etched away using hydrofluoric acid, followed by ALD deposition of an aluminum oxide layer, and annealing at 490°C for 30 min under a nitrogen atmosphere. Then, a silicon nitride layer was deposited using PECVD. Next, it was annealed at 400°C for 60 min using a nitrogen and hydrogen mixture, and finally photoimplanted.

[0055] Comparative Example 2 The following steps were taken to fabricate a double-sided p-type TOPCon passivation wafer: An n-type double-sided planar single-crystal silicon substrate was prepared and RCA cleaned. An interface silicon oxide layer with a thickness of approximately 1.6 nm was grown on both sides of the n-type crystalline silicon substrate using thermal oxidation. An intrinsic amorphous silicon layer with a thickness of approximately 15 nm was deposited using PECVD, followed by a carbon-doped boron-containing amorphous silicon layer of approximately 15 nm. After deposition, the substrate was annealed at 900 °C for 30 min in a tube furnace to complete the crystallization of the amorphous silicon and the diffusion activation of boron. After annealing, the oxide layer on the polycrystalline silicon surface was etched away using hydrofluoric acid, followed by ALD deposition of an aluminum oxide layer, annealed at 490 °C for 30 min under a nitrogen atmosphere. Then, a silicon nitride layer was deposited using PECVD. Finally, the substrate was annealed at 400 °C for 60 min using a nitrogen and hydrogen mixture, and light implantation was performed.

[0056] The boron activation concentration distribution of the passivated sheets prepared in Example 1 and Comparative Example 1 was tested using ECV, and the results are as follows: Figure 5 As shown, the pre-carbon implantation process is beneficial to increasing the boron activation concentration. Under the same boron doping amount, the boron activation ratio is higher, the field passivation effect is better, and it helps to improve the minority carrier lifetime.

[0057] The passivation performance of the double-sided p-type TOPCon structure passivation sheets prepared in Examples 1-6 and Comparative Examples 1-2 was tested using Sinton's method. The results are shown in Table 1. The test results show that the technology of the present invention can significantly improve minority carrier lifetime (τ). eff ) and implicit open-circuit voltage (iVoc), reducing surface recombination current density (J0,p The passivation performance is improved.

[0058] Table 1. Comparison of passivation performance of double-sided P-type TOPCon structures in the examples and comparative examples. sample <![CDATA[iV oc (mV)]]> <![CDATA[J 0,p (fA / cm 2 )]]> <![CDATA[τ eff (ms)]]> Example 1 743 3.7 4.40 Example 2 742 3.9 4.15 Example 3 740 4.2 3.81 Example 4 742 4.0 4.25 Example 5 741 3.8 4.05 Example 6 741 4.0 4.13 Comparative Example 1 735 5 3.00 Comparative Example 2 737 4.5 3.40 While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for preparing a p-type passivated contact structure, characterized in that, Includes the following steps: S1. A pre-carbon-injected structure is prepared on the surface of a silicon substrate, the pre-carbon-injected structure comprising a first interface silicon oxide layer and a carbon-containing silicon dielectric layer sequentially disposed on the silicon substrate; S2. Perform the first high-temperature annealing to form a carbon diffusion layer on the surface of the silicon substrate; S3. Etch away the pre-injected carbon structure; S4. A TOPCon structure is prepared on the surface of the silicon substrate having the carbon diffusion layer.

2. The preparation method according to claim 1, characterized in that, The carbon diffusion layer has a depth greater than 50 nm, and the surface carbon concentration of the carbon diffusion layer is greater than 1 × 10⁻⁶. 20 cm -3 The carbon concentration at a depth of 50 nm is greater than 1 × 10⁻⁶. 17 cm -3 .

3. The preparation method according to claim 1, characterized in that, The thickness of the first interface silicon oxide layer is 1.4~2.5nm, and the thickness of the carbon-silicon dielectric layer is 5~50nm.

4. The preparation method according to claim 1, characterized in that, After the first high-temperature annealing, the carbon concentration in the first interface silicon oxide layer is greater than 1×10⁻⁶. 20 cm -3 The carbon concentration in the carbon-containing silicon dielectric layer gradually increases along the direction away from the first interface silicon oxide layer, and the carbon concentration of the carbon-containing silicon dielectric layer near the surface of the first interface silicon oxide layer is greater than 1×10⁻⁶. 20 cm -3 The carbon concentration of the carbon-containing silicon dielectric layer at a distance greater than 5 × 10⁻⁶ from the surface of the silicon oxide layer at the first interface is also greater than 5 × 10⁻⁶. 21 cm -3 .

5. The preparation method according to claim 1, characterized in that, Step S3 specifically includes the following steps: S31. Use an alkaline solution to etch away the carbon-silicon dielectric layer; S32. Use hydrofluoric acid to etch away the silicon oxide layer at the first interface.

6. The preparation method according to any one of claims 1-5, characterized in that, Step S4 specifically includes the following steps: S41. A second interface silicon oxide layer is prepared on the surface of the silicon substrate having the carbon diffusion layer by an oxidation method; S42. An intrinsic amorphous silicon layer is prepared on the second interface silicon oxide layer by PECVD. S43. A boron-doped amorphous silicon layer is prepared on the intrinsic amorphous silicon layer by PECVD. S44. Perform a second high-temperature annealing to allow boron to diffuse into the silicon substrate, transforming the intrinsic amorphous silicon layer into a first boron-doped polycrystalline silicon layer, and the boron-doped amorphous silicon layer into a second boron-doped polycrystalline silicon layer.

7. The preparation method according to claim 6, characterized in that, The thickness of the second interface silicon oxide layer is 1.4~2.5nm, the thickness of the intrinsic amorphous silicon layer is 10~30nm, and the thickness of the boron-doped amorphous silicon layer is greater than 10nm.

8. The preparation method according to claim 6, characterized in that, After the second high-temperature annealing, the boron concentration on the surface of the silicon substrate is greater than 1×10⁻⁶. 19 cm -3 The carbon concentration in the second interface silicon oxide layer is greater than 1×10⁻⁶. 19 cm -3 The boron concentration in the first boron-doped polycrystalline silicon layer gradually increases along the direction away from the second interface silicon oxide layer, and the boron concentration of the first boron-doped polycrystalline silicon layer near the surface of the second interface silicon oxide layer is greater than 1×10⁻⁶. 19 cm -3 The activation concentration of boron is greater than 5 × 10⁻⁶. 18 cm -3 The boron concentration in the second boron-doped polycrystalline silicon layer is greater than 5 × 10⁻⁶. 20 cm -3 The activation concentration of boron is greater than 5 × 10⁻⁶. 19 cm -3 .

9. The preparation method according to any one of claims 1-5, characterized in that, It also includes the following steps: S5. Prepare a hydrogen-rich dielectric layer on the TOPCon structure and perform sintering, photoimplantation, or dark annealing.

10. A p-type passivated contact structure, characterized in that, It is prepared by any one of the preparation methods described in claims 1-9.

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