A boron-doped source structure, a boron emitter, a method for manufacturing the same, and a solar cell
Patent Information
- Application Number
- CN202510348763.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-24
- Publication Date
- 2026-09-25
AI Technical Summary
该技术虽能实现方阻的灵活调控,但在大规模量产中暴露出以下结构性缺陷:1)B2O3沸点高,在扩散温度下多为液态,容易在硅片表面沉积并产生不均匀的质量分布,进一步加剧了扩散均匀性的问题
(1)降低硼发射极表面硼浓度:硼掺杂源采用氧化硅、非晶硅、硼硅氧化物等叠层设计,利用硼在硅、氧两种不同材料中分凝系数差异,对硅片表面的硼浓度进行有效调节,显著降低硼发射极表面硼的总浓度及激活浓度,突破现有技术的钝化瓶颈。
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Figure CN122825569A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of crystalline silicon solar cell technology, and more specifically, to a boron-doped source structure, a boron emitter, a method for preparing the same, and a solar cell. Background Technology
[0002] In the iterative development of crystalline silicon solar cell technology, the emitter has always played an indispensable role. From the phosphorus emitter of P-type PERC cells to the boron emitter of N-type TOPCon solar cells, and then to back-junction TOPCon cells and perovskite-crystalline silicon tandem solar cells, the quality of the emitter directly determines the carrier transport efficiency and the level of interface recombination loss control, significantly impacting device performance. Especially for the current mainstream N-type TOPCon cells, the front-side boron emitter must simultaneously meet the requirements of surface concentration gradient control and excellent passivation, which places stringent multi-dimensional demands on the fabrication technology.
[0003] Currently, the industry commonly uses low-pressure chemical vapor deposition (LPCVD) technology to prepare boron emitters. This involves reacting boron trichloride (BCl3) with O2 to generate a boron source (B2O3), which then diffuses into the silicon wafer at high temperatures to form the boron emitter. While this technology allows for flexible control of sheet resistance, it exhibits the following structural defects in large-scale production: 1) B2O3 has a high boiling point and is mostly liquid at diffusion temperatures, easily depositing on the silicon wafer surface and producing uneven mass distribution, further exacerbating diffusion uniformity issues. 2) BCl3 produces highly corrosive byproducts such as HCl or Cl2, increasing the difficulty of equipment and pipeline maintenance. 3) LPCVD is a thermal CVD process; the source layer deposits throughout the tube. The B2O3 produced during the reaction adheres to the surface of the quartz tube, quartz boat, and other components. As the process depth increases, the B2O3 thickness increases, generating significant stress and ultimately leading to the breakage of the quartz tube and boat. 4) The coupling effect with laser selective emitter (SE) technology is limited.
[0004] To address the aforementioned issues, patent documents CN117913156A and CN117913157A disclose a multilayer doped source structure that can balance strong laser absorption capability with high boron doping concentration, resulting in a high passivation level for the boron emitter. However, with further research, the aforementioned source layer structure has encountered bottlenecks, mainly manifested in the following ways: the high boron concentration on the emitter surface obtained by diffusion from the source layer structure makes it difficult to meet the requirements for further improving the passivation quality of the boron emitter; the boron concentration shows a trend of first increasing and then decreasing from the silicon wafer surface to the silicon wafer bulk region, exhibiting a significant arched distribution that forms a barrier to hole transport. Summary of the Invention
[0005] In view of the shortcomings of the prior art, the technical problem to be solved by the present invention is how to reduce the boron concentration in the boron emitter and optimize the boron diffusion distribution.
[0006] To address the aforementioned technical problems, the first aspect of this invention provides a boron-doped source structure, comprising a first silicon oxide layer, a second silicon oxide layer, an amorphous silicon layer, and a borosilicate oxide layer sequentially disposed on a silicon wafer. The thickness of the first silicon oxide layer is 1-3 nm, and the thicknesses of the second silicon oxide layer, the amorphous silicon layer, and the borosilicate oxide layer are all greater than that of the first silicon oxide layer. The oxygen concentration in the borosilicate oxide layer is higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3 .
[0007] This invention discloses an innovative stacked boron-doped source structure. A nanoscale first silicon oxide layer protects the silicon wafer surface and reduces defects. The boron-silicon oxide layer has a high boron concentration, ensuring sufficient diffusion source, while the high oxygen concentration inhibits excessively rapid boron diffusion, forming a gentle concentration gradient. By utilizing the difference in segregation coefficients between silicon and oxygen materials, the boron concentration in the first silicon oxide layer, the second silicon oxide layer, and the amorphous silicon layer after diffusion is reduced, achieving effective regulation of the boron concentration on the silicon surface. This helps to reduce the total boron concentration and activation concentration on the silicon surface, thereby improving passivation quality.
[0008] Furthermore, the borosilicate oxide layer contains carbon, and the total concentration of carbon is higher than 1×10⁻⁶. 20 cm -3 Introducing carbon can suppress boron defects in the boron emitter and reduce recombination centers; it also helps to increase the surface hydrogen concentration and improve the passivation effect.
[0009] Furthermore, the second silicon oxide layer contains boron, and the boron concentration in the second silicon oxide layer is lower than the boron concentration in the borosilicate oxide layer; and / or, the second silicon oxide layer contains carbon. The second silicon oxide layer may be appropriately doped with boron, which is beneficial for achieving uniform boron diffusion; carbon doping of the second silicon oxide layer is beneficial for improving the stability of the multilayer structure.
[0010] Furthermore, the amorphous silicon layer contains carbon; and / or, the amorphous silicon layer contains oxygen, and the oxygen concentration is less than 1 × 10⁻⁶. 20 cm -3 ; and / or, the amorphous silicon layer contains boron, and the boron concentration is less than 1 × 10⁻⁶. 18 cm -3 The amorphous silicon layer has strong laser coupling ability. After laser treatment, the boron concentration can be effectively introduced into the silicon surface, thus making it compatible with SE technology. This layer may contain boron and oxygen elements, but the concentration is significantly lower than that of the borosilicate oxide layer.
[0011] Furthermore, a third silicon oxide layer is provided between the amorphous silicon layer and the borosilicate oxide layer. The third silicon oxide layer further regulates the boron diffusion path and prevents abrupt changes in concentration.
[0012] Furthermore, the third silicon oxide layer contains carbon. The carbon doping in the third silicon oxide layer is beneficial for improving the stability of the multilayer structure.
[0013] Furthermore, a borosilicate oxide interlayer is provided between the second silicon oxide layer and the amorphous silicon layer, and / or a borosilicate oxide interlayer is provided between the amorphous silicon layer and the third silicon oxide layer, and / or a borosilicate oxide interlayer is provided between the amorphous silicon layer and the borosilicate oxide layer. The boron concentration of the borosilicate oxide interlayer is lower than that of the borosilicate oxide layer, and the thickness of the borosilicate oxide interlayer is less than that of the borosilicate oxide layer. Providing a borosilicate oxide interlayer ensures sufficient diffusion source and optimizes boron diffusion uniformity.
[0014] Further, the thickness of the second silicon oxide layer is 5-50 nm; and / or, the thickness of the amorphous silicon layer is 5-200 nm; and / or, the thickness of the third silicon oxide layer is 2-20 nm; and / or, the thickness of the borosilicate oxide layer is greater than 10 nm. By adjusting the thickness of each layer within a defined range, the boron concentration curve can be adjusted to achieve the technical objective of low total boron concentration and low activation concentration on the silicon surface.
[0015] A second aspect of this invention provides a method for preparing a boron emitter, comprising the following steps: S1. The above-mentioned boron-doped source structure is prepared on a silicon wafer; S2. High-temperature annealing enables boron diffusion, forming a boron emitter on the silicon wafer; S3. Etching to remove the boron-doped source structure; S4. Prepare a hydrogen-containing dielectric layer to passivate the boron emitter.
[0016] Further, step S1 specifically includes: S11. Prepare a first silicon oxide layer on a silicon wafer, wherein the preparation method is selected from one of wet chemical oxidation, thermal oxidation, plasma-assisted oxidation, and ozone oxidation. S12. A second silicon oxide layer is prepared on the first silicon oxide layer using the PECVD method; S13. Prepare a borosilicate intermediate layer on the second silicon oxide layer using PECVD method. This step can be omitted. S14. An amorphous silicon layer is prepared on the second silicon oxide layer / boron silicon oxide intermediate layer using the PECVD method. S15. Prepare a borosilicate oxide intermediate layer on an amorphous silicon layer using PECVD. This step can be omitted. S16. A third silicon oxide layer is prepared on the amorphous silicon layer / boron silicon oxide intermediate layer using PECVD. This step can be omitted. S17. A borosilicate layer is prepared on an amorphous silicon layer / boron silicon oxide intermediate layer / third silicon oxide layer using the PECVD method.
[0017] This invention uses PECVD to prepare a stacked boron-doped source structure, with uniform distribution of solid boron doped sources. The source layer is deposited only in the region with a plasma field, so it grows only on the silicon wafer and graphite boat and will not be deposited on the quartz tube wall, thus avoiding damage to the quartz components.
[0018] Furthermore, in step S2, the high-temperature annealing temperature is 900~1100℃. At high temperature, boron gradually diffuses from the dopant source structure into the crystalline silicon substrate, causing the amorphous silicon layer to become a polycrystalline silicon layer.
[0019] A third aspect of the present invention provides a boron emitter prepared by the above-described preparation method.
[0020] Furthermore, the activation concentration of boron on the surface of the boron emitter is less than 1×10⁻⁶. 19 cm -3 The boron concentration decreases from the boron emitter surface towards the silicon wafer bulk region. The low activation concentration at the boron emitter surface reduces carrier recombination and improves passivation quality; the boron diffusion curve is more reasonable and does not create a barrier to hole transport and collection.
[0021] Furthermore, the boron emitter contains carbon, oxygen, and hydrogen elements, and the carbon concentration on the surface of the boron emitter is higher than 1 × 10⁻⁶. 18 cm -3 Oxygen concentration higher than 1×10 18 cm -3 Hydrogen concentration higher than 5×10 18 cm -3 The boron emitter contains a high concentration of carbon, oxygen, and hydrogen, which can synergistically passivate interface defects and improve passivation quality.
[0022] A fourth aspect of this invention provides a solar cell comprising the aforementioned boron emitter. The boron emitter of this invention has the advantages of high passivation quality and low recombination current, and is suitable for N-type TOPCon, back-junction TOPCon, perovskite-crystalline silicon tandem cells, etc., providing core technological support for the industrialization of high-efficiency solar cells.
[0023] In summary, the present invention has the following beneficial effects: (1) Reduce the boron concentration on the surface of the boron emitter: The boron doping source adopts a stacked design of silicon oxide, amorphous silicon, boron silicon oxide, etc. By utilizing the difference in the segregation coefficient of boron in silicon and oxygen, the boron concentration on the surface of the silicon wafer is effectively adjusted, significantly reducing the total boron concentration and activation concentration on the surface of the boron emitter, thus breaking through the passivation bottleneck of the existing technology.
[0024] (2) Boron distribution curve reconstruction: Using the boron doped source structure of the present invention as the boron source, the boron activation concentration can be gradually reduced from the silicon surface to the bulk, eliminating the "arched distribution" of the existing process, avoiding the hole transport barrier, and improving the carrier collection efficiency.
[0025] (3) Improved surface quality: The silicon surface has a double layer of silicon oxide protection, which helps to reduce interface defects and improve surface quality.
[0026] (4) Suppressing boron defects: Introducing carbon elements into the boron doped source structure can suppress boron defects in the boron emitter and reduce recombination centers; and it is also beneficial to increase the surface hydrogen concentration and improve the passivation effect.
[0027] (5) Boron source is easy to etch: There is a significant etching selectivity between the material components of each layer in the boron doped source structure, which is easy to wet etch.
[0028] (6) Compatible with SE technology: The boron-doped source structure has an amorphous silicon layer, which has strong coupling ability with laser and is adapted to laser processing to achieve deep activation of boron.
[0029] (7) Uniform distribution of boron source: The solid boron doped source prepared by PECVD has good structural uniformity, and the plasma field only acts on the surface of silicon wafer and graphite boat, avoiding the risk of quartz tube contamination and breakage. Attached Figure Description
[0030] Figure 1 This is a schematic diagram of the boron-doped source structure in a specific embodiment of the present invention.
[0031] Figure 2 This is a schematic diagram of the boron-doped source structure in Embodiment 1 of the present invention.
[0032] Figure 3 This is a schematic diagram of the boron-doped source structure in Embodiment 2 of the present invention.
[0033] Figure 4 This is a schematic diagram of the boron-doped source structure in Embodiment 3 of the present invention.
[0034] Figure 5 This is a schematic diagram of the boron-doped source structure in Embodiment 4 of the present invention.
[0035] Figure 6 This is a schematic diagram of the boron source structure in Comparative Example 1 of the present invention.
[0036] Figure 7 This is a schematic diagram of the boron source structure in Comparative Example 3 of the present invention.
[0037] Figure 8 This is a schematic diagram of the boron source structure in Comparative Example 4 of the present invention.
[0038] Figure 9 The graph shows the electrochemical capacitance voltage test results of the boron emitters prepared in the embodiments and comparative examples of the present invention.
[0039] Explanation of reference numerals in the attached figures: 1-Silicon wafer, 2-Boron emitter, 3-First silicon oxide layer, 4-Second silicon oxide layer, 5-Amorphous silicon layer, 6-Third silicon oxide layer, 7-Boron silicon oxide layer, 8-Boron silicon oxide intermediate layer, 9-Boron silicon glass layer, 10-Boron-doped amorphous silicon layer. Detailed Implementation
[0040] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the following embodiments are only used to illustrate the implementation methods and typical parameters of the present invention, and are not intended to limit the parameter range described in the present invention. Reasonable variations derived therefrom are still within the protection scope of the claims of the present invention.
[0041] It should be noted that the endpoints and any values of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values should be understood to include values close to these ranges or values. For numerical ranges, the endpoint values of the various ranges, the endpoint values of the various ranges and individual point values, and individual point values can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein.
[0042] Specific embodiments of the present invention provide a boron-doped source structure and a method for fabricating a boron emitter using the boron-doped source structure. A typical structure of the boron-doped source structure is as follows: Figure 1 As shown, it includes a first silicon oxide layer 3, a second silicon oxide layer 4, an amorphous silicon layer 5, a third silicon oxide layer 6 and a boron silicon oxide layer 7 arranged sequentially on a silicon wafer 1. After boron diffusion, a boron emitter 2 is formed on the surface of the silicon wafer 1.
[0043] In a specific embodiment, the material of the first silicon oxide layer 3 is nano-silicon oxide, whose main components are silicon and oxygen, and its typical thickness is 1~3nm, which can protect the surface of the silicon wafer 1.
[0044] In a specific embodiment, the second silicon oxide layer 4 is deposited using CVD, and its main components are silicon and oxygen. Its thickness is greater than that of the first silicon oxide layer 3, with a typical thickness of 5-50 nm. The second silicon oxide layer 4 may contain boron, but the boron concentration is lower than that in the borosilicate oxide layer; this layer may also contain carbon.
[0045] In a specific embodiment, the amorphous silicon layer 5 is mainly composed of silicon, and its thickness is greater than that of the first silicon oxide layer 3, typically ranging from 5 to 200 nm. The amorphous silicon layer 5 may contain carbon; it may also contain a small amount of oxygen, with a concentration less than 1 × 10⁻⁶. 20 cm -3 This layer may also contain trace amounts of boron, with a concentration less than 1 × 10⁻⁶. 18 cm -3 .
[0046] In a specific embodiment, the third silicon oxide layer 6 is mainly composed of silicon and oxygen, and its thickness is greater than that of the first silicon oxide layer 3, typically ranging from 2 to 20 nm. The third silicon oxide layer 6 may contain carbon. In some embodiments, the third silicon oxide layer 6 may be omitted.
[0047] In specific embodiments, the thickness of the borosilicate oxide layer 7 is typically greater than 10 nm, and the main components of this layer are silicon and oxygen, with an oxygen concentration higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3 In some embodiments, the borosilicate oxide layer 7 is further carbon-doped, with a total carbon concentration greater than 1 × 10⁻⁶. 20 cm -3 .
[0048] It should be noted that in some embodiments, the second silicon oxide layer 4, the amorphous silicon layer 5, the third silicon oxide layer 6, and the borosilicate oxide layer 7 have a sublayer structure, and the thickness and composition of each layer in the sublayer structure may be the same or different.
[0049] In some embodiments, a borosilicate intermediate layer (not shown in the figure) may be provided between the second silicon oxide layer 4, the amorphous silicon layer 5, the third silicon oxide layer 6 and the borosilicate oxide layer 7, and the boron concentration and thickness of the borosilicate intermediate layer are less than those of the borosilicate oxide layer 7.
[0050] The method for preparing a boron emitter using the above-mentioned boron-doped source structure includes the following steps: (1) Cleaning of silicon wafer 1 surface.
[0051] (2) A first silicon oxide layer 3 is prepared on silicon wafer 1. The preparation method can be wet chemical oxidation, thermal oxidation, plasma-assisted oxidation, ozone oxidation, etc.
[0052] (3) A five-layer boron-doped source structure is obtained by sequentially depositing a second silicon oxide layer 4, an amorphous silicon layer 5, a third silicon oxide layer 6 and a boron silicon oxide layer 7 on the first silicon oxide layer 3 using the PECVD method.
[0053] (4) High-temperature annealing achieves the diffusion of boron. The typical temperature is 900~1100℃. A boron emitter 2 is formed on the silicon wafer 1, and the amorphous silicon layer 5 is transformed into a polycrystalline silicon layer.
[0054] (5) Etching to remove the boron doped source structure. Specifically, the boron silicon oxide layer 7 and the third silicon oxide layer 6 can be etched using an HF acid-based solution; the polysilicon layer can be etched using an alkaline acid-based solution; and then the second silicon oxide layer 4 and the first silicon oxide layer 3 can be etched using an HF acid-based solution. In some embodiments, various additive materials can be used in the solution cleaning process.
[0055] (6) Prepare a hydrogen-containing dielectric layer to passivate the boron emitter 2. The hydrogen-containing dielectric layer is usually made of materials such as alumina, silicon nitride, silicon oxide, or a combination thereof.
[0056] In a specific embodiment, the activation concentration of boron on the surface of the boron emitter 2 prepared by the above method is less than 1×10⁻⁶. 19 cm -3 The boron concentration decreases from the surface to the bulk region of silicon wafer 1; the boron emitter 2 contains carbon, and its surface concentration is higher than 1×10⁻⁶. 18 cm -3 The boron emitter 2 contains oxygen, and its surface concentration is higher than 1×10⁻⁶. 18 cm -3 The boron emitter 2 contains hydrogen, with a surface concentration higher than 5 × 10⁻⁶. 18 cm -3 .
[0057] The above technical solution, through the combination of multi-layer boron doped source structure design and PECVD process, systematically solves the problems of poor uniformity, low passivation quality and safety hazards of traditional boron expansion technology. It reduces the boron activation concentration on the surface of boron emitter, provides passivation effect, and ensures process safety and mass production economy. This technology is applicable to various types of solar cells and provides key support for the upgrading of high-efficiency solar cell technology.
[0058] The technical solution and effects of the present invention will be described below through specific embodiments.
[0059] Example 1 In this embodiment, a boron emitter is fabricated, and the boron-doped source structure is as follows: Figure 2 As shown, the specific process is as follows: Prepare a double-textured N-type crystalline silicon substrate and perform RCA cleaning. A nano-silicon oxide film, the first silicon oxide layer 3, with a thickness of approximately 2 nm, is grown on the surface of silicon wafer 1 using hydrogen peroxide oxidation. Then, a second silicon oxide layer 4, an amorphous silicon layer 5, a third silicon oxide layer 6, and a borosilicate oxide layer 7 are sequentially deposited on the first silicon oxide layer 3 using PECVD. The second silicon oxide layer 4 has a thickness of approximately 10 nm; the amorphous silicon layer 5 has a thickness of approximately 100 nm; the third silicon oxide layer 6 has a thickness of approximately 10 nm; and the borosilicate oxide layer 7 has a thickness of approximately 30 nm, with an oxygen concentration higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3 Multiple samples were subjected to high-temperature annealing at 980℃ and 1000℃ for 240 min to achieve boron diffusion, forming a boron emitter 2 on silicon wafer 1 and transforming the amorphous silicon layer 5 into a polycrystalline silicon layer. The wafer was then held at 800℃ for 90 min and cooled. The boron-silicon oxide layer 7 and the third silicon oxide layer 6 were etched using an HF acid-based solution; the polycrystalline silicon layer was etched using an alkaline acid-based solution; and the second silicon oxide layer 4 and the first silicon oxide layer 3 were etched using an HF acid-based solution to completely remove the boron doping source structure. The samples were then subjected to RCA cleaning, and sheet resistance and electrochemical capacitance voltage (ECV) were measured. An alumina layer with a thickness of approximately 15 nm was then prepared on the boron emitter 2, and the passivation level of the sample was measured using a minority carrier lifetime meter (WCT120).
[0060] Example 2 In this embodiment, a boron emitter is fabricated, and the boron-doped source structure is as follows: Figure 3 As shown, the specific process is as follows: Prepare a double-sided textured N-type crystalline silicon substrate and perform RCA cleaning. A first silicon oxide layer 3, approximately 2 nm thick, is grown on the surface of silicon wafer 1 using hydrogen peroxide oxidation. A second silicon oxide layer 4, an amorphous silicon layer 5, and a borosilicate oxide layer 7 are then sequentially deposited on the first silicon oxide layer 3 using PECVD. The second silicon oxide layer 4 is approximately 10 nm thick; the amorphous silicon layer 5 is approximately 100 nm thick and is doped with trace amounts of carbon, with a concentration less than 1 × 10⁻⁶. 18 cm -3 The thickness of borosilicate layer 7 is approximately 30 nm, and the oxygen concentration in this layer is higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3Multiple samples were subjected to high-temperature annealing at 980℃ and 1000℃ for 240 min to achieve boron diffusion, transforming the amorphous silicon layer 5 into a polycrystalline silicon layer. A boron emitter 2 was formed on silicon wafer 1. The wafers were then held at 800℃ for 90 min and cooled. The boron-silicon oxide layer 7 was etched using an HF acid-based solution; the polycrystalline silicon layer was etched using an alkaline acid-based solution; and the second silicon oxide layer 4 and the first silicon oxide layer 3 were etched using an HF acid-based solution to completely remove the boron doping source structure. The samples were then subjected to RCA cleaning, and sheet resistance and ECV measurements were performed. An aluminum oxide layer with a thickness of approximately 15 nm was then prepared on the boron emitter 2, and the passivation level of the samples was measured using a minority carrier lifetime meter.
[0061] Example 3 In this embodiment, a boron emitter is fabricated, and the boron-doped source structure is as follows: Figure 4 As shown, the specific process is as follows: Prepare a double-textured N-type crystalline silicon substrate and perform RCA cleaning. A first silicon oxide layer 3, approximately 2 nm thick, is grown on the surface of silicon wafer 1 using hydrogen peroxide oxidation. A second silicon oxide layer 4, a borosilicate oxide interlayer 8, an amorphous silicon layer 5, and a borosilicate oxide layer 7 are sequentially deposited on the first silicon oxide layer 3 using PECVD. The second silicon oxide layer 4 is approximately 10 nm thick; the borosilicate oxide interlayer 8 is approximately 10 nm thick, with a lower boron content than the borosilicate oxide layer 7; the amorphous silicon layer 5 is approximately 100 nm thick; and the borosilicate oxide layer 7 is approximately 30 nm thick, with an oxygen concentration higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3 Multiple samples were subjected to high-temperature annealing at 980℃ and 1000℃ for 240 min to achieve boron diffusion, transforming the amorphous silicon layer 5 into a polycrystalline silicon layer. A boron emitter 2 was formed on silicon wafer 1. The samples were then held at 800℃ for 90 min and cooled. The boron-silicon oxide layer 7 was etched using an HF acid-based solution; the polycrystalline silicon layer was etched using an alkaline acid-based solution; and then the boron-silicon oxide intermediate layer 8, the second silicon oxide layer 4, and the first silicon oxide layer 3 were etched using an HF acid-based solution to completely remove the boron doping source structure. The samples were then subjected to RCA cleaning, and sheet resistance and ECV measurements were performed. An aluminum oxide layer with a thickness of approximately 15 nm was then prepared on the boron emitter 2, and the passivation level of the samples was measured using a minority carrier lifetime meter.
[0062] Example 4 In this embodiment, a boron emitter is fabricated, and the boron-doped source structure is as follows: Figure 5 As shown, the specific process is as follows: Prepare a double-textured N-type crystalline silicon substrate and perform RCA cleaning. A first silicon oxide layer 3, approximately 1 nm thick, is grown on the surface of silicon wafer 1 using nitric acid oxidation. A second silicon oxide layer 4, an amorphous silicon layer 5, a borosilicate oxide interlayer 8, and a borosilicate oxide layer 7 are sequentially deposited on the first silicon oxide layer 3 using PECVD. The second silicon oxide layer 4 is approximately 15 nm thick; the amorphous silicon layer 5 is approximately 150 nm thick; the borosilicate oxide interlayer 8 is approximately 15 nm thick, with a lower boron content than the borosilicate oxide layer 7; and the borosilicate oxide layer 7 is approximately 30 nm thick, with an oxygen concentration higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3 Multiple samples were subjected to high-temperature annealing at 980℃ and 1000℃ for 240 min to achieve boron diffusion, transforming the amorphous silicon layer 5 into a polycrystalline silicon layer, and forming a boron emitter 2 on silicon wafer 1. The samples were then held at 800℃ for 90 min and cooled. The boron-silicon oxide layer 7 and the boron-silicon oxide intermediate layer 8 were etched using an HF acid-based solution; the polycrystalline silicon layer was etched using an alkaline acid-based solution; and the second silicon oxide layer 4 and the first silicon oxide layer 3 were etched using an HF acid-based solution to completely remove the boron doping source structure. The samples were then subjected to RCA cleaning, and sheet resistance and ECV measurements were performed. An aluminum oxide layer with a thickness of approximately 15 nm was then prepared on the boron emitter 2, and the passivation level of the samples was measured using a minority carrier lifetime meter.
[0063] Example 5 The boron emitter is prepared in this embodiment, and the specific process is as follows: A double-textured N-type crystalline silicon substrate was prepared and subjected to RCA cleaning. A first silicon oxide layer, approximately 2 nm thick, was grown on the silicon wafer surface using hydrogen peroxide oxidation. A second silicon oxide layer, an amorphous silicon layer, and a borosilicate oxide layer were then sequentially deposited on the first silicon oxide layer using PECVD. The second silicon oxide layer was approximately 10 nm thick and contained trace amounts of carbon, with a concentration less than 1 × 10⁻⁶. 18 cm -3 The amorphous silicon layer is approximately 100 nm thick and contains trace amounts of carbon at a concentration of less than 1 × 10⁻⁶. 18 cm -3 The borosilicate oxide layer is approximately 30 nm thick, and the oxygen concentration in this layer is higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3Multiple samples were subjected to high-temperature annealing at 980℃ and 1000℃ for 240 min to achieve boron diffusion, forming a boron emitter on the silicon wafer and transforming the amorphous silicon layer into a polycrystalline silicon layer. The samples were then held at 800℃ for 90 min and cooled. The boron-silicon oxide layer was etched using an HF acid-based solution; the polycrystalline silicon layer was etched using an alkaline acid-based solution; and the second and first silicon oxide layers were etched again using an HF acid-based solution to completely remove the boron doping source structure. The samples were then subjected to RCA cleaning, and sheet resistance and ECV measurements were performed. An aluminum oxide layer with a thickness of approximately 15 nm was then fabricated on the boron emitter, and the passivation level of the samples was measured using a minority carrier lifetime meter.
[0064] Example 6 The boron emitter is prepared in this embodiment, and the specific process is as follows: Prepare a double-textured N-type crystalline silicon substrate and perform RCA cleaning. A first silicon oxide layer, approximately 2 nm thick, is grown on the silicon wafer surface using hydrogen peroxide oxidation. A second silicon oxide layer, an amorphous silicon layer, and a borosilicate oxide layer are then sequentially deposited on the first silicon oxide layer using PECVD. The second silicon oxide layer is approximately 10 nm thick; the amorphous silicon layer is approximately 100 nm thick and is doped with trace amounts of carbon, with a concentration less than 1 × 10⁻⁶. 18 cm -3 The borosilicate oxide layer is approximately 30 nm thick, and the oxygen concentration in this layer is higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3 This layer contains carbon elements at a concentration higher than 1×10⁻⁶. 20 cm -3 Multiple samples were subjected to high-temperature annealing at 980℃ and 1000℃ for 240 min to achieve boron diffusion, forming a boron emitter on the silicon wafer and transforming the amorphous silicon layer into a polycrystalline silicon layer. The samples were then held at 800℃ for 90 min and cooled. The boron-silicon oxide layer was etched using an HF acid-based solution; the polycrystalline silicon layer was etched using an alkaline acid-based solution; and the second and first silicon oxide layers were etched again using an HF acid-based solution to completely remove the boron doping source structure. The samples were then subjected to RCA cleaning, and sheet resistance and ECV measurements were performed. An aluminum oxide layer with a thickness of approximately 15 nm was then fabricated on the boron emitter, and the passivation level of the samples was measured using a minority carrier lifetime meter.
[0065] Example 7 The boron emitter is prepared in this embodiment, and the specific process is as follows: Prepare a double-textured N-type crystalline silicon substrate and perform RCA cleaning. A first silicon oxide layer, approximately 3 nm thick, is grown on the silicon wafer surface using thermal oxidation. A second silicon oxide layer, an amorphous silicon layer, and a borosilicate oxide layer are then sequentially deposited on the first silicon oxide layer using PECVD. The second silicon oxide layer is approximately 15 nm thick and contains trace amounts of carbon, with a concentration less than 1 × 10⁻⁶. 18 cm -3 The amorphous silicon layer is approximately 50 nm thick and contains trace amounts of carbon at a concentration of less than 1 × 10⁻⁶. 18 cm -3 The borosilicate oxide layer is approximately 20 nm thick, and the oxygen concentration in this layer is higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3 This layer contains carbon elements at a concentration higher than 1×10⁻⁶. 20 cm -3 Multiple samples were subjected to high-temperature annealing at 980℃ and 1000℃ for 240 min to achieve boron diffusion, forming a boron emitter on the silicon wafer and transforming the amorphous silicon layer into a polycrystalline silicon layer. The samples were then held at 800℃ for 90 min and cooled. The boron-silicon oxide layer was etched using an HF acid-based solution; the polycrystalline silicon layer was etched using an alkaline acid-based solution; and the second and first silicon oxide layers were etched again using an HF acid-based solution to completely remove the boron doping source structure. The samples were then subjected to RCA cleaning, and sheet resistance and ECV measurements were performed. An aluminum oxide layer with a thickness of approximately 15 nm was then fabricated on the boron emitter, and the passivation level of the samples was measured using a minority carrier lifetime meter.
[0066] Example 8 The boron emitter is prepared in this embodiment, and the specific process is as follows: Prepare a double-textured N-type crystalline silicon substrate and perform RCA cleaning. A first silicon oxide layer, approximately 1.5 nm thick, is grown on the silicon wafer surface using thermal oxidation. A second silicon oxide layer, an amorphous silicon layer, a third silicon oxide layer, and a borosilicate oxide layer are then sequentially deposited on the first silicon oxide layer using PECVD. The second silicon oxide layer is approximately 5 nm thick and contains trace amounts of carbon, with a concentration less than 1 × 10⁻⁶. 18 cm -3 The amorphous silicon layer is approximately 100 nm thick and contains trace amounts of carbon at a concentration of less than 1 × 10⁻⁶. 18 cm -3 The thickness of the third silicon oxide layer is approximately 15 nm; the thickness of the borosilicate oxide layer is approximately 50 nm, and the oxygen concentration in this layer is higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3Multiple samples were subjected to high-temperature annealing at 980℃ and 1000℃ for 240 min to achieve boron diffusion, forming a boron emitter on the silicon wafer and transforming the amorphous silicon layer into a polycrystalline silicon layer. The samples were then held at 800℃ for 90 min and cooled. The boron-silicon oxide layer and the third silicon oxide layer were etched using an HF-based acid solution; the polycrystalline silicon layer was etched using an alkaline acid solution; and the second and first silicon oxide layers were then etched using an HF-based acid solution to completely remove the boron doping source structure. The samples were then subjected to RCA cleaning, and sheet resistance and ECV measurements were performed. An aluminum oxide layer with a thickness of approximately 15 nm was then fabricated on the boron emitter, and the passivation level of the samples was measured using a minority carrier lifetime meter.
[0067] Example 9 The boron emitter is prepared in this embodiment, and the specific process is as follows: Prepare a double-textured N-type crystalline silicon substrate and perform RCA cleaning. A first silicon oxide layer, approximately 1.5 nm thick, is grown on the silicon wafer surface using thermal oxidation. A second silicon oxide layer, an amorphous silicon layer, a third silicon oxide layer, and a borosilicate oxide layer are then sequentially deposited on the first silicon oxide layer using PECVD. The second silicon oxide layer is approximately 10 nm thick; the amorphous silicon layer is approximately 100 nm thick and is doped with trace amounts of carbon, with a concentration less than 1 × 10⁻⁶. 18 cm -3 The thickness of the third silicon oxide layer is approximately 10 nm; the thickness of the borosilicate oxide layer is approximately 50 nm, and the oxygen concentration in this layer is higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3 This layer contains carbon elements at a concentration higher than 1×10⁻⁶. 20 cm -3 Multiple samples were subjected to high-temperature annealing at 980℃ and 1000℃ for 240 min to achieve boron diffusion, forming a boron emitter on the silicon wafer and transforming the amorphous silicon layer into a polycrystalline silicon layer. The samples were then held at 800℃ for 90 min and cooled. The boron-silicon oxide layer and the third silicon oxide layer were etched using an HF-based acid solution; the polycrystalline silicon layer was etched using an alkaline acid solution; and the second and first silicon oxide layers were then etched using an HF-based acid solution to completely remove the boron doping source structure. The samples were then subjected to RCA cleaning, and sheet resistance and ECV measurements were performed. An aluminum oxide layer with a thickness of approximately 15 nm was then fabricated on the boron emitter, and the passivation level of the samples was measured using a minority carrier lifetime meter.
[0068] Example 10 The boron emitter is prepared in this embodiment, and the specific process is as follows: Prepare a double-textured N-type crystalline silicon substrate and perform RCA cleaning. A first silicon oxide layer, approximately 1.5 nm thick, is grown on the silicon wafer surface using thermal oxidation. A second silicon oxide layer, an amorphous silicon layer, a third silicon oxide layer, and a borosilicate oxide layer are then sequentially deposited on the first silicon oxide layer using PECVD. The second silicon oxide layer is approximately 10 nm thick and contains trace amounts of carbon, with a concentration less than 1 × 10⁻⁶. 18 cm -3 The amorphous silicon layer is approximately 80 nm thick and contains trace amounts of carbon at a concentration of less than 1 × 10⁻⁶. 18 cm -3 The thickness of the third silicon oxide layer is approximately 10 nm; the thickness of the borosilicate oxide layer is approximately 50 nm, and the oxygen concentration in this layer is higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3 This layer contains carbon elements at a concentration higher than 1×10⁻⁶. 20 cm -3 Multiple samples were subjected to high-temperature annealing at 980℃ and 1000℃ for 240 min to achieve boron diffusion, transforming the amorphous silicon layer into a polycrystalline silicon layer and forming a boron emitter on the silicon wafer. The samples were then held at 800℃ for 90 min and cooled. The boron-silicon oxide layer and the third silicon oxide layer were etched using an HF-based acid solution; the polycrystalline silicon layer was etched using an alkaline acid solution; and the second and first silicon oxide layers were etched again using an HF-based acid solution to completely remove the boron doping source structure. The samples were then subjected to RCA cleaning, and sheet resistance and ECV measurements were performed. An aluminum oxide layer with a thickness of approximately 15 nm was then fabricated on the boron emitter, and the passivation level of the samples was measured using a minority carrier lifetime meter.
[0069] Example 11 The boron emitter is prepared in this embodiment, and the specific process is as follows: Prepare a double-textured N-type crystalline silicon substrate and perform RCA cleaning. A first silicon oxide layer, approximately 2 nm thick, is grown on the silicon wafer surface using hydrogen peroxide oxidation. A second silicon oxide layer, an amorphous silicon layer, a third silicon oxide layer, and a borosilicate oxide layer are then sequentially deposited on the first silicon oxide layer using PECVD. The second silicon oxide layer is approximately 10 nm thick; the amorphous silicon layer is approximately 80 nm thick and is doped with trace amounts of carbon, with a concentration less than 1 × 10⁻⁶. 18 cm -3 The third silicon oxide layer is approximately 10 nm thick and contains trace amounts of carbon at a concentration of less than 1 × 10⁻⁶. 18 cm -3 The borosilicate oxide layer is approximately 50 nm thick, and the oxygen concentration in this layer is higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3This layer contains carbon elements at a concentration higher than 1×10⁻⁶. 20 cm -3 Multiple samples were subjected to high-temperature annealing at 980℃ and 1000℃ for 240 min to achieve boron diffusion, transforming the amorphous silicon layer into a polycrystalline silicon layer and forming a boron emitter on the silicon wafer. The samples were then held at 800℃ for 90 min and cooled. The boron-silicon oxide layer and the third silicon oxide layer were etched using an HF-based acid solution; the polycrystalline silicon layer was etched using an alkaline acid solution; and the second and first silicon oxide layers were etched again using an HF-based acid solution to completely remove the boron doping source structure. The samples were then subjected to RCA cleaning, and sheet resistance and ECV measurements were performed. An aluminum oxide layer with a thickness of approximately 15 nm was then fabricated on the boron emitter, and the passivation level of the samples was measured using a minority carrier lifetime meter.
[0070] Example 12 The boron emitter is prepared in this embodiment, and the specific process is as follows: A double-textured N-type crystalline silicon substrate was prepared and subjected to RCA cleaning. A first silicon oxide layer, approximately 2 nm thick, was grown on the silicon wafer surface using hydrogen peroxide oxidation. A second silicon oxide layer, an amorphous silicon layer, a third silicon oxide layer, and a borosilicate oxide layer were then sequentially deposited on the first silicon oxide layer using PECVD. The second silicon oxide layer was approximately 10 nm thick and contained trace amounts of carbon, with a concentration less than 1 × 10⁻⁶. 18 cm -3 The amorphous silicon layer is approximately 80 nm thick and contains trace amounts of carbon at a concentration of less than 1 × 10⁻⁶. 18 cm -3 The third silicon oxide layer is approximately 10 nm thick and contains trace amounts of carbon at a concentration of less than 1 × 10⁻⁶. 18 cm -3 The borosilicate oxide layer is approximately 50 nm thick, and the oxygen concentration in this layer is higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3 This layer contains carbon elements at a concentration higher than 1×10⁻⁶. 20 cm -3 Multiple samples were subjected to high-temperature annealing at 980℃ and 1000℃ for 240 min to achieve boron diffusion, transforming the amorphous silicon layer into a polycrystalline silicon layer and forming a boron emitter on the silicon wafer. The samples were then held at 800℃ for 90 min and cooled. The boron-silicon oxide layer and the third silicon oxide layer were etched using an HF-based acid solution; the polycrystalline silicon layer was etched using an alkaline acid solution; and the second and first silicon oxide layers were etched again using an HF-based acid solution to completely remove the boron doping source structure. The samples were then subjected to RCA cleaning, and sheet resistance and ECV measurements were performed. An aluminum oxide layer with a thickness of approximately 15 nm was then fabricated on the boron emitter, and the passivation level of the samples was measured using a minority carrier lifetime meter.
[0071] Example 13 In this embodiment, a boron emitter is fabricated. The boron-doped source structure is the same as in Example 1. The specific process is as follows: A double-sided planar N-type crystalline silicon substrate was prepared, and surface damage was removed using tetramethylammonium hydroxide followed by RCA cleaning. A nano-silicon oxide film, the first silicon oxide layer, with a thickness of approximately 2 nm, was grown on the silicon wafer surface using hydrogen peroxide oxidation. A second silicon oxide layer, an amorphous silicon layer, a third silicon oxide layer, and a borosilicate oxide layer were then sequentially deposited on the first silicon oxide layer using PECVD. The second silicon oxide layer was approximately 10 nm thick; the amorphous silicon layer was approximately 100 nm thick; the third silicon oxide layer was approximately 10 nm thick; and the borosilicate oxide layer was approximately 30 nm thick, with an oxygen concentration higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3 Multiple samples were subjected to high-temperature annealing at 980℃ and 1000℃ for 240 min to achieve boron diffusion, forming a boron emitter on the silicon wafer and transforming the amorphous silicon layer into a polycrystalline silicon layer. The samples were then held at 800℃ for 90 min and cooled. The boron-silicon oxide layer and the third silicon oxide layer were etched using an HF-based acid solution; the polycrystalline silicon layer was etched using an alkaline acid solution; and the second and first silicon oxide layers were then etched using an HF-based acid solution to completely remove the boron doping source structure. The samples were then subjected to RCA cleaning, and sheet resistance and ECV measurements were performed. An aluminum oxide layer with a thickness of approximately 15 nm was then fabricated on the boron emitter, and the passivation level of the samples was measured using a minority carrier lifetime meter.
[0072] Example 14 In this embodiment, a boron emitter is prepared. The boron-doped source structure is the same as in Example 2. The specific process is as follows: A double-sided planar N-type crystalline silicon substrate was prepared, and surface damage was removed using tetramethylammonium hydroxide followed by RCA cleaning. A first silicon oxide layer, approximately 2 nm thick, was grown on the silicon wafer surface using hydrogen peroxide oxidation. A second silicon oxide layer, an amorphous silicon layer, and a borosilicate oxide layer were then sequentially deposited on the first silicon oxide layer using PECVD. The second silicon oxide layer was approximately 10 nm thick; the amorphous silicon layer was approximately 100 nm thick and contained trace amounts of carbon at a concentration less than 1 × 10⁻⁶. 18 cm -3 The borosilicate oxide layer is approximately 30 nm thick, and the oxygen concentration in this layer is higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3Multiple samples were subjected to high-temperature annealing at 980℃ and 1000℃ for 240 min to achieve boron diffusion, transforming the amorphous silicon layer into a polycrystalline silicon layer and forming a boron emitter on the silicon wafer. The samples were then held at 800℃ for 90 min and cooled. The boron-silicon oxide layer was etched using an HF acid-based solution; the polycrystalline silicon layer was etched using an alkaline acid-based solution; and the second and first silicon oxide layers were etched again using an HF acid-based solution to completely remove the boron doping source structure. The samples were then subjected to RCA cleaning, and sheet resistance and ECV measurements were performed. An alumina layer with a thickness of approximately 15 nm was then fabricated on the boron emitter, and the passivation level of the samples was measured using a minority carrier lifetime meter.
[0073] Comparative Example 1 This comparative example uses LPCVD low-pressure boron diffusion process to prepare boron emitters, and the boron source structure is as follows: Figure 6 As shown, the specific process is as follows: A double-sided textured N-type silicon substrate was prepared and subjected to RCA cleaning. Liquid B₂O₃ and a boron-rich layer (BRL) were formed on silicon wafer 1 using LPCVD with boron tribromide and oxygen as reactants. Multiple samples were subjected to high-temperature diffusion at 1050℃ to form a boron emitter 2 and an outermost borosilicate glass layer 9. The borosilicate glass layer 9 was removed by immersion in high-concentration HF. The samples underwent standard RCA cleaning, and sheet resistance and ECV measurements were performed. Then, an alumina layer with a thickness of approximately 15 nm was prepared on the boron emitter 2, and the passivation level of the samples was measured using a minority carrier lifetime meter.
[0074] Comparative Example 2 This comparative example uses LPCVD low-pressure boron diffusion process to prepare boron emitters. The specific process is as follows: A double-sided textured N-type silicon substrate was prepared and subjected to RCA cleaning. Liquid B₂O₃ and a boron-rich layer (BRL) were formed on the silicon wafer using LPCVD with boron tribromide and oxygen as reactants. Multiple samples underwent high-temperature diffusion at 1050℃ to form a boron emitter and an outermost borosilicate glass layer, followed by holding at 800℃ for 90 min. The borosilicate glass layer was removed by immersion in high-concentration HF. The samples were then subjected to standard RCA cleaning, and sheet resistance and ECV measurements were performed. An alumina layer with a thickness of approximately 15 nm was then prepared on the boron emitter, and the passivation level of the samples was measured using a minority carrier lifetime meter.
[0075] Comparative Example 3 This comparative example prepares a boron emitter, and the boron source structure is as follows: Figure 7 As shown, the specific process is as follows: A double-textured N-type crystalline silicon substrate was prepared and subjected to RCA cleaning. A first silicon oxide layer 3, approximately 2 nm thick, was grown on the surface of silicon wafer 1 using hydrogen peroxide oxidation. A borosilicate oxide layer 7 and a boron-doped amorphous silicon layer 10 were then sequentially deposited on the first silicon oxide layer 3 using PECVD. The borosilicate oxide layer 7 was approximately 30 nm thick and had an oxygen concentration higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3 The boron-doped amorphous silicon layer 10 is approximately 30 nm thick and is mainly composed of silicon. The boron concentration in this layer is higher than 1 × 10⁻⁶. 20 cm -3 Multiple samples underwent high-temperature annealing at 1000℃ for 240 min to achieve boron diffusion, forming a boron emitter 2 on silicon wafer 1. The boron-doped amorphous silicon layer 10 was transformed into a boron-doped polycrystalline silicon layer, followed by holding at 800℃ for 90 min and then cooling. The boron-doped polycrystalline silicon layer was etched using an alkaline-acidic solution; then the boron silicon oxide layer 7 and the first silicon oxide layer 3 were etched using an HF-acidic solution, completely removing the boron source structure. The samples were then subjected to RCA cleaning, and sheet resistance and ECV tests were performed. An aluminum oxide layer with a thickness of approximately 15 nm was then prepared on the boron emitter 2, and the passivation level of the samples was tested using a minority carrier lifetime meter.
[0076] Comparative Example 4 This comparative example prepares a boron emitter, and the boron source structure is as follows: Figure 8 As shown, the specific process is as follows: A double-textured N-type crystalline silicon substrate was prepared and subjected to RCA cleaning. A first silicon oxide layer 3, approximately 2 nm thick, was grown on the surface of silicon wafer 1 using hydrogen peroxide oxidation. An amorphous silicon layer 5 and a borosilicate oxide layer 7 were then sequentially deposited on the first silicon oxide layer 3 using PECVD. The amorphous silicon layer 5 was approximately 100 nm thick and contained trace amounts of carbon, with a concentration less than 1 × 10⁻⁶. 18 cm -3 The thickness of borosilicate layer 7 is approximately 30 nm, and the oxygen concentration in this layer is higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3Multiple samples were subjected to high-temperature annealing at 1000℃ for 240 min to achieve boron diffusion, transforming the amorphous silicon layer 5 into a polycrystalline silicon layer, and forming a boron emitter 2 on silicon wafer 1. The samples were then held at 800℃ for 90 min and cooled. The boron-silicon oxide layer 7 was etched using an HF acid-based solution; the polycrystalline silicon layer was etched using an alkaline acid-based solution; and the first silicon oxide layer 3 was etched again using an HF acid-based solution, completely removing the boron source structure. The samples were then subjected to RCA cleaning, and sheet resistance and ECV measurements were performed. An aluminum oxide layer with a thickness of approximately 15 nm was then prepared on the boron emitter 2, and the passivation level of the samples was measured using a minority carrier lifetime meter.
[0077] The sheet resistance test results of boron emitters in Examples 1-14 are shown in Table 1 below, and the sheet resistance test results of boron emitters in Comparative Examples 1-4 are shown in Table 2 below. The numerical ranges shown in the tables refer to the range of test results for multiple samples.
[0078] Table 1. Results of boron emitter sheet resistance test in the example.
[0079] Table 2 Comparative Boron Emitter Sheet Resistance Test Results
[0080] It is evident that the sheet resistance of the embodiment better meets the industry requirement of an adjustable higher sheet resistance range, and satisfies the rule that it decreases as the annealing temperature increases.
[0081] The ECV test results of the boron emitters prepared in Examples 1, 2, and 5 and Comparative Examples 1, 3, and 4 are as follows: Figure 9 As shown in the figure, the boron surface activation concentration of the boron emitter in the embodiment is lower than that in the comparative example, which is beneficial to achieving a better passivation effect. In addition, the junction depth also meets the requirements of the current industry for boron emitters in laser-assisted sintering (LECO).
[0082] The passivation level test results of the boron emitters in Examples 1-14 and Comparative Examples 1-4 are shown in Table 3 below. The table shows the iV... oc J represents the implied open-circuit voltage. 0,s teff represents the single-sided recombination current density, and teff represents the minority carrier lifetime. The test results for each embodiment shown in the table correspond to samples annealed at 1000°C, and the values shown in the table are the average values of test results for multiple samples.
[0083] Table 3. Test results of boron emitter passivation performance in the examples and comparative examples. sample <![CDATA[iV oc (mV)]]> <![CDATA[J 0,s (fA / cm 2 )]]> teff(μs) Example 1 741 3.9 4001 Example 2 738 4.5 3772 Example 3 735 6.1 3320 Example 4 739 4.8 3821 Example 5 735 6.5 3291 Example 6 735 5.8 3497 Example 7 736 5.6 3610 Example 8 738 4.9 3710 Example 9 738 5.1 3687 Example 10 735 6.4 3198 Example 11 736 6.0 3275 Example 12 739 4.1 3987 Example 13 737 4.5 3876 Example 14 735 5.2 3421 Comparative Example 1 720 11.2 2023 Comparative Example 2 735 4.6 3674 Comparative Example 3 716 12 1756 Comparative Example 4 715 18 1821 As can be seen from the passivation data, the boron emitter structure prepared in this patent embodiment has a higher implicit open-circuit voltage, a lower single-sided saturation current density, and a higher minority carrier lifetime compared with the comparative example, which is beneficial to improving battery efficiency. Overall, it is more in line with the industrial needs for high passivation and low activation concentration.
[0084] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A boron-doped source structure, characterized in that, The silicon oxide layer comprises, in sequence, a first silicon oxide layer, a second silicon oxide layer, an amorphous silicon layer, and a borosilicate oxide layer disposed on a silicon wafer. The thickness of the first silicon oxide layer is 1-3 nm. The thicknesses of the second silicon oxide layer, the amorphous silicon layer, and the borosilicate oxide layer are all greater than that of the first silicon oxide layer. The oxygen concentration in the borosilicate oxide layer is higher than 1 × 10⁻⁶. 22 cm -3 Boron concentration higher than 1×10 20 cm -3 .
2. The boron-doped source structure according to claim 1, characterized in that, The borosilicate oxide layer contains carbon, and the carbon concentration is higher than 1×10⁻⁶. 20 cm -3 .
3. The boron-doped source structure according to claim 1, characterized in that, The second silicon oxide layer contains boron, and the boron concentration in the second silicon oxide layer is lower than the boron concentration in the borosilicate oxide layer; And / or, the second silicon oxide layer contains carbon.
4. The boron-doped source structure according to claim 1, characterized in that, The amorphous silicon layer contains carbon. And / or, the amorphous silicon layer contains oxygen, and the oxygen concentration is less than 1 × 10⁻⁶. 20 cm -3 ; And / or, the amorphous silicon layer contains boron, and the boron concentration is less than 1 × 10⁻⁶. 18 cm -3 .
5. The boron-doped source structure according to any one of claims 1-4, characterized in that, A third silicon oxide layer is provided between the amorphous silicon layer and the borosilicate oxide layer.
6. The boron-doped source structure according to claim 4, characterized in that, The third silicon oxide layer contains carbon.
7. The boron-doped source structure according to claim 5, characterized in that, A borosilicate intermediate layer is provided between the second silicon oxide layer and the amorphous silicon layer, and / or a borosilicate intermediate layer is provided between the amorphous silicon layer and the third silicon oxide layer, and / or a borosilicate intermediate layer is provided between the amorphous silicon layer and the borosilicate layer, wherein the boron concentration of the borosilicate intermediate layer is less than that of the borosilicate layer, and the thickness of the borosilicate intermediate layer is less than that of the borosilicate layer.
8. The boron-doped source structure according to claim 5, characterized in that, The thickness of the second silicon oxide layer is 5~50 nm; And / or, the thickness of the amorphous silicon layer is 5~200nm; And / or, the thickness of the third silicon oxide layer is 2~20 nm; And / or, the thickness of the borosilicate oxide layer is greater than 10 nm.
9. A method for preparing a boron emitter, characterized in that, Includes the following steps: S1. Prepare a boron-doped source structure as described in any one of claims 1-8 on a silicon wafer; S2. High-temperature annealing enables boron diffusion, forming a boron emitter on the silicon wafer; S3. Etching to remove the boron-doped source structure; S4. Prepare a hydrogen-containing dielectric layer to passivate the boron emitter.
10. The method for preparing a boron emitter according to claim 9, characterized in that, Step S1 specifically includes: S11. Prepare a first silicon oxide layer on a silicon wafer, wherein the preparation method is selected from one of wet chemical oxidation, thermal oxidation, plasma-assisted oxidation, and ozone oxidation. S12. A second silicon oxide layer is prepared on the first silicon oxide layer using the PECVD method; S13. Prepare a borosilicate intermediate layer on the second silicon oxide layer using PECVD method. This step can be omitted. S14. An amorphous silicon layer is prepared on the second silicon oxide layer / boron silicon oxide intermediate layer using the PECVD method. S15. Prepare a borosilicate oxide intermediate layer on an amorphous silicon layer using PECVD. This step can be omitted. S16. A third silicon oxide layer is prepared on the amorphous silicon layer / boron silicon oxide intermediate layer using PECVD. This step can be omitted. S17. A borosilicate layer is prepared on an amorphous silicon layer / boron silicon oxide intermediate layer / third silicon oxide layer using the PECVD method.
11. The method for preparing a boron emitter according to claim 9, characterized in that, In step S2, the high-temperature annealing temperature is 900~1100℃.
12. A boron emitter, characterized in that, It is prepared by the preparation method as described in any one of claims 9-11.
13. The boron emitter according to claim 12, characterized in that, The activation concentration of boron on the surface of the boron emitter is less than 1×10⁻⁶. 19 cm -3 The boron concentration decreases from the surface of the boron emitter towards the silicon wafer body.
14. The boron emitter according to claim 13, characterized in that, The boron emitter contains carbon, oxygen, and hydrogen elements, and the carbon concentration on the surface of the boron emitter is higher than 1 × 10⁻⁶. 18 cm -3 Oxygen concentration higher than 1×10 18 cm -3 Hydrogen concentration higher than 5×10 18 cm -3 .
15. A solar cell, characterized in that, Includes the boron emitter as described in any one of claims 12-14.
Citation Information
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