High light efficiency LED chip and preparation method thereof

Abstract

The application discloses a high light efficiency LED chip and a preparation method thereof, and relates to the field of semiconductor photoelectric devices. The high light efficiency LED chip comprises a substrate and a conical structure arranged on the surface of the substrate. The conical structure comprises a frustum arranged at the bottom and a cone arranged at the top. The refractive index of the cone is smaller than that of the frustum. A plurality of pits are formed on the cone, and the depth of the pits is 50nm-500nm. The application can improve the light extraction efficiency and internal quantum efficiency, and further improve the luminous efficiency of the high light efficiency LED chip.

Description

Technical Field

[0001] This invention relates to the field of semiconductor optoelectronic devices, and more particularly to a high-efficiency LED chip and its fabrication method. Background Technology

[0002] Patterned SiO2 sapphire substrates (SPSS) are created by first forming a SiO2 layer on a sapphire substrate, then etching the SiO2 layer and part of the sapphire substrate to form conical, pyramidal, or other patterns. Compared to ordinary patterned sapphire substrates (PSS), this SiO2 patterned substrate utilizes the low refractive index of SiO2 and its inhibitory effect on GaN nucleation, further improving crystal quality and light extraction efficiency. However, it also has the following problems: 1. Because the surface of the SiO2 curved cone is smooth, the scattering of light mainly depends on the geometric contour of the micron-scale pattern, which is a primary geometric optical scattering. This scattering mechanism is effective in changing the propagation path of light in the vertical direction, but ineffective for guided wave mode light propagating laterally within the GaN layer, meaning that this part of the light energy is still confined inside the device and cannot escape. 2. The sidewalls of the SiO2 curved cone are the main path for the lateral epitaxial growth of GaN, but the smooth sidewalls have limited effect on inducing the bending and annihilation of penetrating dislocations (TDs). Therefore, the dislocation density of the epitaxial layer in subsequent growth remains high, which is not conducive to effectively improving the internal quantum efficiency. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a high-efficiency LED chip and its preparation method, which can improve luminous efficiency.

[0004] To address the above problems, this invention discloses a high-efficiency LED chip, comprising: Substrate; A conical structure disposed on the surface of the substrate, the conical structure including a frustum portion at the bottom and a cone portion at the top; the refractive index of the cone portion is less than the refractive index of the frustum portion; The cone-shaped portion has multiple pits with a depth of 50nm to 500nm.

[0005] As an improvement to the above technical solution, the opening width of the pit is 100nm~500nm and the depth is 50nm~300nm; The distance between adjacent pits is 150nm~350nm.

[0006] As an improvement to the above technical solution, the recess extends circumferentially along the cone portion and connects end to end to form an annular groove. A raised strip is formed between adjacent annular grooves.

[0007] As an improvement to the above technical solution, the height of the raised strip is 100nm~400nm and its width is 80nm~300nm.

[0008] As an improvement to the above technical solution, the distance between adjacent protrusions conforms to the following relationship: 0.5λ≤nD≤1.5λ; Where λ is the emission wavelength of the high-efficiency LED chip, D is the distance between adjacent protrusions, and n is a constant with a value range of 1.2 to 1.4.

[0009] As an improvement to the above technical solution, the substrate is a sapphire substrate, the frustum portion is made of the same material as the substrate, and the cone portion is made of silicon oxide; The diameter of the bottom surface of the frustum is 2μm~3.5μm, the diameter of its top surface is 1.2μm~2.7μm, and the height is 0.1μm~1μm; The diameter of the bottom surface of the cone portion is 1.2μm to 2.7μm, and its height is 1μm to 2μm.

[0010] As an improvement to the above technical solution, the sidewall of the cone structure is arc-shaped; the angle between the line connecting the vertex and the bottom of the sidewall and the horizontal plane is 30°~70°.

[0011] Accordingly, the present invention also discloses a method for fabricating a high-efficiency LED chip, which includes: Provide substrate; A dielectric layer is formed on the substrate; The dielectric layer and the substrate are etched to form a conical structure, resulting in an intermediate body; wherein the conical structure includes a frustum at the bottom and a cone at the top; the refractive index of the cone is less than that of the frustum. Multiple pits are formed on the conical portion; wherein the depth of the pits is 50nm~500nm.

[0012] As an improvement to the above technical solution, the step of etching the dielectric layer and the substrate to form a cone structure and obtain the intermediate includes: A photoresist layer is formed on the dielectric layer; the thickness of the photoresist layer is 1μm~3μm. The photoresist layer is exposed and developed to form multiple photoresist cylinders; the diameter of the photoresist cylinders is 2μm~3.5μm, and their period is 2.5μm~4.5μm; The dielectric layer is etched by RIE etching process to form a dielectric layer cylinder; wherein the process parameters of RIE etching process include: the etching gas is CHF3 and CF4, the volume ratio of CHF3 to CF4 is 8:1~12:1, the pressure is 20mtorr~50mtorr, and the power is 200W~500W. The substrate is etched using an ICP etching process to form a substrate cylinder; wherein the process parameters of the ICP etching process include: the etching gases are BCl3 and SF6, the volume ratio of BCl3 to SF6 is 1:0.5 to 1:1.5, the ICP power is 1000W to 1400W, the RF power is 300W to 600W, and the pressure is 3mtorr to 10mtorr; The cylindrical dielectric layer is etched using an ICP etching process to form a conical portion. The process parameters for the ICP etching process include: etching gases of CHF3, CF4, and Ar, with a volume ratio of CHF3, CF4, and Ar of 8:3:15 to 12:6:25; ICP power of 500W to 1000W; RF power of 200W to 400W; and pressure of 10mtorr to 25mtorr. The substrate cylinder is etched using an ICP etching process to form a frustum-shaped portion, resulting in a cone structure. The process parameters for the ICP etching process include: etching gases of BCl3, SF6, and Ar, with a volume ratio of BCl3, SF6, and Ar of 5:1:10 to 10:3:20; ICP power of 800W to 1400W; RF power of 300W to 600W; and pressure of 5mtorr to 15mtorr. Remove the remaining photoresist layer to obtain the intermediate.

[0013] As an improvement to the above technical solution, the step of forming multiple pits on the conical portion includes: A metal mask layer is formed on the intermediate body and patterned. The cone portion is etched by an ion beam etching process to form a pit; wherein the process parameters of the ion beam etching process include an ion energy of 400eV~600eV, an ion beam current of 80mA~150mA, an etching gas of Ar and CF4 with a volume ratio of Ar to CF4 of 0.8:1~1.2:1, and a pressure of 0.01Pa~0.05Pa. Remove the remaining metal mask layer.

[0014] Implementing this invention has the following beneficial effects: In one embodiment of the present invention, a high-efficiency LED chip includes a substrate with a conical structure on its surface. The conical structure includes a frustum at the bottom and a cone at the top, with the refractive index of the cone being lower than that of the frustum. Multiple pits with a depth of 50 nm to 500 nm are formed on the cone. These pits convert light in the transverse waveguide mode into vertically emitted light, reducing total internal reflection loss and effectively improving light extraction efficiency, thereby increasing the luminous efficiency of the LED chip. Furthermore, these pits can reduce the density of penetrating dislocations, improve the quality of the epitaxial layer grown on the substrate, reduce non-radiative recombination centers, and improve internal quantum efficiency, further enhancing the luminous efficiency of the LED chip. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the structure of a high-efficiency LED chip in one embodiment of the present invention; Figure 2 This is a top view of a cone structure in one embodiment of the present invention; Figure 3 This is a top view of the cone structure in another embodiment of the present invention; Figure 4 This is a cross-sectional view of a cone structure in one embodiment of the present invention; Figure 5 This is a flowchart of a method for preparing a high-efficiency LED chip according to an embodiment of the present invention; In the figure, 100 is the substrate, 200 is the conical structure, 210 is the frustum, 220 is the cone, 221 is the pit, 222 is the protrusion, 223 is the annular groove, 300 is the first semiconductor layer, 400 is the active layer, 500 is the second semiconductor layer, 600 is the first electrode, and 700 is the second electrode. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. Furthermore, it should be understood that the specific embodiments described herein are merely for explaining this application and are not intended to limit this application.

[0017] In the description of this application, it should be understood that the terms "length", "width", "upper", "lower", "left", "right", "horizontal", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0018] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0019] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0020] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0021] Please see Figure 1 , Figure 2As a first aspect of the present invention, a high-efficiency LED chip is provided, comprising a substrate 100, on the surface of which a conical structure 200 is provided. The conical structure 200 includes a frustum portion 210 at the bottom and a cone portion 220 at the top, the refractive index of the cone portion 220 being less than that of the frustum portion 210. Multiple pits 221 with a depth of 50 nm to 500 nm are formed on the cone portion 220. These pits 221 can convert light in the transverse waveguide mode into vertically emitted light, reducing total internal reflection loss and effectively improving light extraction efficiency, thereby improving the luminous efficiency of the LED chip. Furthermore, these pits 221 can also reduce the penetration dislocation density, improve the quality of the epitaxial layer grown on the substrate 100, and reduce non-radiative recombination centers, thereby further improving the luminous efficiency of the LED chip.

[0022] Specifically, the substrate 100 is a sapphire substrate, a silicon substrate, a silicon nitride substrate, or a silicon carbide substrate, but is not limited to these. Sapphire substrate is preferred because its process is mature and its application is widespread.

[0023] Specifically, the frustum portion 210 of the conical structure 200 and the substrate 100 are made of the same material, which may be sapphire, silicon, silicon nitride, or silicon carbide, but is not limited to these. Preferably, the frustum portion 210 is made of sapphire.

[0024] Specifically, the bottom and top surfaces of the frustum portion 210 are both circular. The diameter of the bottom surface is 2μm to 3.5μm, exemplarily 2.2μm, 2.5μm, 2.8μm, 3.1μm, or 3.4μm, but not limited thereto. Preferably, it is 2.5μm to 3.5μm. The diameter of the top surface of the frustum portion 210 is 1.2μm to 2.7μm, exemplarily 1.3μm, 1.5μm, 1.7μm, 1.9μm, 2.1μm, 2.3μm, or 2.5μm, but not limited thereto. Preferably, it is 1.7μm to 2.7μm, more preferably 1.7μm to 2.4μm. The height of the frustum portion 210 is 0.1μm to 1μm, exemplarily 0.2μm, 0.4μm, 0.6μm, or 0.8μm, but not limited thereto. Preferably, the micrometer is 0.4μm to 0.8μm.

[0025] Specifically, the sidewall of the frustum portion 210 may be straight, arc-shaped, or polygonal, but is not limited to these. Preferably, in some embodiments, the sidewall of the frustum portion 210 is arc-shaped, and the arc is a convex arc surface, which can optimize the uniformity of light emission.

[0026] Specifically, the cone portion 220 is disposed on the top surface of the frustum portion 210, and its material is silicon dioxide, silicon nitride, or magnesium fluoride, but is not limited thereto. Preferably, in some embodiments, the cone portion 220 is made of silicon dioxide.

[0027] The conical portion 220 and the frustum portion 210 transition continuously, with their sidewalls forming a smooth, continuous plane or curved surface. Preferably, in some embodiments, the sidewall of the conical portion 220 is also arc-shaped, and its radius of curvature matches that of the sidewall of the frustum portion 210, so that the sidewalls of the conical portion 220 and the frustum portion 210 form a continuously changing curved surface. More specifically, please refer to... Figure 4 The angle (α) between the line connecting the apex and the bottom of the sidewall of the conical structure 200 and the horizontal plane is 30° to 70°, which can further improve the luminous efficiency. For example, α is 32.5°, 38°, 43.5°, 55°, 62.5° or 68°, but is not limited to this.

[0028] Specifically, the diameter of the bottom surface of the conical portion 220 is 1.2 μm to 2.7 μm, exemplarily 1.3 μm, 1.5 μm, 1.7 μm, 1.9 μm, 2.1 μm, 2.3 μm, or 2.5 μm, but not limited thereto. Preferably, it is 1.7 μm to 2.7 μm, more preferably 1.7 μm to 2.4 μm. The height of the conical portion 220 is 1 μm to 2 μm, exemplarily 1.1 μm, 1.3 μm, 1.5 μm, 1.7 μm, or 1.9 μm, but not limited thereto. Preferably, it is 1.3 μm to 2 μm.

[0029] Specifically, please refer to Figure 2 Multiple pits 221 are formed on the conical portion 220. These pits 221 may be arranged in an array, but are not limited to this. The cross-sectional shape of the pits 221 may be hemispherical, ellipsoidal, bowl-shaped, cylindrical, conical, prism-shaped, or pyramidal, but is not limited to this. Preferably, the shape of the pits 221 is hemispherical or bowl-shaped to enhance light scattering and improve light emission uniformity. Specifically, the depth direction of the pits 221 is parallel to the axis of the conical portion 220, or forms a certain angle with the axis of the conical portion 220 (see Figure 221). Figure 4 The angles β1, β2, and β3 are, for example, 40° to 80°, exemplarily 43°, 48°, 52°, 59°, 64°, 71°, or 78°, but are not limited thereto. Preferably, the angle is 45° to 70°. It should be noted that the depth direction of the pit 221 refers to the axial direction of the pit 221.

[0030] Specifically, the depth of the pit 221 is 50nm to 500nm, exemplarily 80nm, 120nm, 160nm, 200nm, 250nm, 300nm, 350nm, 400nm, or 450nm, but not limited thereto. Preferably, it is 50nm to 350nm, more preferably 100nm to 300nm.

[0031] Specifically, in some embodiments, the opening width of the recess 221 is 100nm~500nm, exemplarily 120nm, 180nm, 240nm, 300nm, 360nm, 420nm or 480nm, but not limited thereto. Preferably it is 100nm~200nm, more preferably 100nm~150nm.

[0032] Specifically, the distance between adjacent pits 221 is 150nm to 350nm, exemplarily 180nm, 220nm, 260nm or 300nm, but not limited thereto. Preferably, it is 150nm to 250nm.

[0033] Preferably, please refer to Figure 3 , Figure 4 In some embodiments, the recess 221 extends circumferentially along the cone portion 220 and is connected end to end, that is, a through annular groove 223 is formed on a cross section parallel to the surface of the substrate 100, and a raised strip 222 is formed between adjacent annular grooves 223. Such multiple raised strips 222 can form a diffraction structure similar to a grating, which can effectively optimize light extraction efficiency and light purity.

[0034] Specifically, the height of the raised strip 222 is 100nm to 400nm, exemplarily 120nm, 150nm, 180nm, 200nm, 250nm, 300nm or 350nm, but not limited thereto. Preferably it is 100nm to 300nm, more preferably 100nm to 200nm.

[0035] Specifically, the width of the raised strip 222 is 80nm to 300nm, and exemplary values ​​are 100nm, 120nm, 150nm, 180nm, 200nm, 240nm or 280nm, but not limited thereto. Preferably it is 100nm to 300nm, and more preferably it is 100nm to 200nm.

[0036] Preferably, in some embodiments, the distance between adjacent protrusions 222 conforms to the following relationship: 0.5λ≤nD≤1.5λ; Where λ is the emission wavelength of the high-efficiency LED chip, D is the distance between adjacent protrusions 222, and n is a constant ranging from 1.2 to 1.4. Based on this, the light extraction efficiency can be further improved.

[0037] Specifically, in some embodiments, the high-efficiency LED chip further includes an epitaxial layer, a first electrode 600, and a second electrode 700. The epitaxial layer includes a first semiconductor layer 300, an active layer 400, and a second semiconductor layer 500 sequentially stacked on the substrate 100 and the conical structure 200. The first electrode 600 is electrically connected to the second semiconductor layer 500, and the second electrode 700 is electrically connected to the first semiconductor layer 300. The epitaxial layer can be a GaN-based epitaxial layer, an AlGaN-based epitaxial layer, or an AlGaInP-based epitaxial layer, but is not limited to these. Preferably, in some embodiments, the epitaxial layer is a GaN-based epitaxial layer, the first semiconductor layer 300 is an N-type GaN layer, the second semiconductor layer 500 is a P-type GaN layer, and the active layer 400 is an InGaN / GaN multiple quantum well structure, but is not limited to these. The epitaxial layer may also include a buffer layer, an undoped GaN layer, an electron blocking layer, a contact layer, etc., but is not limited to these.

[0038] Preferably, in some embodiments, the high-efficiency LED chip may also include layer structures commonly used in LED chips, such as a transparent conductive layer, a current blocking layer, a passivation layer, and a reflective layer, but is not limited thereto.

[0039] Specifically, the high-efficiency LED chip of the present invention may be a conventional LED chip, a flip-chip LED chip, or a vertical structure LED chip, but is not limited thereto.

[0040] Accordingly, please refer to Figure 5 As a second aspect of the present invention, the present invention also provides a method for preparing a high-efficiency LED chip, which includes the following steps: S1: Provides a substrate; S2: Forming a dielectric layer on the substrate; S3: Etch the dielectric layer and substrate to form a cone structure, thus obtaining the intermediate; S4: Multiple pits are formed on the cone-shaped part; The conical structure includes a frustum at the bottom and a cone at the top; the refractive index of the cone is lower than that of the frustum; the depth of the recess is 50nm~500nm. This recess can convert light in the transverse waveguide mode into vertically emitted light, reducing total internal reflection loss and effectively improving light extraction efficiency, thereby improving the luminous efficiency of the LED chip. Furthermore, this recess can also reduce the penetration dislocation density, improve the quality of the epitaxial layer grown on the substrate, and reduce non-radiative recombination centers, thus further improving the luminous efficiency of the LED chip.

[0041] Specifically, in step S2, the dielectric layer is made of the same material as the cone portion. The dielectric layer can be formed by methods such as PECVD, MOCVD, and LPCVD, but is not limited to these. Preferably, in some embodiments, a SiO2 layer is grown by PECVD as the dielectric layer, and the specific growth process parameters include: the process gases are SiH4 and N2O, the flow rate of SiH4 is 30 sccm to 100 sccm, the flow rate of N2O is 150 sccm to 300 sccm, the pressure is 0.8 torr to 1.2 torr, and the RF power is 150 W to 350 W.

[0042] Specifically, in step S3, the etching process can be dry etching or wet etching, but is not limited to these. Preferably, in some embodiments, step S3 includes: S31: Forming a photoresist layer on the dielectric layer; The photoresist layer can be formed through spin coating, but is not limited to this process. The thickness of the photoresist layer is 1μm to 3μm.

[0043] S32: Expose and develop the photoresist layer to form multiple photoresist cylinders; The diameter of the photoresist cylinders ranges from 2μm to 3.5μm, and the period ranges from 2.5μm to 4.5μm. It should be noted that the period of the photoresist cylinders refers to the distance between the axes of the photoresist cylinders.

[0044] S33: The dielectric layer is etched using RIE etching process to form a dielectric layer cylinder; The process parameters for the RIE etching process include: etching gases are CHF3 and CF4, the volume ratio of CHF3 to CF4 is 8:1 to 12:1, the pressure is 20 mtorr to 50 mtorr, and the power is 200 W to 500 W.

[0045] S34: The substrate is etched using an ICP etching process to form a substrate cylinder; The process parameters for the ICP etching process include: etching gases are BCl3 and SF6, the volume ratio of BCl3 to SF6 is 1:0.5 to 1:1.5, the ICP power is 1000W to 1400W, the RF power is 300W to 600W, and the pressure is 3mtorr to 10mtorr.

[0046] S35: The cylindrical dielectric layer is etched using an ICP etching process to form a cone-shaped portion; The process parameters for the ICP etching process include: etching gases are CHF3, CF4 and Ar, the volume ratio of CHF3, CF4 and Ar is 8:3:15~12:6:25, the ICP power is 500W~1000W, the RF power is 200W~400W, and the pressure is 10mtorr~25mtorr.

[0047] S36: The substrate cylinder is etched using ICP etching process to form a frustum portion, resulting in a cone structure; The process parameters for the ICP etching process include: etching gases are BCl3, SF6 and Ar, the volume ratio of BCl3, SF6 and Ar is 5:1:10~10:3:20, ICP power is 800W~1400W, RF power is 300W~600W, and pressure is 5mtorr~15mtorr.

[0048] S37: Remove the remaining photoresist layer to obtain the intermediate.

[0049] Specifically, in step S4, multiple pits can be formed on the surface of the cone portion by dry etching or wet etching, but is not limited thereto. Preferably, in some embodiments, step S4 includes: S41: Form a metal mask layer on the intermediate and pattern it; The metal mask layer can be a nickel layer, a chromium layer, or a titanium layer, but is not limited to these. The metal mask layer can be formed by processes such as PVD and vapor deposition, but is not limited to these. Preferably, in some embodiments, the metal mask layer is formed by vapor deposition, and its thickness is 10 nm to 30 nm.

[0050] Specifically, part of the metal mask layer can be removed by wet etching or dry etching to achieve patterning, thereby exposing the area to be etched.

[0051] S42: The cone-shaped part is etched by an ion beam etching process to form a pit; The process parameters for the ion beam etching process include: ion energy of 400eV~600eV, ion beam current of 80mA~150mA, etching gases of Ar and CF4, volume ratio of Ar to CF4 of 0.8:1~1.2:1, and pressure of 0.01Pa~0.05Pa.

[0052] S43: Remove the remaining metal mask layer.

[0053] Specifically, in some embodiments, the method for fabricating a high-efficiency LED chip also includes steps such as forming an epitaxial layer, a first electrode, and a second electrode, but is not limited thereto.

[0054] The present invention will be further described below with reference to specific embodiments: Example 1 This embodiment provides a high-efficiency LED chip, which includes a substrate (sapphire substrate) and a conical structure. The conical structure includes a frustum portion (Al2O3 material) at the bottom and a cone portion (SiO2 material) at the top, and multiple pits are formed on the cone portion.

[0055] The frustum portion has a base diameter of 2.9 μm to 3.1 μm and a height of 0.42 μm, while its top diameter is 2.4 μm to 2.55 μm. The cone portion has the same base diameter as the frustum portion, 2.4 μm to 2.55 μm, and a height of 1.4 μm to 1.5 μm.

[0056] The cone section and the frustum section transition continuously, and the sidewalls of both form a smooth and continuous curved surface. The angle (α) between the line connecting the vertex and the bottom of the sidewall of the cone structure and the horizontal plane is 52°~54°.

[0057] Specifically, the pits are arranged in an array, with a bowl-shaped shape. Their depth direction is parallel to the axis of the cone portion, that is, their depth direction is perpendicular to the substrate surface. The pit depth is 90 nm, and the opening width (diameter) is 150 nm to 180 nm. The distance between adjacent pits is 250 nm.

[0058] The high-efficiency LED chip in this embodiment further includes a first semiconductor layer (N-type GaN layer), an active layer (InGaN-GaN multiple quantum well layer), a second semiconductor layer (P-type GaN layer), and a reflective layer (Ag layer) sequentially stacked on a substrate and a conical structure, as well as a first electrode and a second electrode. The first electrode is electrically connected to the second semiconductor layer, and the second electrode is connected to the first semiconductor layer. That is, the high-efficiency LED chip in this embodiment has a flip-chip structure.

[0059] Example 2 This embodiment provides a high-efficiency LED chip, which includes a substrate (sapphire substrate) and a conical structure. The conical structure includes a frustum portion (Al2O3 material) at the bottom and a cone portion (SiO2 material) at the top, and multiple pits are formed on the cone portion.

[0060] The frustum portion has a base diameter of 2.9 μm to 3.1 μm and a height of 0.42 μm, while its top diameter is 2.4 μm to 2.55 μm. The cone portion has the same base diameter as the frustum portion, 2.4 μm to 2.55 μm, and a height of 1.4 μm to 1.5 μm.

[0061] The cone section and the frustum section transition continuously, and the sidewalls of both form a smooth and continuous curved surface. The angle (α) between the line connecting the vertex and the bottom of the sidewall of the cone structure and the horizontal plane is 52°~54°.

[0062] Specifically, the pits are distributed in an array, are bowl-shaped, and their depth direction forms a certain angle with the axis of the cone (see reference). Figure 4 The pits (β1, β2, β3) have an angle of 46.5° to 68.5°. The pit depth is 90 nm, and the opening width (diameter) is 150 nm to 180 nm. The distance between adjacent pits is 250 nm.

[0063] The high-efficiency LED chip in this embodiment further includes a first semiconductor layer (N-type GaN layer), an active layer (InGaN-GaN multiple quantum well layer), a second semiconductor layer (P-type GaN layer), and a reflective layer (Ag layer) sequentially stacked on a substrate and a conical structure, as well as a first electrode and a second electrode. The first electrode is electrically connected to the second semiconductor layer, and the second electrode is connected to the first semiconductor layer. That is, the high-efficiency LED chip in this embodiment has a flip-chip structure.

[0064] Example 3 This embodiment provides a high-efficiency LED chip, which includes a substrate (sapphire substrate) and a conical structure. The conical structure includes a frustum portion (Al2O3 material) at the bottom and a cone portion (SiO2 material) at the top, and multiple pits are formed on the cone portion.

[0065] The frustum portion has a base diameter of 2.9 μm to 3.1 μm and a height of 0.42 μm, while its top diameter is 2.4 μm to 2.55 μm. The cone portion has the same base diameter as the frustum portion, 2.4 μm to 2.55 μm, and a height of 1.4 μm to 1.5 μm.

[0066] The cone section and the frustum section transition continuously, and the sidewalls of both form a smooth and continuous curved surface. The angle (α) between the line connecting the vertex and the bottom of the sidewall of the cone structure and the horizontal plane is 52°~54°.

[0067] Specifically, the depth direction of the pit forms a certain angle with the axis of the cone (see...). Figure 4 The pits (β1, β2, β3) have an angle of 46.5° to 68.5°. The pit depth is 90 nm, and its opening width (diameter) is 150 nm to 180 nm. The distance between adjacent pits is 250 nm. The pits extend circumferentially along the cone portion and are connected end-to-end, forming a continuous annular groove structure on a cross-section parallel to the substrate surface. Raised strips are formed between adjacent pits. The width of the raised strips is 250 nm, and their height is 120 nm.

[0068] The high-efficiency LED chip in this embodiment further includes a first semiconductor layer (N-type GaN layer), an active layer (InGaN-GaN multiple quantum well layer), a second semiconductor layer (P-type GaN layer), and a reflective layer (Ag layer) sequentially stacked on a substrate and a conical structure, as well as a first electrode and a second electrode. The first electrode is electrically connected to the second semiconductor layer, and the second electrode is connected to the first semiconductor layer. That is, the high-efficiency LED chip in this embodiment has a flip-chip structure.

[0069] Examples 1-3 and LED chips based on conventional SPSS were tested, and the brightness improvement rate and dislocation density reduction rate were calculated using conventional SPSS as a benchmark. It should be noted that during the dislocation density measurement, the first semiconductor layer was etched down, and its dislocation density was measured. Specific results are shown in the table below:

[0070] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with the described embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0071] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A high-efficiency LED chip, characterized in that, include: Substrate; A conical structure disposed on the surface of the substrate, the conical structure including a frustum portion at the bottom and a cone portion at the top; the refractive index of the cone portion is less than the refractive index of the frustum portion; The cone-shaped portion has multiple pits with a depth of 50nm to 500nm.

2. The high-efficiency LED chip as described in claim 1, characterized in that, The opening width of the pit is 100nm~500nm, and the depth is 50nm~300nm; The distance between adjacent pits is 150nm~350nm.

3. The high-efficiency LED chip as described in claim 1, characterized in that, The recess extends circumferentially along the cone portion and connects end to end to form an annular groove; A raised strip is formed between adjacent annular grooves.

4. The high-efficiency LED chip as described in claim 3, characterized in that, The height of the raised strip is 100nm~400nm, and its width is 80nm~300nm.

5. The high-efficiency LED chip as described in claim 3, characterized in that, The distance between adjacent raised strips conforms to the following relationship: 0.5λ≤nD≤1.5λ; Where λ is the emission wavelength of the high-efficiency LED chip, D is the distance between adjacent protrusions, and n is a constant with a value range of 1.2 to 1.

4.

6. The high-efficiency LED chip according to any one of claims 1 to 5, characterized in that, The substrate is a sapphire substrate, the frustum portion is made of the same material as the substrate, and the cone portion is made of silicon oxide; The diameter of the bottom surface of the frustum is 2μm~3.5μm, the diameter of its top surface is 1.2μm~2.7μm, and the height is 0.1μm~1μm; The diameter of the bottom surface of the cone portion is 1.2μm to 2.7μm, and its height is 1μm to 2μm.

7. The high-efficiency LED chip according to any one of claims 1 to 5, characterized in that, The sidewalls of the cone structure are arc-shaped; the angle between the line connecting the apex and the bottom of the sidewall and the horizontal plane is 30° to 70°.

8. A method for fabricating a high-efficiency LED chip, characterized in that, include: Provide substrate; A dielectric layer is formed on the substrate; The dielectric layer and the substrate are etched to form a conical structure, resulting in an intermediate body; wherein the conical structure includes a frustum at the bottom and a cone at the top; the refractive index of the cone is less than that of the frustum. Multiple pits are formed on the conical portion; wherein the depth of the pits is 50nm~500nm.

9. The method for preparing a high-efficiency LED chip as described in claim 8, characterized in that, The step of etching the dielectric layer and the substrate to form a cone structure and obtain the intermediate includes: A photoresist layer is formed on the dielectric layer; the thickness of the photoresist layer is 1μm~3μm. The photoresist layer is exposed and developed to form multiple photoresist cylinders; the diameter of the photoresist cylinders is 2μm~3.5μm, and their period is 2.5μm~4.5μm; The dielectric layer is etched by RIE etching process to form a dielectric layer cylinder; wherein the process parameters of RIE etching process include: the etching gas is CHF3 and CF4, the volume ratio of CHF3 to CF4 is 8:1~12:1, the pressure is 20mtorr~50mtorr, and the power is 200W~500W. The substrate is etched using an ICP etching process to form a substrate cylinder; wherein the process parameters of the ICP etching process include: the etching gases are BCl3 and SF6, the volume ratio of BCl3 to SF6 is 1:0.5 to 1:1.5, the ICP power is 1000W to 1400W, the RF power is 300W to 600W, and the pressure is 3mtorr to 10mtorr; The cylindrical dielectric layer is etched using an ICP etching process to form a conical portion. The process parameters for the ICP etching process include: etching gases of CHF3, CF4, and Ar, with a volume ratio of CHF3, CF4, and Ar of 8:3:15 to 12:6:25; ICP power of 500W to 1000W; RF power of 200W to 400W; and pressure of 10mtorr to 25mtorr. The substrate cylinder is etched using an ICP etching process to form a frustum-shaped portion, resulting in a cone structure. The process parameters for the ICP etching process include: etching gases of BCl3, SF6, and Ar, with a volume ratio of BCl3, SF6, and Ar of 5:1:10 to 10:3:20; ICP power of 800W to 1400W; RF power of 300W to 600W; and pressure of 5mtorr to 15mtorr. Remove the remaining photoresist layer to obtain the intermediate.

10. The method for preparing a high-efficiency LED chip as described in claim 8, characterized in that, The step of forming multiple pits on the conical portion includes: A metal mask layer is formed and patterned on the intermediate body; The cone portion is etched by an ion beam etching process to form a pit; wherein the process parameters of the ion beam etching process include an ion energy of 400eV~600eV, an ion beam current of 80mA~150mA, an etching gas of Ar and CF4 with a volume ratio of Ar to CF4 of 0.8:1~1.2:1, and a pressure of 0.01Pa~0.05Pa. Remove the remaining metal mask layer.

Images