Light emitting diode chip and method of manufacturing the same

Abstract

The present disclosure provides a light emitting diode chip and a preparation method thereof, and belongs to the technical field of semiconductor preparation. The light emitting diode chip comprises an epitaxial layer, a bonding layer and a substrate. The bonding layer is located between the epitaxial layer and the substrate. The outer edge of the bonding layer has a recessed groove. The recessed groove extends around the outer edge of the bonding layer. The depth of the recessed groove is at most 2 µm. The present disclosure can improve the preparation yield of the light emitting diode chip.

Description

Technical Field

[0001] This disclosure belongs to the field of semiconductor fabrication technology, and specifically relates to a light-emitting diode chip and its fabrication method. Background Technology

[0002] Mini LED (Mini Light Emitting Diode) is a new type of light-emitting diode. Due to its extremely small size, it can be arranged more densely when applied to displays, thereby significantly improving the resolution of the display.

[0003] In fabricating Micro LEDs that include red light chips, the red light epitaxial layer (such as aluminum gallium indium phosphide) is relatively brittle and typically needs to be transferred and bonded to a transparent substrate using a bonding layer. In related technologies, during ISO etching, the epitaxial layer and the underlying bonding layer are etched together.

[0004] However, due to the isotropic nature of the etching process and differences in material selectivity, the bonding layer typically experiences significant lateral shrinkage, generally reaching around 5 micrometers, leaving the edges of the upper epitaxial layer suspended. During the subsequent photoresist removal process, the strong physical impact of the photoresist remover can easily cause damage and chipping of the suspended epitaxial layer edges, especially the sharp corners, resulting in low chip yield. Summary of the Invention

[0005] This disclosure provides a light-emitting diode (LED) chip and its fabrication method, which can improve the fabrication yield of LED chips. The technical solution is as follows: In a first aspect, embodiments of this disclosure provide a light-emitting diode chip, comprising: an epitaxial layer, a bonding layer, and a substrate; The bonding layer is located between the epitaxial layer and the substrate. The outer edge of the bonding layer has an inward groove that extends around the outer edge of the bonding layer. The depth of the inward groove is at most 2µm.

[0006] In one implementation of this disclosure, the bottom of the recessed groove is an arc surface or a plane; In the epitaxial growth direction, the depth of the recessed groove gradually decreases from the substrate to the epitaxial layer.

[0007] In one implementation of this disclosure, at the junction of the bonding layer and the epitaxial layer, the outer edge of the bonding layer and the outer edge of the epitaxial layer are flush.

[0008] In one implementation of this disclosure, when the bottom of the recessed groove is an arc surface, the tangent at the connection between the bonding layer and the substrate is perpendicular to the substrate.

[0009] In one implementation of this disclosure, the epitaxial layer has an outer edge; The outer edge is a rounded chamfer with a radius of 8~12µm.

[0010] Secondly, embodiments of this disclosure provide a method for fabricating a light-emitting diode chip, comprising: Preparation of epitaxial layer; A bonding layer is prepared on one side of the epitaxial layer; Provide a substrate; The epitaxial layer is bonded to the substrate via the bonding layer; The epitaxial layer and the bonding layer are etched sequentially to form an inward groove at the outer edge of the bonding layer, wherein the inward groove extends around the outer edge of the bonding layer and the depth of the inward groove is at most 2µm.

[0011] In one implementation of this disclosure, etching the bonding layer includes: Continuously monitor the set emission wavelength, where the set emission wavelength is the emission wavelength of the corresponding element of the substrate; When the set emission wavelength is detected, the etching process is stopped after a delay of 50-70 seconds.

[0012] In one implementation of this disclosure, sequentially etching the epitaxial layer (10) and the bonding layer (70) includes: The epitaxial layer (10) is etched, and the etching gas is set to Cl2 and BCl3, wherein the flow rate of Cl2 gas is 70~90 sccm, the flow rate of BCl3 gas is 30~50 sccm, the source power is set to 500~700W, and the bias power is set to 200~400W. The bonding layer (70) is etched, and the etching gas is set to CF2 and O2, wherein the flow rate of CF2 gas is 10~30 sccm, the flow rate of O2 gas is 10~20 sccm, the source power is set to 100~200W, and the bias power is set to 50~150W.

[0013] In one implementation of this disclosure, etching the bonding layer further includes: At the junction of the bonding layer and the epitaxial layer, the outer edge of the bonding layer is flush with the outer edge of the epitaxial layer.

[0014] In one implementation of this disclosure, before sequentially etching the epitaxial layer and the bonding layer, the method includes: A photomask is provided, wherein the outer corners of the photomask are rounded chamfers with a radius of 8~12µm; A photoresist layer is prepared on one side of the epitaxial layer based on the photomask; The epitaxial layer is etched based on the photoresist layer so that the outer edges of the epitaxial layer are rounded chamfers with a radius of 8~12µm.

[0015] The beneficial effects of the technical solutions provided in this disclosure include at least the following: In the LED chip provided in this embodiment, the depth of the recessed groove at the outer edge of the bonding layer is set to a maximum of 2µm. Compared to the approximately 5µm recess in related technologies, this effectively reduces the volume of lateral hollowing out, allowing the physical boundary of the bonding layer to extend further outward. This change in the bonding layer morphology improves the situation where the outer edge of the epitaxial layer above the bonding layer is suspended, fundamentally reducing the bending moment generated at the edge of the epitaxial layer under stress. This allows the bonding layer to provide a more robust bottom mechanical support for the epitaxial layer, effectively preventing edge breakage of the brittle epitaxial layer when subjected to high-pressure resist removal, significantly improving the manufacturing yield of the LED chip. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of the light-emitting diode chip provided in the embodiments of this disclosure; Figure 2 This is provided by the embodiments of this disclosure. Figure 1 A magnified view of a portion of the image; Figure 3 This is a top view of the light-emitting diode chip provided in the embodiments of this disclosure; Figure 4 This is a flowchart illustrating a method for fabricating a light-emitting diode chip according to an embodiment of this disclosure; Figure 5 This is a flowchart of another method for fabricating a light-emitting diode chip provided in this embodiment.

[0018] The symbols in the diagram represent the following meanings: 10. Epitaxial layer; 10a, outer edge; 110, first semiconductor layer; 120, active layer; 130, second semiconductor layer; 140, mesa trench; 210. First electrode; 220. Second electrode; 30. Passivation layer; 410, First pad; 420, Second pad; 50. Protective layer; 60. Substrate; 70. Bonding layer; 710. Inner recessed groove.

[0019] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0021] This disclosure provides a light-emitting diode chip. Figure 1 This is a schematic diagram of the structure of a light-emitting diode chip, combined with... Figure 1 In this embodiment, the light-emitting diode chip includes an epitaxial layer 10, a bonding layer 70, and a substrate 60.

[0022] The bonding layer 70 is located between the epitaxial layer 10 and the substrate 60. The outer edge of the bonding layer 70 has an inward groove 710. The inward groove 710 extends around the outer edge of the bonding layer 70. The depth of the inward groove 710 is at most 2µm. The depth of the inward groove 710 is the distance from the bottom of the groove to the opening of the groove 710 in a direction perpendicular to the epitaxial growth direction.

[0023] In the light-emitting diode chip provided in this embodiment, the depth of the recessed groove 710 at the outer edge of the bonding layer 70 is set to at most 2µm. Compared with the approximately 5µm recess in related technologies, this effectively reduces the volume of the laterally hollowed-out portion, allowing the physical boundary of the bonding layer 70 to extend further outward. This change in the shape of the bonding layer 70 improves the situation where the outer edge of the epitaxial layer 10 above the bonding layer 70 is suspended, fundamentally reducing the bending moment generated at the edge of the epitaxial layer 10 under stress. As a result, the bonding layer 70 can provide a more robust bottom mechanical support for the epitaxial layer 10, effectively preventing the brittle epitaxial layer 10 from fracturing at the edge when subjected to high-pressure impact from subsequent resist removal, significantly improving the manufacturing yield of the light-emitting diode chip.

[0024] It is worth noting that the direction of epitaxial growth, that is... Figure 1 Direction A in the figure represents the growth direction of the epitaxial layer 10 and is perpendicular to the substrate 60. The depth of the recessed groove 710 is perpendicular to the epitaxial growth direction, that is... Figure 1The B direction is parallel to the substrate 60.

[0025] Figure 2 for Figure 1 The enlarged view shows that, in this embodiment, the bottom of the recessed groove 710 is an arc surface or a plane. In the epitaxial growth direction, the depth of the recessed groove 710 gradually decreases from the substrate 60 to the epitaxial layer 10.

[0026] In the above implementation, the gradually decreasing depth of the recessed groove 710 along the epitaxial growth direction results in the bonding layer 70 exhibiting a "narrow at the bottom and wide at the top" physical form. This form causes the bonding layer 70 to extend outward most near the top region of the epitaxial layer 10, making the physical contact surface closest to the outer boundary of the chip. In this way, the morphology of the bonding layer 70 effectively fills the gap below the edge of the epitaxial layer 10 mechanically, eliminating the "suspended" state at the bottom edge of the epitaxial layer 10 and providing direct and solid rigid support for its most vulnerable boundary area. This effectively resists and disperses bending moments when facing external fluid mechanical stress impacts such as resist removal, reducing the risk of chip breakage and corner chipping.

[0027] In this embodiment, at the junction of the bonding layer 70 and the epitaxial layer 10, the outer edge of the bonding layer 70 is flush with the outer edge of the epitaxial layer 10.

[0028] In the above-mentioned technical method, the tight bonding of the two materials at the boundary is ensured. This interface bonding effectively relieves the stress in the region, so that the external load applied to the edge of the epitaxial layer 10 can be directly and uniformly transmitted downward and dissipated into the bonding layer 70, without forming a stress singularity at the interface.

[0029] For example, when the bottom of the recessed groove 710 is an arc surface, the tangent at the connection between the bonding layer 70 and the substrate 60 is perpendicular to the substrate 60.

[0030] In the above implementation, the bonding layer 70 has a vertical landing shape at the bottom, rather than contracting inward at an acute angle or extending outward at an obtuse angle. This vertical physical shape effectively avoids severe stress concentration at the junction between the bonding layer 70 and the substrate 60, and ensures that the bonding layer 70 has sufficient effective adhesion area at its bottom base.

[0031] Figure 3 This is a top view of a light-emitting diode chip, combined with... Figure 3 In this embodiment, the epitaxial layer 10 has an outer edge 10a, which is a rounded chamfer with a radius of 8~12µm.

[0032] In the above implementation, the outer edge of the epitaxial layer 10 is made smoother in terms of physical morphology. The smoother outer edge 10a of the epitaxial layer 10, compared with the sharp outer edge 10a in related technologies, can have a better hydrodynamic buffering effect, allowing the high-pressure liquid flow during wet desizing to glide smoothly, effectively dispersing and releasing the stress concentration phenomenon that is originally very easy to accumulate at sharp angles.

[0033] See you again Figure 1 In this embodiment, the epitaxial layer 10 includes a first semiconductor layer 110, an active layer 120, and a second semiconductor layer 130 stacked sequentially. The epitaxial layer 10 has a mesa trench 140, which extends from the second semiconductor layer 130 to the first semiconductor layer 110 along the epitaxial growth direction.

[0034] See you again Figure 1 In this embodiment, one of the first semiconductor layer 110 and the second semiconductor layer 130 is a p-type layer, and the other of the first semiconductor layer 110 and the second semiconductor layer 130 is an n-type layer.

[0035] In this embodiment, the first semiconductor layer 110 is a p-type layer and the second semiconductor layer 130 is an n-type layer.

[0036] For example, the first semiconductor layer 110 is a p-type AlInP layer, and the second semiconductor layer 130 is an n-type AlGaInP layer.

[0037] In this embodiment, the active layer 120 is a multi-quantum-well layer, comprising alternating AlGaInP quantum well layers and AlGaInP quantum barrier layers, wherein the Al content in the AlGaInP quantum well layers and AlGaInP quantum barrier layers is different. The active layer 120 may include 3 to 8 alternating stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0038] See also Figure 1 In this embodiment, the light-emitting diode chip further includes a first electrode 210, a second electrode 220, and a passivation layer 30. The surface of the second semiconductor layer 130 has a groove that exposes the first semiconductor layer 110. The first electrode 210 is located in the groove, and the second electrode 220 is located on the surface of the second semiconductor layer 130 away from the multiple quantum well layer. The passivation layer 30 is located at least on the surface of the second semiconductor layer 130, the bottom surface of the groove, the surface of the first electrode 210, and the surface of the second electrode 220.

[0039] In this embodiment, the first electrode 210 is a p-type electrode and the second electrode 220 is an n-type electrode.

[0040] For example, the passivation layer 30 can be a distributed Bragg reflection (DBR), which includes multiple periodically alternating layers of SiO2 and TiO2. The number of periods in the distributed Bragg reflection can be between 20 and 50.

[0041] In this embodiment, the number of periods of the distributed Bragg reflector is 32.

[0042] In addition to its passivation function, the distributed Bragg reflector is also used to reflect light emitted from the active layer 120 toward the distributed Bragg reflector back to the epitaxial layer 10, thereby improving the light output effect.

[0043] In this embodiment, the first pad 410 and the second pad 420 are located on the passivation layer 30. The first pad 410 is connected to the first electrode 210 through a through hole, and the second pad 420 is connected to the second electrode 220 through another through hole.

[0044] In this embodiment, the light-emitting diode chip further includes a protective layer 50, which covers the surface of the passivation layer 30 and extends from the surface of the passivation layer 30 to the side of the epitaxial layer 10. The protective layer 50 has through holes exposing the first pad 410 and the second pad 420 to facilitate electrical connection.

[0045] For example, the protective layer 50 is a SiO2 layer.

[0046] Figure 4 This is a flowchart illustrating a method for fabricating a light-emitting diode chip according to an embodiment of the present disclosure, in conjunction with... Figure 4 In this embodiment, the preparation method includes: Step 401: Prepare epitaxial layer 10.

[0047] Step 402: Prepare a bonding layer 70 on one side of the epitaxial layer 10.

[0048] Step 403: Provide a substrate 60.

[0049] Step 404: Bond the epitaxial layer 10 to the substrate 60 via the bonding layer 70.

[0050] Step 405: Etch the epitaxial layer 10 and the bonding layer 70 sequentially, so that the outer edge of the bonding layer 70 forms an inward groove 710.

[0051] The recessed groove 710 extends around the outer edge of the bonding layer 70. The depth of the recessed groove 710 is at most 2µm. The depth of the recessed groove 710 is the distance from the bottom of the recessed groove 710 to the opening of the recessed groove 710 in a direction perpendicular to the epitaxial growth direction.

[0052] In the light-emitting diode chip prepared according to the embodiments of this disclosure, the depth of the recessed groove at the outer edge of the bonding layer is set to a maximum of 2µm. Compared with the approximately 5µm recess in related technologies, this effectively reduces the volume of lateral hollowing out, allowing the physical boundary of the bonding layer to extend further outward. This change in the morphology of the bonding layer improves the problem of the outer edge of the epitaxial layer above the bonding layer being suspended, fundamentally reducing the bending moment generated at the edge of the epitaxial layer under stress. This allows the bonding layer to provide a more robust bottom mechanical support for the epitaxial layer, effectively preventing the brittle epitaxial layer from fracturing at the edges when subjected to high-pressure resist removal, significantly improving the manufacturing yield of the light-emitting diode chip.

[0053] Figure 5 A flowchart illustrating another method for fabricating a light-emitting diode chip provided in this disclosure, in conjunction with... Figure 5 In this embodiment, the preparation method includes: Step 501: Provide a GaAs substrate.

[0054] Step 502: Prepare an epitaxial layer 10 on one side of the GaAs substrate.

[0055] In this embodiment, the epitaxial layer 10 includes a first semiconductor layer 110, an active layer 120, and a second semiconductor layer 130 stacked sequentially.

[0056] In this embodiment, the first semiconductor layer 110 is a p-type layer and the second semiconductor layer 130 is an n-type layer.

[0057] For example, the first semiconductor layer 110 is a p-type AlInP layer, and the second semiconductor layer 130 is an n-type AlGaInP layer.

[0058] In this embodiment, the active layer 120 includes alternating AlGaInP quantum well layers and AlGaInP quantum barrier layers, with different Al contents in the AlGaInP quantum well layers and AlGaInP quantum barrier layers. The active layer 120 may include 3 to 8 alternating stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0059] For example, the active layer 120 includes five alternating stacked AlGaInP quantum well layers and AlGaInP quantum barrier layers.

[0060] Step 503: Provide a sapphire substrate 60.

[0061] In the above implementation, since the sapphire substrate 60 has high light transmittance and the sapphire material is relatively hard and has relatively stable chemical properties, the use of the sapphire substrate 60 can enable the light-emitting diode to have good light-emitting effect and stability.

[0062] Step 504: The epitaxial layer 10 is bonded to the sapphire substrate 60 through the bonding layer 70, and the GaAs wafer is removed to obtain the epitaxial wafer.

[0063] For example, in step 504, a silicon oxide liquid is coated on the surface of the first semiconductor layer 110, and a sapphire substrate 60 is placed on the surface of the first semiconductor layer 110. The silicon oxide liquid is heated and cured to form a bonding layer 70 between the first semiconductor layer 110 and the sapphire substrate 60.

[0064] For example, the heating and curing temperature is between 250°C and 350°C. In this embodiment, the heating temperature can be 300°C.

[0065] Step 505: Etch epitaxial layer 10 and bonding layer 70 sequentially.

[0066] In this embodiment, step 505 includes: Step 5051: Prepare the photoresist layer.

[0067] In this embodiment, step 5051 includes: First, a mask is provided, wherein the outer corners of the mask are rounded chamfers with a radius of 8~12µm.

[0068] In this embodiment, the radius of the rounded chamfer is 10µm.

[0069] Then, a photoresist layer is prepared on one side of the epitaxial layer 10 based on the photomask.

[0070] Step 5052: Etch the epitaxial layer 10.

[0071] Since the epitaxial layer 10 is etched based on the photoresist layer, the outer edge 10a of the epitaxial layer 10 is rounded with a radius of 8~12µm.

[0072] For example, the etching gases are set to Cl2 and BCl3, wherein the flow rate of Cl2 gas is 70~90 sccm and the flow rate of BCl3 gas is 30~50 sccm, the source power is set to 500~700W, and the bias power is set to 200~400W.

[0073] In this embodiment, the flow rate of Cl2 gas is 80 sccm, the flow rate of BCl3 gas is 40 sccm, the source power is set to 600W, and the bias power is set to 300W.

[0074] The higher radio frequency power (600W / 300W) makes the downward bombardment of ions stronger, which can ensure the verticality of the sidewalls of the epitaxial layer 10.

[0075] Step 5053: Etch the bonding layer 70.

[0076] During the etching of the bonding layer 70, a set emission wavelength is continuously monitored. The set emission wavelength is the emission wavelength of the corresponding element of the substrate. When the set emission wavelength is detected, etching is stopped after a delay of 50-70 seconds.

[0077] In the above implementation, since the substrate is a sapphire substrate, the corresponding element is Al. An optical emission spectrometer (OES) is used to capture the emission wavelength of Al. When the emission wavelength of Al is captured, it indicates that the substrate has been etched in the vertical direction. Etching is not stopped immediately, but delayed for 50-70 seconds. This utilizes the characteristic that sapphire is difficult to etch with plasma, causing the etching direction to change from vertical to horizontal, thus achieving lateral etching of the bonding layer 70. During the 50-70 seconds of lateral etching, indentation grooves 710 are formed on the sidewalls of the bonding layer 60, with a maximum depth of 2µm.

[0078] For example, the etching gases are set to CF2 and O2, wherein the flow rate of CF2 gas is 10~30 sccm, the flow rate of O2 gas is 10~20 sccm, the source power is set to 100~200W, and the bias power is set to 50~150W.

[0079] In this embodiment, the flow rate of CF2 gas is 20 sccm, the flow rate of O2 gas is 15 sccm, the source power is set to 150W, and the bias power is set to 100W.

[0080] In the above implementation, due to the lower RF power (150W / 100W), the downward physical bombardment force is weakened, and the chemical isotropic etching by the etching gas begins to dominate. Combined with a delay time of 50-70 seconds, the area where the etching gas resides for the longest time at the bottom is etched the deepest, thus forming a sloping / arc-shaped recessed groove 710 with a larger inward base and a smaller inward top. Exemplarily, after etching the outer wall of the bonding layer 70, at the junction of the bonding layer 70 and the epitaxial layer 10, the outer edge of the bonding layer 70 is flush with the outer edge of the epitaxial layer 10.

[0081] Step 506: Fabricate the first electrode 210 and the second electrode 220.

[0082] For example, the first electrode 210 is mainly composed of AuBe, and the second electrode 220 is mainly composed of AuGe.

[0083] Step 507: Prepare passivation layer 30.

[0084] For example, the passivation layer 30 is a distributed Bragg reflector.

[0085] Step 508: Prepare a first pad 410 and a second pad 420 on the surface of the passivation layer 30.

[0086] The first pad 410 penetrates the passivation layer 30 and is connected to the first electrode 210, and the second pad 420 penetrates the passivation layer 30 and is connected to the second electrode 220.

[0087] Step 509: Prepare a protective layer 50 on the surface of the passivation layer 30.

[0088] For example, the protective layer 50 is a SiO2 layer.

[0089] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” etc., are used only to indicate relative positional relationships; when the absolute position of the described objects changes, the relative positional relationship may also change accordingly.

[0090] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A light-emitting diode chip, characterized in that, include: Epitaxial layer (10), bonding layer (70) and substrate (60); The bonding layer (70) is located between the epitaxial layer (10) and the substrate (60). The outer edge of the bonding layer (70) has a recessed groove (710) that extends around the outer edge of the bonding layer (70) and has a depth of up to 2µm.

2. The light-emitting diode chip according to claim 1, characterized in that, The bottom of the recessed groove (710) is an arc surface or a plane; In the epitaxial growth direction, the depth of the recessed groove (710) gradually decreases from the substrate (60) to the epitaxial layer (10).

3. The light-emitting diode chip according to claim 2, characterized in that, At the junction of the bonding layer (70) and the epitaxial layer (10), the outer edge of the bonding layer (70) is flush with the outer edge of the epitaxial layer (10).

4. The light-emitting diode chip according to claim 2, characterized in that, When the bottom of the recessed groove (710) is an arc surface, the tangent at the connection between the bonding layer (70) and the substrate (60) is perpendicular to the substrate (60).

5. The light-emitting diode chip according to claim 1, characterized in that, The epitaxial layer (10) has an outer edge (10a); The outer edge (10a) is a rounded chamfer with a radius of 8~12µm.

6. A method for fabricating a light-emitting diode chip, characterized in that, include: Prepare an epitaxial layer (10); A bonding layer (70) is prepared on one side of the epitaxial layer (10); A substrate (60) is provided; The epitaxial layer (10) is bonded to the substrate (60) through the bonding layer (70); The epitaxial layer (10) and the bonding layer (70) are etched sequentially, so that an indentation groove (710) is formed on the outer edge of the bonding layer (70), wherein the indentation groove (710) extends around the outer edge of the bonding layer (70), and the depth of the indentation groove (710) is at most 2µm.

7. The preparation method according to claim 6, characterized in that, Etching the bonding layer (70) includes: Continuously monitor the set emission wavelength, where the set emission wavelength is the emission wavelength of the corresponding element of the substrate; When the set emission wavelength is detected, the etching process is stopped after a delay of 50-70 seconds.

8. The preparation method according to claim 6, characterized in that, Etching the epitaxial layer (10) and the bonding layer (70) sequentially includes: The epitaxial layer (10) is etched, and the etching gas is set to Cl2 and BCl3, wherein the flow rate of Cl2 gas is 70~90 sccm, the flow rate of BCl3 gas is 30~50 sccm, the source power is set to 500~700W, and the bias power is set to 200~400W. The bonding layer (70) is etched, and the etching gas is set to CF2 and O2, wherein the flow rate of CF2 gas is 10~30 sccm, the flow rate of O2 gas is 10~20 sccm, the source power is set to 100~200W, and the bias power is set to 50~150W.

9. The preparation method according to claim 8, characterized in that, Etching the bonding layer (70) further includes: At the junction of the bonding layer (70) and the epitaxial layer (10), the outer edge of the bonding layer (70) is flush with the outer edge of the epitaxial layer (10).

10. The preparation method according to claim 6, characterized in that, Before sequentially etching the epitaxial layer (10) and the bonding layer (70), the process includes: A photomask is provided, wherein the outer corners of the photomask are rounded chamfers with a radius of 8~12µm; A photoresist layer is prepared on one side of the epitaxial layer (10) based on the photomask; The epitaxial layer (10) is etched based on the photoresist layer so that the outer edge (10a) of the epitaxial layer (10) is a rounded chamfer, and the radius of the rounded chamfer is 8~12µm.

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