A manufacturing method for improving micro-led pixel density and display device

Abstract

The application provides a manufacturing method for improving MicroLED pixel density and a display device, and belongs to the technical field of semiconductor optoelectronic device manufacturing. The method comprises the following steps: mesa etching from the side of the potential transition layer of an LED epitaxial wafer to form isolation grooves and each pixel light-emitting mesa with a wide top and a narrow bottom; depositing an insulating layer and opening to form a metal layer continuously covering each mesa and groove, filling a dielectric and preparing an epitaxial side conductive column coplanar with the dielectric; wafer-level hybrid bonding of the conductive column and a CMOS driving wafer; after removing the substrate and the buffer layer, isolation etching from the n-type semiconductor layer with a wide top and a narrow bottom, aligning the narrow bottom with the wide opening of the reversed isolation groove, and cutting off the metal layer at the position to isolate adjacent pixels; filling insulating material and planarizing to form an N-type common electrode. The device is manufactured by the above method. The application can improve the effective light-emitting area ratio and light extraction efficiency, simplify the pre-bonding process, reduce the pixel spacing, and improve the pixel density.

Description

Technical Field

[0001] This application relates to the field of semiconductor optoelectronic device manufacturing technology, and in particular to a manufacturing method and display device for improving MicroLED pixel density. Background Technology

[0002] MicroLED, or micro-light-emitting diode display technology, is considered one of the core directions of next-generation display technology due to its advantages such as high brightness, high contrast, low power consumption, fast response speed, and long lifespan. Its applications cover AR / VR near-eye displays, smartwatches, automotive displays, and large-size splicing displays, among others.

[0003] Currently, the manufacturing of MicroLED display devices mainly faces two major technical challenges: limited pixel density and high process complexity. The pixel density of existing MicroLEDs is limited by the traditional mass transfer process, which involves transferring individual LED chips from the growth substrate one by one or in batches to the driving backplane. Due to limitations in transfer accuracy and chip size, it is difficult to further increase the pixel density. Especially in applications such as AR / VR, where high PPI is extremely urgent, existing processes cannot meet the requirements of ultra-high resolution.

[0004] The existing MicroLED manufacturing process is complex, involving multiple photolithography, etching, bonding and alignment processes. The process steps are numerous, the cost is high, and the yield control is difficult. Especially when realizing small-sized pixels, such as when the pixel pitch is less than 5um, the process window is extremely narrow.

[0005] In existing technologies, similar solutions include using wafer-level bonding to directly transfer the epitaxial layer onto the driver IC. However, this typically requires pixel isolation etching of the epitaxial layer before bonding, which increases the number of process steps and complexity before bonding, and also places high demands on the flatness of the bonding surface. Other solutions employ a bonding-then-processing approach, but these still have shortcomings in achieving high-density interconnects, forming effective pixel isolation, and establishing common electrode structures after bonding.

[0006] Therefore, existing MicroLED manufacturing methods have the following drawbacks: (1) Pixel density is limited. In traditional MicroLED manufacturing methods, the electrical isolation and electrical connection structures between pixels occupy a large area, resulting in a low effective light-emitting area ratio and making it difficult to further improve pixel density. (2) The process is complex and involves many steps. Existing solutions usually require pixel-level P and N electrode fabrication before epitaxial layer transfer, which requires multiple high-precision photolithography and alignment, resulting in high process complexity. (3) Bonding reliability and electrical connection quality are difficult to guarantee. Under ultra-high density pixel conditions, traditional bump bonding methods are difficult to apply to devices with submicron pixel pitch due to the limitations of bump size and spacing.

[0007] In summary, existing technologies suffer from several technical problems, including pixel density limitations due to the large area of ​​traditional electrical isolation and interconnect structures, high costs and low yields caused by complex manufacturing processes, and insufficient reliability of traditional bonding methods in ultra-high density pixel interconnects. Summary of the Invention

[0008] This invention provides a manufacturing method and display device for improving the pixel density of MicroLEDs. It can significantly improve the pixel density while simplifying the manufacturing process and improving the reliability of electrical connections, thus solving the technical problems of limited pixel density, high process complexity, and insufficient bonding reliability under ultra-high density conditions in the prior art.

[0009] 1. A method for manufacturing a MicroLED pixel density, characterized in that it comprises: S1, providing a CMOS driving wafer, wherein the bonding surface of the CMOS driving wafer is a coplanar planar structure composed of a dielectric layer and a driving substrate side conductive pillar embedded in the dielectric layer; S2, providing an LED epitaxial wafer, wherein the epitaxial wafer comprises a substrate and an n-type semiconductor layer, an active layer and a p-type semiconductor layer located above the substrate; etching the epitaxial layer from the p-type semiconductor layer side with a wide top and narrow bottom, etching through the p-type semiconductor layer and the active layer and extending into a portion of the n-type semiconductor layer to form an isolation groove, dividing the epitaxial layer into multiple light-emitting mesas, each corresponding to a pixel unit; forming an insulating layer on the surface of the etched mesa structure, the insulating layer having an opening at the top of each light-emitting mesa and remaining on the sidewall and bottom of the isolation groove; forming a metal layer on the surface of the mesa structure, the metal layer being electrically connected to the p-type semiconductor layer side of the light-emitting mesa through the opening, and continuously covering the insulating layer surface of the sidewall and bottom of the isolation groove in adjacent pixel units. The process involves maintaining continuity between pixels; forming a dielectric filling layer covering the metal layer, and forming epitaxial conductive pillars that penetrate the metal layer and are coplanar with the dielectric filling layer at corresponding positions of each pixel unit; S3, aligning the epitaxial side with the driving substrate side, and performing wafer-level hybrid bonding to form dielectric-dielectric bonding between dielectric surfaces and metal-metal bonding between the epitaxial conductive pillars and the driving substrate conductive pillars; S4, removing the substrate of the epitaxial wafer to expose the surface of the n-type semiconductor layer; S5, performing isolation etching with a wide top and narrow bottom on the exposed n-type semiconductor layer surface to etch through the n-type semiconductor layer, aligning the bottom of the formed isolation trench with the narrow opening of the isolation groove facing the light-emitting surface after flipping, and cutting off the insulating layer and the metal layer at the narrow opening at the connection point to achieve patterning of the metal layer, making the metal layers of each pixel unit independent and adjacent pixel units electrically isolated from each other; S6, filling the isolation trench with insulating material and planarizing it to form an N-type common electrode covering the surface of the n-type semiconductor layer of each pixel unit.

[0010] Preferably, the coplanar structure in step S1 is formed by depositing an insulating layer on the surface of the CMOS driving wafer and planarizing it, and then forming a driving substrate side conductive pillar that is coplanar with the insulating layer by etching through holes and filling with conductive material.

[0011] Preferably, the etching of the vias includes step-by-step Via etching: Via1 etching is performed in the transition region of the non-effective pixel area, and the etching depth does not penetrate the insulating layer to retain the bottom insulating medium; Via2 etching is performed in the effective pixel area and the pad area to penetrate the insulating layer and expose the top conductive pillar of the CMOS driver wafer; after sputtering a seed layer on the inner wall of each via and the surface of the insulating layer, conductive material is electroplated to fill it, and the excess conductive material and seed layer on the surface are removed by chemical mechanical polishing.

[0012] Preferably, the epitaxial wafer further includes a buffer layer located between the substrate and the n-type semiconductor layer and a potential transition layer located on the p-type semiconductor layer; the etching in step S2 also etches through the potential transition layer, the opening exposes the potential transition layer, and the metal layer forms an ohmic contact with the potential transition layer through the opening; the substrate and the buffer layer are removed in step S4.

[0013] Preferably, the insulating layer formed in step S2 includes a passivation layer and an insulating isolation layer deposited sequentially. The passivation layer is an Al2O3 thin film formed by atomic layer deposition or a SiN thin film formed by plasma-enhanced chemical vapor deposition, covering all exposed epitaxial layer sidewalls. The insulating isolation layer is a SiO2 layer or a SiON layer formed by plasma-enhanced chemical vapor deposition. The opening is formed by inductively coupled plasma etching.

[0014] Preferably, the metal layer in step S2 is a reflective metal stack, which includes an adhesion layer, a high reflectivity layer and a protective layer stacked sequentially. The adhesion layer is a Ni layer or a Cr layer, the high reflectivity layer is an Ag layer, and the protective layer is a Ti layer. The reflective metal stack also serves as the P electrode of the pixel unit, the bottom and sidewall reflectors, and the current conduction path to the epitaxial conductive pillar. In step S5, the reflective metal stack is etched using an ion beam etching process.

[0015] Preferably, the cross-section of the isolation groove in step S2 is V-shaped, U-shaped, or trapezoidal, and the light-emitting platform surrounded by it has a trapezoidal cross-section that is narrow on one side of the p-type semiconductor layer and wide on the deeper side of the n-type semiconductor layer; the cross-section of the isolation trench in step S5 is V-shaped, U-shaped, or inverted trapezoidal, and the width of its top is less than the center-to-center distance between adjacent pixel units.

[0016] Preferably, the wafer-level hybrid bonding in step S3 includes: performing plasma activation treatment on the epitaxial side surface and the driving substrate side surface; aligning the two sides with an alignment accuracy of submicron level; performing pre-bonding at room temperature to form initial bonding between the dielectric surfaces through van der Waals forces; and performing annealing treatment to form covalent bonding between the dielectric surfaces and metallic bonding between the metal surfaces through thermo-pressure diffusion.

[0017] Preferably, in step S4, at least one of mechanical polishing, chemical etching, and laser ablation is used to remove the substrate, and dry etching or wet etching is used to remove the buffer layer; in step S6, the planarization is chemical mechanical polishing thinning, so that the surface of the n-type semiconductor layer is flush with the trench filler to form a flat light-emitting surface.

[0018] Preferably, the N-type common electrode in step S6 is an ITO thin film formed by reactive plasma deposition and patterned by inductively coupled plasma etching; the manufacturing method further includes: sputtering a metal stack on the N-type common electrode and patterning it to form an electrode extension structure, the electrode extension structure being located above the isolation trench between adjacent pixel units.

[0019] Preferably, the cross-sectional shape of the metal stack of the electrode extension structure is any one of a regular trapezoid, an inverted trapezoid, a square, or a rectangle; the filling conductive material of the epitaxial conductive pillar and the driving substrate conductive pillar is Cu or W, and its seed layer is a Ti / Cu double-layer structure.

[0020] The present invention also provides a MicroLED display device prepared by the above method.

[0021] In summary, the beneficial effects of the present invention are as follows: In a typical embodiment, this invention organically combines Cu / SiO2 wafer-level hybrid bonding, a two-stage inverted triangle etching structure with a wide top and narrow bottom, and a process route of bonding first and then isolating. This overcomes the inherent bottlenecks of existing MicroLED manufacturing technologies: hybrid bonding achieves submicron-level alignment accuracy and can be as small as 1μm. 2The Cu-Cu bonding contact area described below replaces the traditional mass transfer and solder bump bonding, which are limited by bump size and spacing. It also ensures long-term reliable interconnection of the ultra-high density array with lower contact resistance and higher thermal stability. The grooves formed by Mesa etching, after being flipped and bonded, have their narrow ends facing the light-emitting surface and precisely aligned with the bottom of the front isolation etching trench. This compresses the projection width of the isolation structure on the light-emitting surface to the minimum allowed by the process, thereby maximizing the effective light-emitting area ratio. Furthermore, the inclined sidewalls of the two-stage etching facilitate both insulating material filling and conformal metal layer coverage, and also integrate with the Ni / Ag / Ti reflective stack. Together, they form an optical cavity that reflects lateral escape light back to the light-emitting direction, achieving a synergistic improvement in pixel density and light extraction efficiency. The pre-bonding and post-isolation process ensures that only P-electrode processing is required on the epitaxial side before bonding, maintaining a coplanar and flat Cu / SiO2 surface. This satisfies the stringent surface roughness requirements of hybrid bonding while significantly reducing the number of photolithography and alignment steps before bonding, lowering process complexity and cost while improving yield. Furthermore, a single Ni / Ag / Ti stack integrates P-type ohmic contacts, bottom and sidewall mirrors, and current conduction functions, replacing three independent metal layers in traditional solutions with a single metal layer, in conjunction with ALD. The Al2O3 high-conformity passivation layer effectively passivates the sidewalls of the active area with an increased proportion of small-sized pixels to suppress non-radiative recombination. Combined with stepwise Via etching on the driving substrate side, differentiated electrical connections between different functional areas are achieved in the same dielectric layer. Together, these technologies enable the device to achieve a pixel pitch of less than 5μm and a pixel density of over 5000PPI while maintaining a compact structure and thinner thickness. This represents a significant technological advancement and fully meets the ultra-high resolution requirements of AR / VR near-eye displays. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of the initial structure of the CMOS driver wafer and the cross-section after planarization by PECVD SiO2 deposition, provided in an embodiment of the present invention.

[0023] Figure 2 This is a schematic diagram of the cross-section of the drive substrate side Via1 and Via2 after step-by-step etching, as provided in an embodiment of the present invention.

[0024] Figure 3 This is a schematic cross-sectional view of the Ti / Cu seed layer sputtering and Cu-filled planarization on the driving substrate side, as provided in an embodiment of the present invention.

[0025] Figure 4 This is a schematic cross-sectional view of the epitaxial side after inverted triangular Mesa etching, and after ALD Al2O3 and PECVD SiO2 passivation insulating layer deposition and ICP etching opening, provided in an embodiment of the present invention.

[0026] Figure 5This is a schematic cross-sectional view of the Ni / Ag / Ti reflective metal layer after sputtering and SiO2 dielectric filling, provided for an embodiment of the present invention.

[0027] Figure 6 This is a schematic cross-sectional view of the epitaxial side after Via3 etching and Cu conductive pillar filling planarization, as provided in an embodiment of the present invention.

[0028] Figure 7 This is a cross-sectional schematic diagram of the completed hybrid bonding according to an embodiment of the present invention.

[0029] Figure 8 This is a schematic cross-sectional view of the pixel isolation after substrate removal and front-side RE etching, as provided in an embodiment of the present invention.

[0030] Figure 9 This is a schematic cross-sectional view of the RE trench filling and thinning and ITO co-electrode deposition provided in an embodiment of the present invention.

[0031] Figure 10 This is a schematic diagram of the final device cross-section after the formation of the Ti / Al / TiN electrode extended structure provided in the embodiment of the present invention. Detailed Implementation

[0032] The following description and accompanying drawings fully illustrate specific embodiments of this application to enable those skilled in the art to practice them. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operations may vary. Parts and features of some embodiments may be included in or replace parts and features of other embodiments. The scope of embodiments of this application encompasses the entire scope of the technical specification and all available equivalents thereof. In this document, each embodiment may be referred to individually or collectively by the term "invention," which is merely for convenience and, if more than one invention is disclosed, is not intended to automatically limit the scope of the application to any single invention or inventive concept. Relational terms such as "first" and "second" are used herein merely to distinguish one entity or operation from another, without requiring or implying any actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed. The various embodiments in this document are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the structures, products, etc., disclosed in the embodiments, since they correspond to the disclosed parts, the descriptions are relatively simple; relevant details can be found in the method section.

[0033] Before describing the technical solution in detail, the key terms used in this application will be explained first: MicroLED (Micro Light Emitting Diode): refers to LED devices with chip sizes on the order of micrometers. Compared with traditional LEDs, they have smaller light-emitting areas and higher integration densities. In this application, the MicroLED pixel unit is composed of independent light-emitting mesa formed by LED epitaxial structures. Each mesa includes a p-type semiconductor layer / active layer / n-type semiconductor layer light-emitting structure. In a typical implementation, a GaN-based epitaxial structure is used, that is, it includes a p-GaN / MQW / n-GaN light-emitting structure.

[0034] Hybrid bonding: refers to a wafer-level interconnect technology that simultaneously achieves bonding between a dielectric layer (such as SiO2) and a metal (such as Cu). The SiO2 dielectric surfaces are mechanically connected by dielectric-dielectric bonding through van der Waals forces and covalent bonds, while the Cu conductive pillars are electrically interconnected by metal-metal bonding through Cu-Cu thermo-pressure diffusion. In this application, it is used to achieve ultra-high density direct interconnection between epitaxial pixel electrodes and CMOS driving circuits.

[0035] Mesa etching (mesa etching): refers to the process step of selectively etching the epitaxial layer of an LED to form independent light-emitting mesa. In this application, the etching is performed from the P-side (ITO surface) downwards, forming V-shaped, U-shaped, or trapezoidal isolation grooves with a wide top and narrow bottom. Since the widths of the grooves and mesa are complementary on the same horizontal plane, the enclosed light-emitting mesa correspondingly has a trapezoidal cross-section with a narrow ITO side and a wide n-GaN deep side. After flip bonding, the narrow end of the groove and the wide end of the mesa (both n-GaN side) face the light-emitting surface together, minimizing the width of the isolation structure near the light-emitting surface.

[0036] RE etching (front pixel isolation etching): refers to the inverted triangular etching performed from the exposed n-GaN front side after the hybrid bonding and substrate removal. The bottom of the trench is aligned and connected with the narrow opening of the Mesa isolation groove facing the light-emitting surface after flipping. At the connection point, the insulating layer and metal layer are simultaneously etched to complete the patterning of the metal layer. The purpose is to completely electrically isolate adjacent pixels from the light-emitting surface side, ensuring that the P electrode of each pixel can be addressed independently.

[0037] Inverted triangle shaped etching: In this application, it generally refers to a V-shaped, U-shaped, or trapezoidal etching cross-section with a wide top and narrow bottom. For Mesa etching, after flip bonding, its narrow end faces the light-emitting surface to minimize isolation projection; for RE etching, it is performed from the light-emitting surface downwards, and the isolation width on the light-emitting surface is determined by the top width of the trench and controlled to be minimized, and the bottom of the trench is aligned and connected with the narrow opening of the Mesa groove below; the inclined sidewalls of both are beneficial to uniform film coverage and lateral light reflection.

[0038] CMOS driver wafer: refers to a silicon-based wafer that integrates pixel driving circuits. In this application, an 80nm process node is used. Conductive pillars are pre-fabricated in the top metal layer as contact points for subsequent electrical connection with the epitaxial pixel electrodes. The wafer surface is divided into AA region (effective pixel region), transition region, cathode ring region and Pad region (pad region).

[0039] AA area (Active Area): refers to the core area on the CMOS driver wafer where the pixel driver array is arranged. The Cu conductive pillars in this area are etched through the insulating layer by Via2 etching to form electrical contacts with the top metal conductive pillars of the CMOS, which are used to achieve one-to-one electrical connection with the P electrodes of each pixel on the epitaxial side.

[0040] ITO (Indium Tin Oxide): A transparent conductive material that serves two functions in this application: First, on the epitaxial side, it acts as a P-type ohmic contact and current spreading layer on the p-GaN surface to uniformly distribute the driving current to the light-emitting surface; Second, on the front side of the device, it acts as an N-type common electrode covering the n-GaN surface of all pixels.

[0041] Potential transition layer: refers to a conductive layer disposed on the surface of p-GaN, forming a P-type ohmic contact with p-GaN, and uniformly transitioning and extending the driving current and potential to the entire light-emitting surface. In this application, this layer is implemented using an ITO thin film; since this layer is located on the side away from the light-emitting surface after the device is flip-bonded, its core function is potential transition and current extension rather than light transmission, hence it is called a potential transition layer.

[0042] ALD (Atomic Layer Deposition): A high-precision coating technology for depositing thin films one atomic layer at a time. It has extremely high conformability and can achieve complete and uniform coverage on the sidewalls and bottom of deep grooves. In this application, it is used to deposit an Al2O3 passivation layer to effectively passivate the exposed sidewalls of the MQW active region and reduce non-radiative recombination.

[0043] RPD (Reactive Plasma Deposition): A process for depositing high-quality transparent conductive oxides such as ITO. Compared with traditional magnetron sputtering, it can obtain ITO films with higher crystallinity and lower sheet resistance at lower temperatures. In this application, it is used to prepare N-type common electrodes.

[0044] CMP (Chemical Mechanical Polishing): A process for achieving global planarization of the wafer surface. It is used in multiple places in this application to obtain an ultra-low roughness surface (Ra<0.5nm) that meets the requirements of mixed bonding and to form a planar structure in which Cu conductive pillars and SiO2 dielectric are coplanar.

[0045] IBE (Ion Beam Etching): A process that uses a wide-beam ion beam to physically sputter and etch materials. It has a small difference in the selectivity of etching for different materials. In this application, it is used to uniformly etch Ni / Ag / Ti, Cr / Ag / Ti and other multilayer reflective metal stacks in the front isolation etching in step S5, so that the reflective metal electrodes of each pixel are independent of each other.

[0046] Effective light-emitting area ratio: refers to the proportion of the effective light-emitting area in a single pixel to the total area of ​​the pixel. This application improves the effective light-emitting area ratio by minimizing the top area occupied by the isolation area through an inverted triangular etching structure.

[0047] PECVD (Plasma Enhanced Chemical Vapor Deposition): A method for depositing thin films at lower temperatures, used in this application for depositing SiO2 insulating layers and dielectric filling layers.

[0048] ICP (Inductively Coupled Plasma Etching): An anisotropic dry etching process used in this application for selective etching steps such as passivation layer opening, ITO patterning, and electrode extension structure patterning.

[0049] It should be noted that the following embodiments all use GaN-based LED epitaxial material systems as examples, but the manufacturing method of this application is not limited to GaN-based material systems. The core of this method lies in the two-level inverted triangle etching structure, wafer-level hybrid bonding, and the process route of bonding before isolation. It does not depend on the epitaxial material system and is equally applicable to other compound semiconductor LED epitaxial wafers such as GaAs-based, InP-based, AlGaInP-based, and AlGaAs-based. When using other material systems, the n-GaN layer and p-GaN layer in this article are respectively the n-type semiconductor layer and p-type semiconductor layer in that material system. The active layer can be a multi-quantum well or double heterojunction structure of the corresponding material system. The specific materials of the substrate, buffer layer, potential transition layer, passivation layer, and reflective metal layer can be adaptively selected according to the selected epitaxial system using conventional methods in the art. Such substitutions all fall within the protection scope of this application.

[0050] This invention provides a manufacturing method for increasing the pixel density of MicroLEDs. The method provided is performed in a cleanroom environment using semiconductor wafer fabrication equipment and involves three stages: driver substrate fabrication, epitaxial substrate fabrication, and hybrid bonding and subsequent processing. The method includes the following steps: Step S1: Fabrication of the driving substrate side.

[0051] like Figure 1As shown, an 80nm process node CMOS driver wafer is provided. The top metal layer of this wafer has several conductive pillars, which are the top metal contacts in the CMOS back-end interconnect, used for subsequent electrical connections with the epitaxial pixel electrodes. The wafer surface is divided into AA regions (effective pixel areas) for pixel array arrangement, transition regions for connecting different functional areas, cathode ring regions for N-electrode grounding connections, and Pad regions (pad areas) for external circuit connections. A SiO2 insulating layer is deposited on the CMOS wafer surface using a PECVD process. This SiO2 layer protects the CMOS surface metal layer, provides insulation, and serves as a substrate for subsequent etching and filling processes. CMP planarization is then performed to obtain a dielectric layer surface with a flatness sufficient for subsequent hybrid bonding.

[0052] like Figure 2 As shown, the SiO2 insulating layer is etched in steps using Via etching. First, in the transition region outside the AA region, Via1 etching is performed using photolithography and dry etching processes to etch several vias in the SiO2 dielectric layer. The etching depth is controlled to not penetrate the SiO2 layer, leaving a certain thickness of SiO2 at the bottom. The purpose is to form a pre-structure for the interconnect channels in the transition region while ensuring the insulation integrity of this area. Second, Via2 etching is performed in the AA and Pad regions to penetrate the SiO2 and expose the top conductive pillars of the underlying CMOS wafer, so that subsequent metal filling steps can form electrical contacts with the CMOS conductive pillars. The etching depth of Via2 must be precisely controlled to just expose the top metal surface of the CMOS.

[0053] like Figure 3 As shown, a Ti / Cu seed layer is deposited on the inner wall of the via and the SiO2 surface using PVD sputtering. Ti acts as an adhesion and barrier layer to prevent Cu atoms from diffusing into the SiO2 medium, while Cu acts as a conductive seed layer to provide a conductive starting surface for subsequent electroplating. Cu is then filled into the via through-holes via electroplating. Finally, CMP planarization is performed to remove excess Cu and the seed layer from the surface, retaining only the Cu conductive pillars within the vias, forming a coplanar planar structure of Cu conductive pillars embedded in the SiO2 medium. At this point, the bottom of the Cu conductive pillar in the AA region forms an electrical contact with the top metal conductive pillar of the CMOS, establishing a complete electrical path. The bottom of the Cu pillar in the transition region does not contact the CMOS conductive pillar, maintaining electrical insulation. The Cu pillars in the cathode ring region and the Pad region form electrical contacts with their respective CMOS metal layers.

[0054] Step S2: Preparation of the epitaxial side.

[0055] like Figure 4As shown above, a GaN-based LED epitaxial structure grown on a Si substrate by MOCVD is provided. The epitaxial structure includes, from the substrate upwards, a Si substrate, a buffer layer, an n-GaN layer, a multiple quantum well (MQW) active layer, a p-GaN layer, and an ITO layer as a potential transition layer.

[0056] To facilitate the formation of an ohmic contact using the subsequent N-type common electrode, the n-type doping concentration of the n-GaN layer is greater than 1 × 10⁻⁶. 18 cm -3 The ITO layer, acting as a p-type ohmic contact and current spreading layer, uniformly distributes the driving current from the contact point to the entire p-GaN surface, ensuring uniform luminescence of the MQW active layer. This setup is consistent with existing technologies and will not be elaborated further here.

[0057] like Figure 4 As shown in the middle section, a mesa etching process, or mesa etching, is performed on the epitaxial layer in an inverted triangular shape. This etching penetrates the ITO layer and the GaN epitaxial layer, including p-GaN, MQW, and part of n-GaN, forming an isolation groove with a cross-section that is wider at the top and narrower at the bottom. This results in the light-emitting mesas between adjacent grooves having a trapezoidal cross-section that is narrower on one side of the ITO surface and wider on the deeper side of the n-GaN. After flip bonding in the final device, the narrow end of the groove (n-GaN side) faces the light-emitting surface, minimizing the width of the isolation structure near the light-emitting surface, thereby maximizing the effective light-emitting area ratio and increasing pixel density. At the same time, the tilted sidewalls facilitate the uniform coverage of the subsequent insulating layer and metal reflective layer, and the metal reflective layer on the sidewalls can reflect the lateral escape light back to the light-emitting direction.

[0058] like Figure 4 As shown in the lower part, on the surface of the mesa structure after etching, a high-quality Al2O3 thin film is first deposited as a passivation layer using the ALD process. The ALD process, with its atomic-layer deposition, offers high conformality and achieves completely uniform coverage on the sidewalls and bottom of the deep grooves. This Al2O3 passivation layer covers all exposed GaN sidewalls, passivating and protecting the active region sidewalls of the MQW to reduce non-radiative recombination and improve luminous efficiency. Then, a SiO2 layer is deposited using PECVD as an insulating layer. Subsequently, the Al2O3 / SiO2 layer above the ITO on the top of each Mesa is selectively removed using the ICP etching process to form openings that expose the ITO surface, while retaining the insulating layer on the sidewalls and bottom of the inverted triangular grooves to ensure electrical isolation between adjacent pixels.

[0059] like Figure 5As shown, a Ni / Ag / Ti metal reflective layer is sputtered and deposited on the surface of the above structure. Ni acts as an adhesion layer to enhance interface adhesion, Ag acts as a high-reflectivity layer to reflect downward-emitted light back to the light-emitting direction in the visible light band, and Ti acts as a protective layer to prevent oxidation or corrosion of the Ag layer. This Ni / Ag / Ti metal reflective layer covers the ITO opening area at the top of each Mesa, as well as the insulating layer surface on the sidewalls and bottom of the groove, and remains continuous between adjacent pixels through the bottom of the groove. It establishes an ohmic contact with the ITO through the opening to create an electrical path for the P-electrode. Simultaneously, it acts as an optical mirror on the bottom surface of the Mesa, reflecting photons back to the light-emitting direction, and the metal coverage on the sidewalls of the groove provides lateral light reflection. The reflective metal layer simultaneously serves as the ohmic contact for the P-electrode, the bottom mirror, and the current conduction path, achieving multifunctional integration in a single metal layer. It should be noted that this metal layer is not patterned at this stage; it maintains continuous coverage throughout the entire AA area. The independence of the reflective metal electrodes of each pixel is achieved by the simultaneous etching of the front isolation in subsequent step S5. A thick layer of SiO2 was deposited using PECVD to fill the grooves and surface of the entire mesa structure, forming a relatively flat dielectric layer.

[0060] like Figure 6 As shown, the SiO2 dielectric layer is etched, and a deep via (Via3) is etched at the location corresponding to each pixel. The depth penetrates the SiO2 filling layer to reach the surface of the underlying Ni / Ag / Ti metal reflective layer (etching terminates at the Ti protective layer), forming a channel for conductive pillar filling. The position of Via3 is precisely aligned with the reflective metal layer region of each pixel, and the etching termination point is the surface of the Ti protective layer of the Ni / Ag / Ti metal layer. Subsequently, a Ti / Cu seed layer is sputtered into the Via3 via, Cu is electroplated for filling, and then planarized by CMP. Cu conductive pillars are formed on the epitaxial side. The bottom of each Cu conductive pillar is electrically connected to the Ni / Ag / Ti reflective metal layer of the corresponding pixel, thereby forming an electrical path from the top surface of the Cu conductive pillar to p-GaN through the reflective metal layer and ITO. The surface after CMP is a flat surface where the Cu conductive pillars are embedded in the SiO2 dielectric, satisfying the requirements of hybrid bonding.

[0061] Step S3: Mixed bonding.

[0062] like Figure 7As shown, the structure on the driving substrate side (after step S1) and the structure on the epitaxial side (after step S2) are aligned for wafer-level hybrid bonding. The specific process is as follows: First, the surfaces to be bonded on both sides are subjected to plasma activation treatment, activating the SiO2 surface to generate Si-OH hydrophilic groups; then, the two wafers are aligned with alignment precision controlled at the sub-micron level; pre-bonding is performed at room temperature, where the Si-OH groups on opposite sides generate initial attractive forces to form weak bonds; finally, annealing is performed, causing the Si-OH groups between the SiO2 surfaces to dehydrate and condense to form Si-O-Si covalent bonds, establishing a strong permanent bond. Simultaneously, Cu conductive pillars achieve metal-metal bonding through Cu-Cu thermo-pressure diffusion, establishing low-resistance electrical interconnections. After bonding, each Cu conductive pillar on the epitaxial side is precisely aligned with the corresponding Cu conductive pillar on the driving substrate side and forms an electrical connection, establishing a complete P-electrode driving path from the CMOS driving circuit output terminal through the Cu conductive pillars on the driving substrate side, the hybrid bonding interface, the Cu conductive pillars on the epitaxial side, the Ni / Ag / Ti reflective metal layer to ITO, and then to p-GaN.

[0063] Step S4: Remove the substrate and buffer layer.

[0064] like Figure 8 As shown in the upper part, the Si substrate on the epitaxial side is removed by methods such as mechanical polishing, chemical etching, or laser lift-off. The Si substrate serves as a necessary mechanical support and lattice template during the epitaxial growth stage, but because Si is opaque to visible light, it must be removed after device fabrication to allow light generated by the GaN emitting layer to escape from the n-GaN surface. Subsequently, the buffer layer is removed by dry or wet etching to expose the n-GaN layer surface, preparing for subsequent N-electrode fabrication.

[0065] Step S5: Front-side RE etching achieves pixel isolation.

[0066] like Figure 8As shown in the lower part, an inverted triangular RE etching is performed on the exposed n-GaN surface, etching through the n-GaN layer. The bottom of the isolation trench is aligned and connected with the narrow opening of the Mesa isolation groove facing the light-emitting surface after being flipped. At the connection point, the passivation / insulating layer and the Ni / Ag / Ti metal layer at the narrow opening are sequentially etched through, penetrating into the underlying dielectric filling layer. This completes the patterning of the metal layer, making the reflective metal electrodes of each pixel independent, achieving complete physical and electrical isolation between adjacent pixels. The etching of the n-GaN layer can be performed using the ICP process, and the etching of the metal layer can be performed using the IBE process. The necessity of this step is that although the Mesa etching in step S2 has divided the epitaxial layer into independent mesa from the P side, the n-GaN layer has not yet been completely divided, and at this time, the continuously covering reflective metal layer still connects the P electrodes of adjacent pixels. RE etching completely separates adjacent pixels physically from the front side, ensuring that each pixel's P electrode is individually addressed and completely electrically isolated from each other via the ITO→Ni / Ag→Cu pillar→driver IC path. RE etching also adopts an inverted triangular shape, i.e., V-shape or inverted trapezoid, forming structural symmetry with the Mesa etching in step S2.

[0067] Step S6: RE trench filling and thinning / planarization.

[0068] like Figure 9 As shown in the upper part, insulating materials such as SiO2 are filled into the isolation trenches formed by RE etching, and then CMP thinning and planarization are performed to make the n-GaN surface flush with the trench filler, forming a flat light-emitting surface. A flat light-emitting surface is not only a requirement for the subsequent ITO common electrode deposition process, but also beneficial to the uniformity of the final optical output of the device.

[0069] Step S7: Deposit ITO common electrode.

[0070] like Figure 9 As shown in the lower part, a 200nm thick ITO film is deposited on the planarized front side using the RPD process. The RPD process can obtain a high-quality, low-resistance ITO layer with higher crystallinity, greater carrier mobility, and lower sheet resistance. This ITO layer covers the n-GaN surface of all pixels, forming an N-type common electrode. The common cathode structure means that all pixels share the same N electrode, and each pixel achieves independent addressing and brightness control through an independent P electrode. Subsequently, the ITO is patterned by ICP etching, retaining the common electrode area of ​​the AA region and removing unwanted edge areas.

[0071] To achieve a low-resistance ohmic contact between the ITO and n-GaN, the wafer undergoes rapid thermal annealing after ITO deposition and patterning. The annealing atmosphere is N2 or N2 / O2, the temperature is 250℃~300℃, and the time is 1 minute~10 minutes, reducing the specific contact resistivity to 10. -3 Ω·cm2 Below the order of magnitude; this temperature window is not higher than the mixed bonding annealing temperature (300℃), and will not introduce additional thermal budget impact to the already formed Cu-Cu bonding interface, nor is it lower than the temperature at which Ag reflective layer agglomerates and deteriorates, and will not affect the stability of the bonding interface and reflective layer.

[0072] To ensure that the N-type common electrode and the ground potential of the CMOS driving circuit form a complete current loop, during or after RE etching in step S5, residual epitaxial material and underlying dielectric layer in the cathode ring region are removed by etching to form a cathode contact opening that exposes the top surface of the conductive pillar in the cathode ring region. In step S7, when depositing ITO, it extends to cover the opening and contacts the top surface of the conductive pillar. In step S8, the electrode extension metal stack also extends to cover the opening to form a low-resistance lead-out. This establishes the N-electrode current path for each pixel: n-GaN → ITO common electrode → electrode extension metal → cathode contact opening → cathode ring region conductive pillar → CMOS ground potential.

[0073] Step S8: Form the electrode extension structure.

[0074] like Figure 10 As shown, a Ti / Al / TiN metal stack is sputtered and deposited on the ITO common electrode, where Ti serves as the adhesion layer, Al as the main conductive layer, and TiN as the protective and anti-reflective layer. The electrode extension structure, i.e., the N2 metal layer, is formed by ICP etching and patterning. This metal extension structure is located above the isolation trenches between adjacent pixels without obstructing the effective light-emitting area. Its core function is to compensate for the insufficient conductivity of ITO, ensuring uniform current distribution to each pixel by significantly reducing the surface resistance of the common electrode, thus eliminating the brightness unevenness caused by voltage drop differences. The cross-sectional shape of the electrode extension structure can be a regular trapezoid, an inverted trapezoid, a square, or a rectangle. This completes the fabrication of the entire MicroLED display device. Example 1

[0075] The following specific embodiment illustrates in detail the implementation process of the technical solution of the present invention on an 8-inch wafer platform.

[0076] The application scenario of this embodiment is: using 8-inch Si substrate GaN epitaxial wafers and 8-inch 80nm CMOS driving wafers as raw materials, to prepare ultra-high density MicroLED display devices with pixel pitch of less than 5um, which are aimed at being applied to AR / VR near-eye display systems.

[0077] Corresponding to step S1—Fabrication of the driving substrate: An 8-inch CMOS driving wafer with an 80nm process node is provided, in which Cu conductive pillars are pre-fabricated in the top metal layer according to the pixel array arrangement. A 1.5µm thick SiO2 insulating layer is deposited on the surface of the CMOS wafer using PECVD, followed by CMP planarization to a surface roughness Ra < 0.5nm, which meets the stringent requirements for subsequent hybrid bonding. Stepwise Via etching is performed: The first step is Via1 etching in the transition region, with an etching depth of approximately 1.0µm (not penetrating the 1.5µm thick SiO2 layer) to form the interconnect prestructure while maintaining insulation integrity; the second step is Via2 etching in the AA region and Pad region, with via diameters of 0.8µm and depths of 1.5µm (penetrating SiO2 to the top metal layer of the CMOS), exposing the top conductive pillars of the CMOS. A Ti 20nm / Cu 100nm seed layer is sputtered, Cu is electroplated to fill all Via vias, and CMP is used to planarize and remove excess metal from the surface, forming a coplanar planar structure in which Cu conductive pillars are embedded in SiO2.

[0078] Corresponding to step S2—Epithelial Side Fabrication: An 8-inch Si substrate is provided for MOCVD growth of a GaN-based LED epitaxial wafer. The epitaxial structure, from the substrate upwards, consists of a Si substrate, a buffer layer, an n-GaN layer, an MQW active layer, a p-GaN layer, and an ITO layer (approximately 100 nm thick). An inverted triangular Mesa etching process is performed on the epitaxial layers, with an etching depth of approximately 1.2 μm, penetrating through the p-GaN and MQW layers to the n-GaN layer. The resulting groove has a bottom width of approximately 0.3 μm and a top width of approximately 1.0 μm, exhibiting an inverted triangular geometric feature with a wide top and narrow bottom. The light-emitting mesa surrounded by this groove correspondingly has a trapezoidal cross-section, narrow on the ITO side and wide at the deepest part of the n-GaN layer.

[0079] A 20nm thick Al₂O₃ passivation layer was deposited using ALD to cover all exposed GaN sidewalls, and a 200nm thick SiO₂ insulating isolation layer was deposited using PECVD. An opening of approximately 0.5µm in diameter was formed above the ITO on top of each Mesa layer via ICP etching to expose the ITO surface. A 5nm Ni / 150nm Ag / 30nm Ti reflective metal layer was sputtered to cover the opening area, as well as the sidewalls and bottom of the grooves, maintaining continuity between adjacent pixels. The Ni layer provides adhesion, the Ag layer provides high reflectivity, and the Ti layer provides protection. The reflective metal layer was not patterned at this stage, maintaining continuous coverage within the AA region. A thick SiO₂ layer was deposited using PECVD to fill the grooves and planarize them. Via 3 vias with a diameter of 0.8µm were etched, penetrating the SiO₂-filled layer to reach the Ti surface of the Ni / Ag / Ti metal layer. A Ti / Cu seed layer was sputtered, and Cu was electroplated to fill the Via 3. CMP planarization was then performed to form epitaxial Cu conductive pillars.

[0080] Corresponding to step S3—Hybrid Bonding: Plasma activation treatment is performed on the bonding surfaces of the epitaxial side and the driving substrate side. The two wafers are aligned with an alignment precision controlled at <200nm (submicron level) to ensure precise alignment of each Cu conductive pillar on the epitaxial side with its corresponding Cu conductive pillar on the driving substrate side. Pre-bonding is performed at room temperature to form initial bonding using van der Waals forces. Annealing at 300°C for 2 hours allows Si-O-Si covalent bonds to form between the SiO2 surfaces, achieving permanent dielectric bonding, while Cu-Cu thermo-pressure diffusion is completed between the Cu conductive pillars to achieve metallic bonding. After bonding, the P-electrode electrical path for each pixel is fully established.

[0081] The corresponding step S4 is to remove the substrate and buffer layer: the 8-inch Si substrate is removed by mechanical polishing combined with chemical etching, and the buffer layer is removed by wet etching to expose the clean n-GaN surface.

[0082] Corresponding to step S5—Front-side RE etching for pixel isolation: Perform inverted triangular RE etching from the exposed n-GaN front side, with the etching depth penetrating the n-GaN layer to the underlying SiO2 dielectric layer, forming a V-shaped isolation trench with a top width of approximately 1.0 μm and a bottom width of approximately 0.4 μm. The bottom of the trench is aligned and connected with the narrow opening (approximately 0.3 μm wide) of the Mesa groove facing the light-emitting surface after flipping. Simultaneously, use IBE process to etch the Ni / Ag / Ti metal layer and its underlying insulating layer at the narrow opening, and complete the patterning of the reflective metal electrodes of each pixel, completely isolating adjacent pixels and ensuring that the P electrode of each pixel is addressed independently. At the same time, form cathode contact openings on the top surface of the Cu conductive pillars on the exposed driving substrate side by etching in the cathode ring region.

[0083] Corresponding step S6—RE trench filling and thinning planarization: SiO2 is filled into the isolation trench etched by RE, and CMP thinning and planarization is performed to make the n-GaN surface flush with the trench filler to form a flat light-emitting surface.

[0084] Corresponding to step S7—ITO common electrode deposition: A 200nm thick ITO film is deposited on the planarized front side using RPD technology, covering all pixel n-GaN surfaces to form an N-type common electrode. The ITO is patterned using ICP etching, retaining the common electrode area in region AA. Since step S5 has already formed a cathode contact opening exposing the top surface of the Cu conductive pillars in the cathode ring region, the ITO deposited in this step extends to cover this opening and contacts the top surface of the Cu conductive pillars. The Ti / Al / TiN metal stack in subsequent step S8 also extends to cover this opening, forming a low-resistance lead-out, achieving a common ground connection between the N-type common electrode and the CMOS ground potential. Subsequently, rapid thermal annealing at 280°C for 5 minutes in an N2 atmosphere forms an ITO / n-GaN low-resistance ohmic contact.

[0085] Corresponding to step S8—forming the electrode extension structure: a Ti 20nm / Al 500nm / TiN 50nm metal stack is sputtered, and an electrode extension structure is formed above the isolation trenches of adjacent pixels by ICP etching to reduce the common electrode surface resistance and ensure uniform current distribution. In this embodiment, the electrode extension structure adopts a square cross-sectional shape.

[0086] The MicroLED display device finally fabricated in this embodiment achieves a pixel density of less than 5µm and over 5000 PPI, meeting the ultra-high resolution requirements of AR / VR near-eye displays. The low-contact-resistance Cu-Cu interconnect achieved through hybrid bonding ensures the long-term stable operation of the high-density array. The inverted triangular sidewall reflective structure, combined with the Ag bottom reflector, forms an effective optical cavity, significantly improving light extraction efficiency. Compared to traditional methods, the bonding-then-isolation process route reduces the number of pre-bonding steps and alignment operations, lowering process complexity and cost. Example 2

[0087] The implementation of the technical solution of the present invention under different material selection and geometric configuration conditions will be illustrated below through a second specific embodiment.

[0088] The application scenario of this embodiment is as follows: using 8-inch Si substrate GaN epitaxial wafers and 8-inch 80nm CMOS driver wafers as raw materials, a MicroLED display device is fabricated using alternative material combinations to verify the applicability of the present invention under different process platform conditions. Compared with Embodiment 1, this embodiment adopts alternative solutions in terms of passivation layer materials, reflective metal combinations, conductive pillar filling materials, and electrode extension structure materials.

[0089] Corresponding to step S1—Fabrication of the driving substrate side: An 8-inch 80nm CMOS driving wafer is provided. A 1.5µm thick SiO2 insulating layer is deposited on the surface of the CMOS wafer using PECVD and planarized to Ra < 0.5nm using CMP. Stepwise Via etching is performed: the transition region Via1 is not etched through, while the AA region and Pad region Via2 are etched through to expose the top conductive pillars of the CMOS. The Via2 aperture is 0.8µm and the depth is 1.5µm. Unlike Example 1, in this example, after seed layer sputtering, W (tungsten) is used to fill the Via vias vias using CVD instead of electroplated Cu. W has good via-filling ability and high-temperature stability, making it suitable for the compatibility requirements of certain process platforms. After CMP planarization, a coplanar planar structure is formed in which the W conductive pillars are embedded in SiO2.

[0090] Corresponding to step S2—Epithelial Side Fabrication: An 8-inch GaN epitaxial wafer is provided, with the epitaxial structure being the same as in Example 1. An inverted triangular Mesa etching is performed on the epitaxial layer. In this example, a U-shaped cross-section is used (still satisfying the geometric characteristics of a narrow bottom and a wide top), with an etching depth of approximately 1.2 μm, a trench bottom width of approximately 0.3 μm, and a top width of approximately 1.0 μm. Unlike ALDAl2O3 in Example 1, this example uses SiN (silicon nitride) as the passivation layer material, achieving sidewall passivation protection through PECVD deposition. The insulating isolation layer uses SiON (silicon oxynitride) instead of SiO2. An opening with a diameter of approximately 0.5 μm is formed above the ITO through ICP etching. Unlike Ni / Ag / Ti in Example 1, this example sputters Cr / Ag / Ti as the reflective metal layer, where Cr replaces Ni as the adhesion layer to provide good adhesion to the insulating layer, Ag remains as the high-reflectivity layer, and Ti remains as the protective layer. This Cr / Ag / Ti is also not patterned in this stage, maintaining continuous coverage. PECVD is used to deposit SiON-filled trenches and planarize them. Via3 apertures of 0.8 μm are etched. In this embodiment, W-filled Via3 is also used on the epitaxial side to form epitaxial W conductive pillars. After CMP planarization, a W / SiON coplanar flat surface is formed.

[0091] It should be noted that the SiON dielectric filling and W conductive pillar filling on the epitaxial side are both performed after the Ag reflective layer is formed. Therefore, the PECVD deposition temperature and W filling temperature on the epitaxial side are both controlled to be no higher than 300℃. The W filling is achieved by low-temperature CVD or PVD sputtering W process to avoid introducing thermal budgets that exceed the agglomeration and degradation temperature of the Ag reflective layer. Since the driving substrate side does not contain an Ag layer, the W filling can be performed by a conventional temperature CVD process.

[0092] Corresponding to step S3—Hybrid Bonding: Plasma activation treatment is performed on the bonding surfaces of the epitaxial side and the driving substrate side. Alignment accuracy is controlled to <200nm. Room temperature pre-bonding. Due to the extremely low self-diffusion coefficient of W, direct W diffusion bonding is not feasible at 300°C. In this embodiment, after CMP planarization and before bonding, the tops of the W conductive pillars on both sides are selectively etched back to form a controllable recess with a depth of about 10-30nm. Then, a Cu bonding auxiliary layer of matching thickness is deposited in the recess by selective chemical plating, so that the Cu top surface is kept 0-10nm concave relative to the dielectric surface to maintain coplanar adhesion of the dielectric surfaces. Subsequently, room temperature pre-bonding and annealing at 300°C for 2 hours are performed to form covalent bonds between the dielectric surfaces. The Cu auxiliary layers on both sides are closed by thermal expansion and metal bonding is achieved through Cu-Cu hot-press diffusion. Reliable electrical interconnection is established through the W conductive pillars. After bonding, the electrical path of the P electrode of each pixel is established.

[0093] Corresponding step S4 - Removal of substrate and buffer layer: The Si substrate is removed by laser lift-off (replacing the mechanical polishing + chemical etching method in Example 1), and the buffer layer is removed by dry etching to expose the n-GaN surface.

[0094] Corresponding to step S5—Front-side RE etching for pixel isolation: An inverted triangular RE etching is performed from the front side of the n-GaN. In this embodiment, an inverted trapezoidal cross-section is used. The etching penetrates through the n-GaN to the underlying dielectric layer, and simultaneously breaks the Cr / Ag / Ti metal layer at the narrow opening of the isolation groove to achieve its patterning, thus completely isolating adjacent pixels electrically. Simultaneously, a cathode contact opening is formed in the cathode ring region, referring to Embodiment 1.

[0095] Corresponding step S6—RE trench filling and thinning planarization: SiON is filled into the RE isolation trench, and CMP planarization is performed to form a flat light-emitting surface.

[0096] Corresponding step S7 – Deposition of ITO common electrode: A 200nm thick ITO is deposited using RPD process to form an N-type common electrode, and ICP patterning is used to retain the AA region.

[0097] Corresponding to step S8—forming the electrode extension structure: Unlike the Ti / Al / TiN in Example 1, this example uses a sputtered Ti / Cu / TiN metal stack as the electrode extension structure material. Cu, as the main conductive layer, has a lower resistivity than Al, which can further reduce the common electrode surface resistance. Through ICP etching patterning, the electrode extension structure in this example adopts an inverted trapezoidal cross-sectional shape.

[0098] The MicroLED display device finally fabricated in this embodiment also achieved an ultra-high density with a pixel pitch of less than 5 μm, verifying the applicability and robustness of the technical solution of this invention under different material combinations. Specifically: the SiN passivation layer and SiON dielectric layer, after replacing Al2O3 and SiO2, still achieve effective sidewall protection and insulation isolation; the function of the reflective metal layer (P electrode, reflector, current conduction) can still be realized normally after Cr / Ag / Ti replaces Ni / Ag / Ti; the electrical interconnection of the hybrid bonding can still be reliably established after W conductive pillars replace Cu conductive pillars, achieved through the Cu bonding auxiliary layer at the top of the W pillars; the function of reducing the surface resistance of the electrode extension structure is further enhanced after Ti / Cu / TiN replaces Ti / Al / TiN; the same high FillFactor effect can be achieved as long as the geometric characteristics of narrow bottom and wide top are met, after replacing the V-shape with U-shaped and inverted trapezoidal etched cross sections. The comparison between this embodiment and Embodiment 1 further confirms the flexibility and universality of the technical solution of this invention.

[0099] The present invention also provides a MicroLED display device, which is manufactured using the above-described method and corresponds to the corresponding description in the foregoing method embodiments, and will not be repeated here.

Claims

1. A manufacturing method for increasing the pixel density of MicroLEDs, characterized in that, include: S1. Provide a CMOS driver wafer, wherein the bonding surface of the CMOS driver wafer is a coplanar flat structure consisting of a dielectric layer and a driving substrate side conductive pillar embedded in the dielectric layer. S2. Provide an LED epitaxial wafer, the epitaxial wafer including a substrate and an n-type semiconductor layer, an active layer and a p-type semiconductor layer located above the substrate; etch the epitaxial layer from the p-type semiconductor layer side with a wide top and narrow bottom, etching through the p-type semiconductor layer and the active layer and into part of the n-type semiconductor layer to form an isolation groove, dividing the epitaxial layer into multiple light-emitting mesas corresponding to one pixel unit; An insulating layer is formed on the surface of the etched mesa structure. The insulating layer has an opening at the top of each light-emitting mesa and is retained on the sidewalls and bottom of the isolation groove. A metal layer is formed on the surface of the mesa structure. The metal layer is electrically connected to one side of the p-type semiconductor layer of the light-emitting mesa through the opening and continuously covers the insulating layer surface of the sidewall and bottom of the isolation groove, thus maintaining continuity between adjacent pixel units. A dielectric filling layer is formed covering the metal layer, and an epitaxial conductive post is formed at the corresponding position of each pixel unit, penetrating the metal layer and coplanar with the dielectric filling layer. S3. Align the epitaxial side with the driving substrate side and perform wafer-level hybrid bonding to form a dielectric-dielectric bond between the dielectric surfaces and a metal-metal bond between the conductive pillars on the epitaxial side and the conductive pillars on the driving substrate side. S4. Remove the substrate of the epitaxial wafer to expose the surface of the n-type semiconductor layer; S5. Perform isolation etching with a wide top and narrow bottom on the exposed n-type semiconductor layer surface to etch through the n-type semiconductor layer. Align the bottom of the formed isolation trench with the narrow opening of the isolation groove facing the light-emitting surface after flipping. Cut the insulating layer and the metal layer at the narrow opening at the connection point to realize the patterning of the metal layer, so that the metal layers of each pixel unit are independent of each other and adjacent pixel units are electrically isolated from each other. S6. After filling the isolation trench with insulating material and planarizing it, an N-type common electrode is formed covering the surface of the n-type semiconductor layer of each pixel unit.

2. The manufacturing method according to claim 1, characterized in that, The coplanar structure described in step S1 is formed as follows: an insulating layer is deposited and planarized on the surface of the CMOS driving wafer, and conductive pillars on the driving substrate side are formed by etching vias and filling with conductive material.

3. The manufacturing method according to claim 2, characterized in that, The etched vias include step-by-step Via etching: Via1 etching is performed in the transition area of ​​the non-effective pixel area, and its etching depth does not penetrate the insulating layer to retain the bottom insulating medium; Via2 etching is performed in the effective pixel area and the pad area to penetrate the insulating layer to expose the top conductive pillar of the CMOS driver wafer. After sputtering a seed layer onto the inner wall of each through hole and the surface of the insulating layer, conductive material is electroplated to fill the hole, and then the excess conductive material and seed layer are removed by chemical mechanical polishing.

4. The manufacturing method according to claim 1, characterized in that, The epitaxial wafer also includes a buffer layer between the substrate and the n-type semiconductor layer and a potential transition layer on the p-type semiconductor layer; the etching in step S2 also etches through the potential transition layer, the opening exposes the potential transition layer, and the metal layer forms an ohmic contact with the potential transition layer through the opening; the substrate and the buffer layer are removed in step S4.

5. The manufacturing method according to claim 4, characterized in that, The insulating layer comprises a passivation layer and an insulating isolation layer deposited sequentially. The passivation layer is an Al2O3 thin film formed by atomic layer deposition or a SiN thin film formed by plasma-enhanced chemical vapor deposition, covering all exposed epitaxial layer sidewalls. The insulating isolation layer is a SiO2 layer or a SiON layer formed by plasma-enhanced chemical vapor deposition. The opening is formed by inductively coupled plasma etching.

6. The manufacturing method according to claim 1, characterized in that, The metal layer mentioned in step S2 is a reflective metal stack, which includes an adhesion layer, a high reflectivity layer and a protective layer stacked sequentially. The adhesion layer is a Ni layer or a Cr layer, the high reflectivity layer is an Ag layer, and the protective layer is a Ti layer. The reflective metal stack also serves as the P electrode of the pixel unit, the bottom and sidewall reflectors, and the current conduction path to the epitaxial conductive pillar. In step S5, the reflective metal stack is etched using an ion beam etching process.

7. The manufacturing method according to claim 1, characterized in that, The isolation groove in step S2 has a V-shaped, U-shaped, or trapezoidal cross section, and the light-emitting platform surrounded by it has a trapezoidal cross section that is narrow on one side of the p-type semiconductor layer and wide on the deeper side of the n-type semiconductor layer; the isolation trench in step S5 has a V-shaped, U-shaped, or inverted trapezoidal cross section, and its top width is less than the center-to-center distance between adjacent pixel units.

8. The manufacturing method according to claim 1, characterized in that, The wafer-level hybrid bonding in step S3 includes: performing plasma activation treatment on the epitaxial side surface and the driving substrate side surface; aligning the two sides with an alignment accuracy of submicron level; performing pre-bonding at room temperature to form initial bonding between the dielectric surfaces through van der Waals forces; and performing annealing treatment to form covalent bonding between the dielectric surfaces and metallic bonding between the metal surfaces through thermo-pressure diffusion.

9. The manufacturing method according to claim 4, characterized in that, In step S4, at least one of mechanical polishing, chemical etching, and laser lift-off is used to remove the substrate, and dry etching or wet etching is used to remove the buffer layer; in step S6, the planarization is chemical mechanical polishing thinning, so that the surface of the n-type semiconductor layer is flush with the trench filler to form a flat light-emitting surface.

10. The manufacturing method according to claim 1, characterized in that, The N-type common electrode mentioned in step S6 is an ITO thin film formed by reactive plasma deposition and patterned by inductively coupled plasma etching. The manufacturing method further includes: sputtering a metal stack on the N-type common electrode and patterning it to form an electrode extension structure, wherein the electrode extension structure is located above the isolation trench between adjacent pixel units.

11. The manufacturing method according to claim 10, characterized in that, The cross-sectional shape of the metal stack of the electrode extension structure is any one of a regular trapezoid, an inverted trapezoid, a square, or a rectangle; the filling conductive material of the epitaxial conductive pillar and the driving substrate conductive pillar is Cu or W, and its seed layer is a Ti / Cu double-layer structure.

12. A MicroLED display device, characterized in that, It is prepared by the manufacturing method according to any one of claims 1 to 11.

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