Chip structure and display substrate
Patent Information
- Application Number
- CN202611023006.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-10
- Publication Date
- 2026-09-25
Smart Images
Figure CN122825616A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and in particular to a chip structure and a display substrate. Background Technology
[0002] Light-emitting diode (LED) chips have advantages such as pure color, wide dynamic range, high brightness, low operating voltage, low power consumption, long lifespan, shock resistance, and stable and reliable operation, leading to their widespread application. Display substrates using LED chips offer advantages such as pure color, wide dynamic range, high definition, low power consumption, long lifespan, and wide viewing angles, making them the most advantageous next-generation display medium. Summary of the Invention
[0003] In a first aspect, this disclosure provides a chip structure, including: a first substrate, a light-emitting unit, and a color conversion unit, wherein the color conversion unit is located on the light-emitting side of the light-emitting unit; the color conversion unit includes:
[0004] A defined dam layer located on one side of the first substrate, the defined dam layer having a plurality of opening regions;
[0005] An optical functional layer located inside the opening region, at least a portion of the optical functional layer being used to convert the color of light entering the optical functional layer;
[0006] And, a first encapsulation layer group located on the side of the defined dam layer opposite to the first substrate, wherein the orthographic projection of the defined dam layer on the first substrate is located inside the orthographic projection of the first encapsulation layer group on the first substrate;
[0007] The first encapsulation layer group includes one first encapsulation layer or multiple stacked first encapsulation layers. The first encapsulation layer includes a stacked first sub-encapsulation layer and a second sub-encapsulation layer, wherein the first sub-encapsulation layer and the second sub-encapsulation layer have different compositions.
[0008] In some embodiments, the defining dam layer includes a first surface facing the first substrate, a second surface facing away from the substrate, and an outer contour surface located on one side of the first surface and the second surface, the outer contour surface being a surface surrounding the entire defining dam layer, and the included angle between the first surface and the contour surface being an obtuse angle.
[0009] The first encapsulation layer group includes a first encapsulation surface that is attached to the second surface, a second encapsulation surface that is attached to the outer contour surface, and a third encapsulation surface that extends along the first substrate extension surface, wherein the first encapsulation surface is directly connected to the second encapsulation surface, the second encapsulation surface is directly connected to the third encapsulation surface, and the third encapsulation surface is disposed around the entire limiting layer;
[0010] The angle between the second packaging surface and the third packaging surface is an acute angle.
[0011] In some embodiments, the angle between the second surface and the outer contour surface is an acute angle.
[0012] In some embodiments, the opening area includes a wall and a bottom, the wall forming an obtuse angle with the first surface and the wall forming an acute angle with the second surface.
[0013] In some embodiments, a light-shielding layer is further included between the defined dam layer and the first substrate. The light-shielding layer includes light-transmitting holes that correspond one-to-one with the opening regions. The orthographic projection of the opening region on the first substrate overlaps with the orthographic projection of the corresponding light-transmitting hole on the first substrate.
[0014] Wherein, the orthographic projection of the first surface on the first substrate is located inside the orthographic projection of the light-shielding layer on the first substrate, and the light-shielding layer protrudes from the outer contour of the first surface in a direction parallel to the first substrate, such that at least a portion of the third encapsulation surface extends on the light-shielding layer.
[0015] In some embodiments, a second encapsulation layer group is further located between the light-shielding layer and the first substrate;
[0016] The second encapsulation layer group is disposed in contact with the first encapsulation layer group and forms a receiving space to completely enclose the limiting dam layer and the optical functional layer.
[0017] In some embodiments, the material of the first sub-encapsulation layer includes an inorganic material containing silicon and nitrogen;
[0018] The thickness of the first sub-encapsulation layer is in the range of 300nm to 600nm.
[0019] In some embodiments, the material of the second sub-encapsulation layer includes inorganic materials containing silicon, carbon, and nitrogen;
[0020] The thickness of the second sub-encapsulation layer is in the range of 400nm to 600nm.
[0021] In some embodiments, the atomic ratio of silicon to carbon in the second sub-encapsulation layer is between 0.4 and 0.6.
[0022] In some embodiments, the first encapsulation layer group further includes a second encapsulation layer, which is located on the side of the first encapsulation layer group furthest from the first substrate. The material of the second encapsulation layer is the same as that of the first sub-encapsulation layer, and the thickness of the second encapsulation layer is in the range of 300 nm to 600 nm.
[0023] In some embodiments, the first encapsulation layer group further includes at least one third encapsulation layer located on the side of the first sub-encapsulation layer closest to the defining dam layer within the first encapsulation layer group that is away from the defining dam layer.
[0024] In some embodiments, the material of the third encapsulation layer includes at least one of aluminum oxide, silicon nitride, silicon oxide, and titanium dioxide, and the thickness of the third encapsulation layer is in the range of 50 nm to 1000 nm.
[0025] In some embodiments, the outer contour of the first encapsulation layer group projected onto the first substrate is located inside the contour edge of the first substrate;
[0026] At least in some locations, the outer contour of the first encapsulation layer group projected onto the first substrate is spaced apart from the outer contour of the first substrate projected onto the first substrate and the contour edge of the first substrate.
[0027] In some embodiments, the light-emitting unit includes a plurality of sub-light-emitting functional layers corresponding one-to-one with the plurality of opening regions, wherein the orthographic projection of the sub-light-emitting functional layer on the first substrate overlaps with the orthographic projection of the corresponding opening region on the first substrate.
[0028] In some embodiments, the plurality of sub-light-emitting functional layers include: a first sub-light-emitting functional layer, a second sub-light-emitting functional layer, and a third sub-light-emitting functional layer; the plurality of sub-light-emitting functional layers emit a first light in a working state, the first light including at least one of blue light and ultraviolet light;
[0029] The plurality of opening regions include: a first opening region, a second opening region, and a third opening region; the first opening region is configured corresponding to the first sub-light-emitting functional layer, the second opening region is configured corresponding to the second sub-light-emitting functional layer, and the third opening region is configured corresponding to the third sub-light-emitting functional layer.
[0030] The optical functional layer includes: a first color conversion unit for converting a first light ray into red light, a second color conversion unit for converting the first light ray into green light, and a third color conversion unit for converting the first light ray into blue light or maintaining blue light; the first color conversion unit is located in the first opening area, the second color conversion unit is located in the second opening area, and the third color conversion unit is located in the third opening area.
[0031] The chip structure also includes an bonding layer located between the light-emitting unit and the color conversion unit, the bonding layer connecting the light-emitting unit and the color conversion unit.
[0032] In some embodiments, each of the plurality of sub-light-emitting functional layers includes: a first electrode, a first semiconductor layer, and a light-emitting layer stacked along a direction perpendicular to and toward the first substrate;
[0033] The light-emitting unit further includes a second semiconductor layer and a common electrode layer, wherein the second semiconductor layer is located on the light-emitting side of the plurality of sub-light-emitting functional layers;
[0034] The second semiconductor layer includes: a connecting portion and an auxiliary portion arranged in a direction parallel to the first substrate, the connecting portion being connected to the sub-light-emitting functional layer, at least a portion of the auxiliary portion being located between adjacent connecting portions, the auxiliary portion and the connecting portion being an integral structure, and the common electrode layer being connected to the auxiliary portion.
[0035] In some embodiments, the light-emitting unit is an LED.
[0036] Secondly, this disclosure also provides a display substrate, including: a driving backplane, and a plurality of chip structures arranged in an array on one side of the driving backplane, wherein the chip structures are the chip structures described above. Attached Figure Description
[0037] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:
[0038] Figure 1 This is a top view of a chip structure provided in some embodiments of this disclosure, parallel to a first substrate.
[0039] Figure 2 For along Figure 1 A cross-sectional view along line AA in the middle.
[0040] Figure 3 This is a schematic diagram of a first substrate and a color conversion unit provided in some embodiments of this disclosure.
[0041] Figure 4A for Figure 3 A schematic diagram of the first encapsulation layer group in the diagram.
[0042] Figure 4B for Figure 3 A schematic diagram of the first substrate, the defining dam layer, and the optical functional layer.
[0043] Figure 5 This is a schematic diagram showing the locations where the first encapsulation layer group is prone to film breakage.
[0044] Figure 6 The curve showing the relationship between the WVTR value and thickness of the first sub-encapsulation layer.
[0045] Figure 7 The curve showing the relationship between the WVTR value and thickness of the second sub-encapsulation layer.
[0046] Figure 8 For along Figure 1 Another cross-sectional view of line AA in the middle.
[0047] Figure 9 This is a top view of a light-emitting unit provided in some embodiments of the present disclosure, parallel to a first substrate.
[0048] Figure 10 For along Figure 9 A cross-sectional view along the BB line.
[0049] Figure 11 This is a top view of a second semiconductor layer provided in some embodiments of the present disclosure in a direction parallel to the first substrate.
[0050] Figure 12 This is a schematic diagram of the structure of an initial wafer provided for some embodiments of this disclosure.
[0051] Figure 13 This is a schematic diagram of the structure of the large plate of the initial mating plate provided in some embodiments of this disclosure.
[0052] Figure 14 This is a schematic diagram of the structure of the initial mating plate provided in some embodiments of this disclosure. Detailed Implementation
[0053] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.
[0054] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.
[0055] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.
[0056] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.
[0057] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.
[0058] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.
[0059] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.
[0060] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
[0061] The color-conversion LED display substrate in related technologies includes multiple chip structures. Each chip structure includes a color conversion unit and an LED light-emitting unit. The color conversion unit is located on the light-emitting side of the LED light-emitting unit. The color conversion unit includes a defining dam layer with multiple opening areas and an optical functional layer located inside the opening areas. The color conversion unit and the defining dam layer need to be encapsulated using a packaging structure. The water and oxygen barrier properties and side-wrapping properties of the packaging structure have a significant impact on the packaging reliability of the chip structure.
[0062] Figure 1 This is a top view of a chip structure provided in some embodiments of this disclosure, parallel to a first substrate. Figure 2 For along Figure 1 Sectional view of line AA in the middle. Figure 3 This is a schematic diagram of a first substrate and a color conversion unit provided in some embodiments of this disclosure. Figure 4A for Figure 3A schematic diagram of the first encapsulation layer group in the diagram. Figure 4B for Figure 3 A schematic diagram of the first substrate, the defining dam layer, and the optical functional layer.
[0063] like Figure 1 and Figure 2 As shown, the chip structure 1 includes a first substrate 15, a light-emitting unit 11, and a color conversion unit 12. Exemplarily, the first substrate 15 is, for example, a glass substrate. Specifically, the first substrate 15 is transparent in the visible light band. Specifically, the light-emitting unit 11 can be an LED, such as a Mini-LED or Micro-LED.
[0064] A color conversion unit 12 is disposed on a first substrate 15 and located on the light-emitting side of the light-emitting unit 11. The color conversion unit 12 includes a defining dam layer 121, an optical functional layer 122, and a first encapsulation layer group 123. The defining dam layer 121 is located on one side of the first substrate 15 and has multiple opening regions. The optical functional layer 122 is located inside the opening regions, and at least a portion of the optical functional layer 122 is used to convert the color of light entering the optical functional layer 122. The first encapsulation layer group 123 is located on the side of the defining dam layer 121 opposite to the first substrate 15. The orthographic projection of the defining dam layer 121 onto the first substrate 15 is located inside the orthographic projection of the first encapsulation layer group 123 onto the first substrate 15, so that the first encapsulation layer group 123 can encapsulate the defining dam layer 121 and the multiple optical functional layers 122, thereby protecting the defining dam layer 121 and the multiple optical functional layers 122.
[0065] like Figure 2 and Figure 3 As shown, the first encapsulation layer group 123 includes one first encapsulation layer 1231 or multiple stacked first encapsulation layers 1231. The first encapsulation layer 1231 includes a stacked first sub-encapsulation layer 1231a and a second sub-encapsulation layer 1231b. The first sub-encapsulation layer 1231a and the second sub-encapsulation layer 1231b have different compositions. Therefore, by selecting the materials of the first sub-encapsulation layer 1231a and the second sub-encapsulation layer 1231b, the first encapsulation layer group 123 as a whole can achieve good waterproof and oxygen-resistant effects on the front side of the color conversion unit 12 (i.e., the side facing the light-emitting unit 11), and can also effectively wrap the limiting dam layer 121 from the periphery, reducing or preventing the sides of the color conversion unit 12 from being eroded, and improving the encapsulation reliability of the color conversion unit 12.
[0066] In some embodiments, such as Figure 4BAs shown, the defining dam layer 121 includes a first surface 121a facing the first substrate 15, a second surface 121b facing away from the substrate, and an outer contour surface 121c located on one side of the first surface 121a and the second surface 121b. The outer contour surface 121c is a surface that surrounds the entire defining dam layer 121, and the included angle between the first surface 121a and the outer contour surface 121c is an obtuse angle.
[0067] The angle between the first surface 121a and the outer contour surface 121c is an obtuse angle. On the one hand, the color conversion unit 12 can have a larger bonding area without changing the distance between the opening area and the chip boundary, thus improving the bonding stability between the color conversion unit 12 and the light-emitting unit 11 while ensuring a small chip size. On the other hand, it can play a light-shielding role at the edge of the chip structure 1, reducing the impact of side light leakage caused by the light-emitting unit 11 on the light-emitting effect.
[0068] like Figure 4A As shown, the first encapsulation layer group 123 includes a first encapsulation surface S01 that is attached to the second surface 121b, a second encapsulation surface S02 that is attached to the outer contour surface 121c, and a third encapsulation surface S03 that extends along the extension surface of the first substrate 15. The first encapsulation surface S01 is directly connected to the second encapsulation surface S02, the second encapsulation surface S02 is directly connected to the third encapsulation surface S03, and the third encapsulation surface S03 is integrally disposed around the defining dam layer 121. The included angle between the second encapsulation surface S02 and the third encapsulation surface S03 is an acute angle.
[0069] Figure 5 This is a schematic diagram showing the locations where the first encapsulation layer group is prone to film layer breakage, as shown below. Figure 5 As shown, the angle C between the second encapsulation surface S02 and the third encapsulation surface S03 (that is, the angle between the first surface 121a and the outer contour surface 121c, hereinafter referred to as the "tilt position") is the stress concentration position of the first encapsulation layer group 123. The more concentrated the stress at this position, the more likely the first encapsulation layer group 123 is to break at this position, making the color conversion unit 12 susceptible to corrosion by external water and oxygen.
[0070] In one example, such as Figure 4BAs shown, the angle α between the second encapsulation surface S02 and the third encapsulation surface S03 is an acute angle. When α is an acute angle, if the first sub-encapsulation layer 1231a and the second sub-encapsulation layer 1231b have the same composition and both use film layers with good water and oxygen barrier properties, then the first sub-encapsulation layer 1231a and the second sub-encapsulation layer 1231b as a whole are equivalent to a film layer with a large thickness. At this time, the stress of the first encapsulation layer 1231 is more concentrated at the tilt position, and it is easy to break. If the first sub-encapsulation layer 1231a and the second sub-encapsulation layer 1231b have the same composition and both use buffer film layers with low stress, then the stress of the first encapsulation layer 1231 at the tilt position is small, and it is not easy to break. However, the water and oxygen barrier properties of these buffer film layers with low stress are often poor. In this embodiment, a material with good water and oxygen barrier properties can be used as the first sub-encapsulation layer 1231a, and a material with low stress can be used as the second sub-encapsulation layer 1231b. This can reduce the possibility of the first encapsulation layer 1231 breaking at the tilt position and ensure the water and oxygen barrier effect of the first encapsulation layer 1231.
[0071] In some embodiments, such as Figure 4B As shown, the included angle α between the second surface 121b and the outer contour surface 121c is an acute angle. For example, the included angle α is in the range of (0, 40°); for another example, the included angle α is in the range of (40°, 60°); for another example, the included angle α is in the range of (60°, 75°); for another example, the included angle α is in the range of (75°, 90°).
[0072] Of course, when α is a right angle or an obtuse angle (for example, when α is between 90° and 140°), the design of the first encapsulation layer group 123 in this disclosure can also be adopted to reduce the possibility of the first encapsulation layer 1231 breaking at the tilt position and to ensure the water and oxygen barrier effect of the first encapsulation layer 1231.
[0073] For example, the opening area includes a wall and a bottom, the angle γ between the wall and the first surface 121a is an obtuse angle, and the angle β between the wall and the second surface 121b is an acute angle. For example, the angle β between the wall and the second surface 121b is in the range of (0, 40°); for another example, the angle is in the range of (40°, 60°); for another example, the angle is in the range of (60°, 75°); for another example, the angle is in the range of (75°, 90°).
[0074] The angle between the wall and the first surface 121a is an obtuse angle, and the angle between the wall and the second surface 121b is an acute angle. In this way, when the optical functional layer 122 is prepared by inkjet printing, the limiting dam layer 121 can better limit the optical functional layer 122 during the preparation process, reduce or prevent the ink used in the preparation of the optical functional layer 122 from overflowing from the opening area, and improve the production yield.
[0075] In some embodiments, the material of the first sub-encapsulation layer 1231a includes an inorganic material containing silicon and nitrogen. For example, the material of the first sub-encapsulation layer 1231a includes at least one of silicon nitride and silicon oxide nitride. For example, the material of the first sub-encapsulation layer 1231a is silicon nitride or silicon oxynitride. For example, the thickness of the first sub-encapsulation layer 1231a is in the range of 300 nm to 600 nm. Figure 6 The curve showing the relationship between the WVTR value and thickness of the first sub-encapsulation layer 1231a is shown below. Figure 6 As shown, a thicker first sub-encapsulation layer 1231a provides better water and oxygen barrier properties, but it also increases film stress, making it more prone to fracture at tilt angles due to stress concentration. Conversely, a thinner first sub-encapsulation layer 1231a reduces film stress but weakens water and oxygen barrier properties. When the thickness of the first sub-encapsulation layer 1231a is set within the range of 300 nm to 600 nm, its water vapor transmission rate (WVTR) is less than 1 × 10⁻⁶. -3 g / m 2 The first sub-encapsulation layer 1231a exhibits good water vapor barrier properties, and the stress within this thickness range is relatively low. For example, the thickness of the first sub-encapsulation layer 1231a is 300 nm, 400 nm, 500 nm, or 600 nm.
[0076] Furthermore, the first sub-encapsulation layer 1231a exhibits poor step coverage within the aforementioned thickness range. Specifically, the thickness of the portion of the first sub-encapsulation layer 1231a located on the side away from the first substrate 15 between the optical functional layer 122 and the limiting dam layer 121 is denoted as the first thickness, while the thickness of the portion of the first sub-encapsulation layer 1231a opposite to the outer contour surface 121c of the limiting dam layer 121 is denoted as the second thickness. The second thickness is less than or equal to the first thickness, and the greater the difference between the first and second thicknesses, the worse the step coverage of the film layer, which can easily affect... The chip structure 1 has a water and oxygen barrier effect on its side. In this embodiment, the first encapsulation layer 1231 includes not only the first sub-encapsulation layer 1231a, but also the second sub-encapsulation layer 1231b. The second sub-encapsulation layer 1231b can be made of a material with a low Young's modulus to achieve good step coverage. This allows it to cover the outer contour surface 121c of the limiting dam layer 121, ensuring the water and oxygen barrier effect on the side of the chip structure 1. It can also fill the tilt angle position, reducing the stress of the subsequently formed film layer at the tilt angle position and preventing film layer breakage.
[0077] For example, the material of the second sub-encapsulation layer 1231b includes inorganic materials containing silicon, carbon, and nitrogen; the thickness of the second sub-encapsulation layer 1231b is in the range of 400nm to 600nm. Figure 7 The curve showing the relationship between the WVTR value and thickness of the second sub-encapsulation layer is shown below. Figure 7It can be seen that when the thickness of the second sub-encapsulation layer 1231b is in the range of 400nm to 600nm, the second sub-encapsulation layer 1231b has relatively low stress, with the absolute value of the stress between 14MPa and 28MPa. For example, the material of the second sub-encapsulation layer 1231b includes silicon carbonitride. For example, the material of the second sub-encapsulation layer 1231b is silicon carbonitride. For example, the thickness of the second sub-encapsulation layer 1231b is 400nm, or 450nm, or 500nm, or 550nm, or 600nm.
[0078] For example, in the second sub-encapsulation layer 1231b, the atomic ratio of silicon to carbon is between 0.4 and 0.6, which helps to reduce the stress of the second sub-encapsulation layer 1231b. Preferably, the atomic ratio of silicon to carbon is between 0.45 and 0.55, which further reduces the stress of the second sub-encapsulation layer 1231b. Herein, the atomic ratio refers to the ratio of the number of the two types of atoms.
[0079] Table 1 shows the simulation results of water and oxygen resistance of the first sub-encapsulation layer 1231a and the second sub-encapsulation layer 1231b. As shown in Table 1, when the thickness of the first sub-encapsulation layer 1231a increases from 400nm to 600nm, the time for external water and oxygen to penetrate the first sub-encapsulation layer 1231a (hereinafter referred to as "first erosion time") increases by 64.2%. For every 1μm increase in thickness, the first erosion time increases by 321%. When the WVTR value of the first sub-encapsulation layer 1231a changes from 2.39×E-3 to 0.99×E-3, the first erosion time increases by 102%. For every 1×E-3 change, the first erosion time increases by 321%. When the thickness of the second sub-encapsulation layer 1231b increases from 130 nm to 400 nm, the time for external water and oxygen to permeate through the second sub-encapsulation layer 1231b (hereinafter referred to as "second erosion time") increases by 52%, and for every 1 μm increase in thickness, the second erosion time increases by 193%. When the WVTR value of the second sub-encapsulation layer 1231b changes from 1.8 to 0.18, the first erosion time increases by 8.1%, and for every 1 decrease in the WVTR value, the second erosion time increases by 5%.
[0080] Table 1
[0081]
[0082] In some embodiments, the part of the first encapsulation layer 1231 furthest from the first substrate 15 is the second sub-encapsulation layer 1231b; the first encapsulation layer group 123 also includes a second encapsulation layer 1232, which is located on the side of the first encapsulation layer group 123 furthest from the first substrate 15. The material of the second encapsulation layer 1232 is the same as that of the first sub-encapsulation layer 1231a, and the thickness of the second encapsulation layer 1232 is in the range of 300nm to 600nm, thereby further improving the waterproof and oxygen-resistant effect of the first encapsulation layer group 123. Furthermore, since the second sub-encapsulation layer 1231b with a smaller Young's modulus is provided on the side of the second encapsulation layer 1232 closer to the first substrate 15, the second encapsulation layer 1232 can be prevented from breaking at the aforementioned tilt angle position.
[0083] In some embodiments, the first encapsulation layer group 123 may further include at least one third encapsulation layer (not shown), the third encapsulation layer being located on the side of the first sub-encapsulation layer 1231a closest to the defining dam layer 121 within the first encapsulation layer group 123 that is away from the defining dam layer 121. That is, the first sub-encapsulation layer 1231a is disposed between the third encapsulation layer and the defining dam layer 121.
[0084] For example, at the same thickness, the WVTR of the third encapsulation layer is less than or equal to the WVTR of the first sub-encapsulation layer 1231a. That is, the water and oxygen resistance of the third encapsulation layer is similar to or better than that of the first sub-encapsulation layer 1231a, thereby further improving the water and oxygen resistance of the first encapsulation layer group 123.
[0085] Specifically, the material of the third encapsulation layer includes at least one of aluminum oxide, silicon oxide (SiOx), silicon nitride (SiNy), and titanium dioxide. The thickness of the third encapsulation layer is between 50 nm and 1000 nm. In this case, the WVTR of the third encapsulation layer is less than or equal to 10. -4 .
[0086] For example, the third encapsulation layer may be disposed between the first sub-encapsulation layer 1231a and the second sub-encapsulation layer 1231b; or, the third encapsulation layer may be disposed on the side of the first encapsulation layer group 123 furthest from the first substrate 15.
[0087] In some embodiments, the thickness of the first encapsulation layer group 123 can be less than or equal to 5 μm, thereby reducing the distance between the light-emitting unit 11 and the optical functional layer 122, and thus reducing the problem of color crosstalk between adjacent optical functional layers 122. In practical applications, the number of the first encapsulation layers 1231 can be set according to the actual situation (e.g., limiting the height of the dam layer 121, the angle of the tilt position, etc.) to ensure that the first encapsulation layer group 123 as a whole can achieve good step coverage.
[0088] In some embodiments, reference Figure 2 The outer contour of the first encapsulation layer group 123 projected on the first substrate 15 is located inside the contour edge of the first substrate 15; at least in some locations, there is a first gap distance d1 between the outer contour of the first encapsulation layer group 123 projected on the first substrate 15 and the outer contour of the first substrate 15 projected on the first substrate 15 and the contour edge of the first substrate 15, thereby preventing the film layer in the first encapsulation layer group 123 from cracking due to cutting during the fabrication process of the chip structure 1.
[0089] For example, in the fabrication process of chip structure 1, an initial wafer A comprising multiple light-emitting units 11 can be prepared first, and a large plate N can be prepared, comprising an initial substrate and multiple color conversion units 12 located on the initial substrate. Furthermore, a gap is left between the first encapsulation layer groups 123 of adjacent color conversion units 12. Then, the large plate N is cut to form an initial cassette plate B; subsequently, the initial wafer A and the initial cassette plate B are bonded together to obtain an initial chip board; then, the initial chip board is cut to obtain a single chip structure 1. The gap between the first encapsulation layer groups 123 of adjacent color conversion units 12 can prevent cracks in the film layer due to cutting.
[0090] In some embodiments, such as Figure 2 As shown, the chip structure 1 also includes a light-shielding layer 124 located between the defining dam layer 121 and the first substrate 15. The light-shielding layer 124 includes light-transmitting holes corresponding to the opening regions. The orthographic projection of the opening region on the first substrate 15 overlaps with the orthographic projection of the corresponding light-transmitting hole on the first substrate 15, so that light emitted through the multiple opening regions can pass through the light-transmitting holes and exit from the light-emitting side of the chip structure 1. For example, the orthographic projection of the light-transmitting hole on the first substrate 15 is located inside the orthographic projection of the opening region on the first substrate 15.
[0091] Wherein, the orthographic projection of the first surface 121a on the first substrate 15 is located inside the orthographic projection of the light-shielding layer 124 on the first substrate 15, and the light-shielding layer 124 protrudes from the outer contour of the first surface 121a in a direction parallel to the first substrate 15, such that at least a portion of the third package surface S03 extends on the light-shielding layer 124.
[0092] Preferably, refer to Figure 2The outer contour projected onto the first substrate 15 by the light-shielding layer 124 is located inside the contour edge of the first substrate 15. At least in some locations, there is a second spacing distance d2 between the outer contour projected onto the first substrate 15 and the contour edge of the first substrate 15. This prevents cracks or tears in the film layer of the light-shielding layer 124 due to cutting during the fabrication of the chip structure 1, which would reduce the overall water and oxygen resistance of the chip structure 1. Specifically, the first spacing distance d1 and the second spacing distance d2 can be equal or unequal.
[0093] Figure 8 For along Figure 1 Another cross-sectional view of line AA, such as Figure 8 As shown, the chip structure 1 also includes a second packaging layer group 126 located between the light-shielding layer 124 and the first substrate 15; the second packaging layer group 126 is disposed in contact with the first packaging layer group 123 and forms a receiving space to completely enclose the limiting dam layer 121 and the optical functional layer 122, thereby further preventing the limiting dam layer 121 and the optical functional layer 122 from being eroded by external water and oxygen.
[0094] In some examples, the second encapsulation layer group 126 may include one or more stacked fourth encapsulation layers. The fourth encapsulation layer includes a stacked third sub-encapsulation layer and a fourth sub-encapsulation layer. The material of the third sub-encapsulation layer may be the same as that of the first sub-encapsulation layer 1231a, and the material of the fourth sub-encapsulation layer may be the same as that of the second sub-encapsulation layer 1231b. Alternatively, the second encapsulation layer group 126 may also include a fifth encapsulation layer made of the same material as the second encapsulation layer 1232, disposed on the side of the fourth encapsulation layer away from the first substrate 15.
[0095] In some examples, the outer contour projected onto the first substrate 15 by the second encapsulation layer group 126 is located inside the contour edge of the first substrate 15; at least in some locations, there is a third spacing distance d3 between the outer contour projected onto the first substrate 15 and the contour edge of the first substrate 15. This prevents cracks or tears in the film layer of the second encapsulation layer group 126 due to cutting during the fabrication of the chip structure 1, which would reduce the overall water and oxygen resistance of the chip structure 1. Specifically, the third spacing distance d3 and the aforementioned first spacing distance d1 may be equal or unequal.
[0096] Figure 9 This is a top view of a light-emitting unit provided in some embodiments of this disclosure, parallel to the first substrate. Figure 10 For along Figure 9 Sectional view of the middle BB line. Figure 11 This is a top view of a second semiconductor layer provided in some embodiments of this disclosure, in a direction parallel to the first substrate. (See attached image.) Figure 9 and Figure 10As shown, the light-emitting unit 11 includes a plurality of sub-light-emitting functional layers 111 corresponding to a plurality of opening regions. The orthographic projection of the sub-light-emitting functional layer 111 on the first substrate 15 overlaps with the orthographic projection of the corresponding opening region on the first substrate 15, so that the light emitted by the sub-light-emitting functional layer 111 can be incident on the optical functional layer 122 in the opening region.
[0097] Each of the plurality of sub-light-emitting functional layers 111 includes a first electrode 1112, a first semiconductor layer 1111, and a light-emitting layer 1113 stacked along a direction perpendicular to and toward the first substrate 15. The light-emitting unit also includes a second semiconductor layer 112 and a common electrode layer 113, wherein the second semiconductor layer 112 is located on the light-emitting side of the plurality of sub-light-emitting functional layers 111.
[0098] The first electrode 1112 and the common electrode layer 113 can be used as the anode and cathode, respectively, so that after the first electrode 1112 and the common electrode layer 113 are fed with current, holes and electrons will be transported in the first semiconductor layer 1111, the light-emitting layer 1113 and the second semiconductor layer 112 between them, thereby exciting the light-emitting layer 1113 to emit light.
[0099] For example, such as Figure 10 As shown, the common electrode layer 113 includes a first common electrode layer 1131 and a second common electrode layer 1132 sequentially stacked along a direction perpendicular to the first substrate 15; the second common electrode layer 1132 is located on the side of the first common electrode layer 1131 closest to the second semiconductor layer 112. The first common electrode layer 1131 is used for electrical connection to external traces, and the second common electrode layer 1132 is electrically connected to the second semiconductor layer 112. The second common electrode layer 1132 can serve as a current spreader.
[0100] For example, the common electrode layer 113 can be a common cathode.
[0101] For example, the first electrode 1112 is made of an anode material such as indium tin oxide (ITO) or silver (Ag); the common electrode layer 113 is made of a cathode material such as an alloy metal; the first semiconductor layer 1111 is, for example, a P-type gallium nitride (GaN) layer; the light-emitting layer 1113 is, for example, a quantum well (MQW) material layer; and the second semiconductor layer 112 is, for example, an N-type gallium nitride layer.
[0102] For example, a current spreading layer may also be disposed between the first electrode 1112 and the first semiconductor layer 1111. The material of the current spreading layer may be indium tin oxide (ITO), and its function is, for example, to facilitate the transport of holes.
[0103] like Figure 11As shown, the second semiconductor layer 112 includes: a connecting portion 1121 and an auxiliary portion arranged in a direction parallel to the first substrate 15. The connecting portion 1121 is connected to the sub-light-emitting functional layer 111. At least a portion of the auxiliary portion is located between adjacent connecting portions 1121. The auxiliary portion and the connecting portion 1121 are integral structures. The common electrode layer 113 is connected to the auxiliary portion. That is, multiple sub-light-emitting functional layers 111 are all connected to the entire second semiconductor layer 112, that is, multiple sub-light-emitting functional layers 111 share the same second semiconductor layer 112.
[0104] In some examples, such as Figure 11 As shown, the auxiliary part includes a first auxiliary part 1122a connected to the common electrode 113, a second auxiliary part 1122 located between two adjacent connecting parts 1121 or between the connecting part 1121 and the first connecting part 1121, and a third auxiliary part 1122c surrounding the first auxiliary part 1122a, the second auxiliary part 1122, and the connecting part 1121 as a whole.
[0105] In some examples, such as Figure 11 As shown, the projection shape of the second semiconductor layer 112 on the first substrate 15 is rectangular. There are three connecting portions 1121, corresponding one-to-one with the three color filter units (see description below). The aforementioned first auxiliary portion 1122a and the three connecting portions 1121 are arranged in a 2×2 array so that the projection shape of the light-emitting unit 11 on the plane of the first substrate 15 is approximately rectangular, thereby facilitating cutting during the fabrication process.
[0106] For example, the second semiconductor layer 112 may also include a buffer layer made of gallium nitride, which is disposed on the side of the second semiconductor layer 112 near the optical functional layer 122 and on the side of the N-type gallium nitride layer away from the light-emitting functional layer 111.
[0107] For example, such as Figure 10 As shown, the side of the light-emitting functional layer 111 away from the second semiconductor layer 112 is also covered with an insulating protective layer 1114 to protect the light-emitting functional layer 111 and the second semiconductor layer 112.
[0108] In some embodiments, the plurality of sub-light-emitting functional layers 111 include: a first sub-light-emitting functional layer, a second sub-light-emitting functional layer, and a third sub-light-emitting functional layer. The plurality of sub-light-emitting functional layers 111 emit a first light ray in an operational state, the first light ray including at least one of blue light and ultraviolet light. The plurality of opening regions include: a first opening region, a second opening region, and a third opening region. The first opening region is correspondingly disposed with respect to the first sub-light-emitting functional layer, the second opening region is correspondingly disposed with respect to the second sub-light-emitting functional layer, and the third opening region is correspondingly disposed with respect to the third sub-light-emitting functional layer.
[0109] The optical functional layer 122 includes: a first color conversion unit for converting a first light ray into red light, a second color conversion unit for converting the first light ray into green light, and a third color conversion unit for converting the first light ray into blue light or maintaining blue light. The first color conversion unit is located in a first opening region, the second color conversion unit is located in a second opening region, and the third color conversion unit is located in a third opening region.
[0110] For example, the first color conversion unit includes a red quantum dot material that converts light into red light; preferably, the first color conversion unit also includes scattering particles for scattering light. Here, the light emitted from the corresponding first sub-light-emitting functional layer, after striking the first color conversion unit distributed in the corresponding opening area, is converted into red light by the red quantum dots, and the light and red light are scattered by the scattering particles, so as to ensure that more light can be converted into red light by the red quantum dots, and to ensure that the emitted angle of the converted red light is large, so as to ensure that the viewing angle of the chip structure is large.
[0111] For example, the second color conversion section includes a green quantum dot material that converts light into green light; preferably, the second color conversion section also includes scattering particles for scattering light. Here, the light emitted from the corresponding second sub-light-emitting functional layer, after being incident on the first color conversion section distributed in the corresponding opening area, can be converted into green light by the green quantum dots, and the light and green light can be scattered by the scattering particles, so as to ensure that more light can be converted into green light by the green quantum dots, and to ensure that the emitted green light has a large exit angle, so as to ensure that the light-emitting component has a large viewing angle.
[0112] For example, the third color conversion unit is used to convert light into blue light or maintain blue light emission. For instance, when the light contains only blue light, the third color conversion unit can be a transparent portion or include blue quantum dots; wherein, the transparent portion allows direct light transmission, and the blue quantum dots are used to convert the light into blue light with a different wavelength. Preferably, the third color conversion unit also includes scattering particles that scatter the light. Here, the light emitted from the corresponding third sub-light-emitting functional layer, after striking the third color conversion unit distributed within the corresponding opening area, is scattered by the scattering particles to ensure a large blue light emission angle, thereby ensuring a large viewing angle for the integrated light-emitting component. For example, when the light contains ultraviolet light, the third color conversion unit includes blue quantum dots that convert the light into blue light, or the third color conversion unit simultaneously contains scattering particles for scattering light and blue quantum dots for converting ultraviolet light into blue light.
[0113] In some embodiments, such as Figure 1 and Figure 2As shown, the chip structure 1 also includes multiple filter units 125, which are located between the first substrate 15 and the optical functional layer 122. The orthographic projection of the filter unit 125 on the first substrate 15 overlaps with the orthographic projection of the corresponding light-transmitting hole on the first substrate 15. The filter units 125 and the optical functional layer 122 are arranged in a one-to-one correspondence, and the orthographic projection of the filter unit 125 on the first substrate 15 overlaps with the orthographic projection of the corresponding optical functional layer 122 on the first substrate 15, so that light passing through the optical functional layer 122 can enter the filter unit 125 and be filtered by the filter unit 125 to obtain light of a specified color (or wavelength).
[0114] The multiple filter units 125 may include a first filter unit 125a, a second filter unit 125b, and a third filter unit 125c; wherein, the first filter unit 125a is a red color resist or a red-green-blue-reflecting filter film, and is disposed corresponding to the first color conversion unit to ensure that red light passes through; the second filter unit 125b is a green color resist or a red-green-blue-reflecting filter film, and is disposed corresponding to the second color conversion unit to ensure that green light passes through; the third filter unit 125c is a blue color resist or a transparent layer, and is disposed corresponding to the third color conversion unit to ensure that blue light passes through.
[0115] For example, the aforementioned red color filter can transmit red light and absorb light of other colors. In this way, the light emitted from the first color conversion unit can pass through the first filter unit 125a before being emitted, and the first filter unit 125a can filter out light of other colors except red light, so as to ensure that the blue light component in the light is filtered out.
[0116] For example, the aforementioned red-green anti-blue filter film allows the red portion of the light emitted from the first color conversion unit to pass through and reflect blue light. In this way, the red light in the light can pass through the first filter unit 125a and be emitted, while the blue light can be reflected back to the first color conversion unit by the first filter unit 125a. This allows the red quantum dots in the first color conversion unit to excite the blue light into red light, thereby further improving the excitation efficiency of the red quantum dots.
[0117] For example, the aforementioned green color filter can transmit green light and absorb light of other colors. In this way, the light emitted from the second color conversion unit can pass through the second filter unit 125b before being emitted, and the second filter unit 125b can filter out light of other colors except green light, so as to ensure that the blue light component in the light is filtered out.
[0118] For example, the aforementioned red-green-blue-reflecting filter film allows the green portion of the light emitted from the second color conversion unit to pass through and reflects blue light. In this way, the green light in the light can pass through the second filter unit 125b and be emitted, while the blue light can be reflected back to the second color conversion unit by the second filter unit 125b. This allows the green quantum dots in the second color conversion unit to excite the blue light back into green light, thereby further improving the excitation efficiency of the green quantum dots.
[0119] For example, the aforementioned blue color filter can transmit blue light and absorb other colors of light. In this way, the light emitted from the third color conversion unit can pass through the third filter unit 125c before being emitted, and the third filter unit 125c can filter out light of other colors except blue light, so that the third filter unit 125c transmits relatively pure blue light.
[0120] For example, since the first color conversion unit, the second color conversion unit, and the third color conversion unit can all generate blue light, a transparent layer can be used as the third filter unit 125c to transmit blue light.
[0121] In some embodiments, such as Figure 2 and Figure 8 As shown, the chip structure 1 also includes an adhesive layer 13 located between the light-emitting unit 11 and the color conversion unit 12, connecting the light-emitting unit 11 and the color conversion unit 12. It should be noted that the adhesive layer 13 allows light emitted by the light-emitting unit 11 to pass through, i.e., the adhesive layer 13 is light-transmitting, to ensure normal light emission from the chip structure 1. For example, the material of the adhesive layer 13 may be an epoxy resin-based organic adhesive, utilizing the adhesive effect of the adhesive material to achieve bonding between the color conversion unit 12 and the light-emitting unit 11.
[0122] The fabrication method of the above-mentioned chip structure 1 is described below. Specifically, the fabrication method of chip structure 1 includes:
[0123] S1. Light-emitting unit 11 and color conversion unit 12 are manufactured independently.
[0124] S2. An adhesive is formed on at least one of the light-emitting side of the light-emitting unit 11 and the light-incident side of the color conversion unit 12.
[0125] S3. The light-emitting side of the light-emitting unit 11 and the light-incident side of the color conversion unit 12 are attached to each other to achieve the alignment of the light-emitting unit 11 and the color conversion unit 12.
[0126] If, in step S2, an adhesive is formed on the light-emitting side of the light-emitting unit 11, then step S2 may specifically include:
[0127] S211. A temporary substrate is provided, and the light-emitting unit 11 is bonded to the temporary substrate, with the second semiconductor layer 112 disposed away from the temporary substrate.
[0128] S212, an adhesive material layer is coated on the surface of the light-emitting unit 11 away from the temporary substrate; that is, an adhesive material layer is coated on the surface of the second semiconductor layer 112 away from the temporary substrate.
[0129] For example, the adhesive material is an epoxy resin-based organic adhesive material, and the adhesive material layer can be formed by a stencil printing process.
[0130] If adhesive is formed on the color conversion unit 12 in step S2 above, then the step of forming an adhesive layer on the color conversion unit 12 specifically includes:
[0131] S221. A temporary substrate is provided, and the color conversion unit 12 is bonded to the temporary substrate, with the first encapsulation layer group 123 disposed away from the temporary substrate.
[0132] S222, Apply an adhesive material layer to the surface of the light-emitting unit 11 on the side away from the temporary substrate; that is, apply an adhesive material layer to the surface of the first encapsulation layer group 123 on the side away from the temporary substrate.
[0133] Figure 12 This is a schematic diagram of the structure of an initial wafer provided in some embodiments of this disclosure. Figure 13 This is a schematic diagram of the structure of the large plate of the initial mating plate provided in some embodiments of this disclosure. Figure 14 This is a schematic diagram of the structure of an initial mating plate provided in some embodiments of this disclosure. It is understood that in the fabrication process of the light-emitting unit 11, an initial wafer A is typically used for the process, specifically, as shown below. Figure 12 As shown, the initial chip A includes multiple light-emitting units 11 arranged in an array. Figure 13 As shown, during the fabrication of the color conversion unit 12, multiple color conversion units 12 arranged in an array can be simultaneously formed on the initial substrate 15a to obtain a large plate N. Therefore, before the color conversion unit 12 and the light-emitting unit 11 are aligned, a step of cutting the large plate N is included to form multiple initial alignment plates B; specifically, as shown... Figure 14 As shown, the initial mating plate B includes multiple color conversion units 12.
[0134] The process of simultaneously forming multiple arrayed color conversion units 12 on the initial substrate 15a may specifically include: simultaneously forming a defining dam layer 121 for the multiple color conversion units 12; then, forming a corresponding optical functional layer 122 in each opening region of the defining dam layer 121; wherein the optical functional layers 122 of the same material can be formed simultaneously; then, forming a complete encapsulation structure and etching the encapsulation structure to form a first encapsulation layer group 123 corresponding to each color conversion unit 12. After etching, the encapsulation structure can be divided into multiple first encapsulation layer groups 123, thereby preventing cracks in the film layer of the first encapsulation layer group 123 due to cutting during the subsequent cutting step S33.
[0135] Each encapsulation layer in the first encapsulation layer group 123 can be formed using a chemical vapor deposition (CVD) process, thereby improving the coating effect of the first encapsulation layer group 123 on the side of the defined dam layer 121.
[0136] The following describes the steps involved in joining the initial wafer A and the initial mating plate B to form a single light-emitting component 1. Specifically, steps S31 to S34 are described below:
[0137] S31. Align the initial wafer A and the initial mating plate B to bond the initial wafer A and the initial mating plate B together through an adhesive material layer on the surface of one of them.
[0138] It is easy to understand that, in order to ensure that the multiple light-emitting units 11 in the initial wafer A and the multiple color-conversion units 12 in the initial mating plate B are in one-to-one correspondence, two initial wafers A and initial mating plates B with the same unit distribution can be selected. Therefore, in step S31 above, the edges of the initial wafer A and the initial mating plate B can be overlapped to ensure that the multiple light-emitting units 11 and the multiple color-conversion units 12 are in one-to-one correspondence. For example, after preparing the initial wafer A, the bonding layer can be entirely disposed on the surface of the second semiconductor layer 112, or the bonding layer can be entirely disposed on the surface of the first encapsulation layer group 123 away from the initial substrate 15a, or a portion of the bonding layer can be disposed on the surface of the second semiconductor layer 112 and another portion on the surface of the first encapsulation layer group 123 away from the initial substrate 15a.
[0139] S32. Remove the temporary substrate to form the initial chip board.
[0140] For example, the adhesive between the temporary substrate and the initial wafer A or the temporary substrate and the initial mating plate B can be debonded by ultraviolet light irradiation, so as to remove the temporary substrate and the adhesive.
[0141] S33. Cut the initial chip board to obtain a single chip structure 1.
[0142] For example, the initial substrate 15a is cut to form a first substrate 15; the projection of the bonding layer 13 on the multiple sub-light-emitting functional layers 111 in the single chip structure obtained after cutting covers the multiple sub-light-emitting functional layers 111.
[0143] As another technical solution, this disclosure also provides a display substrate, including the above-mentioned chip structure and a driving substrate; wherein, the chip structure array is arranged on the driving substrate; the driving substrate is used to electrically connect with the chip structure and drive the chip structure to emit light.
[0144] In some examples, the driving substrate in the display substrate includes a circuit layer, which includes, for example, multiple pad groups, each pad group including multiple separately arranged pads. The first electrode and common electrode of each chip structure are electrically connected to one of the multiple pads, so that the driving substrate can drive the corresponding chip structure to emit light, thereby achieving the effect of displaying an image.
[0145] Exemplary examples show that the display device provided in this disclosure can be any device that displays text or images, whether in motion (e.g., video) or still (e.g., a static image). More specifically, the embodiments are contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.
[0146] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.
Claims
1. A chip structure, characterized in that, include: A first substrate, a light-emitting unit, and a color conversion unit, wherein the color conversion unit is located on the light-emitting side of the light-emitting unit; The color conversion unit includes: A defined dam layer located on one side of the first substrate, the defined dam layer having an opening region; An optical functional layer located inside the opening area is used to convert the color of light entering the optical functional layer; And, a first encapsulation layer group located on the side of the defining dam layer and the optical functional layer facing away from the first substrate, wherein the orthographic projection of the defining dam layer on the first substrate is located inside the orthographic projection of the first encapsulation layer group on the first substrate; The first encapsulation layer group includes a second encapsulation layer and a third encapsulation layer, wherein the second encapsulation layer is located on the side of the third encapsulation layer away from the first substrate, and the second encapsulation layer and the third encapsulation layer have different compositions; The material of the third encapsulation layer includes at least one of aluminum oxide, silicon oxide, silicon nitride, and titanium dioxide; the material of the second encapsulation layer includes an inorganic substance containing silicon and nitrogen.
2. The chip structure according to claim 1, characterized in that, The thickness of the second encapsulation layer is in the range of 300nm to 600nm, and / or the thickness of the third encapsulation layer is in the range of 50nm to 1000nm.
3. The chip structure according to claim 1, characterized in that, The material of the second encapsulation layer includes at least one of silicon nitride and silicon oxide.
4. The chip structure according to claim 1, characterized in that, The first encapsulation layer group further includes a first encapsulation layer located between the third encapsulation layer and the second encapsulation layer. The first encapsulation layer includes a first sub-encapsulation layer and a second sub-encapsulation layer stacked together. The second sub-encapsulation layer is located on the side of the first sub-encapsulation layer away from the third encapsulation layer. The first sub-encapsulation layer and the second sub-encapsulation layer have different compositions. The material of the first sub-encapsulation layer includes inorganic materials containing silicon and nitrogen, and the material of the first sub-encapsulation layer is different from the material of the third encapsulation layer.
5. The chip structure according to claim 4, characterized in that, The thickness of the first sub-encapsulation layer is in the range of 300nm to 600nm, and / or the thickness of the second sub-encapsulation layer is in the range of 400nm to 600nm.
6. The chip structure according to claim 5, characterized in that, The material of the second sub-encapsulation layer includes inorganic materials containing silicon, carbon, and nitrogen.
7. The chip structure according to claim 4, characterized in that, The first encapsulation layer group includes a plurality of stacked first encapsulation layers, wherein a first sub-encapsulation layer of one of the first encapsulation layers is located between the defining dam layer and the third encapsulation layer.
8. The chip structure according to claim 1, characterized in that, The first encapsulation layer group includes a first encapsulation layer, the first encapsulation layer includes a first sub-encapsulation layer, the first sub-encapsulation layer is located between the third encapsulation layer and the defining dam layer, the material of the first sub-encapsulation layer includes an inorganic material containing silicon and nitrogen, and the material of the first sub-encapsulation layer is different from the material of the third encapsulation layer.
9. The chip structure according to claim 8, characterized in that, The first sub-encapsulation layer is in direct contact with the third encapsulation layer.
10. The chip structure according to claim 9, characterized in that, The thickness of the first sub-encapsulation layer is in the range of 300nm to 600nm.
11. The chip structure according to claim 8, characterized in that, The first encapsulation layer further includes a second sub-encapsulation layer, which is located between the third encapsulation layer and the second encapsulation layer.
12. The chip structure according to claim 11, characterized in that, The material of the second sub-encapsulation layer includes inorganic substances containing silicon, carbon, and nitrogen; The thickness of the second sub-encapsulation layer is in the range of 400nm to 600nm.
13. The chip structure according to claim 1, characterized in that, The water vapor transmission rate of the third encapsulation layer is less than or equal to 10. -4 g / m 2 .
14. The chip structure according to any one of claims 1-13, characterized in that, The defined dam layer includes a first surface facing the first substrate, a second surface facing away from the first substrate, and an outer contour surface located on one side of the first surface and the second surface. The outer contour surface is a surface that surrounds the entire defined dam layer, and the included angle between the first surface and the contour surface is an obtuse angle. The first encapsulation layer group includes a first encapsulation surface that is attached to the second surface, a second encapsulation surface that is attached to the outer contour surface, and a third encapsulation surface that extends along the first substrate extension surface, wherein the first encapsulation surface is directly connected to the second encapsulation surface, the second encapsulation surface is directly connected to the third encapsulation surface, and the third encapsulation surface is disposed around the entire limiting layer; The angle between the second packaging surface and the third packaging surface is an acute angle.
15. The chip structure according to claim 14, characterized in that, The angle between the second surface and the outer contour surface is an acute angle.
16. The chip structure according to claim 15, characterized in that, The opening area includes a wall and a bottom. The angle between the wall and the first surface is an obtuse angle, and the angle between the wall and the second surface is an acute angle.
17. The chip structure according to claim 14, characterized in that, It also includes a light-shielding layer located between the defined dam layer and the first substrate, the light-shielding layer including light-transmitting holes corresponding one-to-one with the opening areas, the orthographic projection of the opening area on the first substrate and the orthographic projection of the corresponding light-transmitting hole on the first substrate overlapping; Wherein, the orthographic projection of the first surface on the first substrate is located inside the orthographic projection of the light-shielding layer on the first substrate, and the light-shielding layer protrudes from the outer contour of the first surface in a direction parallel to the first substrate, such that at least a portion of the third encapsulation surface extends on the light-shielding layer.
18. The chip structure according to any one of claims 1-13, characterized in that, It also includes a second encapsulation layer group located between the defining dam layer and the first substrate; the second encapsulation layer group is disposed in contact with the first encapsulation layer group and forms a receiving space to completely encapsulate the defining dam layer and the optical functional layer.
19. The chip structure according to any one of claims 1-13, characterized in that, The outer contour of the first encapsulation layer group projected onto the first substrate is located inside the contour edge of the first substrate; At least in some locations, the outer contour of the first encapsulation layer group projected onto the first substrate is spaced apart from the outer contour of the first substrate projected onto the first substrate and the contour edge of the first substrate.
20. The chip structure according to any one of claims 1-13, characterized in that, The light-emitting unit includes a sub-light-emitting functional layer corresponding to the opening region, wherein the orthographic projection of the sub-light-emitting functional layer on the first substrate overlaps with the orthographic projection of the opening region on the first substrate; The light-emitting unit is a Mini-LED or a Micro-LED.
21. A chip structure, characterized in that, include: A first substrate, a light-emitting unit, and a color conversion unit, wherein the color conversion unit is located on the light-emitting side of the light-emitting unit; The color conversion unit includes: A defined dam layer located on one side of the first substrate, the defined dam layer having an opening region; An optical functional layer located inside the opening area is used to convert the color of light entering the optical functional layer; And, a first encapsulation layer group located on the side of the defined dam layer opposite to the first substrate, wherein the orthographic projection of the defined dam layer on the first substrate is located inside the orthographic projection of the first encapsulation layer group on the first substrate; The first encapsulation layer group includes one first encapsulation layer or multiple stacked first encapsulation layers. The first encapsulation layer includes a stacked first sub-encapsulation layer and a second sub-encapsulation layer, wherein the first sub-encapsulation layer and the second sub-encapsulation layer have different compositions. The material of the first sub-encapsulation layer includes an inorganic material containing silicon and nitrogen; the Young's modulus of the second sub-encapsulation layer is less than that of the first sub-encapsulation layer.
22. The chip structure according to claim 21, characterized in that, The first encapsulation layer group further includes a second encapsulation layer, which is located on the side of the first encapsulation layer group furthest from the first substrate, and the material of the second encapsulation layer is the same as that of the first sub-encapsulation layer.
23. The chip structure according to claim 22, characterized in that, The thickness of the second encapsulation layer is in the range of 300nm to 600nm.
24. The chip structure according to claim 23, characterized in that, The thickness of the first sub-encapsulation layer is in the range of 300nm to 600nm.
25. The chip structure according to any one of claims 21-24, characterized in that, The defined dam layer includes a first surface facing the first substrate, a second surface facing away from the first substrate, and an outer contour surface located on one side of the first surface and the second surface. The outer contour surface is a surface that surrounds the entire defined dam layer, and the included angle between the first surface and the contour surface is an obtuse angle. The first encapsulation layer group includes a first encapsulation surface that is attached to the second surface, a second encapsulation surface that is attached to the outer contour surface, and a third encapsulation surface that extends along the first substrate extension surface, wherein the first encapsulation surface is directly connected to the second encapsulation surface, the second encapsulation surface is directly connected to the third encapsulation surface, and the third encapsulation surface is disposed around the entire limiting layer; The angle between the second packaging surface and the third packaging surface is an acute angle.
26. The chip structure according to claim 25, characterized in that, The light-emitting unit includes a sub-light-emitting functional layer corresponding to the opening region, wherein the orthographic projection of the sub-light-emitting functional layer on the first substrate overlaps with the orthographic projection of the opening region on the first substrate; The light-emitting unit is a Mini-LED or a Micro-LED.
27. A display substrate, characterized in that, include: A driving backplane, and a plurality of chip structures arranged in an array on one side of the driving backplane, wherein the chip structures are any of the chip structures described in claims 1 to 26.