Display device and electronic device including the same

Abstract

The present disclosure relates to a display device and an electronic device including the same. The display device includes a substrate, a pixel driving circuit on the substrate and including a transistor, a connection electrode on the substrate and electrically connected to the pixel driving circuit, a first electrode on the substrate and spaced apart from the connection electrode, a pixel defining layer on the substrate, the pixel defining layer defining an opening exposing a portion of the first electrode, an electrode layer on the first electrode and electrically connected to the connection electrode, a first driving voltage line in a same layer as the first electrode and configured to receive a first power voltage, the first driving voltage line extending in a first direction, and a second driving voltage line in a same layer as the first electrode and configured to receive the first power voltage, the second driving voltage line extending in a second direction intersecting the first direction.

Description

Technical Field

[0001] This disclosure generally relates to display devices. More specifically, this disclosure relates to display devices and electronic devices including display devices. Background Technology

[0002] With the development of information technology, the importance of display devices, which provide a connection medium between users and information, has become increasingly prominent. For example, the use of display devices such as liquid crystal displays (LCDs), organic light-emitting diode (OLEDs), plasma display panels (PDPs), and quantum dot displays is increasing.

[0003] The display device includes a light-emitting element and a pixel driving circuit for driving the light-emitting element. The light-emitting element is driven by the pixel driving circuit to emit light. Summary of the Invention

[0004] Some exemplary embodiments provide display devices with improved display quality. Some exemplary embodiments provide display devices with improved reliability.

[0005] Some exemplary embodiments provide electronic devices that include a display device.

[0006] A display device according to some exemplary embodiments of the present disclosure includes: a substrate; a pixel driving circuit on the substrate, the pixel driving circuit including transistors; a connection electrode on the substrate, the connection electrode electrically connected to the pixel driving circuit; a first electrode on the substrate, the first electrode spaced apart from the connection electrode; a pixel defining layer on the substrate, the pixel defining layer defining an opening exposing a portion of the first electrode; an electrode layer on the first electrode, the electrode layer electrically connected to the connection electrode; a first driving voltage line in the same layer as the first electrode, the first driving voltage line configured to receive a first electrical voltage and extending in a first direction; and a second driving voltage line in the same layer as the first electrode, the second driving voltage line configured to receive the first electrical voltage and extending in a second direction intersecting the first direction.

[0007] In some exemplary embodiments, the first driving voltage line and the second driving voltage line may have a mesh shape in a plan view.

[0008] In some exemplary embodiments, the display device may further include: a third driving voltage line between the substrate and the first electrode, the third driving voltage line being configured to receive a first electrical voltage; and a fourth driving voltage line between the third driving voltage line and the first electrode, the fourth driving voltage line being configured to receive the first electrical voltage.

[0009] In some exemplary embodiments, the third and fourth driving voltage lines may have a mesh shape in a plan view.

[0010] In some exemplary embodiments, the display device may further include: a separator on the pixel defining layer, the separator being configured to divide the electrode layer into a plurality of second electrodes spaced apart from each other, and a connection pattern on the connection electrodes and the pixel defining layer, the connection pattern being connected to the connection electrodes.

[0011] In some exemplary embodiments, the connection pattern may be connected to one of a plurality of second electrodes at a location adjacent to or overlapping with the separator.

[0012] In some exemplary embodiments, the display device may further include a driving voltage connection pattern in the same layer as the first electrode, the driving voltage connection pattern electrically connecting the first driving voltage line and the fourth driving voltage line.

[0013] In some exemplary embodiments, the connection pattern can be connected to the connection electrode through the pattern contact hole, the drive voltage connection pattern can be connected to the fourth drive voltage line through the drive contact hole, and the pattern contact hole and the drive contact hole can be spaced apart from each other in a plan view.

[0014] In some exemplary embodiments, the pixel driving circuit may further include a lower active pattern on a substrate, a first gate electrode on the lower active pattern, and a contact electrode on the first gate electrode.

[0015] In some exemplary embodiments, the third driving voltage line and the contact electrode may be in the same layer, and the fourth driving voltage line and the connection electrode may be in the same layer.

[0016] In some exemplary embodiments, the first driving voltage line, the second driving voltage line, and the first electrode can be integrally formed.

[0017] A display device according to some exemplary embodiments of the present disclosure includes: a substrate; a pixel driving circuit on the substrate, the pixel driving circuit including transistors; a connection electrode on the substrate, the connection electrode electrically connected to the pixel driving circuit; a first electrode on the substrate, the first electrode spaced apart from the connection electrode; a pixel defining layer on the substrate, the pixel defining layer defining an opening exposing a portion of the first electrode; an electrode layer on the first electrode, the electrode layer electrically connected to the connection electrode; a first initialization voltage line between the substrate and the first electrode, the first initialization voltage line configured to receive an initialization voltage, and the first initialization voltage line extending in a first direction; a second... A second initialization voltage line is located between a first initialization voltage line and a first electrode, the second initialization voltage line being configured to receive an initialization voltage and extending in a second direction intersecting the first direction; a first driving voltage line is located in the same layer as the first electrode, the first driving voltage line being configured to receive a first electrical voltage and extending in a first oblique direction between the first and second directions; and a second driving voltage line is located in the same layer as the first electrode, the second driving voltage line being configured to receive the first electrical voltage and extending in a second oblique direction intersecting the first oblique direction.

[0018] In some exemplary embodiments, the first driving voltage line and the second driving voltage line may have a mesh shape in a plan view, and the first initialization voltage line and the second initialization voltage line may have a mesh shape in a plan view.

[0019] In some exemplary embodiments, the display device may further include: a third driving voltage line between a substrate and a first electrode, the third driving voltage line being configured to receive a first electrical voltage and extending in a first direction; and a fourth driving voltage line between the third driving voltage line and the first electrode, the fourth driving voltage line being configured to receive the first electrical voltage and extending in a second direction.

[0020] In some exemplary embodiments, the display device may further include an initialization voltage connection pattern that electrically connects the first initialization voltage line and the second initialization voltage line, a fourth driving voltage line that can be connected to the third driving voltage line through a first driving contact hole, a second initialization voltage line that can be connected to the initialization voltage connection pattern through an initialization contact hole, and the first driving contact hole and the initialization contact hole may be spaced apart from each other in a plan view.

[0021] In some exemplary embodiments, the first drive contact hole and the initialization contact hole may be arranged alternately along one direction in a plan view.

[0022] In some exemplary embodiments, the display device may further include a driving voltage connection pattern in the same layer as the first electrode, the driving voltage connection pattern electrically connecting the first driving voltage line and the fourth driving voltage line, the driving voltage connection pattern being connected to the fourth driving voltage line through a second driving contact hole, and the first driving contact hole and the second driving contact hole being spaced apart from each other in a plan view.

[0023] In some exemplary embodiments, the third driving voltage line may be on the first initialization voltage line, and the fourth driving voltage line and the second initialization voltage line may be in the same layer.

[0024] In some exemplary embodiments, the first driving voltage line, the second driving voltage line, and the first electrode can be integrally formed.

[0025] An electronic device according to some exemplary embodiments of the present disclosure includes: a display device including pixels; and processing circuitry configured to transmit image data signals and input control signals to the display device, wherein the display device includes: a substrate; a pixel driving circuit on the substrate, the pixel driving circuit including transistors; a connection electrode on the substrate, the connection electrode being electrically connected to the pixel driving circuit; a first electrode on the substrate, the first electrode being spaced apart from the connection electrode; a pixel defining layer on the substrate, the pixel defining layer defining an opening exposing a portion of the first electrode; an electrode layer on the first electrode, the electrode layer being electrically connected to the connection electrode; a first driving voltage line in the same layer as the first electrode, the first driving voltage line being configured to receive a first electrical voltage and extending in a first direction; and a second driving voltage line in the same layer as the first electrode, the second driving voltage line being configured to receive the first electrical voltage and extending in a second direction intersecting the first direction.

[0026] A display device according to some exemplary embodiments of this disclosure may include a light-emitting element comprising a first electrode and an electrode layer disposed on the first electrode, a connecting electrode spaced apart from the first electrode, a connecting pattern disposed on the connecting electrode, and a separator dividing the electrode layer into a plurality of second electrodes spaced apart from each other. The electrode layer (e.g., a cathode) disposed on the first electrode (e.g., an anode) may be connected to the drain of a driving transistor in a pixel driving circuit via the connecting electrode and the connecting pattern. Therefore, even when the light-emitting element deteriorates, the gate-source voltage of the driving transistor may remain unchanged. Therefore, the range of driving current variation due to light-emitting element deterioration can be reduced. Therefore, afterimage defects in the display device due to increased usage time can be reduced, and the lifespan of the display device can be improved (e.g., increased).

[0027] Furthermore, according to some exemplary embodiments, the display device may further include a first driving voltage line and a second driving voltage line, which are disposed in the same layer as the first electrode and receive the first electrical voltage. The first driving voltage line may extend in a first direction, and the second driving voltage line may extend in a second direction intersecting the first direction. That is, the first and second driving voltage lines may have a mesh shape in a plan view. Therefore, the resistance generated in the lines transmitting the first electrical voltage can be effectively reduced, and the voltage drop of the first electrical voltage can be effectively prevented (or reduced). Attached Figure Description

[0028] The illustrative, non-limiting examples will become clearer through the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 This is a block diagram illustrating a display device according to some exemplary embodiments of the present disclosure.

[0030] Figure 2A It is shown Figure 1 A floor plan of an example display device.

[0031] Figure 2B It is shown Figure 1 A floor plan of another example of a display device.

[0032] Figure 3A It is shown that it includes Figure 1 A circuit diagram illustrating an example of the circuit structure of pixels in a display device.

[0033] Figure 3B It is shown Figure 1 The display device for Figure 3A A timing diagram of an example of performing an address scan operation on a pixel.

[0034] Figure 3C It is shown Figure 1 The display device for Figure 3A A timing diagram of an example of a pixel performing a self-scanning operation.

[0035] Figure 3D It is shown that it includes Figure 1 A circuit diagram of another example of the circuit structure of a pixel in a display device.

[0036] Figure 3E It is shown Figure 1 The display device for Figure 3D A timing diagram of an example of performing an address scan operation on a pixel.

[0037] Figure 4A It is shown that it includes Figure 1A circuit diagram illustrating yet another example of the circuit structure of pixels in a display device.

[0038] Figure 4B It is shown Figure 1 The display device for Figure 4A A timing diagram of an example of performing an address scan operation on a pixel.

[0039] Figure 5A It is shown that it includes Figure 1 A circuit diagram illustrating yet another example of the circuit structure of pixels in a display device.

[0040] Figure 5B It is shown Figure 1 The display device for Figure 5A A timing diagram of an example of performing an address scan operation on a pixel.

[0041] Figure 6 It is shown schematically. Figure 2A and Figure 2B A floor plan of a portion of the area of ​​the display device.

[0042] Figure 7 It is along Figure 6 A sectional view taken from line I-I'.

[0043] Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 and Figure 20 It is shown that it includes Figure 1 An example layout diagram of pixels in a display device.

[0044] Figure 21 It shows that it is set with Figure 7 The layout diagram of the pixel layer of the first electrode.

[0045] Figure 22 It is one of them Figure 21 The pixel layer is also set Figure 19 The layout diagram on the fifth conductive layer.

[0046] Figure 23 This is a block diagram illustrating an electronic device according to some exemplary embodiments of the present disclosure.

[0047] Figure 24 This is a schematic diagram of an electronic device according to some exemplary embodiments. Detailed Implementation

[0048] Some exemplary embodiments will be described more fully below with reference to the accompanying drawings, in which some exemplary embodiments are illustrated. However, the inventive concept can be implemented in many different forms and should not be construed as limited to the examples set forth herein. Rather, these examples are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity.

[0049] Various modifications and forms may be made in this disclosure, and specific examples will be shown in the accompanying drawings and described in detail herein. However, this is not intended to limit this disclosure to the particular forms disclosed, and it will be understood that all changes, equivalents, or substitutions falling within the spirit and technical scope of this disclosure should be included.

[0050] It will be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of the inventive concept, the first element discussed below may be referred to as the second element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0051] It will be understood that when an element is referred to as “connected” or “linked” to another element, the element may be directly connected or directly linked to said other element, or there may be an intermediary element. Conversely, when an element is referred to as “directly connected” or “directly linked” to another element, there is no intermediary element. Other terms used to describe the relationship between elements should be interpreted in a similar manner (e.g., “between” vs. “directly between”, “adjacent to” vs. “directly adjacent to”, etc.).

[0052] The terminology used herein is for the purpose of describing particular examples only and is not intended to limit the inventive concept. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that, when used in this specification, the terms “comprising” and / or “including” specify the presence of the stated features, integrals, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, operations, elements, components, and / or groups thereof.

[0053] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the relative terms are intended to also include different orientations of the device. For example, if a device in one of the drawings is flipped, an element described as being “down” to the other element will be oriented to be “up” to the other element. Thus, the term “down” can include both “down” and “up” orientations, depending on the specific orientation of the drawing. Similarly, if a device in one of the drawings is flipped, an element described as being “below” or “under” the other element will be oriented to be “above” the other element. Thus, the term “below” or “under” can include both “up” and “down” orientations.

[0054] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same or similar meaning as commonly understood by one of ordinary skill in the art to which the inventive concept pertains. It will also be understood that terms (such as those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0055] In the following description, some exemplary embodiments will be described in detail with reference to the accompanying drawings. The same components (or similar components) in the drawings use the same reference numerals (or similar reference numerals), and redundant descriptions of the same components (or similar components) will be omitted.

[0056] Figure 1 This is a block diagram illustrating a display device according to some exemplary embodiments of the present disclosure.

[0057] refer to Figure 1A display device DD according to some exemplary embodiments of the present disclosure may include a display panel DP and a panel driver driving the display panel DP. The panel driver may include a drive controller CON, a gate driver GDV, a gamma reference voltage generator GMG, a data driver DDV, and / or a transmit driver EDV. According to some exemplary embodiments, operations described herein as being performed by the display device DD, the display panel DP, the panel driver, the drive controller CON, the gate driver GDV, the gamma reference voltage generator GMG, the data driver DDV, and / or the transmit driver EDV may be performed by processing circuitry. As used herein, the term "processing circuitry" may refer to, for example, hardware including logic circuitry; a hardware / software combination (such as a processor executing software); or a combination thereof. For example, processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0058] For example, the drive controller CON and the data driver DDV can be integrated into one unit. This integrated drive module, comprising the drive controller CON and the data driver DDV, can be referred to as a timing controller embedded data driver (TED).

[0059] The display panel DP may include gate lines GL, emission control lines ECL, data lines DL, and pixels PX. Pixels PX may be electrically connected to the gate lines GL, ECL, and DL. Each pixel PX may generate light in response to a drive signal. For example, each gate line GL may extend in a first direction DR1, and each emission control line ECL may extend in the first direction DR1. Each data line DL may extend in a second direction DR2 intersecting the first direction DR1. For example, the first direction DR1 and the second direction DR2 may be perpendicular to each other.

[0060] The drive controller CON can be controlled from an external device (e.g., Figure 23 The processor 12) receives an image data signal IMG and an input control signal CONT. For example, the image data signal IMG may include red image data, green image data, and blue image data. In some exemplary embodiments, the image data signal IMG may also include white image data. The input control signal CONT may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a master clock signal, etc.

[0061] The drive controller CON can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the image data signal IMG and the input control signal CONT.

[0062] The drive controller CON can output a first control signal CONT1 to the gate driver GDV. The first control signal CONT1 may include a vertical start signal and a gate clock signal. The drive controller CON can output a second control signal CONT2 and a data signal DATA to the data driver DDV. The second control signal CONT2 may include a horizontal start signal and a load signal. The drive controller CON can output a third control signal CONT3 to the gamma reference voltage generator GMG. The drive controller CON can output a fourth control signal CONT4 to the transmit driver EDV.

[0063] The gate driver GDV can generate a gate signal in response to a first control signal CONT1. The gate driver GDV can output the gate signal to the gate line GL. In some exemplary embodiments, the gate signal may include... Figure 3A , Figure 3D , Figure 4A and Figure 5A The first gate signal GW, the second gate signal GR, and the third gate signal GC are shown in the diagram. However, this disclosure is not necessarily limited thereto.

[0064] The Gamma Reference Voltage Generator (GMG) generates a gamma reference voltage VGREF in response to a third control signal CONT3. The GMG then provides the VGREF to the data driver DDV. For example, the GMG can be located in the drive controller CON or in the data driver DDV.

[0065] The data driver DDV can receive the second control signal CONT2 and the data signal DATA from the drive controller CON, and can receive the gamma reference voltage VGREF from the gamma reference voltage generator GMG. The data driver DDV can use the gamma reference voltage VGREF to convert the data signal DATA into an analog data voltage VDATA. The data driver DDV can then output the data voltage VDATA to the data line DL.

[0066] The transmit driver EDV can generate a transmit signal in response to the fourth control signal CONT4. The transmit driver EDV can output the transmit signal to the transmit control line ECL. In some exemplary embodiments, the transmit signal may include... Figure 3A , Figure 3D , Figure 4Aand Figure 5A The first transmit control signal EM1 and the second transmit control signal EM2 are shown in the diagram. However, this disclosure is not necessarily limited thereto.

[0067] exist Figure 1 In this illustration, for ease of description, the gate driver GDV is shown disposed on a first side of the display panel DP, and the emitter driver EDV is shown disposed on a second side of the display panel DP opposite to the first side; however, this disclosure is not necessarily limited to this. For example, both the gate driver GDV and the emitter driver EDV may be disposed on the first side of the display panel DP. In another example, both the gate driver GDV and the emitter driver EDV may be disposed on opposite sides of the display panel DP. In yet another example, the gate driver GDV and the emitter driver EDV may be integrally formed.

[0068] Figure 2A It is shown Figure 1 A floor plan of an example display device. Figure 2B It is shown Figure 1 A floor plan of another example of a display device.

[0069] In this specification, a plane may be defined by a first direction DR1 and a second direction DR2, and a direction perpendicular to the plane may be a third direction DR3. In other words, the third direction DR3 may be perpendicular to each of the first direction DR1 and the second direction DR2. As used herein, a "plan view" is a view on the third direction DR3.

[0070] refer to Figure 2A and Figure 2B Each of the display devices DDa and DDb can be a device activated in response to an electrical signal. For example, display device DDa can be a small display device used in small electronic devices such as smartphones, cellular phones, smartwatches, game consoles, and cameras. Furthermore, display device DDb can be a medium to large display device used in medium to large electronic devices such as laptops, tablet computers, televisions, computer monitors, in-vehicle monitors, and external billboards. Figure 2A In the diagram, the display device DDA is shown as an example of a small display device, and in... Figure 2B In the diagram, the display device DDb is shown as an example of a medium to large-sized display device.

[0071] Each of the display devices DDa and DDb may include a display area DA and a peripheral area NDA. The display area DA may be an area that displays an image by generating light or adjusting the transmittance of light provided from an external light source. The peripheral area NDA may be adjacent to the display area DA. In a plan view, the peripheral area NDA may surround at least a portion of the display area DA. For example, in a plan view, the peripheral area NDA may completely surround the display area DA. In some exemplary embodiments, the peripheral area NDA may be an area where no image is displayed. However, this disclosure is not necessarily limited to this, and an image may be displayed in at least a portion of the peripheral area NDA.

[0072] Each of the display devices DDa and DDb may include a display panel DP, a scan driver SDV, and a driver chip D-IC, and the display panel DP may include a substrate (substrate SUB, see below). Figure 7 ( ), pixels PX, scan lines SL and / or data lines DL. According to some exemplary embodiments, the operations described herein as being performed by each of the display devices DDa and DDb, the display panel DP, the scan driver SDV and the driver chip D-IC can be performed by processing circuitry.

[0073] A substrate can form the base of each of the display devices DDa and DDb. Examples of materials that can be used as substrates include glass, quartz, silicon, polymers, etc. These can be used individually or in combination with each other.

[0074] Pixels PX can be disposed on the substrate within the display area DA. Pixels PX can be electrically connected to scan lines SL and data lines DL. Scan lines SL can correspond to... Figure 1 The gate line GL or the emitter control line ECL.

[0075] Each pixel PX may include multiple sub-pixels. For example, each pixel PX may include a first sub-pixel, a second sub-pixel, and a third sub-pixel. Each of the first to third sub-pixels may include a light-emitting element and a pixel driving circuit connected to the light-emitting element. The light-emitting element may emit light. In some exemplary embodiments, the first to third sub-pixels may emit light of different wavelength bands. That is, the first to third sub-pixels may emit light of different colors. For example, the first sub-pixel may emit red light, the second sub-pixel may emit green light, and the third sub-pixel may emit blue light. However, this disclosure is not necessarily limited to this.

[0076] The driver chip D-IC can be disposed on the substrate within the peripheral region NDA. The driver chip D-IC can correspond to Figure 1 The data driver DDV. That is, the driver chip D-IC can output a data voltage (data voltage VDATA, see [link]) to the data line DL. Figure 1 The data voltage can be applied to the pixel PX via the data line DL.

[0077] In some exemplary embodiments, the driver chip D-IC may be mounted on the substrate. However, this disclosure is not necessarily limited to this, and the driver chip D-IC may be disposed on a flexible film bonded to the substrate in the form of a chip on film (COF).

[0078] In some exemplary embodiments, Figure 2B The display device DDb may include multiple driver chips D-ICs. For example, the driver chips D-ICs may be disposed on opposite sides of the display area DA in the second direction DR2. For example, the driver chips D-ICs may be disposed along the long side of the display device DDb. However, this disclosure is not necessarily limited to this.

[0079] The scan driver SDV can be positioned on the substrate within the peripheral region NDA. The scan driver SDV can correspond to... Figure 1 The gate driver (GDV) or emitter driver (EDV) can be used. For example, the scan driver (SDV) can output a gate signal to the scan line (SL). The gate signal can be applied to the pixel (PX) through the scan line (SL). Similarly, the scan driver (SDV) can output an emitter signal to the scan line (SL). The emitter signal can be applied to the pixel (PX) through the scan line (SL).

[0080] In some exemplary embodiments, the scan driver SDV may be located on the opposite side of the display area DA in the first direction DR1. However, this disclosure is not necessarily limited to this.

[0081] Figure 2A and Figure 2B The number or arrangement of driver chips D-IC and scan drivers SDV shown are merely examples, and this disclosure is not necessarily limited thereto.

[0082] Furthermore, despite Figure 2A The display device DDA is shown to have a generally rectangular planar shape, having a short side extending in a first direction DR1 and a long side extending in a second direction DR2, but this disclosure is not necessarily limited thereto. Furthermore, although Figure 2B The display device DDb is shown to have a generally rectangular planar shape, which has a long side extending in a first direction DR1 and a short side extending in a second direction DR2, but this disclosure is not necessarily limited thereto. That is, according to some exemplary embodiments, the planar shape of each of the display devices DDa and DDb can be varied.

[0083] The description with reference to the following figures can be applied in the same (or similar) way to... Figure 2A The display device DDA and Figure 2B The display device DDb. In the following text, for ease of description, the terms (e.g., Figure 2A The display device DDA and Figure 2B The display device DDb will be unified as display device DD.

[0084] Figure 3A It is shown that it includes Figure 1 A circuit diagram illustrating an example of the circuit structure of pixels in a display device. For example, Figure 3A It can be a circuit diagram that includes any one of the first to third sub-pixels in pixel PX.

[0085] refer to Figure 3A Pixel PX may include a light-emitting element (LD) and a pixel driving circuit PC connected to the LD. In some exemplary embodiments, the pixel driving circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, a first capacitor C1, and a second capacitor C2. Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be a metal-oxide-semiconductor field-effect transistor (MOSFET) formed by a semiconductor process.

[0086] exist Figure 3A In this design, the fourth transistor T4 and the fifth transistor T5 are shown as p-type transistors, and the first transistor T1, the second transistor T2, the third transistor T3, and the sixth transistor T6 are shown as n-type transistors. However, this disclosure is not necessarily limited thereto, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be n-type transistors.

[0087] When a pixel PX includes an n-type transistor and a p-type transistor, the active pattern of the n-type transistor may include an oxide semiconductor material, and the active pattern of the p-type transistor may include a silicon semiconductor material. However, this disclosure is not necessarily limited thereto, and both the active patterns of the n-type transistor and the active patterns of the p-type transistor may include silicon semiconductor materials.

[0088] In the case of a p-type transistor, the transistor can be turned off when the gate signal has a high level voltage (hereinafter referred to as high gate voltage), and can be turned on when the gate signal has a low level voltage (hereinafter referred to as low gate voltage). That is, a high gate voltage can have a relatively high voltage level, and a low gate voltage can have a relatively low voltage level. Conversely, in the case of an n-type transistor, the transistor can be turned off when the gate signal has a low gate voltage, and can be turned on when the gate signal has a high gate voltage.

[0089] The pixel driver circuit PC can be connected to the first gate line GWL, the second gate line GRL, the third gate line GCL, the data line DL, the first voltage line VL1, the second voltage line VL2, the third voltage line VL3, the fourth voltage line VL4, the first transmit control line ECL1, and the second transmit control line ECL2. The first gate line GWL can transmit the first gate signal GW. The second gate line GRL can transmit the second gate signal GR. The third gate line GCL can transmit the third gate signal GC. The data line DL can transmit the data voltage VDATA. The first voltage line VL1 can transmit a first power voltage ELVDD with a relatively high voltage level. The second voltage line VL2 can transmit a second power voltage ELVSS with a relatively low voltage level. The third voltage line VL3 can transmit a reference voltage VREF. The reference voltage VREF can have a voltage level lower than the first power voltage ELVDD. The fourth voltage line VL4 can transmit the initialization voltage VCINT.

[0090] The first transistor T1 may include a gate terminal (or gate electrode), a first terminal, and a second terminal. In some exemplary embodiments, the first terminal of the first transistor T1 may be the source, and the second terminal of the first transistor T1 may be the drain. The gate terminal of the first transistor T1 may be connected to a first node N1. The first terminal of the first transistor T1 may be connected to a second node N2. The second terminal of the first transistor T1 may be connected to a third node N3. The second terminal of the first transistor T1 may be connected to a light-emitting element LD via a fifth transistor T5. The first transistor T1 may control the drive current ID supplied to the light-emitting element LD.

[0091] In some exemplary embodiments, the first transistor T1 may further include a lower gate terminal. The lower gate terminal of the first transistor T1 may be connected to the second node N2. That is, the lower gate terminal of the first transistor T1 may be connected to the first terminal of the first transistor T1.

[0092] The second transistor T2 may include a gate terminal, a first terminal, and a second terminal. In some exemplary embodiments, the first terminal of the second transistor T2 may be the source, and the second terminal of the second transistor T2 may be the drain. However, this disclosure is not necessarily limited to this, and the first terminal of the second transistor T2 may be the drain, and the second terminal of the second transistor T2 may be the source. The gate terminal of the second transistor T2 may receive a first gate signal GW via a first gate line GWL. The first terminal of the second transistor T2 may receive a data voltage VDATA via a data line DL. The second terminal of the second transistor T2 may be connected to a first node N1.

[0093] The second transistor T2 can be turned on or off in response to the first gate signal GW. For example, when the second transistor T2 is an n-type transistor, it can be turned off when the first gate signal GW has a low gate voltage and turned on when the first gate signal GW has a high gate voltage. When the second transistor T2 is on, it can provide the data voltage VDATA to the first node N1. Therefore, the second transistor T2 can drive the first transistor T1.

[0094] The third transistor T3 may include a gate terminal, a first terminal, and a second terminal. In some exemplary embodiments, the first terminal of the third transistor T3 may be the source, and the second terminal of the third transistor T3 may be the drain. However, this disclosure is not necessarily limited to this, and the first terminal of the third transistor T3 may be the drain, and the second terminal of the third transistor T3 may be the source. The gate terminal of the third transistor T3 may receive a second gate signal GR via a second gate line GRL. The first terminal of the third transistor T3 may be connected to a first node N1. The second terminal of the third transistor T3 may receive a reference voltage VREF via a third voltage line VL3.

[0095] The third transistor T3 can be turned on or off in response to the second gate signal GR. For example, when the third transistor T3 is an n-type transistor, it can be turned off when the second gate signal GR has a low gate voltage, and it can be turned on when the second gate signal GR has a high gate voltage. When the third transistor T3 is turned on, it can provide a reference voltage VREF to the first node N1.

[0096] The fourth transistor T4 may include a gate terminal, a first terminal, and a second terminal. In some exemplary embodiments, the first terminal of the fourth transistor T4 may be the source, and the second terminal of the fourth transistor T4 may be the drain. However, this disclosure is not necessarily limited to this, and the first terminal of the fourth transistor T4 may be the drain, and the second terminal of the fourth transistor T4 may be the source. The gate terminal of the fourth transistor T4 may receive a third gate signal GC via a third gate line GCL. The first terminal of the fourth transistor T4 may receive an initialization voltage VCINT via a fourth voltage line VL4. The second terminal of the fourth transistor T4 may be connected to a fourth node N4.

[0097] The fourth transistor T4 can be turned on or off in response to the third gate signal GC. For example, when the fourth transistor T4 is a p-type transistor, it can be turned off when the third gate signal GC has a high gate voltage and turned on when the third gate signal GC has a low gate voltage. Furthermore, when the fourth transistor T4 is an n-type transistor, it can be turned off when the third gate signal GC has a low gate voltage and turned on when the third gate signal GC has a high gate voltage. When the fourth transistor T4 is turned on, it can provide an initialization voltage VCINT to the fourth node N4. That is, the fourth transistor T4 can provide an initialization voltage VCINT to the cathode of the light-emitting element LD in response to the third gate signal GC to initialize the cathode voltage.

[0098] The fifth transistor T5 may include a gate terminal, a first terminal, and a second terminal. In some exemplary embodiments, the first terminal of the fifth transistor T5 may be the source, and the second terminal of the fifth transistor T5 may be the drain. However, this disclosure is not necessarily limited to this, and the first terminal of the fifth transistor T5 may be the drain, and the second terminal of the fifth transistor T5 may be the source. The gate terminal of the fifth transistor T5 can receive a first transmit control signal EM1 through a first transmit control line ECL1. The first terminal of the fifth transistor T5 may be connected to a fourth node N4. That is, the first terminal of the fifth transistor T5 may be connected to a light-emitting element LD. The second terminal of the fifth transistor T5 may be connected to a third node N3. That is, the second terminal of the fifth transistor T5 may be connected to the second terminal of the first transistor T1.

[0099] The fifth transistor T5 can be turned on or off in response to the first transmit control signal EM1. For example, when the fifth transistor T5 is a p-type transistor, it can be turned off when the first transmit control signal EM1 has a high gate voltage, and it can be turned on when the first transmit control signal EM1 has a low gate voltage. Furthermore, when the fifth transistor T5 is an n-type transistor, it can be turned off when the first transmit control signal EM1 has a low gate voltage, and it can be turned on when the first transmit control signal EM1 has a high gate voltage. When the fifth transistor T5 is turned on, it can electrically connect the first transistor T1 and the light-emitting element LD. That is, the fifth transistor T5 can electrically connect the second terminal of the first transistor T1 and the cathode of the light-emitting element LD in response to the first transmit control signal EM1.

[0100] The sixth transistor T6 may include a gate terminal, a first terminal, and a second terminal. In some exemplary embodiments, the first terminal of the sixth transistor T6 may be the source, and the second terminal of the sixth transistor T6 may be the drain. However, this disclosure is not necessarily limited to this, and the first terminal of the sixth transistor T6 may be the drain, and the second terminal of the sixth transistor T6 may be the source. The gate terminal of the sixth transistor T6 may receive a second transmit control signal EM2 via a second transmit control line ECL2. The first terminal of the sixth transistor T6 may receive a second power supply voltage ELVSS via a second voltage line VL2. The second terminal of the sixth transistor T6 may be connected to a second node N2.

[0101] The sixth transistor T6 can be turned on or off in response to the second emitter control signal EM2. For example, when the sixth transistor T6 is an n-type transistor, the sixth transistor T6 can be turned off when the second emitter control signal EM2 has a low gate voltage, and the sixth transistor T6 can be turned on when the second emitter control signal EM2 has a high gate voltage. When the sixth transistor T6 is turned on, the sixth transistor T6 can provide the second power voltage ELVSS to the second node N2.

[0102] Although the fifth transistor T5 and the sixth transistor T6 are in Figure 3A The transistors are shown to be driven independently by different transmit control signals, but this disclosure is not necessarily limited to this. For example, the fifth transistor T5 and the sixth transistor T6 can be turned on or off simultaneously (or synchronously) in response to a substantially single transmit control signal. In this case, both the fifth transistor T5 and the sixth transistor T6 can be n-type transistors.

[0103] The first capacitor C1 may include a first terminal and a second terminal. The first terminal of the first capacitor C1 may be connected to a first node N1. The second terminal of the first capacitor C1 may be connected to a second node N2. The first capacitor C1 can be charged and discharged according to the data voltage VDATA transmitted to the first node N1.

[0104] The second capacitor C2 may include a first terminal and a second terminal. The first terminal of the second capacitor C2 may be connected to the second node N2. The second terminal of the second capacitor C2 may be connected to the second voltage line VL2. For example, the second capacitor C2 may be connected in series with the first capacitor C1. The data voltage VDATA may be transmitted to the first node N1, and due to the series connection of the first capacitor C1 and the second capacitor C2, the data voltage VDATA may be divided and transmitted to the second node N2. Since the first transistor T1 controls the drive current ID based on the voltage of the first node N1 and the voltage of the second node N2, the data voltage range can be extended.

[0105] The light-emitting element (LD) may include an anode and a cathode. The anode of the LD may be connected to the first voltage line VL1. The cathode of the LD may be connected to the fourth node N4. That is, the cathode of the LD may be connected to the second terminal of the first transistor T1 via the fifth transistor T5.

[0106] Despite Figure 3A Not shown, but the pixel driving circuit PC may also include a transmitting capacitor, which includes a first terminal and a second terminal. The first terminal of the transmitting capacitor can receive a first electrical voltage ELVDD. The second terminal of the transmitting capacitor can be connected to a fourth node N4.

[0107] Figure 3B It is shown Figure 1 The display device for Figure 3A A timing diagram of an example of performing an address scan operation on a pixel. Figure 3C It is shown Figure 1 The display device for Figure 3A A timing diagram of an example of a pixel performing a self-scanning operation.

[0108] refer to Figure 1 , Figure 3A , Figure 3B and Figure 3C The drive controller CON can perform address scan operation (ADS) and self-scan operation (SES).

[0109] The drive controller CON can change the drive frequency (or drive frame length) of the display panel DP by adjusting the length of the self-scan operation SES. For example, at the maximum (or highest) drive frequency of the display panel DP (e.g., 240Hz), one frame of the address scan operation ADS can be repeated continuously. In this case, the drive controller CON can execute one frame of the address scan operation ADS as a drive frame. For example, when the drive frequency of the display panel DP is 120Hz, one frame of the address scan operation ADS and one frame of the self-scan operation SES can be repeated. In this case, the drive controller CON can execute one frame of the address scan operation ADS and one frame of the self-scan operation SES as a drive frame. For example, when the drive frequency of the display panel DP is 60Hz, one frame of the address scan operation ADS and three frames of the self-scan operation SES can be repeated. In this case, the drive controller CON can execute one frame of the address scan operation ADS and three frames of the self-scan operation SES as a drive frame. However, this disclosure is not necessarily limited to this.

[0110] like Figure 3B As shown, the address scan operation ADS may include a first part AS1, a second part AS2, a third part AS3, a fourth part AS4, and a fifth part AS5.

[0111] In the first part AS1 of the address scan operation ADS, the first transmit control signal EM1, the second transmit control signal EM2, and the second gate signal GR can have high gate voltages, and the first gate signal GW and the third gate signal GC can have low gate voltages. In this case, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 can be turned on, while the second transistor T2 and the fifth transistor T5 can be turned off. Therefore, a reference voltage VREF can be applied to the gate terminal of the first transistor T1, thereby initializing the voltage at the gate terminal of the first transistor T1. Furthermore, a second power voltage ELVSS can be applied to the first terminal of the first transistor T1. Additionally, an initialization voltage VCINT can be applied to the cathode of the light-emitting element LD, thereby initializing the voltage at the cathode. For example, the first part AS1 of the address scan operation ADS can be referred to as the gate initialization and cathode initialization operation.

[0112] In the second part AS2 of the address scan operation ADS, the first transmit control signal EM1, the second transmit control signal EM2, the first gate signal GW, and the third gate signal GC can have low gate voltages, and the second gate signal GR can have a high gate voltage. In this case, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be turned on, while the second transistor T2 and the sixth transistor T6 can be turned off. Therefore, a reference voltage VREF can be applied to the gate terminal of the first transistor T1, and an initialization voltage VCINT can be applied to the second terminal of the first transistor T1, thereby compensating for the threshold voltage of the first transistor T1. Furthermore, the initialization voltage VCINT can be applied to the cathode of the light-emitting element LD, thereby initializing the cathode voltage. For example, the second part AS2 of the address scan operation ADS can be referred to as the threshold voltage compensation and cathode initialization operation.

[0113] In the third part AS3 of the address scan operation ADS, the first transmit control signal EM1, the first gate signal GW, and the third gate signal GC can have high gate voltages, while the second transmit control signal EM2 and the second gate signal GR can have low gate voltages. In this case, the second transistor T2 can be turned on, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be turned off. Therefore, the data voltage VDATA can be applied to the gate terminal of the first transistor T1. For example, the third part AS3 of the address scan operation ADS can be referred to as a data write operation.

[0114] In the fourth part AS4 of the address scan operation ADS, the first transmit control signal EM1, the second transmit control signal EM2, and the third gate signal GC can have high gate voltages, while the first gate signal GW and the second gate signal GR can have low gate voltages. In this case, the sixth transistor T6 can be turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be turned off. Therefore, the second power voltage ELVSS can be applied to the first terminal of the first transistor T1. For example, the fourth part AS4 of the address scan operation ADS can be referred to as the source initialization operation.

[0115] In the fifth part AS5 of the address scan operation ADS, the first emit control signal EM1, the first gate signal GW, and the second gate signal GR can have low gate voltages, while the second emit control signal EM2 and the third gate signal GC can have high gate voltages. In this case, the fifth transistor T5 and the sixth transistor T6 can be turned on, while the second transistor T2, the third transistor T3, and the fourth transistor T4 can be turned off. Therefore, the first transistor T1 can generate a drive current ID based on its gate terminal, and the light-emitting element LD can emit light due to the drive current ID. For example, the fifth part AS5 of the address scan operation ADS can be referred to as the emit operation.

[0116] like Figure 3C As shown, the self-scanning operation SES may include a first part SS1, a second part SS2, a third part SS3, and a fourth part SS4.

[0117] In the first part SS1 of the self-scan operation SES, the first transmit control signal EM1 and the second transmit control signal EM2 can have high gate voltages, and the first gate signal GW, the second gate signal GR, and the third gate signal GC can have low gate voltages. In this case, the fourth transistor T4 and the sixth transistor T6 can be turned on, and the second transistor T2, the third transistor T3, and the fifth transistor T5 can be turned off. Therefore, the second power voltage ELVSS can be applied to the first terminal of the first transistor T1. In addition, the initialization voltage VCINT can be applied to the cathode of the light-emitting element LD, thereby initializing the cathode voltage. Unlike the first part AS1 of the address scan operation ADS, the first part SS1 of the self-scan operation SES may not include the operation of initializing the voltage of the gate terminal of the first transistor T1. For example, the first part SS1 of the self-scan operation SES can be referred to as the cathode initialization operation.

[0118] In the second part (SS2) of the self-scanning operation (SES), the first transmit control signal EM1, the second transmit control signal EM2, the first gate signal GW, the second gate signal GR, and the third gate signal GC can all have low gate voltages. In this case, the fourth transistor T4 and the fifth transistor T5 can be turned on, while the second transistor T2, the third transistor T3, and the sixth transistor T6 can be turned off. Therefore, an initialization voltage VCINT can be applied to the second terminal of the first transistor T1, thereby compensating for the threshold voltage of the first transistor T1. Furthermore, the initialization voltage VCINT can be applied to the cathode of the light-emitting element (LD), thereby initializing the cathode voltage. For example, the second part (SS2) of the self-scanning operation (SES) can be referred to as the threshold voltage compensation and cathode initialization operation.

[0119] Unlike the Address Scan operation (ADS), the Self Scan operation (SES) may not include a data write operation that applies the data voltage VDATA to the gate terminal of the first transistor T1.

[0120] In the third part (SS3) of the self-scanning operation (SES), the first transmit control signal EM1, the second transmit control signal EM2, and the third gate signal GC can have high gate voltages, while the first gate signal GW and the second gate signal GR can have low gate voltages. In this case, the sixth transistor T6 can be turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be turned off. Therefore, the second power voltage ELVSS can be applied to the first terminal of the first transistor T1. For example, the third part (SS3) of the self-scanning operation (SES) can be referred to as the source initialization operation.

[0121] In the fourth part (SS4) of the self-scanning operation (SES), the first emit control signal EM1, the first gate signal GW, and the second gate signal GR can have low gate voltages, while the second emit control signal EM2 and the third gate signal GC can have high gate voltages. In this case, the fifth transistor T5 and the sixth transistor T6 can be turned on, while the second transistor T2, the third transistor T3, and the fourth transistor T4 can be turned off. Therefore, the first transistor T1 can generate a drive current ID based on its gate terminal, and the light-emitting element LD can emit light due to the drive current ID. For example, the fourth part (SS4) of the self-scanning operation (SES) can be referred to as the emit operation.

[0122] In summary, the Address Scan Operation (ADS) can perform gate initialization, cathode initialization, threshold voltage compensation, data write, source initialization, and emit operations. The Self Scan Operation (SES) can perform cathode initialization, threshold voltage compensation, source initialization, and emit operations. That is, the Self Scan Operation (SES) can perform emit operations without gate initialization and data write operations. In the Self Scan Operation (SES), the first gate signal GW and the second gate signal GR can maintain low gate voltages.

[0123] Figure 3D It is shown that it includes Figure 1 A circuit diagram illustrating another example of the circuit structure of pixels in a display device. For example, Figure 3D It can be a circuit diagram that includes any one of the first to third sub-pixels in pixel PX.

[0124] Except for the fourth transistor T4 and the fifth transistor T5, which are n-type transistors. Figure 3D The pixel driving circuit PCn can be basically the same as the above reference. Figure 3AThe pixel driving circuit PC described is the same. Therefore, redundant descriptions of some components have been omitted or summarized.

[0125] refer to Figure 3D Pixel PX may include a light-emitting element (LD) and a pixel driving circuit PCn connected to the LD. In some exemplary embodiments, the pixel driving circuit PCn may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6, a first capacitor C1, and a second capacitor C2. In some exemplary embodiments, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may all be n-type transistors.

[0126] The fourth transistor T4 may include a gate terminal, a first terminal, and a second terminal. In some exemplary embodiments, the first terminal of the fourth transistor T4 may be the source, and the second terminal of the fourth transistor T4 may be the drain. However, this disclosure is not necessarily limited to this, and the first terminal of the fourth transistor T4 may be the drain, and the second terminal of the fourth transistor T4 may be the source. The gate terminal of the fourth transistor T4 may receive a third gate signal GC via a third gate line GCL. The first terminal of the fourth transistor T4 may be connected to a fourth node N4. The second terminal of the fourth transistor T4 may receive an initialization voltage VCINT via a fourth voltage line VL4.

[0127] The fourth transistor T4 can be turned on or off in response to the third gate signal GC. For example, when the fourth transistor T4 is an n-type transistor, it can be turned off when the third gate signal GC has a low gate voltage and turned on when the third gate signal GC has a high gate voltage. When the fourth transistor T4 is turned on, it can provide an initialization voltage VCINT to the fourth node N4. That is, the fourth transistor T4 can provide an initialization voltage VCINT to the cathode of the light-emitting element LD in response to the third gate signal GC to initialize the cathode voltage.

[0128] The fifth transistor T5 may include a gate terminal, a first terminal, and a second terminal. In some exemplary embodiments, the first terminal of the fifth transistor T5 may be the source, and the second terminal of the fifth transistor T5 may be the drain. However, this disclosure is not necessarily limited to this, and the first terminal of the fifth transistor T5 may be the drain, and the second terminal of the fifth transistor T5 may be the source. The gate terminal of the fifth transistor T5 can receive a first transmit control signal EM1 through a first transmit control line ECL1. The first terminal of the fifth transistor T5 may be connected to a third node N3. That is, the first terminal of the fifth transistor T5 may be connected to the second terminal of the first transistor T1. The second terminal of the fifth transistor T5 may be connected to a fourth node N4. That is, the second terminal of the fifth transistor T5 may be connected to a light-emitting element LD.

[0129] The fifth transistor T5 can be turned on or off in response to the first emission control signal EM1. For example, when the fifth transistor T5 is an n-type transistor, it can be turned off when the first emission control signal EM1 has a low gate voltage, and it can be turned on when the first emission control signal EM1 has a high gate voltage. When the fifth transistor T5 is turned on, it can electrically connect the first transistor T1 and the light-emitting element LD. That is, the fifth transistor T5 can electrically connect the second terminal of the first transistor T1 and the cathode of the light-emitting element LD in response to the first emission control signal EM1.

[0130] Figure 3E It is shown Figure 1 The display device for Figure 3D A timing diagram of an example of performing an address scan operation on a pixel.

[0131] In addition to the first transmit control signal EM1 and the third gate signal GC Figure 3E The address scanning operation ADSn can be basically the same as the above reference. Figure 3B The address scan operation described is the same as that of ADS.

[0132] refer to Figure 1 , Figure 3D and Figure 3E The drive controller CON can perform address scan operation (ADSn) and self-scan operation. The drive controller CON can change the drive frequency of the display panel (DP) by adjusting the length of the self-scan operation.

[0133] like Figure 3E As shown, the address scan operation ADSn may include a first part AS1n, a second part AS2n, a third part AS3n, a fourth part AS4n, and a fifth part AS5n.

[0134] In the first part AS1n of the address scan operation ADSn, the second emit control signal EM2, the second gate signal GR, and the third gate signal GC can have high gate voltages, while the first emit control signal EM1 and the first gate signal GW can have low gate voltages. In this case, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 can be turned on, while the second transistor T2 and the fifth transistor T5 can be turned off. Therefore, a reference voltage VREF can be applied to the gate terminal of the first transistor T1, thereby initializing the voltage at the gate terminal of the first transistor T1. Furthermore, a second power voltage ELVSS can be applied to the first terminal of the first transistor T1. Additionally, an initialization voltage VCINT can be applied to the cathode of the light-emitting element LD, thereby initializing the cathode voltage. For example, the first part AS1n of the address scan operation ADSn can be referred to as the gate initialization and cathode initialization operation.

[0135] In the second part AS2n of the address scan operation ADSn, the first emit control signal EM1, the second gate signal GR, and the third gate signal GC can have high gate voltages, while the second emit control signal EM2 and the first gate signal GW can have low gate voltages. In this case, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be turned on, while the second transistor T2 and the sixth transistor T6 can be turned off. Therefore, a reference voltage VREF can be applied to the gate terminal of the first transistor T1, and an initialization voltage VCINT can be applied to the second terminal of the first transistor T1, thereby compensating for the threshold voltage of the first transistor T1. Furthermore, the initialization voltage VCINT can be applied to the cathode of the light-emitting element LD, thereby initializing the cathode voltage. For example, the second part AS2n of the address scan operation ADSn can be referred to as the threshold voltage compensation and cathode initialization operation.

[0136] In the third part AS3n of the address scan operation ADSn, the first gate signal GW can have a high gate voltage, and the first transmit control signal EM1, the second transmit control signal EM2, the second gate signal GR, and the third gate signal GC can have low gate voltages. In this case, the second transistor T2 can be turned on, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 can be turned off. Therefore, the data voltage VDATA can be applied to the gate terminal of the first transistor T1. For example, the third part AS3n of the address scan operation ADSn can be referred to as a data write operation.

[0137] In the fourth part AS4n of the address scan operation ADSn, the second emit control signal EM2 can have a high gate voltage, and the first emit control signal EM1, the first gate signal GW, the second gate signal GR, and the third gate signal GC can have low gate voltages. In this case, the sixth transistor T6 can be turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 can be turned off. Therefore, the second power voltage ELVSS can be applied to the first terminal of the first transistor T1. For example, the fourth part AS4n of the address scan operation ADSn can be referred to as the source initialization operation.

[0138] In the fifth part AS5n of the address scan operation ADSn, the first emit control signal EM1 and the second emit control signal EM2 can have high gate voltages, and the first gate signal GW, the second gate signal GR, and the third gate signal GC can have low gate voltages. In this case, the fifth transistor T5 and the sixth transistor T6 can be turned on, and the second transistor T2, the third transistor T3, and the fourth transistor T4 can be turned off. Therefore, the first transistor T1 can generate a drive current ID based on its gate terminal, and the light-emitting element LD can emit light due to the drive current ID. For example, the fifth part AS5n of the address scan operation ADSn can be referred to as the emit operation.

[0139] right Figure 3D The difference between the address scan operation (ADSn) and the self-scan operation performed on pixel PX can be essentially compared to the... Figure 3A The differences between the address scan operation (ADS) and the self-scan operation (SES) performed on pixel PX are the same. That is, the address scan operation (ADSn) can perform gate initialization, cathode initialization, threshold voltage compensation, data writing, source initialization, and emission operations, and the self-scan operation can perform cathode initialization, threshold voltage compensation, source initialization, and emission operations. In other words, the self-scan operation can perform emission operations without gate initialization and data writing operations. In the self-scan operation, the first gate signal GW and the second gate signal GR can maintain a low gate voltage.

[0140] Figure 4A It is shown that it includes Figure 1 A circuit diagram illustrating another example of the circuit structure of pixels in a display device. For example, Figure 4A It can be a circuit diagram that includes any one of the first to third sub-pixels in pixel PX.

[0141] References above Figure 3A Compared to the example of the circuit structure of the described pixel PX, in the reference Figure 4AIn some exemplary embodiments of the described circuit structure of pixel PX, the pixel driving circuit PC' may further include a seventh transistor T7. Therefore, redundant descriptions of some components are omitted or summarized.

[0142] refer to Figure 4A Pixel PX may include a light-emitting element LD and a pixel driving circuit PC' connected to the light-emitting element LD. In some exemplary embodiments, the pixel driving circuit PC' may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a first capacitor C1, and a second capacitor C2.

[0143] exist Figure 4A In this diagram, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 are shown as p-type transistors, and the first transistor T1, the second transistor T2, the third transistor T3, and the sixth transistor T6 are shown as n-type transistors. However, this disclosure is not necessarily limited thereto, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may all be n-type transistors.

[0144] Figure 4A The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6, the first capacitor C1, and the second capacitor C2 can be substantially the same as those mentioned above. Figure 3A The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6, as well as the first capacitor C1 and the second capacitor C2, are described as identical. Therefore, the above reference... Figure 3A The descriptions of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6, as well as the first capacitor C1 and the second capacitor C2, can be applied in the same (or similar) manner. Therefore, redundant descriptions are omitted.

[0145] The seventh transistor T7 may include a gate terminal, a first terminal, and a second terminal. In some exemplary embodiments, the first terminal of the seventh transistor T7 may be the source, and the second terminal of the seventh transistor T7 may be the drain. However, this disclosure is not necessarily limited thereto, and the first terminal of the seventh transistor T7 may be the drain, and the second terminal of the seventh transistor T7 may be the source. The gate terminal of the seventh transistor T7 may receive a third gate signal GC via a third gate line GCL. The first terminal of the seventh transistor T7 may receive a first power voltage ELVDD via a first voltage line VL1. The second terminal of the seventh transistor T7 may be connected to a third node N3.

[0146] The seventh transistor T7 can be turned on or off in response to the third gate signal GC. For example, when the seventh transistor T7 is a p-type transistor, it can be turned off when the third gate signal GC has a high gate voltage, and it can be turned on when the third gate signal GC has a low gate voltage. Furthermore, when the seventh transistor T7 is an n-type transistor, it can be turned off when the third gate signal GC has a low gate voltage, and it can be turned on when the third gate signal GC has a high gate voltage. When the seventh transistor T7 is turned on, it can provide a first power voltage ELVDD to the third node N3.

[0147] Although the gate line connected to the fourth transistor T4 and the gate line connected to the seventh transistor T7 are in Figure 4A The gate line is shown as a single gate line (e.g., the third gate line GCL), but this disclosure is not necessarily limited to this. For example, the gate line connected to the fourth transistor T4 and the gate line connected to the seventh transistor T7 may be different gate lines from each other.

[0148] Furthermore, although the fourth transistor T4 and the seventh transistor T7 are in Figure 4A The transistors are shown to be driven simultaneously (or synchronously) by the third gate signal GC, but this disclosure is not necessarily limited to this. For example, the fourth transistor T4 and the seventh transistor T7 can be driven independently by different signals.

[0149] Figure 4A The light-emitting element LD can be basically the same as the above reference. Figure 3A The described light-emitting element (LD) is the same. Therefore, the above reference... Figure 3A The description of the light-emitting element LD can be applied in the same (or similar) way. Therefore, redundant descriptions have been omitted.

[0150] Figure 4B It is shown Figure 1 The display device for Figure 4A A timing diagram of an example of performing an address scan operation on a pixel.

[0151] refer to Figure 1 , Figure 4A and Figure 4B The drive controller CON can perform address scan operation ADS' and self-scan operation. The drive controller CON can change the drive frequency of the display panel DP by adjusting the length of the self-scan operation.

[0152] like Figure 4B As shown, the address scan operation ADS' may include a first part AS1', a second part AS2', a third part AS3', a fourth part AS4', and a fifth part AS5'.

[0153] In the first part AS1' of the address scan operation ADS', the first transmit control signal EM1, the second transmit control signal EM2, the second gate signal GR, and the third gate signal GC can have high gate voltages, and the first gate signal GW can have a low gate voltage. In this case, the third transistor T3 and the sixth transistor T6 can be turned on, and the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 can be turned off. Therefore, a reference voltage VREF can be applied to the gate terminal of the first transistor T1, thereby initializing the voltage at the gate terminal of the first transistor T1. Furthermore, a second power voltage ELVSS can be applied to the first terminal of the first transistor T1. For example, the first part AS1' of the address scan operation ADS' can be referred to as a gate initialization operation.

[0154] In the second part AS2' of the address scan operation ADS', the first transmit control signal EM1 and the second gate signal GR can have high gate voltages, and the second transmit control signal EM2, the first gate signal GW, and the third gate signal GC can have low gate voltages. In this case, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 can be turned on, and the second transistor T2, the fifth transistor T5, and the sixth transistor T6 can be turned off. Therefore, a reference voltage VREF can be applied to the gate terminal of the first transistor T1, and a first power voltage ELVDD can be applied to the second terminal of the first transistor T1, thereby compensating for the threshold voltage of the first transistor T1. Furthermore, an initialization voltage VCINT can be applied to the cathode of the light-emitting element LD, thereby initializing the cathode voltage. For example, the second part AS2' of the address scan operation ADS' can be referred to as a threshold voltage compensation and cathode initialization operation.

[0155] In the third part AS3' of the address scan operation ADS', the first transmit control signal EM1, the first gate signal GW, and the third gate signal GC can have high gate voltages, while the second transmit control signal EM2 and the second gate signal GR can have low gate voltages. In this case, the second transistor T2 can be turned on, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be turned off. Therefore, the data voltage VDATA can be applied to the gate terminal of the first transistor T1. For example, the third part AS3' of the address scan operation ADS' can be referred to as a data write operation.

[0156] In the fourth part AS4' of the address scan operation ADS', the first transmit control signal EM1, the second transmit control signal EM2, and the third gate signal GC can have high gate voltages, while the first gate signal GW and the second gate signal GR can have low gate voltages. In this case, the sixth transistor T6 can be turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the seventh transistor T7 can be turned off. Therefore, the second power voltage ELVSS can be applied to the first terminal of the first transistor T1. For example, the fourth part AS4' of the address scan operation ADS' can be referred to as the source initialization operation.

[0157] In the fifth part AS5' of the address scan operation ADS', the first emit control signal EM1, the first gate signal GW, and the second gate signal GR can have low gate voltages, and the second emit control signal EM2 and the third gate signal GC can have high gate voltages. In this case, the fifth transistor T5 and the sixth transistor T6 can be turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 can be turned off. Therefore, the first transistor T1 can generate a drive current ID based on its gate terminal, and the light-emitting element LD can emit light due to the drive current ID. For example, the fifth part AS5' of the address scan operation ADS' can be referred to as the emit operation.

[0158] right Figure 4A The difference between the address scan operation ADS' performed on pixel PX and the self-scan operation can be essentially compared with the address scan operation ADS' performed on pixel PX. Figure 3AThe differences between the address scan operation (ADS) and the self-scan operation (SES) performed on pixel PX are the same. That is, the address scan operation (ADS) can perform gate initialization, cathode initialization, threshold voltage compensation, data writing, source initialization, and emission operations, and the self-scan operation can perform cathode initialization, threshold voltage compensation, source initialization, and emission operations. In other words, the self-scan operation can perform emission operations without gate initialization and data writing operations. In the self-scan operation, the first gate signal GW and the second gate signal GR can maintain a low gate voltage.

[0159] Figure 5A It is shown that it includes Figure 1 A circuit diagram illustrating another example of the circuit structure of pixels in a display device. For example, Figure 5A It can be a circuit diagram that includes any one of the first to third sub-pixels in pixel PX.

[0160] In addition to the signals applied to the gate electrodes of the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, Figure 5A The pixel driving circuit PC'' can be basically the same as the above reference. Figure 4A The pixel driving circuit PC' described is the same. Therefore, redundant descriptions of some components have been omitted or summarized.

[0161] refer to Figure 5A Pixel PX may include a light-emitting element LD and a pixel driving circuit PC'' connected to the light-emitting element LD. In some exemplary embodiments, the pixel driving circuit PC'' may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a first capacitor C1, and a second capacitor C2.

[0162] exist Figure 5A In this diagram, the fourth transistor T4 and the seventh transistor T7 are shown as p-type transistors, and the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 are shown as n-type transistors. However, this disclosure is not necessarily limited thereto, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may all be n-type transistors.

[0163] The fifth transistor T5 may include a gate terminal, a first terminal, and a second terminal. In some exemplary embodiments, the first terminal of the fifth transistor T5 may be the source, and the second terminal of the fifth transistor T5 may be the drain. However, this disclosure is not necessarily limited to this, and the first terminal of the fifth transistor T5 may be the drain, and the second terminal of the fifth transistor T5 may be the source. The gate terminal of the fifth transistor T5 can receive a first transmit control signal EM1 through a first transmit control line ECL1. The first terminal of the fifth transistor T5 may be connected to a third node N3. That is, the first terminal of the fifth transistor T5 may be connected to the second terminal of the first transistor T1. The second terminal of the fifth transistor T5 may be connected to a fourth node N4. That is, the second terminal of the fifth transistor T5 may be connected to a light-emitting element LD.

[0164] The fifth transistor T5 can be turned on or off in response to the first emission control signal EM1. For example, when the fifth transistor T5 is an n-type transistor, it can be turned off when the first emission control signal EM1 has a low gate voltage, and it can be turned on when the first emission control signal EM1 has a high gate voltage. When the fifth transistor T5 is turned on, it can electrically connect the first transistor T1 and the light-emitting element LD. That is, the fifth transistor T5 can electrically connect the second terminal of the first transistor T1 and the cathode of the light-emitting element LD in response to the first emission control signal EM1.

[0165] The sixth transistor T6 may include a gate terminal, a first terminal, and a second terminal. In some exemplary embodiments, the first terminal of the sixth transistor T6 may be the source, and the second terminal of the sixth transistor T6 may be the drain. However, this disclosure is not necessarily limited to this, and the first terminal of the sixth transistor T6 may be the drain, and the second terminal of the sixth transistor T6 may be the source. The gate terminal of the sixth transistor T6 may receive a first transmit control signal EM1 via a first transmit control line ECL1. The first terminal of the sixth transistor T6 may receive a second power voltage ELVSS via a second voltage line VL2. The second terminal of the sixth transistor T6 may be connected to a second node N2.

[0166] The sixth transistor T6 can be turned on or off in response to the first transmit control signal EM1. For example, when the sixth transistor T6 is an n-type transistor, the sixth transistor T6 can be turned off when the first transmit control signal EM1 has a low gate voltage, and the sixth transistor T6 can be turned on when the first transmit control signal EM1 has a high gate voltage. When the sixth transistor T6 is turned on, the sixth transistor T6 can provide a second power voltage ELVSS to the second node N2.

[0167] exist Figure 5A In this embodiment, the fifth transistor T5 and the sixth transistor T6 can be simultaneously (or synchronously) turned on or off in response to a substantially single transmit control signal (e.g., the first transmit control signal EM1). However, this disclosure is not necessarily limited thereto.

[0168] The seventh transistor T7 may include a gate terminal, a first terminal, and a second terminal. In some exemplary embodiments, the first terminal of the seventh transistor T7 may be the source, and the second terminal of the seventh transistor T7 may be the drain. However, this disclosure is not necessarily limited to this, and the first terminal of the seventh transistor T7 may be the drain, and the second terminal of the seventh transistor T7 may be the source. The gate terminal of the seventh transistor T7 may receive a second transmit control signal EM2 via a second transmit control line ECL2. The first terminal of the seventh transistor T7 may receive a first power voltage ELVDD via a first voltage line VL1. The second terminal of the seventh transistor T7 may be connected to a third node N3.

[0169] The seventh transistor T7 can be turned on or off in response to the second emitter control signal EM2. For example, when the seventh transistor T7 is a p-type transistor, it can be turned off when the second emitter control signal EM2 has a high gate voltage, and it can be turned on when the second emitter control signal EM2 has a low gate voltage. When the seventh transistor T7 is turned on, it can provide a first power voltage ELVDD to the third node N3.

[0170] Figure 5B It is shown Figure 1 The display device for Figure 5A A timing diagram of an example of performing an address scan operation on a pixel.

[0171] refer to Figure 1 , Figure 5A and Figure 5B The drive controller CON can perform address scan operation (ADS'') and self-scan operation. The drive controller CON can change the drive frequency of the display panel DP by adjusting the length of the self-scan operation.

[0172] like Figure 5B As shown, the address scan operation ADS'' may include a first part AS1'', a second part AS2'', a third part AS3'', a fourth part AS4'', and a fifth part AS5''.

[0173] In the first part AS1 of the address scan operation ADS'', the first transmit control signal EM1, the second transmit control signal EM2, the second gate signal GR, and the third gate signal GC can have high gate voltages, and the first gate signal GW can have a low gate voltage. In this case, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 can be turned on, and the second transistor T2, the fourth transistor T4, and the seventh transistor T7 can be turned off. Therefore, a reference voltage VREF can be applied to the gate terminal of the first transistor T1, thereby initializing the voltage at the gate terminal of the first transistor T1. A second power voltage ELVSS can be applied to the first terminal of the first transistor T1. For example, the first part AS1 of the address scan operation ADS'' can be referred to as the gate initialization operation.

[0174] In the second part AS2'' of the address scan operation ADS'', the first emit control signal EM1, the first gate signal GW, and the third gate signal GC can have low gate voltages. The second gate signal GR and the second emit control signal EM2 can have either low or high gate voltages. In this case, the fourth transistor T4 can be turned on, and the second transistor T2, the fifth transistor T5, and the sixth transistor T6 can be turned off. The third transistor T3 and the seventh transistor T7 can be turned on or off. Therefore, an initialization voltage VCINT can be applied to the cathode of the light-emitting element LD, thereby initializing the cathode voltage. For example, the second part AS2'' of the address scan operation ADS'' can be referred to as the cathode initialization operation.

[0175] In the third part AS3'' of the address scan operation ADS'', the first transmit control signal EM1, the second transmit control signal EM2, and the first gate signal GW can have low gate voltages, and the second gate signal GR can have high gate voltages. The third gate signal GC can have either low or high gate voltages. In this case, the third transistor T3 and the seventh transistor T7 can be turned on, and the second transistor T2, the fifth transistor T5, and the sixth transistor T6 can be turned off. The fourth transistor T4 can be turned on or off. Therefore, a reference voltage VREF can be applied to the gate terminal of the first transistor T1, and a first power voltage ELVDD can be applied to the second terminal of the first transistor T1, thereby compensating for the threshold voltage of the first transistor T1. For example, the third part AS3'' of the address scan operation ADS'' can be referred to as a threshold voltage compensation operation.

[0176] In the fourth part AS4'' of the address scan operation ADS'', the second transmit control signal EM2, the first gate signal GW, and the third gate signal GC can have high gate voltages, while the first transmit control signal EM1 and the second gate signal GR can have low gate voltages. Therefore, the second transistor T2 can be turned on, and the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be turned off. Thus, the data voltage VDATA can be applied to the gate terminal of the first transistor T1. For example, the fourth part AS4'' of the address scan operation ADS'' can be referred to as a data write operation.

[0177] In the fifth part AS5'' of the address scan operation ADS'', the first emit control signal EM1, the second emit control signal EM2, and the third gate signal GC can have high gate voltages, and the first gate signal GW and the second gate signal GR can have low gate voltages. In this case, the fifth transistor T5 and the sixth transistor T6 can be turned on, and the second transistor T2, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 can be turned off. Therefore, the first transistor T1 can generate a drive current ID based on its gate terminal, and the light-emitting element LD can emit light due to the drive current ID. For example, the fifth part AS5'' of the address scan operation ADS'' can be referred to as the emit operation.

[0178] right Figure 5A The difference between the address scan operation ADS'' and the self-scan operation performed on the pixel PX can be essentially compared to the... Figure 3A The differences between the address scan operation (ADS) and the self-scan operation (SES) performed on the pixel PX are the same. That is, the self-scan operation can perform the transmit operation without gate initialization and data write operations. During the self-scan operation, the first gate signal GW and the second gate signal GR can maintain low gate voltages.

[0179] According to some exemplary implementations, such as Figure 3A , Figure 3D , Figure 4A and Figure 5A As shown, the anode of the light-emitting element LD can receive a first power voltage ELVDD through the first voltage line VL1, and the cathode of the light-emitting element LD can be connected to the second terminal of the first transistor T1. That is, the potential of the cathode of the light-emitting element LD can be controlled by electrically connecting it to the first transistor T1.

[0180] Since the first voltage line VL1 provides a first power voltage ELVDD (or drive voltage) with a relatively high voltage level, and the second voltage line VL2 provides a second power voltage ELVSS (or common voltage) with a relatively low voltage level, the second terminal of the first transistor T1 can be the drain when the first transistor T1 is an n-type transistor. That is, according to some exemplary embodiments, the cathode of the light-emitting element LD can be connected to the drain of the first transistor T1.

[0181] When the first transistor T1 is an n-type transistor, if the anode of the light-emitting element LD is connected to the source of the first transistor T1, the source voltage of the first transistor T1 may shift due to the degradation of the light-emitting element LD. This will cause a change in the gate-source voltage of the first transistor T1. Therefore, the range of variation in the drive current ID may increase, which can lead to afterimage defects and reduce the lifespan of the display device.

[0182] According to some exemplary embodiments, the anode of the light-emitting element LD can receive a first power voltage ELVDD, and the cathode of the light-emitting element LD can be connected to the drain of the first transistor T1. Therefore, even when the light-emitting element LD deteriorates, the gate-source voltage of the first transistor T1 can remain unchanged. Therefore, the range of changes in the drive current ID due to the deterioration of the light-emitting element LD can be reduced. Therefore, the afterimage defects of the display device DD due to increased usage time can be reduced, and the lifespan of the display device DD can be improved (e.g., increased).

[0183] exist Figure 3A , Figure 3D , Figure 4A and Figure 5A The circuit structure of the pixel PX shown (e.g., the number or arrangement of transistors, the number or arrangement of capacitors, etc.) is merely an example and may vary according to some exemplary implementations.

[0184] Figure 6 It is shown schematically. Figure 2A and Figure 2B A floor plan of a portion of the area of ​​the display device. Figure 7 It is along Figure 6 A cross-sectional view taken along line I-I'. For ease of description, in... Figure 6 The text omits or emphasizes Figure 7 Some of the components shown.

[0185] refer to Figure 6The display device DD may include a first pixel driving circuit to a third pixel driving circuit, a first light-emitting element LDa, a second light-emitting element LDb and a third light-emitting element LDc, a first connecting pattern CNPa, a second connecting pattern CNPb and a third connecting pattern CNPc, and a separator SPR.

[0186] Each of the first to third pixel driving circuits can correspond to the above reference. Figure 3A , Figure 3D , Figure 4A and Figure 5A The pixel driving circuit described is any one of PC, PCn, PC', and PC''. Each of the first to third pixel driving circuits may include at least one transistor and at least one capacitor. For example, each of the first to third pixel driving circuits may include Figure 7 The first transistor TR1, the second transistor TR2, the first capacitor CAP1, and the second capacitor CAP2 are shown in the figure.

[0187] Figure 7 The second transistor TR2 can be a transistor connected to the light-emitting element via connecting electrodes and connecting patterns. For example, when the first pixel driving circuit to the third pixel driving circuit is... Figure 5A When the pixel driving circuit PC'' is in use, the second transistor TR2 can be Figure 5A The fifth transistor T5, and the first transistor TR1 can be Figure 5A The fourth transistor T4 or the seventh transistor T7. However, this disclosure is not necessarily limited to this.

[0188] In some exemplary embodiments, Figure 7 The first capacitor CAP1 can correspond to Figure 3A , Figure 3D , Figure 4A and Figure 5A The first capacitor C1, and Figure 7 The second capacitor CAP2 can correspond to Figure 3A , Figure 3D , Figure 4A and Figure 5A The second capacitor C2. However, this disclosure is not necessarily limited thereto, and Figure 7 The first capacitor CAP1 can correspond to Figure 3A , Figure 3D , Figure 4A and Figure 5A The second capacitor C2, and Figure 7 The second capacitor CAP2 can correspond to Figure 3A , Figure 3D , Figure 4A and Figure 5AThe first capacitor is C1.

[0189] The following is for reference. Figure 7 The components of the first transistor TR1, the second transistor TR2, the first capacitor CAP1, and the second capacitor CAP2 are described in more detail.

[0190] The display device DD may include a first light-emitting region EAa, a second light-emitting region EAb, and a third light-emitting region EAc. The first light-emitting region EAa, the second light-emitting region EAb, and the third light-emitting region EAc may be arranged in various shapes. In some exemplary embodiments, such as... Figure 6 As shown, the first light-emitting region EAa, the second light-emitting region EAb, and the third light-emitting region EAc can be arranged in a pentile configuration. ® Shape. However, this disclosure is not necessarily limited to this, and the first luminous region EAa, the second luminous region EAb, and the third luminous region EAc can be arranged in an S-shape or a Diamond Pixel shape. ® shape.

[0191] The first luminescent region EAa, the second luminescent region EAb, and the third luminescent region EAc can be defined by the pixel-defined layer PDL as described below (see [link]). Figure 7 The pixel opening is defined by the light-emitting region EAa. That is, the first light-emitting region EAa, the second light-emitting region EAb, and the third light-emitting region EAc can all be regions where light is emitted by light-emitting elements. For example, the first light-emitting element LDa can be disposed in the first light-emitting region EAa, and the first light-emitting region EAa can be the region where light is emitted by the first light-emitting element LDa. Furthermore, the second light-emitting element LDb can be disposed in the second light-emitting region EAb, and the second light-emitting region EAb can be the region where light is emitted by the second light-emitting element LDb. Furthermore, the third light-emitting element LDc can be disposed in the third light-emitting region EAc, and the third light-emitting region EAc can be the region where light is emitted by the third light-emitting element LDc.

[0192] The first light-emitting element LDa, the second light-emitting element LDb, and the third light-emitting element LDc can be connected to the first pixel driving circuit to the third pixel driving circuit, respectively. For example, the first light-emitting element LDa can be connected to the first pixel driving circuit, the second light-emitting element LDb can be connected to the second pixel driving circuit, and the third light-emitting element LDc can be connected to the third pixel driving circuit. Therefore, the first pixel driving circuit and the first light-emitting element LDa can form a sub-pixel (e.g., the first sub-pixel). The second pixel driving circuit and the second light-emitting element LDb can form a sub-pixel (e.g., the second sub-pixel). The third pixel driving circuit and the third light-emitting element LDc can form a sub-pixel (e.g., the third sub-pixel).

[0193] The first light-emitting element LDa, the second light-emitting element LDb, and the third light-emitting element LDc can emit light of different colors. For example, the first light-emitting element LDa can emit red light (from...). Figure 6 (The "R" in the image indicates that the second light-emitting element LDb can emit green light (by...) Figure 6 The "G" in the middle represents the light source, and the third light-emitting element LDc can emit blue light (by...). Figure 6 (The letter "B" indicates this). However, this disclosure is not necessarily limited thereto.

[0194] Each of the first light-emitting element LDa, the second light-emitting element LDb, and the third light-emitting element LDc can correspond to the above reference. Figure 3A , Figure 3D , Figure 4A and Figure 5A The light-emitting element LD is described. For example, each of the first light-emitting element LDa, the second light-emitting element LDb, and the third light-emitting element LDc may include a first electrode E1 (see [link to documentation]). Figure 7 ), and the intermediate layer ML disposed on the first electrode E1 (see Figure 7 ) and the electrode layer E2L disposed on the intermediate layer ML (see Figure 7 In some exemplary embodiments, the first electrode E1 can be used as... Figure 3A , Figure 3D , Figure 4A and Figure 5A The anode, and the electrode layer E2L can be used as... Figure 3A , Figure 3D , Figure 4A and Figure 5A The cathode.

[0195] In a plan view, the spacer SPR can be disposed between the first light-emitting region EAa, the second light-emitting region EAb, and the third light-emitting region EAc. For example, in a plan view, the spacer SPR can be disposed between the first light-emitting region EAa and the second light-emitting region EAb, between the second light-emitting region EAb and the third light-emitting region EAc, and between the first light-emitting region EAa and the third light-emitting region EAc. In some exemplary embodiments, in a plan view, the spacer SPR can completely surround each of the first light-emitting region EAa, the second light-emitting region EAb, and the third light-emitting region EAc. In some exemplary embodiments, the spacer SPR may include an organic insulating material.

[0196] The separator SPR can separate the electrode layer E2L (see Figure 7 The electrode layer E2L can be divided (or disconnected) into multiple second electrodes spaced apart from each other. For example, the electrode layer E2L can be divided (or disconnected) into the second electrode E2 of the first light-emitting element LDa (see...). Figure 7The second electrode of the first light-emitting element LDa, the second electrode of the second light-emitting element LDb, and the second electrode of the third light-emitting element LDc are respectively. Therefore, the second electrode E2 of the first light-emitting element LDa, the second electrode of the second light-emitting element LDb, and the second electrode of the third light-emitting element LDc can be spaced apart from each other. In addition, the second electrode E2 of the first light-emitting element LDa, the second electrode of the second light-emitting element LDb, and the second electrode of the third light-emitting element LDc can be electrically independent of each other.

[0197] The first connection pattern CNPa can connect the first light-emitting element LDa and the first pixel driving circuit, the second connection pattern CNPb can connect the second light-emitting element LDb and the second pixel driving circuit, and the third connection pattern CNPc can connect the third light-emitting element LDc and the third pixel driving circuit.

[0198] In some exemplary embodiments, the first connection pattern CNPa, the second connection pattern CNPb, and the third connection pattern CNPc may comprise transparent conductive oxides. Examples of transparent conductive oxides that can be used as the first connection pattern CNPa, the second connection pattern CNPb, and the third connection pattern CNPc may include indium gallium zinc oxide (IGZO), indium tin zinc oxide (ITZO), indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), zinc oxide (ZnO), indium oxide (InO), tin oxide (SnO), gallium oxide (GaO), aluminum zinc oxide (AZO), etc. They may be used individually or in combination with each other.

[0199] However, this disclosure is not necessarily limited thereto, and the first connection pattern CNPa, the second connection pattern CNPb, and the third connection pattern CNPc may include conductive materials, such as metals, alloys, conductive metal nitrides, etc. Examples of conductive materials that can be used as the first connection pattern CNPa, the second connection pattern CNPb, and the third connection pattern CNPc may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), alloys containing aluminum (Al), alloys containing silver (Ag), alloys containing copper (Cu), alloys containing molybdenum (Mo), aluminum nitride (AlN), tungsten nitride (WN), titanium nitride (TiN), chromium nitride (CrN), tantalum nitride (TaN), etc. These may be used alone or in combination with each other.

[0200] In some exemplary embodiments, the first connection pattern CNPa, the second connection pattern CNPb, and the third connection pattern CNPc may have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked.

[0201] The first connection pattern CNPa can be connected to the first connection electrode CE (see...). Figure 7 In some exemplary embodiments, the first connection pattern CNPa can contact the first connection electrode CE through the first pattern contact hole TCNTa.

[0202] In a plan view, the first connecting pattern CNPa may not overlap with the first luminous region EAa. In some exemplary embodiments, in a plan view, the first connecting pattern CNPa may surround at least a portion of the first luminous region EAa. For example, in a plan view, the first connecting pattern CNPa may have a closed-loop shape that completely surrounds the first luminous region EAa. However, this disclosure is not necessarily limited to this.

[0203] The second electrode E2 of the first light-emitting element LDa (see...) Figure 7 The first light-emitting element LTa can be connected to the first connection pattern CNPa. For example, the second electrode E2 of the first light-emitting element LTa can contact the first connection pattern CNPa. Therefore, the first connection pattern CNPa can be electrically connected to the first connection electrode CE (see...). Figure 7 The first light-emitting element LDa and its second electrode E2. Therefore, the second electrode E2 of the first light-emitting element LDa can be electrically connected to the first pixel driving circuit through the first connecting electrode CE and the first connecting pattern CNPa.

[0204] In some exemplary embodiments, the planar profile of the area where the second electrode E2 of the first light-emitting element LDa contacts the first connecting pattern CNPa can be substantially the same as or similar to the planar profile of the edge of the first connecting pattern CNPa. For example, when the first connecting pattern CNPa has a closed-loop shape that completely surrounds the first light-emitting region EAa in a planar view, the area where the second electrode E2 of the first light-emitting element LDa contacts the first connecting pattern CNPa can also have a closed-loop shape in a planar view. That is, the second electrode E2 of the first light-emitting element LDa and the first connecting pattern CNPa can contact at a location that does not overlap with the first light-emitting region EAa. Therefore, the second electrode E2 of the first light-emitting element LDa can be electrically connected to the first pixel driving circuit through the first connecting electrode CE and the first connecting pattern CNPa without reducing the size of the first light-emitting region EAa.

[0205] The second connection pattern CNPb can be connected to the second connection electrode. In some exemplary embodiments, the second connection pattern CNPb can contact the second connection electrode through the second pattern contact hole TCNTb. In some exemplary embodiments, the first connection electrode CE and the second connection electrode can be spaced apart from each other in a planar view. That is, the first connection electrode CE and the second connection electrode can be different electrodes from each other.

[0206] In a plan view, the second connecting pattern CNPb may not overlap with the second light-emitting region EAb. In some exemplary embodiments, in a plan view, the second connecting pattern CNPb may surround at least a portion of the second light-emitting region EAb. For example, in a plan view, the second connecting pattern CNPb may have a closed-loop shape that completely surrounds the second light-emitting region EAb. However, this disclosure is not necessarily limited to this.

[0207] The second electrode of the second light-emitting element LDb can be connected to the second connection pattern CNPb. For example, the second electrode of the second light-emitting element LDb can contact the second connection pattern CNPb. Therefore, the second connection pattern CNPb can electrically connect the second connection electrode and the second electrode of the second light-emitting element LDb. Thus, the second electrode of the second light-emitting element LDb can be electrically connected to the second pixel driving circuit through the second connection electrode and the second connection pattern CNPb.

[0208] In some exemplary embodiments, the planar profile of the area where the second electrode of the second light-emitting element LDb contacts the second connection pattern CNPb can be substantially the same as or similar to the planar profile of the edge of the second connection pattern CNPb. For example, when the second connection pattern CNPb has a closed-loop shape that completely surrounds the second light-emitting region EAb in a planar view, the area where the second electrode of the second light-emitting element LDb contacts the second connection pattern CNPb can also have a closed-loop shape in a planar view. That is, the second electrode of the second light-emitting element LDb and the second connection pattern CNPb can contact at a location that does not overlap with the second light-emitting region EAb. Therefore, the second electrode of the second light-emitting element LDb can be electrically connected to the second pixel driving circuit through the second connection electrode and the second connection pattern CNPb without reducing the size of the second light-emitting region EAb.

[0209] The third connection pattern CNPc can be connected to the third connection electrode. In some exemplary embodiments, the third connection pattern CNPc can contact the third connection electrode through the third pattern contact hole TCNTc. In some exemplary embodiments, the first connection electrode CE, the second connection electrode, and the third connection electrode can be spaced apart from each other in a plan view. That is, the first connection electrode CE, the second connection electrode, and the third connection electrode can be different electrodes from each other.

[0210] In a plan view, the third connecting pattern CNPc may not overlap with the third light-emitting region EAc. In some exemplary embodiments, in a plan view, the third connecting pattern CNPc may surround at least a portion of the third light-emitting region EAc. For example, in a plan view, the third connecting pattern CNPc may have a closed-loop shape that completely surrounds the third light-emitting region EAc. However, this disclosure is not necessarily limited to this.

[0211] The second electrode of the third light-emitting element LDc can be connected to the third connection pattern CNPc. For example, the second electrode of the third light-emitting element LDc can contact the third connection pattern CNPc. Therefore, the third connection pattern CNPc can electrically connect the third connection electrode and the second electrode of the third light-emitting element LDc. Thus, the second electrode of the third light-emitting element LDc can be electrically connected to the third pixel driving circuit through the third connection electrode and the third connection pattern CNPc.

[0212] In some exemplary embodiments, the planar profile of the area where the second electrode of the third light-emitting element LDc and the third connecting pattern CNPc contact can be substantially the same as or similar to the planar profile of the edge of the third connecting pattern CNPc. For example, when the third connecting pattern CNPc has a closed-loop shape that completely surrounds the third light-emitting region EAc in a planar view, the area where the second electrode of the third light-emitting element LDc and the third connecting pattern CNPc contact can also have a closed-loop shape in a planar view. That is, the second electrode of the third light-emitting element LDc and the third connecting pattern CNPc can contact at a location that does not overlap with the third light-emitting region EAc. Therefore, the second electrode of the third light-emitting element LDc can be electrically connected to the third pixel driving circuit through the third connecting electrode and the third connecting pattern CNPc without reducing the size of the third light-emitting region EAc.

[0213] As described above, the display device DD may include a separator SPR. The separator SPR may overlap with the first connection pattern CNPa, the second connection pattern CNPb, and the third connection pattern CNPc in a planar view. For example, the separator SPR may cover a portion of the first connection pattern CNPa, the second connection pattern CNPb, and the third connection pattern CNPc. That is, at least a portion of the separator SPR may extend along the edges of the first connection pattern CNPa, the second connection pattern CNPb, and the third connection pattern CNPc in a planar view. Therefore, in a planar view, the areas where the second electrodes of the first light-emitting element LDa, the second light-emitting element LDb, and the third light-emitting element LDc respectively contact the first connection pattern CNPa, the second connection pattern CNPb, and the third connection pattern CNPc may be adjacent to or overlap with the areas where the separator SPR is disposed.

[0214] The separator SPR can define a first opening region OA1, a second opening region OA2, and a third opening region OA3. For example, in a plan view, the separator SPR can have a mesh structure surrounding the second electrode. The second electrode E2 of the first light-emitting element LTa can be disposed in the first opening region OA1 of the separator SPR, the second electrode of the second light-emitting element LDb can be disposed in the second opening region OA2 of the separator SPR, and the second electrode of the third light-emitting element LDc can be disposed in the third opening region OA3 of the separator SPR.

[0215] The first opening region OA1, the second opening region OA2, and the third opening region OA3 of the separator SPR can correspond to the first connecting pattern CNPa, the second connecting pattern CNPb, and the third connecting pattern CNPc, respectively. For example, the first connecting pattern CNPa can overlap with the first opening region OA1, the second connecting pattern CNPb can overlap with the second opening region OA2, and the third connecting pattern CNPc can overlap with the third opening region OA3.

[0216] In the following text, reference will be made to Figure 7 The cross-sectional structure of the display device DD is described in more detail focusing on the first light-emitting region EAa. The following description of the cross-sectional structure of the display device DD can be applied in the same (or similarly) to all light-emitting regions.

[0217] Further reference Figure 7 The display device DD may include a substrate SUB, a circuit element layer PCL, a pixel defining layer PDL, a first connection pattern CNPa, a first light-emitting element LDa, a separator SPR, a first dummy layer DP1, a second dummy layer DP2, and / or a packaging layer ENC. The circuit element layer PCL may include a first transistor TR1, a second transistor TR2, a first capacitor CAP1, a second capacitor CAP2, a first connection electrode CE, and / or a first insulating layer IL1, a second insulating layer IL2, a third insulating layer IL3, a fourth insulating layer IL4, a fifth insulating layer IL5, a sixth insulating layer IL6, and a seventh insulating layer IL7.

[0218] The first transistor TR1 may include a lower active pattern PACT, a first gate electrode GE1, a first contact electrode SE1, and a second contact electrode DE1. The second transistor TR2 may include an upper active pattern OACT, a second gate electrode GE2, a third contact electrode SE2, and a fourth contact electrode DE2. The first capacitor CAP1 may include a first capacitor electrode CPE1 and a third capacitor electrode CPE3. The second capacitor CAP2 may include a second capacitor electrode CPE2 and a fourth capacitor electrode CPE4. The first light-emitting element LDa may include a first electrode E1, an intermediate layer ML, and a second electrode E2.

[0219] As described above, the first transistor TR1, the second transistor TR2, the first capacitor CAP1, and the second capacitor CAP2 may be components included in the first pixel driving circuit.

[0220] The lower active pattern PACT can be disposed on the substrate SUB. In some exemplary embodiments, the lower active pattern PACT may include a silicon semiconductor material. Examples of silicon semiconductor materials may include amorphous silicon, polycrystalline silicon, etc. The lower active pattern PACT may include a first contact region S1, a second contact region D1, and a first channel region CH1 between the first contact region S1 and the second contact region D1. The first contact region S1 and the second contact region D1 may have a higher conductivity than the first channel region CH1.

[0221] A first insulating layer IL1 may be disposed on a substrate SUB. The first insulating layer IL1 may cover the lower active pattern PACT on the substrate SUB. The first insulating layer IL1 may include an insulating material. Examples of insulating materials that can be used as the first insulating layer IL1 may include silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y These can be used individually or in combination with each other.

[0222] The first gate electrode GE1 can be disposed on the lower active pattern PACT. For example, the first gate electrode GE1 can be disposed on the first insulating layer IL1. The first gate electrode GE1 can overlap with the first channel region CH1 of the lower active pattern PACT. The first gate electrode GE1 can include a conductive material, such as a metal, alloy, conductive metal oxide, conductive metal nitride, transparent conductive oxide, etc.

[0223] The first capacitor electrode CPE1 and the second capacitor electrode CPE2 can be disposed on the first insulating layer IL1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 can be spaced apart from each other. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 can include conductive materials, such as metals, alloys, conductive metal oxides, conductive metal nitrides, transparent conductive oxides, etc.

[0224] A second insulating layer IL2 may be disposed on the first insulating layer IL1. The second insulating layer IL2 may cover the first gate electrode GE1, the first capacitor electrode CPE1, and the second capacitor electrode CPE2 on the first insulating layer IL1. The second insulating layer IL2 may include an insulating material. Examples of insulating materials that can be used as the second insulating layer IL2 may include silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y These can be used individually or in combination with each other.

[0225] The third capacitor electrode CPE3 and the fourth capacitor electrode CPE4 can be disposed on the second insulating layer IL2. The third capacitor electrode CPE3 and the fourth capacitor electrode CPE4 can be spaced apart from each other. In a planar view, the third capacitor electrode CPE3 can overlap with the first capacitor electrode CPE1. The first capacitor electrode CPE1 and the third capacitor electrode CPE3 can form a first capacitor CAP1. In a planar view, the fourth capacitor electrode CPE4 can overlap with the second capacitor electrode CPE2. The second capacitor electrode CPE2 and the fourth capacitor electrode CPE4 can form a second capacitor CAP2. The third capacitor electrode CPE3 and the fourth capacitor electrode CPE4 can include conductive materials, such as metals, alloys, conductive metal oxides, conductive metal nitrides, transparent conductive oxides, etc.

[0226] A third insulating layer IL3 may be disposed on the second insulating layer IL2. The third insulating layer IL3 may cover the third capacitor electrode CPE3 and the fourth capacitor electrode CPE4 on the second insulating layer IL2. The third insulating layer IL3 may include an insulating material. Examples of insulating materials that can be used as the third insulating layer IL3 may include silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y These can be used individually or in combination with each other.

[0227] The upper active pattern OACT can be disposed between the first gate electrode GE1 and the first contact electrode SE1. For example, the upper active pattern OACT can be disposed on the third insulating layer IL3. In some exemplary embodiments, the upper active pattern OACT and the lower active pattern PACT can include different materials. For example, the upper active pattern OACT can include an oxide semiconductor material. Examples of oxide semiconductor materials can include indium gallium zinc oxide (IGZO), zinc tin oxide (ZTO), and indium tin zinc oxide (ITZO). They can be used alone or in combination with each other.

[0228] The upper active pattern OACT may include a third contact region S2, a fourth contact region D2, and a second channel region CH2 between the third contact region S2 and the fourth contact region D2. The third contact region S2 and the fourth contact region D2 may have higher conductivity than the second channel region CH2.

[0229] A fourth insulating layer IL4 may be disposed on the third insulating layer IL3. The fourth insulating layer IL4 may cover the upper active pattern OACT on the third insulating layer IL3. The fourth insulating layer IL4 may include an insulating material. Examples of insulating materials that may be used as the fourth insulating layer IL4 may include silicon oxide (SiO2).x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y These can be used individually or in combination with each other.

[0230] The second gate electrode GE2 can be disposed on the upper active pattern OACT. For example, the second gate electrode GE2 can be disposed on the fourth insulating layer IL4. The second gate electrode GE2 can overlap with the second channel region CH2 of the upper active pattern OACT. The second gate electrode GE2 can include a conductive material, such as a metal, alloy, conductive metal oxide, conductive metal nitride, transparent conductive oxide, etc.

[0231] A fifth insulating layer IL5 may be disposed on the fourth insulating layer IL4. The fifth insulating layer IL5 may cover the second gate electrode GE2 on the fourth insulating layer IL4. The fifth insulating layer IL5 may include an insulating material. Examples of insulating materials that may be used as the fifth insulating layer IL5 may include silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon oxynitride (SiO) x N y These can be used individually or in combination with each other.

[0232] The first contact electrode SE1, the second contact electrode DE1, the third contact electrode SE2, and the fourth contact electrode DE2 can be disposed on the fifth insulating layer IL5. The first contact electrode SE1 can contact the first contact area S1 of the lower active pattern PACT, and the second contact electrode DE1 can contact the second contact area D1 of the lower active pattern PACT. The third contact electrode SE2 can contact the third contact area S2 of the upper active pattern OACT, and the fourth contact electrode DE2 can contact the fourth contact area D2 of the upper active pattern OACT. In some exemplary embodiments, the third contact electrode SE2 can contact the first capacitor electrode CPE1. However, this disclosure is not necessarily limited to this. The first contact electrode SE1, the second contact electrode DE1, the third contact electrode SE2, and the fourth contact electrode DE2 can include conductive materials, such as metals, alloys, conductive metal oxides, conductive metal nitrides, transparent conductive oxides, etc.

[0233] A sixth insulating layer IL6 may be disposed on the fifth insulating layer IL5. The sixth insulating layer IL6 may cover the first contact electrode SE1, the second contact electrode DE1, the third contact electrode SE2, and the fourth contact electrode DE2 on the fifth insulating layer IL5. The sixth insulating layer IL6 may include an insulating material. For example, the sixth insulating layer IL6 may include an organic insulating material. Examples of organic insulating materials that can be used as the sixth insulating layer IL6 may include polyacrylate-based resins, polyimide-based resins, polyamide-based resins, siloxane-based resins, acrylic-based resins, epoxy-based resins, etc. These may be used alone or in combination with each other.

[0234] The first connection electrode CE can be disposed on the sixth insulating layer IL6. The first connection electrode CE can be connected to the second transistor TR2. For example, the first connection electrode CE can contact the second transistor TR2 (e.g., the fourth contact electrode DE2) through a contact hole penetrating the sixth insulating layer IL6. The first connection electrode CE can include a conductive material, such as a metal, alloy, conductive metal oxide, conductive metal nitride, transparent conductive oxide, etc. In some exemplary embodiments, the first connection electrode CE can have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked.

[0235] A seventh insulating layer IL7 may partially cover the first connecting electrode CE and may be disposed on the sixth insulating layer IL6. The seventh insulating layer IL7 may define a first sub-opening SO1 that exposes at least a portion of the first connecting electrode CE. The seventh insulating layer IL7 may include an insulating material. For example, the seventh insulating layer IL7 may include an organic insulating material. Examples of organic insulating materials that can be used as the seventh insulating layer IL7 may include polyacrylate-based resins, polyimide-based resins, polyamide-based resins, siloxane-based resins, acrylic-based resins, epoxy-based resins, etc. These may be used alone or in combination with each other.

[0236] The first electrode E1 can be disposed on the seventh insulating layer IL7. The first electrode E1 can be spaced apart from the first connecting electrode CE. The first electrode E1 can include a conductive material, such as a metal, alloy, conductive metal oxide, conductive metal nitride, transparent conductive oxide, etc. As described above, the first electrode E1 can be used as... Figure 3A , Figure 3D , Figure 4A and Figure 5A The anode.

[0237] A pixel defining layer (PDL) can be disposed on the seventh insulating layer (IL7) and the first electrode (E1). The PDL can define a pixel opening that exposes a portion of the first electrode (E1). A first light-emitting region (EAa) can be defined by the pixel opening.

[0238] Furthermore, the pixel defining layer PDL can also define a second sub-opening SO2 corresponding to the first sub-opening SO1 of the seventh insulating layer IL7. In a plan view, the second sub-opening SO2 can overlap with the first sub-opening SO1. The first sub-opening SO1 and the second sub-opening SO2 can be spatially connected to each other. That is, a sub-opening OP can be defined at the location where the first sub-opening SO1 and the second sub-opening SO2 are connected, and the sub-opening OP can expose a portion of the first connecting electrode CE.

[0239] The first connection pattern CNPa can be disposed on the first connection electrode CE, the seventh insulating layer IL7, and the pixel defining layer PDL. The first connection pattern CNPa can be connected to the first connection electrode CE. For example, the first connection pattern CNPa can contact the first connection electrode CE through a sub-opening OP (or a first pattern contact hole TCNTa) that penetrates the seventh insulating layer IL7 and the pixel defining layer PDL.

[0240] In some exemplary embodiments, the first connection pattern CNPa may include a transparent conductive oxide. However, this disclosure is not necessarily limited thereto, and the first connection pattern CNPa may include conductive materials such as metals, alloys, conductive metal nitrides, etc. In some exemplary embodiments, the first connection pattern CNPa may have a single-layer structure or a multilayer structure in which multiple conductive layers are stacked.

[0241] The separator SPR can be disposed on the pixel-defining layer PDL and the first connection pattern CNPa. In a planar view, the separator SPR can overlap with the first connection pattern CNPa. For example, the separator SPR can cover a portion of the first connection pattern CNPa.

[0242] The width of the upper part of the partition SPR can be greater than the width of the lower part of the partition SPR. That is, the side surface of the partition SPR connecting the upper and lower surfaces of the partition SPR can have an inverted conical slope. In other words, at least a portion of the cross-section of the partition SPR can be an inverted trapezoid.

[0243] In some exemplary implementations, such as Figure 7 As shown, the side surface of the separator SPR can have multiple inverted conical bevels. That is, the separator SPR can have a double inverted conical structure. Therefore, it is easier to achieve separation (or disconnection) of the electrode layer E2L by the separator SPR.

[0244] An intermediate layer ML can be disposed on the first electrode E1, the pixel defining layer PDL, and the first connection pattern CNPa. A portion of the intermediate layer ML can be disposed in a pixel opening of the pixel defining layer PDL. In some exemplary embodiments, the intermediate layer ML may include a first functional layer comprising an organic material, a light-emitting layer disposed on the first functional layer and comprising a light-emitting material, and a second functional layer disposed on the light-emitting layer and comprising an organic material. For example, the first functional layer may include a hole injection layer, a hole transport layer, etc., and the second functional layer may include an electron transport layer, an electron injection layer, etc.

[0245] Around the separator SPR with its inverted conical slope, there may be shaded areas where it is difficult to deposit the intermediate layer ML. Therefore, in and / or at the periphery of these shaded areas, the intermediate layer ML may have a structure separated (or disconnected) by the separator SPR. For example, the first and second functional layers included in the intermediate layer ML may have a structure separated (or disconnected) by the separator SPR. Because the intermediate layer ML has a separated (or disconnected) structure, it may not completely cover the first connection pattern CNPa. That is, the intermediate layer ML may expose a portion of the first connection pattern CNPa at locations adjacent to or overlapping with the separator SPR. Therefore, the second electrode E2 of the first light-emitting element LDa can contact the first connection pattern CNPa.

[0246] The first dummy layer DP1 can be disposed on the separator SPR. Since the intermediate layer ML has a structure separated (or disconnected) by the separator SPR, the first dummy layer DP1 can be formed. That is, the first dummy layer DP1 can be formed using the same (or similar) process as the intermediate layer ML. In some exemplary embodiments, the first dummy layer DP1 can be omitted.

[0247] Electrode layer E2L may be disposed on intermediate layer ML. Electrode layer E2L may include conductive materials, such as metals, alloys, conductive metal oxides, conductive metal nitrides, transparent conductive oxides, etc. In some exemplary embodiments, electrode layer E2L may have a single-layer structure. However, this disclosure is not necessarily limited to this, and electrode layer E2L may have a multilayer structure in which multiple conductive layers are stacked. For example, electrode layer E2L may have a two-layer structure in which a first sub-electrode layer including a metal and a second sub-electrode layer disposed on the first sub-electrode layer and including a transparent conductive oxide are stacked.

[0248] Around the separator SPR with its inverted conical slope, there may be shaded regions where it is difficult to deposit the electrode layer E2L. Therefore, in and / or at the periphery of these shaded regions, the electrode layer E2L may have a structure separated (or broken) by the separator SPR. For example, as... Figure 6 and Figure 7 As shown, the electrode layer E2L can be divided (or disconnected) into a second electrode E2 of the first light-emitting element LDa disposed in the first opening region OA1 of the separator SPR, a second electrode of the second light-emitting element LDb disposed in the second opening region OA2 of the separator SPR, and a second electrode of the third light-emitting element LDc disposed in the third opening region OA3 of the separator SPR. That is, the second electrodes can be electrically independent of each other.

[0249] like Figure 7 As shown, the second electrode E2 of the first light-emitting element LTa can be connected to the first connection pattern CNPa. For example, the second electrode E2 can contact the first connection pattern CNPa at a location adjacent to or overlapping with the separator SPR. For example, when the deposition angle of the deposition process forming the electrode layer E2L is greater than the deposition angle of the deposition process forming the intermediate layer ML, the electrode layer E2L (specifically, the second electrode E2) can be formed to contact the first connection pattern CNPa while covering the broken side of the intermediate layer ML. Therefore, the second electrode E2 can be electrically connected to the second transistor TR2 through the first connection electrode CE and the first connection pattern CNPa.

[0250] The second dummy layer DP2 can be disposed on the separator SPR. For example, the second dummy layer DP2 can be disposed on the first dummy layer DP1. Since the electrode layer E2L has a structure separated (or disconnected) by the separator SPR, the second dummy layer DP2 can be formed. That is, the second dummy layer DP2 can be formed using the same process (or a similar process) as the electrode layer E2L. In some exemplary embodiments, the second dummy layer DP2 can be omitted.

[0251] The encapsulation layer ENC can be disposed on the electrode layer E2L. The encapsulation layer ENC can completely cover the electrode layer E2L, the first connection pattern CNPa, the separator SPR, the first dummy layer DP1, and the second dummy layer DP2. In some exemplary embodiments, the encapsulation layer ENC may include a first inorganic encapsulation layer IEL1 comprising inorganic insulating material, an organic encapsulation layer OEL disposed on the first inorganic encapsulation layer IEL1 and comprising organic insulating material, and a second inorganic encapsulation layer IEL2 disposed on the organic encapsulation layer OEL and comprising inorganic insulating material.

[0252] In some exemplary embodiments, the display device DD may further include a touch sensing layer disposed on the encapsulation layer ENC. For example, the touch sensing layer may include a plurality of touch electrode arrays for capacitively sensing a user's touch, touch pad portions, and a plurality of touch lines electrically connecting the touch electrode arrays and the touch pad portions. However, this disclosure is not necessarily limited thereto. In some exemplary embodiments, the touch sensing layer may be omitted.

[0253] According to some exemplary embodiments, the display device DD may include a connecting electrode (e.g., a first connecting electrode CE), a connecting pattern (e.g., a first connecting pattern CNPa), and a separator SPR. Therefore, the electrode layer E2L (e.g., a cathode) disposed on the first electrode E1 (e.g., an anode) can be easily connected to the pixel driving circuit. For example, the electrode layer E2L disposed on the first electrode E1 can be connected to the driving transistor (e.g., a drive transistor) of the pixel driving circuit via the connecting electrode and the connecting pattern. Figure 3A , Figure 3D , Figure 4A and Figure 5A The drain of the first transistor T1 is used. Therefore, even when the light-emitting element deteriorates, the gate-source voltage of the driving transistor can remain unchanged. Therefore, the range of changes in the driving current due to the deterioration of the light-emitting element can be reduced. Therefore, the afterimage defects of the display device DD due to increased usage time can be reduced, and the lifespan of the display device DD can be improved (e.g., increased).

[0254] Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18 , Figure 19 and Figure 20 It is shown that it includes Figure 1 A layout diagram of an example of pixels in a display device. For example, Figures 8 to 20 It is shown Figure 7 The layout diagram of the circuit element layer PCL, which includes... Figure 5A The pixel driving circuit PC''.

[0255] Figure 8 This is a layout diagram showing the lower active layer ACL1.

[0256] refer to Figure 5A , Figure 7 and Figure 8 The lower active layer ACL1 can be disposed on the substrate SUB. In some exemplary embodiments, the lower active layer ACL1 may include a silicon semiconductor material.

[0257] The lower active layer ACL1 may include a lower active pattern PACT, and the lower active pattern PACT may include a first lower active pattern PACT1 and a second lower active pattern PACT2. The first lower active pattern PACT1 and the second lower active pattern PACT2 may be spaced apart from each other. The first lower active pattern PACT1 may include the channel of the seventh transistor T7 included in the pixel driving circuit PC''. The second lower active pattern PACT2 may include the channel of the fourth transistor T4 included in the pixel driving circuit PC''.

[0258] A first insulating layer IL1 can be disposed on a substrate SUB. The first insulating layer IL1 can cover a first lower active pattern PACT1 and a second lower active pattern PACT2 on the substrate SUB.

[0259] Figure 9 This is a layout diagram showing the first conductive layer CL1. Figure 10 The first conductive layer CL1 is also set in Figure 8 The layout diagram on the lower active layer ACL1.

[0260] Further reference Figure 9 and Figure 10 The first conductive layer CL1 can be disposed on the lower active layer ACL1. For example, the first conductive layer CL1 can be disposed on the first insulating layer IL1. The first conductive layer CL1 can include conductive materials, such as metals, alloys, conductive metal oxides, conductive metal nitrides, transparent conductive oxides, etc. For example, the first conductive layer CL1 can be referred to as the first gate conductive layer.

[0261] The first conductive layer CL1 may include a first lower gate pattern LGP1, a second lower gate pattern LGP2, a third lower gate pattern LGP3, and a fourth lower gate pattern LGP4. The first lower gate pattern LGP1, the second lower gate pattern LGP2, the third lower gate pattern LGP3, and the fourth lower gate pattern LGP4 may be spaced apart from each other in a planar view. The first lower gate pattern LGP1, the second lower gate pattern LGP2, the third lower gate pattern LGP3, and the fourth lower gate pattern LGP4 may be connected to... Figure 7 The first gate electrode GE1 is disposed in the same layer (or a similar layer).

[0262] The first lower gate pattern LGP1 can be compared with the first upper active pattern OACT1 described below in the plan view (see [link]). Figure 13 The overlap between the first lower gate pattern LGP1 and the first upper active pattern OACT1 can form the first transistor T1. The overlap between the first lower gate pattern LGP1 and the first upper active pattern OACT1 can be the lower gate electrode of the first transistor T1.

[0263] In the plan view, the second lower gate pattern LGP2 can overlap with the first lower active pattern PACT1. The portion of the second lower gate pattern LGP2 that overlaps with the first lower active pattern PACT1 can form the seventh transistor T7. The portion of the second lower gate pattern LGP2 that overlaps with the first lower active pattern PACT1 can be the gate electrode of the seventh transistor T7. The second lower gate pattern LGP2 can receive the second transmit control signal EM2.

[0264] The third lower gate pattern LGP3 can extend along the first direction DR1. The third lower gate pattern LGP3 can receive the second power voltage ELVSS. For example, the third lower gate pattern LGP3 can correspond to Figure 5A The second voltage line VL2. For example, the third lower gate pattern LGP3 can be referred to as the first common voltage line.

[0265] The fourth lower gate pattern LGP4 can extend along the first direction DR1. In a plan view, the fourth lower gate pattern LGP4 can overlap with the second lower active pattern PACT2. The portion of the fourth lower gate pattern LGP4 that overlaps with the second lower active pattern PACT2 can form the fourth transistor T4. The portion of the fourth lower gate pattern LGP4 that overlaps with the second lower active pattern PACT2 can be the gate electrode of the fourth transistor T4. The fourth lower gate pattern LGP4 can receive the third gate signal GC. For example, the fourth lower gate pattern LGP4 can correspond to... Figure 5A The third gate line GCL.

[0266] The second insulating layer IL2 can be disposed on the first insulating layer IL1. The second insulating layer IL2 can cover the first lower gate pattern LGP1, the second lower gate pattern LGP2, the third lower gate pattern LGP3 and the fourth lower gate pattern LGP4 on the first insulating layer IL1.

[0267] Figure 11 This is a layout diagram showing the second conductive layer CL2. Figure 12 The second conductive layer CL2 is also set in Figure 10 The layout diagram on the first conductive layer CL1.

[0268] Further reference Figure 11 and Figure 12 The second conductive layer CL2 can be disposed on the first conductive layer CL1. For example, the second conductive layer CL2 can be disposed on the second insulating layer IL2. The second conductive layer CL2 may include conductive materials, such as metals, alloys, conductive metal oxides, conductive metal nitrides, transparent conductive oxides, etc. For example, the second conductive layer CL2 can be referred to as the second gate conductive layer.

[0269] The second conductive layer CL2 may include a first intermediate gate pattern MGP1 and a second intermediate gate pattern MGP2. In a plan view, the first intermediate gate pattern MGP1 and the second intermediate gate pattern MGP2 may be spaced apart from each other. The first intermediate gate pattern MGP1 and the second intermediate gate pattern MGP2 may be... Figure 7 The third capacitor electrode CPE3 is disposed in the same layer (or a similar layer).

[0270] In the plan view, a first portion of the first intermediate gate pattern MGP1 may overlap with the first lower gate pattern LGP1. The first portion of the first intermediate gate pattern MGP1 may be spaced apart from the first lower gate pattern LGP1 by a second insulating layer IL2. The first portion of the first intermediate gate pattern MGP1 and the first lower gate pattern LGP1 may form a first capacitor C1. For example, the first lower gate pattern LGP1 may correspond to... Figure 7 The first capacitor electrode CPE1 and the first portion of the first intermediate gate pattern MGP1 can correspond to Figure 7 The third capacitor electrode, CPE3.

[0271] In the plan view, the second portion of the first intermediate gate pattern MGP1 may overlap with the third lower gate pattern LGP3. The second portion of the first intermediate gate pattern MGP1 may be spaced apart from the third lower gate pattern LGP3 by a second insulating layer IL2. The second portion of the first intermediate gate pattern MGP1 and the third lower gate pattern LGP3 may form a second capacitor C2. For example, the third lower gate pattern LGP3 may correspond to... Figure 7 The second capacitor electrode CPE2, and the second portion of the first intermediate gate pattern MGP1 can correspond to Figure 7 The fourth capacitor electrode, CPE4.

[0272] The second intermediate gate pattern MGP2 can extend along the first direction DR1. The second intermediate gate pattern MGP2 can receive a reference voltage VREF. For example, the second intermediate gate pattern MGP2 can correspond to... Figure 5A The third voltage line, VL3.

[0273] A third insulating layer IL3 may be disposed on the second insulating layer IL2. The third insulating layer IL3 may cover the first intermediate gate pattern MGP1 and the second intermediate gate pattern MGP2 on the second insulating layer IL2.

[0274] Figure 13 This is a layout diagram showing the upper active layer ACL2. Figure 14 The upper active layer ACL2 is also set Figure 12The layout diagram on the second conductive layer CL2.

[0275] Further reference Figure 13 and Figure 14 The upper active layer ACL2 can be disposed on the second conductive layer CL2. For example, the upper active layer ACL2 can be disposed on the third insulating layer IL3. In some exemplary embodiments, the upper active layer ACL2 may include an oxide semiconductor material.

[0276] The upper active layer ACL2 may include an upper active pattern OACT, and the upper active pattern OACT may include a first upper active pattern OACT1 and a second upper active pattern OACT2. The first upper active pattern OACT1 and the second upper active pattern OACT2 may be spaced apart from each other. The first upper active pattern OACT1 may include the channel of the first transistor T1, the channel of the fifth transistor T5, and the channel of the sixth transistor T6. The second upper active pattern OACT2 may include the channel of the second transistor T2 and the channel of the third transistor T3.

[0277] The fourth insulating layer IL4 can be disposed on the third insulating layer IL3. The fourth insulating layer IL4 can cover the first upper active pattern OACT1 and the second upper active pattern OACT2 on the third insulating layer IL3.

[0278] Figure 15 This is a layout diagram showing the third conductive layer CL3. Figure 16 The third conductive layer CL3 is also set in Figure 14 The layout diagram on the upper active layer ACL2.

[0279] Further reference Figure 15 and Figure 16 The third conductive layer CL3 can be disposed on the upper active layer ACL2. For example, the third conductive layer CL3 can be disposed on the fourth insulating layer IL4. The third conductive layer CL3 can include conductive materials, such as metals, alloys, conductive metal oxides, conductive metal nitrides, transparent conductive oxides, etc. For example, the third conductive layer CL3 can be referred to as the third gate conductive layer.

[0280] The third conductive layer CL3 may include a first upper gate pattern UGP1, a second upper gate pattern UGP2, a third upper gate pattern UGP3, a fourth upper gate pattern UGP4, and a fifth upper gate pattern UGP5. The first upper gate pattern UGP1, the second upper gate pattern UGP2, the third upper gate pattern UGP3, the fourth upper gate pattern UGP4, and the fifth upper gate pattern UGP5 may be spaced apart from each other in a planar view. The first upper gate pattern UGP1, the second upper gate pattern UGP2, the third upper gate pattern UGP3, the fourth upper gate pattern UGP4, and the fifth upper gate pattern UGP5 may be... Figure 7 The second gate electrode GE2 is disposed in the same layer (or a similar layer).

[0281] In the plan view, the first upper gate pattern UGP1 may overlap with a first portion of the first upper active pattern OACT1. The overlapping portion of the first upper gate pattern UGP1 and the first portion of the first upper active pattern OACT1 may form the first transistor T1. The overlapping portion of the first upper gate pattern UGP1 and the first portion of the first upper active pattern OACT1 may be the gate electrode of the first transistor T1.

[0282] The second upper gate pattern UGP2 can extend along the first direction DR1. In a plan view, the second upper gate pattern UGP2 can overlap with the second and third portions of the first upper active pattern OACT1. The first portion of the second upper gate pattern UGP2 that overlaps with the second portion of the first upper active pattern OACT1 can form the fifth transistor T5. The first portion of the second upper gate pattern UGP2 that overlaps with the second portion of the first upper active pattern OACT1 can be the gate electrode of the fifth transistor T5. The second portion of the second upper gate pattern UGP2 that overlaps with the third portion of the first upper active pattern OACT1 can form the sixth transistor T6. The second portion of the second upper gate pattern UGP2 that overlaps with the third portion of the first upper active pattern OACT1 can be the gate electrode of the sixth transistor T6. The second upper gate pattern UGP2 can receive the first transmit control signal EM1. For example, the second upper gate pattern UGP2 can correspond to... Figure 5A The first launch control line is ECL1.

[0283] The third upper gate pattern UGP3 can extend along the first direction DR1. The third upper gate pattern UGP3 can receive the initialization voltage VCINT. For example, the third upper gate pattern UGP3 can correspond to... Figure 5A The fourth voltage line VL4. For example, the third upper gate pattern UGP3 can be referred to as the first initialization voltage line.

[0284] The fourth upper gate pattern UGP4 can extend along the first direction DR1. In a plan view, the fourth upper gate pattern UGP4 can overlap with a first portion of the second upper active pattern OACT2. The portion of the fourth upper gate pattern UGP4 that overlaps with the first portion of the second upper active pattern OACT2 can form the third transistor T3. The portion of the fourth upper gate pattern UGP4 that overlaps with the first portion of the second upper active pattern OACT2 can be the gate electrode of the third transistor T3. The fourth upper gate pattern UGP4 can receive the second gate signal GR. For example, the fourth upper gate pattern UGP4 can correspond to... Figure 5A The second gate line GRL.

[0285] In the plan view, the fifth upper gate pattern UGP5 can overlap with the second portion of the second upper active pattern OACT2. The overlapping portion of the fifth upper gate pattern UGP5 and the second portion of the second upper active pattern OACT2 can form the second transistor T2. The overlapping portion of the fifth upper gate pattern UGP5 and the second portion of the second upper active pattern OACT2 can be the gate electrode of the second transistor T2. The fifth upper gate pattern UGP5 can receive the first gate signal GW.

[0286] The fifth insulating layer IL5 can be disposed on the fourth insulating layer IL4. The fifth insulating layer IL5 can cover the first upper gate pattern UGP1, the second upper gate pattern UGP2, the third upper gate pattern UGP3, the fourth upper gate pattern UGP4 and the fifth upper gate pattern UGP5 on the fourth insulating layer IL4.

[0287] Figure 17 This is a layout diagram showing the fourth conductive layer CL4. Figure 18 The fourth conductive layer CL4 is also set in Figure 16 The layout diagram on the third conductive layer CL3.

[0288] Further reference Figure 17 and Figure 18 The fourth conductive layer CL4 can be disposed on the third conductive layer CL3. For example, the fourth conductive layer CL4 can be disposed on the fifth insulating layer IL5. The fourth conductive layer CL4 can include conductive materials, such as metals, alloys, conductive metal oxides, conductive metal nitrides, transparent conductive oxides, etc. For example, the fourth conductive layer CL4 can be referred to as the first source-drain conductive layer.

[0289] The fourth conductive layer CL4 may include a first lower source pattern LSP1, a second lower source pattern LSP2, a third lower source pattern LSP3, a fourth lower source pattern LSP4, a fifth lower source pattern LSP5, a sixth lower source pattern LSP6, a seventh lower source pattern LSP7, an eighth lower source pattern LSP8, a ninth lower source pattern LSP9, a tenth lower source pattern LSP10, an eleventh lower source pattern LSP11, and a twelfth lower source pattern LSP12. The first lower source pattern LSP1, the second lower source pattern LSP2, the third lower source pattern LSP3, the fourth lower source pattern LSP4, the fifth lower source pattern LSP5, the sixth lower source pattern LSP6, the seventh lower source pattern LSP7, the eighth lower source pattern LSP8, the ninth lower source pattern LSP9, the tenth lower source pattern LSP10, the eleventh lower source pattern LSP11, and the twelfth lower source pattern LSP12 can be spaced apart from each other in the planar diagram. The first lower source pattern LSP1, the second lower source pattern LSP2, the third lower source pattern LSP3, the fourth lower source pattern LSP4, the fifth lower source pattern LSP5, the sixth lower source pattern LSP6, the seventh lower source pattern LSP7, the eighth lower source pattern LSP8, the ninth lower source pattern LSP9, the tenth lower source pattern LSP10, the eleventh lower source pattern LSP11, and the twelfth lower source pattern LSP12 can be combined with... Figure 7 The first contact electrode SE1 is disposed in the same layer (or a similar layer).

[0290] In the plan view, the first lower source pattern LSP1 can overlap with the first lower gate pattern LGP1, the first upper gate pattern UGP1, and the first upper active pattern OACT1. The first lower source pattern LSP1 can be connected to the first lower gate pattern LGP1, the first upper gate pattern UGP1, and the first upper active pattern OACT1 through contact holes. Therefore, the first lower source pattern LSP1 can be electrically connected to the gate electrode of the first transistor T1, the second transistor T2, and the first capacitor C1.

[0291] In the plan view, the second lower source pattern LSP2 can overlap with the first lower active pattern PACT1 and the first upper active pattern OACT1. The second lower source pattern LSP2 can be connected to the first lower active pattern PACT1 and the first upper active pattern OACT1 through contact holes. Therefore, the second lower source pattern LSP2 can electrically connect the first transistor T1 and the seventh transistor T7.

[0292] In the plan view, the third lower source pattern LSP3 can overlap with the first upper active pattern OACT1 and the first intermediate gate pattern MGP1. The third lower source pattern LSP3 can be connected to the first upper active pattern OACT1 and the first intermediate gate pattern MGP1 through contact holes. Therefore, the third lower source pattern LSP3 can be electrically connected to the first capacitor C1, the second capacitor C2, and the first transistor T1.

[0293] The fourth lower source pattern LSP4 can extend along the first direction DR1. In a plan view, the fourth lower source pattern LSP4 can overlap with the second lower gate pattern LGP2. The fourth lower source pattern LSP4 can be connected to the second lower gate pattern LGP2 via a contact hole. The fourth lower source pattern LSP4 can receive the second transmit control signal EM2. Therefore, the fourth lower source pattern LSP4 can provide the second transmit control signal EM2 to the second lower gate pattern LGP2. For example, the fourth lower source pattern LSP4 can correspond to... Figure 5A The second launch control line, ECL2.

[0294] The fifth lower source pattern LSP5 can extend along the first direction DR1. In a plan view, the fifth lower source pattern LSP5 can overlap with the first lower active pattern PACT1. The fifth lower source pattern LSP5 can be connected to the first lower active pattern PACT1 via a contact hole. The fifth lower source pattern LSP5 can receive a first power voltage ELVDD. Therefore, the fifth lower source pattern LSP5 can provide the first power voltage ELVDD to the seventh transistor T7. For example, the fifth lower source pattern LSP5 can correspond to... Figure 5A The first voltage line is VL1. For example, the fifth lower source pattern LSP5 can be referred to as the third drive voltage line.

[0295] In some exemplary embodiments, the fifth lower source pattern LSP5 (or the third drive voltage line) may be disposed on the third upper gate pattern UGP3 (or the first initialization voltage line).

[0296] In the plan view, the sixth lower source pattern LSP6 can overlap with the first upper active pattern OACT1 and the third lower gate pattern LGP3. The sixth lower source pattern LSP6 can be connected to the first upper active pattern OACT1 and the third lower gate pattern LGP3 via contact holes. Therefore, the sixth lower source pattern LSP6 can electrically connect the first upper active pattern OACT1 and the third lower gate pattern LGP3. The third lower gate pattern LGP3 can provide a second power voltage ELVSS to the sixth transistor T6 through the sixth lower source pattern LSP6.

[0297] In the plan view, the seventh lower source pattern LSP7 can overlap with the second lower active pattern PACT2 and the first upper active pattern OACT1. The seventh lower source pattern LSP7 can be connected to the second lower active pattern PACT2 and the first upper active pattern OACT1 through contact holes. Therefore, the seventh lower source pattern LSP7 can electrically connect the fourth transistor T4 and the fifth transistor T5.

[0298] In the plan view, the eighth lower source pattern LSP8 can overlap with the second lower active pattern PACT2 and the third upper gate pattern UGP3. The eighth lower source pattern LSP8 can be connected to the second lower active pattern PACT2 and the third upper gate pattern UGP3 through contact holes. Therefore, the eighth lower source pattern LSP8 can electrically connect the second lower active pattern PACT2 and the third upper gate pattern UGP3. The third upper gate pattern UGP3 can provide the initialization voltage VCINT to the fourth transistor T4 through the eighth lower source pattern LSP8. For example, the eighth lower source pattern LSP8 can be referred to as the initialization voltage connection pattern.

[0299] The ninth lower source pattern LSP9 can extend along the first direction DR1. The ninth lower source pattern LSP9 can be connected in a planar view to the third upper source pattern USP3 described below (see...). Figure 19 )overlapping.

[0300] In the plan view, the tenth lower source pattern LSP10 can overlap with the second upper active pattern OACT2 and the second intermediate gate pattern MGP2. The tenth lower source pattern LSP10 can be connected to the second upper active pattern OACT2 and the second intermediate gate pattern MGP2 through contact holes. Therefore, the tenth lower source pattern LSP10 can electrically connect the second upper active pattern OACT2 and the second intermediate gate pattern MGP2. The second intermediate gate pattern MGP2 can provide a reference voltage VREF to the third transistor T3 through the tenth lower source pattern LSP10.

[0301] The eleventh lower source pattern LSP11 can extend along the first direction DR1. In a plan view, the eleventh lower source pattern LSP11 can overlap with the fifth upper gate pattern UGP5. The eleventh lower source pattern LSP11 can be connected to the fifth upper gate pattern UGP5 via a contact hole. The eleventh lower source pattern LSP11 can receive the first gate signal GW. Therefore, the eleventh lower source pattern LSP11 can provide the first gate signal GW to the fifth upper gate pattern UGP5. For example, the eleventh lower source pattern LSP11 can correspond to... Figure 5A The first gate line GWL.

[0302] In the plan view, the twelfth lower source pattern LSP12 can overlap with the second upper active pattern OACT2. The twelfth lower source pattern LSP12 can be connected to the second upper active pattern OACT2 through a contact hole. The twelfth lower source pattern LSP12 can receive the data voltage VDATA. Therefore, the twelfth lower source pattern LSP12 can provide the data voltage VDATA to the second transistor T2.

[0303] The sixth insulating layer IL6 can be disposed on the fifth insulating layer IL5. The sixth insulating layer IL6 can cover the first lower source pattern LSP1, the second lower source pattern LSP2, the third lower source pattern LSP3, the fourth lower source pattern LSP4, the fifth lower source pattern LSP5, the sixth lower source pattern LSP6, the seventh lower source pattern LSP7, the eighth lower source pattern LSP8, the ninth lower source pattern LSP9, the tenth lower source pattern LSP10, the eleventh lower source pattern LSP11, and the twelfth lower source pattern LSP12 on the fifth insulating layer IL5.

[0304] Figure 19 This is a layout diagram showing the fifth conductive layer CL5. Figure 20 The fifth conductive layer CL5 is also set in Figure 18 The layout diagram on the fourth conductive layer CL4.

[0305] Further reference Figure 19 and Figure 20 The fifth conductive layer CL5 can be disposed on the fourth conductive layer CL4. For example, the fifth conductive layer CL5 can be disposed on the sixth insulating layer IL6. The fifth conductive layer CL5 can include conductive materials, such as metals, alloys, conductive metal oxides, conductive metal nitrides, transparent conductive oxides, etc. For example, the fifth conductive layer CL5 can be referred to as the second source-drain conductive layer.

[0306] The fifth conductive layer CL5 may include a first upper source pattern USP1, a second upper source pattern USP2, a third upper source pattern USP3, a fourth upper source pattern USP4, a fifth upper source pattern USP5, and a sixth upper source pattern USP6. The first upper source pattern USP1, the second upper source pattern USP2, the third upper source pattern USP3, the fourth upper source pattern USP4, the fifth upper source pattern USP5, and the sixth upper source pattern USP6 may be spaced apart from each other in a planar view. The first upper source pattern USP1, the second upper source pattern USP2, the third upper source pattern USP3, the fourth upper source pattern USP4, the fifth upper source pattern USP5, and the sixth upper source pattern USP6 may be connected to... Figure 7 The first connecting electrode CE is disposed in the same layer (or a similar layer).

[0307] The first upper source pattern USP1 can extend in the second direction DR2. In a plan view, the first upper source pattern USP1 can overlap with the sixth lower source pattern LSP6. The first upper source pattern USP1 can be connected to the sixth lower source pattern LSP6 via a contact hole. The first upper source pattern USP1 can receive a second power voltage ELVSS. Therefore, the first upper source pattern USP1 can provide the second power voltage ELVSS to the sixth lower source pattern LSP6. For example, the first upper source pattern USP1 can correspond to... Figure 5A The second voltage line VL2. For example, the first upper source pattern USP1 can be referred to as the second common voltage line.

[0308] In some exemplary embodiments, the first upper source pattern USP1 and the third lower gate pattern LGP3 that receive the second power voltage ELVSS (see...) Figure 9 The pattern can have a mesh shape in the planar view. The third lower gate pattern LGP3 can extend in the first direction DR1, and the first upper source pattern USP1 can extend in the second direction DR2. Therefore, the resistance generated in the pattern (or line) transmitting the second power voltage ELVSS can be effectively reduced, and the voltage drop of the second power voltage ELVSS can be effectively prevented (or reduced).

[0309] The second upper source pattern USP2 can extend along the second direction DR2. In a plan view, the second upper source pattern USP2 can overlap with the twelfth lower source pattern LSP12. The second upper source pattern USP2 can be connected to the twelfth lower source pattern LSP12 via a contact hole. The second upper source pattern USP2 can receive a data voltage VDATA. Therefore, the second upper source pattern USP2 can provide the data voltage VDATA to the twelfth lower source pattern LSP12. For example, the second upper source pattern USP2 can correspond to... Figure 5A DL data cable.

[0310] The third upper source pattern USP3 can extend along the second direction DR2. In a plan view, the third upper source pattern USP3 can overlap with a portion of the ninth lower source pattern LSP9. The third upper source pattern USP3 can be used to direct light to the display area DA (see...). Figure 2A The sub-pixels at the edge of the region provide additional data lines for the data voltage VDATA.

[0311] The fourth upper source pattern USP4 can extend along the second direction DR2. In a plan view, the fourth upper source pattern USP4 can overlap with the eighth lower source pattern LSP8. The fourth upper source pattern USP4 can be connected to the eighth lower source pattern LSP8 via the initialization contact hole CCNT. The fourth upper source pattern USP4 can receive the initialization voltage VCINT. Therefore, the fourth upper source pattern USP4 can provide the initialization voltage VCINT to the eighth lower source pattern LSP8. For example, the fourth upper source pattern USP4 can correspond to... Figure 5A The fourth voltage line VL4. For example, the fourth upper source pattern USP4 can be referred to as the second initialization voltage line. According to some exemplary embodiments, the eighth lower source pattern LSP8 can be electrically connected to the third upper gate pattern UGP3 and the fourth upper source pattern USP4.

[0312] In some exemplary embodiments, the fourth upper source pattern USP4 and the third upper gate pattern UGP3 (see [reference]) receive the initialization voltage VCINT. Figure 15 The pattern can have a mesh shape in the planar view. The third upper gate pattern UGP3 can extend in the first direction DR1, and the fourth upper source pattern USP4 can extend in the second direction DR2. Therefore, the resistance generated in the pattern (or line) for transmitting the initialization voltage VCINT can be effectively reduced. Therefore, the brightness difference between pixels due to resistance can be reduced, defects such as smudges detected in the display device DD can be effectively prevented (or reduced), and the display quality of the display device DD can be improved.

[0313] The fifth upper source pattern USP5 can extend along the second direction DR2. In a plan view, the fifth upper source pattern USP5 can overlap with the fifth lower source pattern LSP5. The fifth upper source pattern USP5 can be connected to the fifth lower source pattern LSP5 through the first drive contact hole DCNT1. The fifth upper source pattern USP5 can receive a first power voltage ELVDD. Therefore, the fifth upper source pattern USP5 can provide the first power voltage ELVDD to the fifth lower source pattern LSP5. For example, the fifth upper source pattern USP5 can correspond to... Figure 5A The first voltage line is VL1. For example, the fifth upper source pattern USP5 can be referred to as the fourth drive voltage line.

[0314] In some exemplary embodiments, the fifth upper source pattern USP5 and the fifth lower source pattern LSP5 that receive the first power voltage ELVDD (see...) Figure 17The fifth lower source pattern LSP5 can extend in the first direction DR1, and the fifth upper source pattern USP5 can extend in the second direction DR2.

[0315] In some exemplary embodiments, the first drive contact hole DCNT1 and the initialization contact hole CCNT may be spaced apart from each other in a plan view.

[0316] In some exemplary embodiments, the first driving contact hole DCNT1 and the initialization contact hole CCNT can be arranged alternately along one direction in a plan view. For example, the first driving contact hole DCNT1 and the initialization contact hole CCNT can be arranged along a first direction DR1 in the order of initialization contact hole CCNT, first driving contact hole DCNT1, initialization contact hole CCNT, and first driving contact hole DCNT1. For example, the first driving contact hole DCNT1 and the initialization contact hole CCNT can be arranged along a direction opposite to the second direction DR2 in the order of first driving contact hole DCNT1, initialization contact hole CCNT, first driving contact hole DCNT1, and initialization contact hole CCNT. However, this disclosure is not necessarily limited to these embodiments.

[0317] In the plan view, the sixth upper source pattern USP6 can overlap with the seventh lower source pattern LSP7. The sixth upper source pattern USP6 can be connected to the seventh lower source pattern LSP7 via a contact hole. The sixth upper source pattern USP6 can be electrically connected. Figure 6 The connection pattern is any one of CNPa, CNPb and CNPc and the seventh lower source pattern LSP7.

[0318] The seventh insulating layer IL7 can be disposed on the sixth insulating layer IL6. The seventh insulating layer IL7 can cover the first upper source pattern USP1, the second upper source pattern USP2, the third upper source pattern USP3, the fourth upper source pattern USP4, the fifth upper source pattern USP5, and the sixth upper source pattern USP6 on the sixth insulating layer IL6.

[0319] Figure 21 It shows that it is set with Figure 7 The layout diagram of the pixel layer of the first electrode. Figure 22 It is one of them Figure 21 The pixel layer is also set Figure 19 The layout diagram on the fifth conductive layer.

[0320] Further reference Figure 21 and Figure 22The pixel layer PXL can be disposed on the fifth conductive layer CL5. For example, the pixel layer PXL can be disposed on the seventh insulating layer IL7. The pixel layer PXL can include conductive materials, such as metals, alloys, conductive metal oxides, conductive metal nitrides, transparent conductive oxides, etc.

[0321] The pixel layer PXL may include a first electrode E1, a first driving voltage line DML1, a second driving voltage line DML2, and a driving voltage connection pattern DCP. In some exemplary embodiments, the first electrode E1, the first driving voltage line DML1, the second driving voltage line DML2, and the driving voltage connection pattern DCP may be integrally formed.

[0322] Figure 21 The first electrode E1 can correspond to Figure 7 The first electrode E1. That is, the first electrode E1 can be used as... Figure 5A The anode of the light-emitting element LD.

[0323] The first driving voltage line DML1 can extend in a first oblique direction between the first direction DR1 and the second direction DR2. That is, the first oblique direction of the first driving voltage line DML1 can be different from the first direction DR1 of the third upper gate pattern UGP3 (or the first initialization voltage line) and the second direction DR2 of the fourth upper source pattern USP4 (or the second initialization voltage line). Furthermore, the first oblique direction of the first driving voltage line DML1 can be different from the first direction DR1 of the fifth lower source pattern LSP5 (or the third driving voltage line) and the second direction DR2 of the fifth upper source pattern USP5 (or the fourth driving voltage line). The first driving voltage line DML1 can overlap with the first electrode E1. The first driving voltage line DML1 can receive a first power voltage ELVDD.

[0324] The second driving voltage line DML2 can extend in a second oblique direction between the opposite direction of the first direction DR1 and the opposite direction of the second direction DR2. The second oblique direction can intersect the first oblique direction. For example, the first oblique direction and the second oblique direction can be perpendicular. That is, the second oblique direction of the second driving voltage line DML2 can be different from the first direction DR1 of the third upper gate pattern UGP3 (or the first initialization voltage line) and the second direction DR2 of the fourth upper source pattern USP4 (or the second initialization voltage line). Furthermore, the second oblique direction of the second driving voltage line DML2 can be different from the first direction DR1 of the fifth lower source pattern LSP5 (or the third driving voltage line) and the second direction DR2 of the fifth upper source pattern USP5 (or the fourth driving voltage line). The second driving voltage line DML2 can overlap with the first electrode E1. The second driving voltage line DML2 can receive the first power voltage ELVDD.

[0325] like Figure 21 As shown, the drive voltage connection pattern DCP may overlap with the second drive voltage line DML2. However, this disclosure is not necessarily limited to this, and the drive voltage connection pattern DCP may overlap with the first drive voltage line DML1. In the plan view, the drive voltage connection pattern DCP may overlap with the fifth upper source pattern USP5. The drive voltage connection pattern DCP can be connected to the fifth upper source pattern USP5 through the second drive contact hole DCNT2. In some exemplary embodiments, in the plan view, the second drive contact hole DCNT2 may overlap with... Figure 19 The first drive contact hole DCNT1 is spaced apart. The drive voltage connection pattern DCP can be electrically connected to the fifth upper source pattern USP5 and the second drive voltage line DML2 (or the first drive voltage line DML1).

[0326] Figure 21 The patterned contact hole TCNT can correspond to Figure 6 The first patterned contact hole TCNTa, the second patterned contact hole TCNTb, and the third patterned contact hole TCNTc. In some exemplary embodiments, the patterned contact hole TCNT and the second drive contact hole DCNT2 may be spaced apart from each other in a plan view.

[0327] In some exemplary embodiments, the first drive voltage line DML1 and the second drive voltage line DML2, which receive the first power voltage ELVDD, may have a second mesh shape in a plan view. The first drive voltage line DML1 may extend in a first diagonal direction, and the second drive voltage line DML2 may extend in a second diagonal direction.

[0328] As described above, the fifth lower source pattern LSP5 and the fifth upper source pattern USP5, which receive the first power voltage ELVDD, can have a first mesh shape in the planar view, and the first driving voltage line DML1 and the second driving voltage line DML2, which receive the first power voltage ELVDD, can have a second mesh shape in the planar view. That is, the line (or pattern) transmitting the first power voltage ELVDD can have a double mesh shape in the planar view. Therefore, the resistance generated in the line (or pattern) transmitting the first power voltage ELVDD can be effectively reduced, and the voltage drop of the first power voltage ELVDD can be effectively prevented (or reduced).

[0329] Figure 23 This is a block diagram illustrating an electronic device according to some exemplary embodiments of the present disclosure.

[0330] refer to Figure 23 An electronic device 10 according to some exemplary embodiments may include a display module 11, a processor 12, a memory 13, and / or a power module 14. The display device according to some exemplary embodiments can be applied to various electronic devices 10. An electronic device 10 according to some exemplary embodiments may include the aforementioned display device, and may also include modules or devices with other additional functions in addition to the display device. According to some exemplary embodiments, the operations described herein as being performed by the electronic device 10, display module 11, processor 12, and / or power module 14 can be performed by processing circuitry.

[0331] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0332] The memory 13 can store data information required for the operation of the processor 12 and / or the display module 11 (or for other uses). When the processor 12 executes the application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11, and the display module 11 can process the received signals and output image information through the display screen.

[0333] The power module 14 may include a power module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power module to generate the power required for the operation (or otherwise used) of the electronic device 10. That is, the power module 14 can supply power to the display device according to the example above.

[0334] At least one of the components of the electronic device 10 described above may be included in the display device according to the example above. Furthermore, some of the modules functionally included in a single module may be included in the display device, and other modules may be disposed separately from the display device. For example, the display device may include a display module 11, and the processor 12, memory 13, and / or power module 14 may be disposed in the electronic device 10 as other devices besides the display device.

[0335] Figure 24 This is a schematic diagram of an electronic device according to some exemplary embodiments.

[0336] refer to Figure 24 Various electronic devices that apply display devices according to some exemplary embodiments may include image display electronic devices such as smartphones 10_1a, tablet computers 10_1b, laptop computers 10_1c, televisions 10_1d, desktop monitors 10_1e, etc.; wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays 10_2b, smartwatches 10_2c, etc.; and vehicle electronic devices 10_3 including display modules such as CID (Central Information Display) and interior mirror displays that can be installed on the dashboard, center dashboard, and instrument panel of a vehicle.

[0337] The various operations of the above-described methods can be performed by any suitable device (such as the processing circuit described above). For example, as mentioned above, the operations of the above-described methods can be performed by various software and / or hardware implemented in some form of hardware (e.g., processor, ASIC, etc.).

[0338] The software may include an ordered list of executable instructions for implementing logical functions and may be implemented in any processor-readable medium for use by or in conjunction with an instruction execution system, apparatus or device, such as a single-core or multi-core processor or a system including a processor.

[0339] The methods or algorithms and / or functional blocks or operations described in conjunction with some of the exemplary embodiments disclosed herein can be implemented directly in hardware, as software modules executed by a processor, or a combination of both. If implemented in software, the functionality can be stored as one or more instructions or code on or transmitted thereon on a tangible, non-transitory computer-readable medium. The software module can reside in random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the art.

[0340] This disclosure can be applied to various display devices. For example, this disclosure can be applied to various display devices such as those used in vehicles, ships and aircraft, portable communication devices, display devices for display or information transmission, medical display devices, etc.

[0341] The above is a description of some exemplary embodiments of this disclosure and should not be construed as limiting it. Although some exemplary embodiments have been described with reference to the accompanying drawings, those skilled in the art will readily understand that many changes and modifications can be made therein without departing from the spirit and scope of this disclosure as defined in the appended claims.

Claims

1. A display device, comprising: Substrate; A pixel driving circuit, on the substrate, the pixel driving circuit includes transistors; A connecting electrode is provided on the substrate, and the connecting electrode is electrically connected to the pixel driving circuit. A first electrode is located on the substrate and is spaced apart from the connecting electrode. A pixel defining layer on the substrate, the pixel defining layer defining an opening that exposes a portion of the first electrode; An electrode layer is provided on the first electrode and electrically connected to the connecting electrode. A first driving voltage line is in the same layer as the first electrode, the first driving voltage line is configured to receive a first electrical voltage, and the first driving voltage line extends in a first direction; as well as The second driving voltage line is in the same layer as the first electrode, the second driving voltage line is configured to receive the first power voltage, and the second driving voltage line extends in a second direction intersecting the first direction.

2. The display device according to claim 1, wherein, The first driving voltage line and the second driving voltage line have a mesh shape in the plan view.

3. The display device according to claim 1, further comprising: A third driving voltage line is located between the substrate and the first electrode, the third driving voltage line being configured to receive the first electrical voltage; as well as A fourth driving voltage line is located between the third driving voltage line and the first electrode, and the fourth driving voltage line is configured to receive the first power voltage.

4. The display device according to claim 3, wherein, The third driving voltage line and the fourth driving voltage line have a mesh-like shape in the plan view.

5. The display device according to claim 3, further comprising: A separator, on the pixel defining layer, and the separator is configured to divide the electrode layer into a plurality of second electrodes spaced apart from each other; as well as A connection pattern is provided on the connection electrode and the pixel defining layer, and the connection pattern is connected to the connection electrode.

6. The display device according to claim 5, wherein, The connection pattern is connected to one of the plurality of second electrodes at a location adjacent to or overlapping with the separator.

7. The display device according to claim 5, further comprising: The driving voltage connection pattern is in the same layer as the first electrode, and the driving voltage connection pattern electrically connects the first driving voltage line and the fourth driving voltage line.

8. The display device according to claim 7, wherein, The connection pattern is connected to the connection electrode through a patterned contact hole; The driving voltage connection pattern is connected to the fourth driving voltage line through a driving contact hole; as well as The patterned contact holes and the driving contact holes are spaced apart from each other in the plan view.

9. The display device according to claim 3, wherein, The pixel driving circuit also includes: The lower active pattern is on the substrate; The first gate electrode is on the lower active pattern; and The contact electrode is located on the first gate electrode.

10. The display device according to claim 9, wherein, The third driving voltage line is in the same layer as the contact electrode; and The fourth driving voltage line is in the same layer as the connecting electrode.

11. The display device according to claim 1, wherein, The first driving voltage line, the second driving voltage line, and the first electrode are integrally formed.

12. A display device, comprising: Substrate; A pixel driving circuit, on the substrate, the pixel driving circuit includes transistors; A connecting electrode is provided on the substrate, and the connecting electrode is electrically connected to the pixel driving circuit. A first electrode is located on the substrate and is spaced apart from the connecting electrode. A pixel defining layer on the substrate, the pixel defining layer defining an opening that exposes a portion of the first electrode; An electrode layer is provided on the first electrode and electrically connected to the connecting electrode. A first initialization voltage line is provided between the substrate and the first electrode, the first initialization voltage line is configured to receive an initialization voltage, and the first initialization voltage line extends in a first direction. A second initialization voltage line is located between the first initialization voltage line and the first electrode. The second initialization voltage line is configured to receive the initialization voltage and extends in a second direction intersecting the first direction. A first driving voltage line is in the same layer as the first electrode, the first driving voltage line is configured to receive a first electrical voltage, and the first driving voltage line extends in a first oblique direction between the first direction and the second direction; as well as The second driving voltage line is in the same layer as the first electrode, the second driving voltage line is configured to receive the first power voltage, and the second driving voltage line extends in a second oblique direction that intersects the first oblique direction.

13. The display device according to claim 12, wherein, The first driving voltage line and the second driving voltage line have a mesh-like shape in the plan view; and The first initialization voltage line and the second initialization voltage line have a mesh shape in the plan view.

14. The display device according to claim 12, further comprising: A third driving voltage line is located between the substrate and the first electrode, the third driving voltage line is configured to receive the first electrical voltage, and the third driving voltage line extends in the first direction; as well as A fourth driving voltage line is located between the third driving voltage line and the first electrode, the fourth driving voltage line being configured to receive the first power voltage, and the fourth driving voltage line extending in the second direction.

15. The display device according to claim 14, further comprising: The initialization voltage connection pattern electrically connects the first initialization voltage line and the second initialization voltage line. in: The fourth driving voltage line is connected to the third driving voltage line through the first driving contact hole. The second initialization voltage line is connected to the initialization voltage connection pattern through an initialization contact hole, and The first driving contact hole and the initialization contact hole are spaced apart from each other in the plan view.

16. The display device according to claim 15, wherein, The first drive contact hole and the initialization contact hole are arranged alternately along one direction in the plan view.

17. The display device according to claim 15, further comprising: A driving voltage connection pattern is located in the same layer as the first electrode, and the driving voltage connection pattern electrically connects the first driving voltage line and the fourth driving voltage line. in: The driving voltage connection pattern is connected to the fourth driving voltage line through the second driving contact hole, and The first drive contact hole and the second drive contact hole are spaced apart from each other in the plan view.

18. The display device according to claim 14, wherein, The third driving voltage line is on the first initialization voltage line, and The fourth driving voltage line is in the same layer as the second initialization voltage line.

19. The display device according to claim 12, wherein, The first driving voltage line, the second driving voltage line, and the first electrode are integrally formed.

20. An electronic device comprising: Display device, including pixels; as well as The processing circuitry is configured to transmit image data signals and input control signals to the display device. The display device includes: Substrate, A pixel driving circuit, on the substrate, includes transistors. A connecting electrode is provided on the substrate, and the connecting electrode is electrically connected to the pixel driving circuit. A first electrode is located on the substrate, and the first electrode is spaced apart from the connecting electrode. A pixel defining layer, on the substrate, defines an opening that exposes a portion of the first electrode. An electrode layer is provided on the first electrode and electrically connected to the connecting electrode. A first driving voltage line, located in the same layer as the first electrode, is configured to receive a first electrical voltage and extends in a first direction. The second driving voltage line is in the same layer as the first electrode, the second driving voltage line is configured to receive the first power voltage, and the second driving voltage line extends in a second direction intersecting the first direction.

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